2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
106 static struct ath5k_srev_name srev_names[] = {
107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
145 static struct ieee80211_rate ath5k_rates[] = {
147 .hw_value = ATH5K_RATE_CODE_1M, },
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_6M,
164 .hw_value = ATH5K_RATE_CODE_9M,
167 .hw_value = ATH5K_RATE_CODE_12M,
170 .hw_value = ATH5K_RATE_CODE_18M,
173 .hw_value = ATH5K_RATE_CODE_24M,
176 .hw_value = ATH5K_RATE_CODE_36M,
179 .hw_value = ATH5K_RATE_CODE_48M,
182 .hw_value = ATH5K_RATE_CODE_54M,
188 * Prototypes - PCI stack related functions
190 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
194 static int ath5k_pci_suspend(struct pci_dev *pdev,
196 static int ath5k_pci_resume(struct pci_dev *pdev);
198 #define ath5k_pci_suspend NULL
199 #define ath5k_pci_resume NULL
200 #endif /* CONFIG_PM */
202 static struct pci_driver ath5k_pci_driver = {
203 .name = KBUILD_MODNAME,
204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
214 * Prototypes - MAC 802.11 stack related functions
216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218 static int ath5k_reset_wake(struct ath5k_softc *sc);
219 static int ath5k_start(struct ieee80211_hw *hw);
220 static void ath5k_stop(struct ieee80211_hw *hw);
221 static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
226 static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
228 struct ieee80211_if_conf *conf);
229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233 static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
236 struct ieee80211_key_conf *key);
237 static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
243 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
244 static int ath5k_beacon_update(struct ath5k_softc *sc,
245 struct sk_buff *skb);
246 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
251 static struct ieee80211_ops ath5k_hw_ops = {
253 .start = ath5k_start,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
265 .set_tsf = ath5k_set_tsf,
266 .reset_tsf = ath5k_reset_tsf,
267 .bss_info_changed = ath5k_bss_info_changed,
271 * Prototypes - Internal functions
274 static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
284 static int ath5k_setup_bands(struct ieee80211_hw *hw);
285 static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287 static void ath5k_setcurmode(struct ath5k_softc *sc,
289 static void ath5k_mode_setup(struct ath5k_softc *sc);
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294 static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
297 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
300 struct ath5k_buf *bf);
301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
309 dev_kfree_skb_any(bf->skb);
313 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
321 dev_kfree_skb_any(bf->skb);
327 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330 static int ath5k_beaconq_config(struct ath5k_softc *sc);
331 static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334 static void ath5k_txq_release(struct ath5k_softc *sc);
336 static int ath5k_rx_start(struct ath5k_softc *sc);
337 static void ath5k_rx_stop(struct ath5k_softc *sc);
338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
341 struct ath5k_rx_status *rs);
342 static void ath5k_tasklet_rx(unsigned long data);
344 static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346 static void ath5k_tasklet_tx(unsigned long data);
347 /* Beacon handling */
348 static int ath5k_beacon_setup(struct ath5k_softc *sc,
349 struct ath5k_buf *bf);
350 static void ath5k_beacon_send(struct ath5k_softc *sc);
351 static void ath5k_beacon_config(struct ath5k_softc *sc);
352 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
354 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356 u64 tsf = ath5k_hw_get_tsf64(ah);
358 if ((tsf & 0x7fff) < rstamp)
361 return (tsf & ~0x7fff) | rstamp;
364 /* Interrupt handling */
365 static int ath5k_init(struct ath5k_softc *sc);
366 static int ath5k_stop_locked(struct ath5k_softc *sc);
367 static int ath5k_stop_hw(struct ath5k_softc *sc);
368 static irqreturn_t ath5k_intr(int irq, void *dev_id);
369 static void ath5k_tasklet_reset(unsigned long data);
371 static void ath5k_calibrate(unsigned long data);
373 static int ath5k_init_leds(struct ath5k_softc *sc);
374 static void ath5k_led_enable(struct ath5k_softc *sc);
375 static void ath5k_led_off(struct ath5k_softc *sc);
376 static void ath5k_unregister_leds(struct ath5k_softc *sc);
379 * Module init/exit functions
388 ret = pci_register_driver(&ath5k_pci_driver);
390 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
400 pci_unregister_driver(&ath5k_pci_driver);
402 ath5k_debug_finish();
405 module_init(init_ath5k_pci);
406 module_exit(exit_ath5k_pci);
409 /********************\
410 * PCI Initialization *
411 \********************/
414 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
416 const char *name = "xxxxx";
419 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
420 if (srev_names[i].sr_type != type)
423 if ((val & 0xf0) == srev_names[i].sr_val)
424 name = srev_names[i].sr_name;
426 if ((val & 0xff) == srev_names[i].sr_val) {
427 name = srev_names[i].sr_name;
436 ath5k_pci_probe(struct pci_dev *pdev,
437 const struct pci_device_id *id)
440 struct ath5k_softc *sc;
441 struct ieee80211_hw *hw;
445 ret = pci_enable_device(pdev);
447 dev_err(&pdev->dev, "can't enable device\n");
451 /* XXX 32-bit addressing only */
452 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
454 dev_err(&pdev->dev, "32-bit DMA not available\n");
459 * Cache line size is used to size and align various
460 * structures used to communicate with the hardware.
462 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
465 * Linux 2.4.18 (at least) writes the cache line size
466 * register as a 16-bit wide register which is wrong.
467 * We must have this setup properly for rx buffer
468 * DMA to work so force a reasonable value here if it
471 csz = L1_CACHE_BYTES / sizeof(u32);
472 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
475 * The default setting of latency timer yields poor results,
476 * set it to the value used by other systems. It may be worth
477 * tweaking this setting more.
479 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
481 /* Enable bus mastering */
482 pci_set_master(pdev);
485 * Disable the RETRY_TIMEOUT register (0x41) to keep
486 * PCI Tx retries from interfering with C3 CPU state.
488 pci_write_config_byte(pdev, 0x41, 0);
490 ret = pci_request_region(pdev, 0, "ath5k");
492 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
496 mem = pci_iomap(pdev, 0, 0);
498 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
504 * Allocate hw (mac80211 main struct)
505 * and hw->priv (driver private data)
507 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
509 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
514 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
516 /* Initialize driver private data */
517 SET_IEEE80211_DEV(hw, &pdev->dev);
518 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
519 IEEE80211_HW_SIGNAL_DBM |
520 IEEE80211_HW_NOISE_DBM;
522 hw->wiphy->interface_modes =
523 BIT(NL80211_IFTYPE_STATION) |
524 BIT(NL80211_IFTYPE_ADHOC) |
525 BIT(NL80211_IFTYPE_MESH_POINT);
527 hw->extra_tx_headroom = 2;
528 hw->channel_change_time = 5000;
533 ath5k_debug_init_device(sc);
536 * Mark the device as detached to avoid processing
537 * interrupts until setup is complete.
539 __set_bit(ATH_STAT_INVALID, sc->status);
541 sc->iobase = mem; /* So we can unmap it on detach */
542 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
543 sc->opmode = NL80211_IFTYPE_STATION;
544 mutex_init(&sc->lock);
545 spin_lock_init(&sc->rxbuflock);
546 spin_lock_init(&sc->txbuflock);
547 spin_lock_init(&sc->block);
549 /* Set private data */
550 pci_set_drvdata(pdev, hw);
552 /* Setup interrupt handler */
553 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
555 ATH5K_ERR(sc, "request_irq failed\n");
559 /* Initialize device */
560 sc->ah = ath5k_hw_attach(sc, id->driver_data);
561 if (IS_ERR(sc->ah)) {
562 ret = PTR_ERR(sc->ah);
566 /* set up multi-rate retry capabilities */
567 if (sc->ah->ah_version == AR5K_AR5212) {
569 hw->max_rate_tries = 11;
572 /* Finish private driver data initialization */
573 ret = ath5k_attach(pdev, hw);
577 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
578 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
580 sc->ah->ah_phy_revision);
582 if (!sc->ah->ah_single_chip) {
583 /* Single chip radio (!RF5111) */
584 if (sc->ah->ah_radio_5ghz_revision &&
585 !sc->ah->ah_radio_2ghz_revision) {
586 /* No 5GHz support -> report 2GHz radio */
587 if (!test_bit(AR5K_MODE_11A,
588 sc->ah->ah_capabilities.cap_mode)) {
589 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
593 /* No 2GHz support (5110 and some
594 * 5Ghz only cards) -> report 5Ghz radio */
595 } else if (!test_bit(AR5K_MODE_11B,
596 sc->ah->ah_capabilities.cap_mode)) {
597 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
598 ath5k_chip_name(AR5K_VERSION_RAD,
599 sc->ah->ah_radio_5ghz_revision),
600 sc->ah->ah_radio_5ghz_revision);
601 /* Multiband radio */
603 ATH5K_INFO(sc, "RF%s multiband radio found"
605 ath5k_chip_name(AR5K_VERSION_RAD,
606 sc->ah->ah_radio_5ghz_revision),
607 sc->ah->ah_radio_5ghz_revision);
610 /* Multi chip radio (RF5111 - RF2111) ->
611 * report both 2GHz/5GHz radios */
612 else if (sc->ah->ah_radio_5ghz_revision &&
613 sc->ah->ah_radio_2ghz_revision){
614 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_5ghz_revision),
617 sc->ah->ah_radio_5ghz_revision);
618 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
619 ath5k_chip_name(AR5K_VERSION_RAD,
620 sc->ah->ah_radio_2ghz_revision),
621 sc->ah->ah_radio_2ghz_revision);
626 /* ready to process interrupts */
627 __clear_bit(ATH_STAT_INVALID, sc->status);
631 ath5k_hw_detach(sc->ah);
633 free_irq(pdev->irq, sc);
635 ieee80211_free_hw(hw);
637 pci_iounmap(pdev, mem);
639 pci_release_region(pdev, 0);
641 pci_disable_device(pdev);
646 static void __devexit
647 ath5k_pci_remove(struct pci_dev *pdev)
649 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
650 struct ath5k_softc *sc = hw->priv;
652 ath5k_debug_finish_device(sc);
653 ath5k_detach(pdev, hw);
654 ath5k_hw_detach(sc->ah);
655 free_irq(pdev->irq, sc);
656 pci_iounmap(pdev, sc->iobase);
657 pci_release_region(pdev, 0);
658 pci_disable_device(pdev);
659 ieee80211_free_hw(hw);
664 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
666 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
667 struct ath5k_softc *sc = hw->priv;
671 free_irq(pdev->irq, sc);
672 pci_save_state(pdev);
673 pci_disable_device(pdev);
674 pci_set_power_state(pdev, PCI_D3hot);
680 ath5k_pci_resume(struct pci_dev *pdev)
682 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
683 struct ath5k_softc *sc = hw->priv;
686 pci_restore_state(pdev);
688 err = pci_enable_device(pdev);
693 * Suspend/Resume resets the PCI configuration space, so we have to
694 * re-disable the RETRY_TIMEOUT register (0x41) to keep
695 * PCI Tx retries from interfering with C3 CPU state
697 pci_write_config_byte(pdev, 0x41, 0);
699 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
701 ATH5K_ERR(sc, "request_irq failed\n");
705 ath5k_led_enable(sc);
709 pci_disable_device(pdev);
712 #endif /* CONFIG_PM */
715 /***********************\
716 * Driver Initialization *
717 \***********************/
720 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
722 struct ath5k_softc *sc = hw->priv;
723 struct ath5k_hw *ah = sc->ah;
724 u8 mac[ETH_ALEN] = {};
727 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
730 * Check if the MAC has multi-rate retry support.
731 * We do this by trying to setup a fake extended
732 * descriptor. MAC's that don't have support will
733 * return false w/o doing anything. MAC's that do
734 * support it will return true w/o doing anything.
736 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
740 __set_bit(ATH_STAT_MRRETRY, sc->status);
743 * Collect the channel list. The 802.11 layer
744 * is resposible for filtering this list based
745 * on settings like the phy mode and regulatory
746 * domain restrictions.
748 ret = ath5k_setup_bands(hw);
750 ATH5K_ERR(sc, "can't get channels\n");
754 /* NB: setup here so ath5k_rate_update is happy */
755 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
756 ath5k_setcurmode(sc, AR5K_MODE_11A);
758 ath5k_setcurmode(sc, AR5K_MODE_11B);
761 * Allocate tx+rx descriptors and populate the lists.
763 ret = ath5k_desc_alloc(sc, pdev);
765 ATH5K_ERR(sc, "can't allocate descriptors\n");
770 * Allocate hardware transmit queues: one queue for
771 * beacon frames and one data queue for each QoS
772 * priority. Note that hw functions handle reseting
773 * these queues at the needed time.
775 ret = ath5k_beaconq_setup(ah);
777 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
782 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
783 if (IS_ERR(sc->txq)) {
784 ATH5K_ERR(sc, "can't setup xmit queue\n");
785 ret = PTR_ERR(sc->txq);
789 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
790 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
791 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
792 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
794 ret = ath5k_eeprom_read_mac(ah, mac);
796 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
801 SET_IEEE80211_PERM_ADDR(hw, mac);
802 /* All MAC address bits matter for ACKs */
803 memset(sc->bssidmask, 0xff, ETH_ALEN);
804 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
806 ret = ieee80211_register_hw(hw);
808 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
816 ath5k_txq_release(sc);
818 ath5k_hw_release_tx_queue(ah, sc->bhalq);
820 ath5k_desc_free(sc, pdev);
826 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
828 struct ath5k_softc *sc = hw->priv;
831 * NB: the order of these is important:
832 * o call the 802.11 layer before detaching ath5k_hw to
833 * insure callbacks into the driver to delete global
834 * key cache entries can be handled
835 * o reclaim the tx queue data structures after calling
836 * the 802.11 layer as we'll get called back to reclaim
837 * node state and potentially want to use them
838 * o to cleanup the tx queues the hal is called, so detach
840 * XXX: ??? detach ath5k_hw ???
841 * Other than that, it's straightforward...
843 ieee80211_unregister_hw(hw);
844 ath5k_desc_free(sc, pdev);
845 ath5k_txq_release(sc);
846 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
847 ath5k_unregister_leds(sc);
850 * NB: can't reclaim these until after ieee80211_ifdetach
851 * returns because we'll get called back to reclaim node
852 * state and potentially want to use them.
859 /********************\
860 * Channel/mode setup *
861 \********************/
864 * Convert IEEE channel number to MHz frequency.
867 ath5k_ieee2mhz(short chan)
869 if (chan <= 14 || chan >= 27)
870 return ieee80211chan2mhz(chan);
872 return 2212 + chan * 20;
876 ath5k_copy_channels(struct ath5k_hw *ah,
877 struct ieee80211_channel *channels,
881 unsigned int i, count, size, chfreq, freq, ch;
883 if (!test_bit(mode, ah->ah_modes))
888 case AR5K_MODE_11A_TURBO:
889 /* 1..220, but 2GHz frequencies are filtered by check_channel */
891 chfreq = CHANNEL_5GHZ;
895 case AR5K_MODE_11G_TURBO:
897 chfreq = CHANNEL_2GHZ;
900 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
904 for (i = 0, count = 0; i < size && max > 0; i++) {
906 freq = ath5k_ieee2mhz(ch);
908 /* Check if channel is supported by the chipset */
909 if (!ath5k_channel_ok(ah, freq, chfreq))
912 /* Write channel info and increment counter */
913 channels[count].center_freq = freq;
914 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
915 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
919 channels[count].hw_value = chfreq | CHANNEL_OFDM;
921 case AR5K_MODE_11A_TURBO:
922 case AR5K_MODE_11G_TURBO:
923 channels[count].hw_value = chfreq |
924 CHANNEL_OFDM | CHANNEL_TURBO;
927 channels[count].hw_value = CHANNEL_B;
938 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
942 for (i = 0; i < AR5K_MAX_RATES; i++)
943 sc->rate_idx[b->band][i] = -1;
945 for (i = 0; i < b->n_bitrates; i++) {
946 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
947 if (b->bitrates[i].hw_value_short)
948 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
953 ath5k_setup_bands(struct ieee80211_hw *hw)
955 struct ath5k_softc *sc = hw->priv;
956 struct ath5k_hw *ah = sc->ah;
957 struct ieee80211_supported_band *sband;
958 int max_c, count_c = 0;
961 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
962 max_c = ARRAY_SIZE(sc->channels);
965 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
966 sband->band = IEEE80211_BAND_2GHZ;
967 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
969 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
971 memcpy(sband->bitrates, &ath5k_rates[0],
972 sizeof(struct ieee80211_rate) * 12);
973 sband->n_bitrates = 12;
975 sband->channels = sc->channels;
976 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
977 AR5K_MODE_11G, max_c);
979 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
980 count_c = sband->n_channels;
982 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
984 memcpy(sband->bitrates, &ath5k_rates[0],
985 sizeof(struct ieee80211_rate) * 4);
986 sband->n_bitrates = 4;
988 /* 5211 only supports B rates and uses 4bit rate codes
989 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
992 if (ah->ah_version == AR5K_AR5211) {
993 for (i = 0; i < 4; i++) {
994 sband->bitrates[i].hw_value =
995 sband->bitrates[i].hw_value & 0xF;
996 sband->bitrates[i].hw_value_short =
997 sband->bitrates[i].hw_value_short & 0xF;
1001 sband->channels = sc->channels;
1002 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1003 AR5K_MODE_11B, max_c);
1005 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1006 count_c = sband->n_channels;
1009 ath5k_setup_rate_idx(sc, sband);
1011 /* 5GHz band, A mode */
1012 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1013 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1014 sband->band = IEEE80211_BAND_5GHZ;
1015 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1017 memcpy(sband->bitrates, &ath5k_rates[4],
1018 sizeof(struct ieee80211_rate) * 8);
1019 sband->n_bitrates = 8;
1021 sband->channels = &sc->channels[count_c];
1022 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1023 AR5K_MODE_11A, max_c);
1025 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1027 ath5k_setup_rate_idx(sc, sband);
1029 ath5k_debug_dump_bands(sc);
1035 * Set/change channels. If the channel is really being changed,
1036 * it's done by reseting the chip. To accomplish this we must
1037 * first cleanup any pending DMA, then restart stuff after a la
1040 * Called with sc->lock.
1043 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1045 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1046 sc->curchan->center_freq, chan->center_freq);
1048 if (chan->center_freq != sc->curchan->center_freq ||
1049 chan->hw_value != sc->curchan->hw_value) {
1052 sc->curband = &sc->sbands[chan->band];
1055 * To switch channels clear any pending DMA operations;
1056 * wait long enough for the RX fifo to drain, reset the
1057 * hardware at the new frequency, and then re-enable
1058 * the relevant bits of the h/w.
1060 return ath5k_reset(sc, true, true);
1067 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1071 if (mode == AR5K_MODE_11A) {
1072 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1074 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1079 ath5k_mode_setup(struct ath5k_softc *sc)
1081 struct ath5k_hw *ah = sc->ah;
1084 /* configure rx filter */
1085 rfilt = sc->filter_flags;
1086 ath5k_hw_set_rx_filter(ah, rfilt);
1088 if (ath5k_hw_hasbssidmask(ah))
1089 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1091 /* configure operational mode */
1092 ath5k_hw_set_opmode(ah);
1094 ath5k_hw_set_mcast_filter(ah, 0, 0);
1095 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1099 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1101 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1102 return sc->rate_idx[sc->curband->band][hw_rix];
1110 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1112 struct sk_buff *skb;
1116 * Allocate buffer with headroom_needed space for the
1117 * fake physical layer header at the start.
1119 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1122 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1123 sc->rxbufsize + sc->cachelsz - 1);
1127 * Cache-line-align. This is important (for the
1128 * 5210 at least) as not doing so causes bogus data
1131 off = ((unsigned long)skb->data) % sc->cachelsz;
1133 skb_reserve(skb, sc->cachelsz - off);
1135 *skb_addr = pci_map_single(sc->pdev,
1136 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1137 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1138 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1146 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1148 struct ath5k_hw *ah = sc->ah;
1149 struct sk_buff *skb = bf->skb;
1150 struct ath5k_desc *ds;
1153 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1160 * Setup descriptors. For receive we always terminate
1161 * the descriptor list with a self-linked entry so we'll
1162 * not get overrun under high load (as can happen with a
1163 * 5212 when ANI processing enables PHY error frames).
1165 * To insure the last descriptor is self-linked we create
1166 * each descriptor as self-linked and add it to the end. As
1167 * each additional descriptor is added the previous self-linked
1168 * entry is ``fixed'' naturally. This should be safe even
1169 * if DMA is happening. When processing RX interrupts we
1170 * never remove/process the last, self-linked, entry on the
1171 * descriptor list. This insures the hardware always has
1172 * someplace to write a new frame.
1175 ds->ds_link = bf->daddr; /* link to self */
1176 ds->ds_data = bf->skbaddr;
1177 ah->ah_setup_rx_desc(ah, ds,
1178 skb_tailroom(skb), /* buffer size */
1181 if (sc->rxlink != NULL)
1182 *sc->rxlink = bf->daddr;
1183 sc->rxlink = &ds->ds_link;
1188 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1190 struct ath5k_hw *ah = sc->ah;
1191 struct ath5k_txq *txq = sc->txq;
1192 struct ath5k_desc *ds = bf->desc;
1193 struct sk_buff *skb = bf->skb;
1194 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1195 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1196 struct ieee80211_rate *rate;
1197 unsigned int mrr_rate[3], mrr_tries[3];
1204 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1206 /* XXX endianness */
1207 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1210 rate = ieee80211_get_tx_rate(sc->hw, info);
1212 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1213 flags |= AR5K_TXDESC_NOACK;
1215 rc_flags = info->control.rates[0].flags;
1216 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1217 rate->hw_value_short : rate->hw_value;
1221 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1222 flags |= AR5K_TXDESC_RTSENA;
1223 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1224 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1225 sc->vif, pktlen, info));
1227 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1228 flags |= AR5K_TXDESC_CTSENA;
1229 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1230 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1231 sc->vif, pktlen, info));
1234 if (info->control.hw_key) {
1235 keyidx = info->control.hw_key->hw_key_idx;
1236 pktlen += info->control.hw_key->icv_len;
1238 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1239 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1240 (sc->power_level * 2),
1242 info->control.rates[0].count, keyidx, 0, flags,
1243 cts_rate, duration);
1247 memset(mrr_rate, 0, sizeof(mrr_rate));
1248 memset(mrr_tries, 0, sizeof(mrr_tries));
1249 for (i = 0; i < 3; i++) {
1250 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1254 mrr_rate[i] = rate->hw_value;
1255 mrr_tries[i] = info->control.rates[i + 1].count;
1258 ah->ah_setup_mrr_tx_desc(ah, ds,
1259 mrr_rate[0], mrr_tries[0],
1260 mrr_rate[1], mrr_tries[1],
1261 mrr_rate[2], mrr_tries[2]);
1264 ds->ds_data = bf->skbaddr;
1266 spin_lock_bh(&txq->lock);
1267 list_add_tail(&bf->list, &txq->q);
1268 sc->tx_stats[txq->qnum].len++;
1269 if (txq->link == NULL) /* is this first packet? */
1270 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1271 else /* no, so only link it */
1272 *txq->link = bf->daddr;
1274 txq->link = &ds->ds_link;
1275 ath5k_hw_start_tx_dma(ah, txq->qnum);
1277 spin_unlock_bh(&txq->lock);
1281 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1285 /*******************\
1286 * Descriptors setup *
1287 \*******************/
1290 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1292 struct ath5k_desc *ds;
1293 struct ath5k_buf *bf;
1298 /* allocate descriptors */
1299 sc->desc_len = sizeof(struct ath5k_desc) *
1300 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1301 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1302 if (sc->desc == NULL) {
1303 ATH5K_ERR(sc, "can't allocate descriptors\n");
1308 da = sc->desc_daddr;
1309 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1310 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1312 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1313 sizeof(struct ath5k_buf), GFP_KERNEL);
1315 ATH5K_ERR(sc, "can't allocate bufptr\n");
1321 INIT_LIST_HEAD(&sc->rxbuf);
1322 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1325 list_add_tail(&bf->list, &sc->rxbuf);
1328 INIT_LIST_HEAD(&sc->txbuf);
1329 sc->txbuf_len = ATH_TXBUF;
1330 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1331 da += sizeof(*ds)) {
1334 list_add_tail(&bf->list, &sc->txbuf);
1344 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1351 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1353 struct ath5k_buf *bf;
1355 ath5k_txbuf_free(sc, sc->bbuf);
1356 list_for_each_entry(bf, &sc->txbuf, list)
1357 ath5k_txbuf_free(sc, bf);
1358 list_for_each_entry(bf, &sc->rxbuf, list)
1359 ath5k_rxbuf_free(sc, bf);
1361 /* Free memory associated with all descriptors */
1362 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1376 static struct ath5k_txq *
1377 ath5k_txq_setup(struct ath5k_softc *sc,
1378 int qtype, int subtype)
1380 struct ath5k_hw *ah = sc->ah;
1381 struct ath5k_txq *txq;
1382 struct ath5k_txq_info qi = {
1383 .tqi_subtype = subtype,
1384 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1385 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1386 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1391 * Enable interrupts only for EOL and DESC conditions.
1392 * We mark tx descriptors to receive a DESC interrupt
1393 * when a tx queue gets deep; otherwise waiting for the
1394 * EOL to reap descriptors. Note that this is done to
1395 * reduce interrupt load and this only defers reaping
1396 * descriptors, never transmitting frames. Aside from
1397 * reducing interrupts this also permits more concurrency.
1398 * The only potential downside is if the tx queue backs
1399 * up in which case the top half of the kernel may backup
1400 * due to a lack of tx descriptors.
1402 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1403 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1404 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1407 * NB: don't print a message, this happens
1408 * normally on parts with too few tx queues
1410 return ERR_PTR(qnum);
1412 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1413 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1414 qnum, ARRAY_SIZE(sc->txqs));
1415 ath5k_hw_release_tx_queue(ah, qnum);
1416 return ERR_PTR(-EINVAL);
1418 txq = &sc->txqs[qnum];
1422 INIT_LIST_HEAD(&txq->q);
1423 spin_lock_init(&txq->lock);
1426 return &sc->txqs[qnum];
1430 ath5k_beaconq_setup(struct ath5k_hw *ah)
1432 struct ath5k_txq_info qi = {
1433 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1434 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1435 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1436 /* NB: for dynamic turbo, don't enable any other interrupts */
1437 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1440 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1444 ath5k_beaconq_config(struct ath5k_softc *sc)
1446 struct ath5k_hw *ah = sc->ah;
1447 struct ath5k_txq_info qi;
1450 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1453 if (sc->opmode == NL80211_IFTYPE_AP ||
1454 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1456 * Always burst out beacon and CAB traffic
1457 * (aifs = cwmin = cwmax = 0)
1462 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1464 * Adhoc mode; backoff between 0 and (2 * cw_min).
1468 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1471 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1472 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1473 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1475 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1477 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1478 "hardware queue!\n", __func__);
1482 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1486 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1488 struct ath5k_buf *bf, *bf0;
1491 * NB: this assumes output has been stopped and
1492 * we do not need to block ath5k_tx_tasklet
1494 spin_lock_bh(&txq->lock);
1495 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1496 ath5k_debug_printtxbuf(sc, bf);
1498 ath5k_txbuf_free(sc, bf);
1500 spin_lock_bh(&sc->txbuflock);
1501 sc->tx_stats[txq->qnum].len--;
1502 list_move_tail(&bf->list, &sc->txbuf);
1504 spin_unlock_bh(&sc->txbuflock);
1507 spin_unlock_bh(&txq->lock);
1511 * Drain the transmit queues and reclaim resources.
1514 ath5k_txq_cleanup(struct ath5k_softc *sc)
1516 struct ath5k_hw *ah = sc->ah;
1519 /* XXX return value */
1520 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1521 /* don't touch the hardware if marked invalid */
1522 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1524 ath5k_hw_get_txdp(ah, sc->bhalq));
1525 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1526 if (sc->txqs[i].setup) {
1527 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1531 ath5k_hw_get_txdp(ah,
1536 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1538 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1539 if (sc->txqs[i].setup)
1540 ath5k_txq_drainq(sc, &sc->txqs[i]);
1544 ath5k_txq_release(struct ath5k_softc *sc)
1546 struct ath5k_txq *txq = sc->txqs;
1549 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1551 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1564 * Enable the receive h/w following a reset.
1567 ath5k_rx_start(struct ath5k_softc *sc)
1569 struct ath5k_hw *ah = sc->ah;
1570 struct ath5k_buf *bf;
1573 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1575 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1576 sc->cachelsz, sc->rxbufsize);
1580 spin_lock_bh(&sc->rxbuflock);
1581 list_for_each_entry(bf, &sc->rxbuf, list) {
1582 ret = ath5k_rxbuf_setup(sc, bf);
1584 spin_unlock_bh(&sc->rxbuflock);
1588 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1589 spin_unlock_bh(&sc->rxbuflock);
1591 ath5k_hw_set_rxdp(ah, bf->daddr);
1592 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1593 ath5k_mode_setup(sc); /* set filters, etc. */
1594 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1602 * Disable the receive h/w in preparation for a reset.
1605 ath5k_rx_stop(struct ath5k_softc *sc)
1607 struct ath5k_hw *ah = sc->ah;
1609 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1610 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1611 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1613 ath5k_debug_printrxbuffs(sc, ah);
1615 sc->rxlink = NULL; /* just in case */
1619 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1620 struct sk_buff *skb, struct ath5k_rx_status *rs)
1622 struct ieee80211_hdr *hdr = (void *)skb->data;
1623 unsigned int keyix, hlen;
1625 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1626 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1627 return RX_FLAG_DECRYPTED;
1629 /* Apparently when a default key is used to decrypt the packet
1630 the hw does not set the index used to decrypt. In such cases
1631 get the index from the packet. */
1632 hlen = ieee80211_hdrlen(hdr->frame_control);
1633 if (ieee80211_has_protected(hdr->frame_control) &&
1634 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1635 skb->len >= hlen + 4) {
1636 keyix = skb->data[hlen + 3] >> 6;
1638 if (test_bit(keyix, sc->keymap))
1639 return RX_FLAG_DECRYPTED;
1647 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1648 struct ieee80211_rx_status *rxs)
1652 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1654 if (ieee80211_is_beacon(mgmt->frame_control) &&
1655 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1656 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1658 * Received an IBSS beacon with the same BSSID. Hardware *must*
1659 * have updated the local TSF. We have to work around various
1660 * hardware bugs, though...
1662 tsf = ath5k_hw_get_tsf64(sc->ah);
1663 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1664 hw_tu = TSF_TO_TU(tsf);
1666 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1667 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1668 (unsigned long long)bc_tstamp,
1669 (unsigned long long)rxs->mactime,
1670 (unsigned long long)(rxs->mactime - bc_tstamp),
1671 (unsigned long long)tsf);
1674 * Sometimes the HW will give us a wrong tstamp in the rx
1675 * status, causing the timestamp extension to go wrong.
1676 * (This seems to happen especially with beacon frames bigger
1677 * than 78 byte (incl. FCS))
1678 * But we know that the receive timestamp must be later than the
1679 * timestamp of the beacon since HW must have synced to that.
1681 * NOTE: here we assume mactime to be after the frame was
1682 * received, not like mac80211 which defines it at the start.
1684 if (bc_tstamp > rxs->mactime) {
1685 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1686 "fixing mactime from %llx to %llx\n",
1687 (unsigned long long)rxs->mactime,
1688 (unsigned long long)tsf);
1693 * Local TSF might have moved higher than our beacon timers,
1694 * in that case we have to update them to continue sending
1695 * beacons. This also takes care of synchronizing beacon sending
1696 * times with other stations.
1698 if (hw_tu >= sc->nexttbtt)
1699 ath5k_beacon_update_timers(sc, bc_tstamp);
1705 ath5k_tasklet_rx(unsigned long data)
1707 struct ieee80211_rx_status rxs = {};
1708 struct ath5k_rx_status rs = {};
1709 struct sk_buff *skb, *next_skb;
1710 dma_addr_t next_skb_addr;
1711 struct ath5k_softc *sc = (void *)data;
1712 struct ath5k_buf *bf, *bf_last;
1713 struct ath5k_desc *ds;
1718 spin_lock(&sc->rxbuflock);
1719 if (list_empty(&sc->rxbuf)) {
1720 ATH5K_WARN(sc, "empty rx buf pool\n");
1723 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1727 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1728 BUG_ON(bf->skb == NULL);
1733 * last buffer must not be freed to ensure proper hardware
1734 * function. When the hardware finishes also a packet next to
1735 * it, we are sure, it doesn't use it anymore and we can go on.
1740 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1741 struct ath5k_buf, list);
1742 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1747 /* skip the overwritten one (even status is martian) */
1751 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1752 if (unlikely(ret == -EINPROGRESS))
1754 else if (unlikely(ret)) {
1755 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1756 spin_unlock(&sc->rxbuflock);
1760 if (unlikely(rs.rs_more)) {
1761 ATH5K_WARN(sc, "unsupported jumbo\n");
1765 if (unlikely(rs.rs_status)) {
1766 if (rs.rs_status & AR5K_RXERR_PHY)
1768 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1770 * Decrypt error. If the error occurred
1771 * because there was no hardware key, then
1772 * let the frame through so the upper layers
1773 * can process it. This is necessary for 5210
1774 * parts which have no way to setup a ``clear''
1777 * XXX do key cache faulting
1779 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1780 !(rs.rs_status & AR5K_RXERR_CRC))
1783 if (rs.rs_status & AR5K_RXERR_MIC) {
1784 rxs.flag |= RX_FLAG_MMIC_ERROR;
1788 /* let crypto-error packets fall through in MNTR */
1790 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1791 sc->opmode != NL80211_IFTYPE_MONITOR)
1795 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1798 * If we can't replace bf->skb with a new skb under memory
1799 * pressure, just skip this packet
1804 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1805 PCI_DMA_FROMDEVICE);
1806 skb_put(skb, rs.rs_datalen);
1808 /* The MAC header is padded to have 32-bit boundary if the
1809 * packet payload is non-zero. The general calculation for
1810 * padsize would take into account odd header lengths:
1811 * padsize = (4 - hdrlen % 4) % 4; However, since only
1812 * even-length headers are used, padding can only be 0 or 2
1813 * bytes and we can optimize this a bit. In addition, we must
1814 * not try to remove padding from short control frames that do
1815 * not have payload. */
1816 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1817 padsize = ath5k_pad_size(hdrlen);
1819 memmove(skb->data + padsize, skb->data, hdrlen);
1820 skb_pull(skb, padsize);
1824 * always extend the mac timestamp, since this information is
1825 * also needed for proper IBSS merging.
1827 * XXX: it might be too late to do it here, since rs_tstamp is
1828 * 15bit only. that means TSF extension has to be done within
1829 * 32768usec (about 32ms). it might be necessary to move this to
1830 * the interrupt handler, like it is done in madwifi.
1832 * Unfortunately we don't know when the hardware takes the rx
1833 * timestamp (beginning of phy frame, data frame, end of rx?).
1834 * The only thing we know is that it is hardware specific...
1835 * On AR5213 it seems the rx timestamp is at the end of the
1836 * frame, but i'm not sure.
1838 * NOTE: mac80211 defines mactime at the beginning of the first
1839 * data symbol. Since we don't have any time references it's
1840 * impossible to comply to that. This affects IBSS merge only
1841 * right now, so it's not too bad...
1843 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1844 rxs.flag |= RX_FLAG_TSFT;
1846 rxs.freq = sc->curchan->center_freq;
1847 rxs.band = sc->curband->band;
1849 rxs.noise = sc->ah->ah_noise_floor;
1850 rxs.signal = rxs.noise + rs.rs_rssi;
1852 /* An rssi of 35 indicates you should be able use
1853 * 54 Mbps reliably. A more elaborate scheme can be used
1854 * here but it requires a map of SNR/throughput for each
1855 * possible mode used */
1856 rxs.qual = rs.rs_rssi * 100 / 35;
1858 /* rssi can be more than 35 though, anything above that
1859 * should be considered at 100% */
1863 rxs.antenna = rs.rs_antenna;
1864 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1865 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1867 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1868 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1869 rxs.flag |= RX_FLAG_SHORTPRE;
1871 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1873 /* check beacons in IBSS mode */
1874 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1875 ath5k_check_ibss_tsf(sc, skb, &rxs);
1877 __ieee80211_rx(sc->hw, skb, &rxs);
1880 bf->skbaddr = next_skb_addr;
1882 list_move_tail(&bf->list, &sc->rxbuf);
1883 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1885 spin_unlock(&sc->rxbuflock);
1896 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1898 struct ath5k_tx_status ts = {};
1899 struct ath5k_buf *bf, *bf0;
1900 struct ath5k_desc *ds;
1901 struct sk_buff *skb;
1902 struct ieee80211_tx_info *info;
1905 spin_lock(&txq->lock);
1906 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1909 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1910 if (unlikely(ret == -EINPROGRESS))
1912 else if (unlikely(ret)) {
1913 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1919 info = IEEE80211_SKB_CB(skb);
1922 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1925 ieee80211_tx_info_clear_status(info);
1926 for (i = 0; i < 4; i++) {
1927 struct ieee80211_tx_rate *r =
1928 &info->status.rates[i];
1930 if (ts.ts_rate[i]) {
1931 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1932 r->count = ts.ts_retry[i];
1939 /* count the successful attempt as well */
1940 info->status.rates[ts.ts_final_idx].count++;
1942 if (unlikely(ts.ts_status)) {
1943 sc->ll_stats.dot11ACKFailureCount++;
1944 if (ts.ts_status & AR5K_TXERR_FILT)
1945 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1947 info->flags |= IEEE80211_TX_STAT_ACK;
1948 info->status.ack_signal = ts.ts_rssi;
1951 ieee80211_tx_status(sc->hw, skb);
1952 sc->tx_stats[txq->qnum].count++;
1954 spin_lock(&sc->txbuflock);
1955 sc->tx_stats[txq->qnum].len--;
1956 list_move_tail(&bf->list, &sc->txbuf);
1958 spin_unlock(&sc->txbuflock);
1960 if (likely(list_empty(&txq->q)))
1962 spin_unlock(&txq->lock);
1963 if (sc->txbuf_len > ATH_TXBUF / 5)
1964 ieee80211_wake_queues(sc->hw);
1968 ath5k_tasklet_tx(unsigned long data)
1970 struct ath5k_softc *sc = (void *)data;
1972 ath5k_tx_processq(sc, sc->txq);
1981 * Setup the beacon frame for transmit.
1984 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1986 struct sk_buff *skb = bf->skb;
1987 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1988 struct ath5k_hw *ah = sc->ah;
1989 struct ath5k_desc *ds;
1990 int ret, antenna = 0;
1993 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1995 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1996 "skbaddr %llx\n", skb, skb->data, skb->len,
1997 (unsigned long long)bf->skbaddr);
1998 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1999 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2005 flags = AR5K_TXDESC_NOACK;
2006 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2007 ds->ds_link = bf->daddr; /* self-linked */
2008 flags |= AR5K_TXDESC_VEOL;
2010 * Let hardware handle antenna switching if txantenna is not set
2015 * Switch antenna every 4 beacons if txantenna is not set
2016 * XXX assumes two antennas
2019 antenna = sc->bsent & 4 ? 2 : 1;
2022 ds->ds_data = bf->skbaddr;
2023 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2024 ieee80211_get_hdrlen_from_skb(skb),
2025 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2026 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2027 1, AR5K_TXKEYIX_INVALID,
2028 antenna, flags, 0, 0);
2034 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2039 * Transmit a beacon frame at SWBA. Dynamic updates to the
2040 * frame contents are done as needed and the slot time is
2041 * also adjusted based on current state.
2043 * this is usually called from interrupt context (ath5k_intr())
2044 * but also from ath5k_beacon_config() in IBSS mode which in turn
2045 * can be called from a tasklet and user context
2048 ath5k_beacon_send(struct ath5k_softc *sc)
2050 struct ath5k_buf *bf = sc->bbuf;
2051 struct ath5k_hw *ah = sc->ah;
2053 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2055 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2056 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2057 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2061 * Check if the previous beacon has gone out. If
2062 * not don't don't try to post another, skip this
2063 * period and wait for the next. Missed beacons
2064 * indicate a problem and should not occur. If we
2065 * miss too many consecutive beacons reset the device.
2067 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2069 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2070 "missed %u consecutive beacons\n", sc->bmisscount);
2071 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2072 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2073 "stuck beacon time (%u missed)\n",
2075 tasklet_schedule(&sc->restq);
2079 if (unlikely(sc->bmisscount != 0)) {
2080 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2081 "resume beacon xmit after %u misses\n",
2087 * Stop any current dma and put the new frame on the queue.
2088 * This should never fail since we check above that no frames
2089 * are still pending on the queue.
2091 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2092 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2093 /* NB: hw still stops DMA, so proceed */
2096 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2097 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2098 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2099 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2106 * ath5k_beacon_update_timers - update beacon timers
2108 * @sc: struct ath5k_softc pointer we are operating on
2109 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2110 * beacon timer update based on the current HW TSF.
2112 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2113 * of a received beacon or the current local hardware TSF and write it to the
2114 * beacon timer registers.
2116 * This is called in a variety of situations, e.g. when a beacon is received,
2117 * when a TSF update has been detected, but also when an new IBSS is created or
2118 * when we otherwise know we have to update the timers, but we keep it in this
2119 * function to have it all together in one place.
2122 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2124 struct ath5k_hw *ah = sc->ah;
2125 u32 nexttbtt, intval, hw_tu, bc_tu;
2128 intval = sc->bintval & AR5K_BEACON_PERIOD;
2129 if (WARN_ON(!intval))
2132 /* beacon TSF converted to TU */
2133 bc_tu = TSF_TO_TU(bc_tsf);
2135 /* current TSF converted to TU */
2136 hw_tsf = ath5k_hw_get_tsf64(ah);
2137 hw_tu = TSF_TO_TU(hw_tsf);
2140 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2143 * no beacons received, called internally.
2144 * just need to refresh timers based on HW TSF.
2146 nexttbtt = roundup(hw_tu + FUDGE, intval);
2147 } else if (bc_tsf == 0) {
2149 * no beacon received, probably called by ath5k_reset_tsf().
2150 * reset TSF to start with 0.
2153 intval |= AR5K_BEACON_RESET_TSF;
2154 } else if (bc_tsf > hw_tsf) {
2156 * beacon received, SW merge happend but HW TSF not yet updated.
2157 * not possible to reconfigure timers yet, but next time we
2158 * receive a beacon with the same BSSID, the hardware will
2159 * automatically update the TSF and then we need to reconfigure
2162 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2163 "need to wait for HW TSF sync\n");
2167 * most important case for beacon synchronization between STA.
2169 * beacon received and HW TSF has been already updated by HW.
2170 * update next TBTT based on the TSF of the beacon, but make
2171 * sure it is ahead of our local TSF timer.
2173 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2177 sc->nexttbtt = nexttbtt;
2179 intval |= AR5K_BEACON_ENA;
2180 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2183 * debugging output last in order to preserve the time critical aspect
2187 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2188 "reconfigured timers based on HW TSF\n");
2189 else if (bc_tsf == 0)
2190 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2191 "reset HW TSF and timers\n");
2193 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2194 "updated timers based on beacon TSF\n");
2196 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2197 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2198 (unsigned long long) bc_tsf,
2199 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2200 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2201 intval & AR5K_BEACON_PERIOD,
2202 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2203 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2208 * ath5k_beacon_config - Configure the beacon queues and interrupts
2210 * @sc: struct ath5k_softc pointer we are operating on
2212 * When operating in station mode we want to receive a BMISS interrupt when we
2213 * stop seeing beacons from the AP we've associated with so we can look for
2214 * another AP to associate with.
2216 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2217 * interrupts to detect TSF updates only.
2220 ath5k_beacon_config(struct ath5k_softc *sc)
2222 struct ath5k_hw *ah = sc->ah;
2224 ath5k_hw_set_imr(ah, 0);
2226 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2228 if (sc->opmode == NL80211_IFTYPE_STATION) {
2229 sc->imask |= AR5K_INT_BMISS;
2230 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2231 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2232 sc->opmode == NL80211_IFTYPE_AP) {
2234 * In IBSS mode we use a self-linked tx descriptor and let the
2235 * hardware send the beacons automatically. We have to load it
2237 * We use the SWBA interrupt only to keep track of the beacon
2238 * timers in order to detect automatic TSF updates.
2240 ath5k_beaconq_config(sc);
2242 sc->imask |= AR5K_INT_SWBA;
2244 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2245 if (ath5k_hw_hasveol(ah)) {
2246 spin_lock(&sc->block);
2247 ath5k_beacon_send(sc);
2248 spin_unlock(&sc->block);
2251 ath5k_beacon_update_timers(sc, -1);
2254 ath5k_hw_set_imr(ah, sc->imask);
2258 /********************\
2259 * Interrupt handling *
2260 \********************/
2263 ath5k_init(struct ath5k_softc *sc)
2265 struct ath5k_hw *ah = sc->ah;
2268 mutex_lock(&sc->lock);
2270 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2273 * Stop anything previously setup. This is safe
2274 * no matter this is the first time through or not.
2276 ath5k_stop_locked(sc);
2279 * The basic interface to setting the hardware in a good
2280 * state is ``reset''. On return the hardware is known to
2281 * be powered up and with interrupts disabled. This must
2282 * be followed by initialization of the appropriate bits
2283 * and then setup of the interrupt mask.
2285 sc->curchan = sc->hw->conf.channel;
2286 sc->curband = &sc->sbands[sc->curchan->band];
2287 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2288 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2289 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2290 ret = ath5k_reset(sc, false, false);
2295 * Reset the key cache since some parts do not reset the
2296 * contents on initial power up or resume from suspend.
2298 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2299 ath5k_hw_reset_key(ah, i);
2301 /* Set ack to be sent at low bit-rates */
2302 ath5k_hw_set_ack_bitrate_high(ah, false);
2304 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2305 msecs_to_jiffies(ath5k_calinterval * 1000)));
2310 mutex_unlock(&sc->lock);
2315 ath5k_stop_locked(struct ath5k_softc *sc)
2317 struct ath5k_hw *ah = sc->ah;
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2320 test_bit(ATH_STAT_INVALID, sc->status));
2323 * Shutdown the hardware and driver:
2324 * stop output from above
2325 * disable interrupts
2327 * turn off the radio
2328 * clear transmit machinery
2329 * clear receive machinery
2330 * drain and release tx queues
2331 * reclaim beacon resources
2332 * power down hardware
2334 * Note that some of this work is not possible if the
2335 * hardware is gone (invalid).
2337 ieee80211_stop_queues(sc->hw);
2339 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2341 ath5k_hw_set_imr(ah, 0);
2342 synchronize_irq(sc->pdev->irq);
2344 ath5k_txq_cleanup(sc);
2345 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2347 ath5k_hw_phy_disable(ah);
2355 * Stop the device, grabbing the top-level lock to protect
2356 * against concurrent entry through ath5k_init (which can happen
2357 * if another thread does a system call and the thread doing the
2358 * stop is preempted).
2361 ath5k_stop_hw(struct ath5k_softc *sc)
2365 mutex_lock(&sc->lock);
2366 ret = ath5k_stop_locked(sc);
2367 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2369 * Set the chip in full sleep mode. Note that we are
2370 * careful to do this only when bringing the interface
2371 * completely to a stop. When the chip is in this state
2372 * it must be carefully woken up or references to
2373 * registers in the PCI clock domain may freeze the bus
2374 * (and system). This varies by chip and is mostly an
2375 * issue with newer parts that go to sleep more quickly.
2377 if (sc->ah->ah_mac_srev >= 0x78) {
2380 * don't put newer MAC revisions > 7.8 to sleep because
2381 * of the above mentioned problems
2383 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2384 "not putting device to sleep\n");
2386 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2387 "putting device to full sleep\n");
2388 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2391 ath5k_txbuf_free(sc, sc->bbuf);
2394 mutex_unlock(&sc->lock);
2396 del_timer_sync(&sc->calib_tim);
2397 tasklet_kill(&sc->rxtq);
2398 tasklet_kill(&sc->txtq);
2399 tasklet_kill(&sc->restq);
2405 ath5k_intr(int irq, void *dev_id)
2407 struct ath5k_softc *sc = dev_id;
2408 struct ath5k_hw *ah = sc->ah;
2409 enum ath5k_int status;
2410 unsigned int counter = 1000;
2412 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2413 !ath5k_hw_is_intr_pending(ah)))
2418 * Figure out the reason(s) for the interrupt. Note
2419 * that get_isr returns a pseudo-ISR that may include
2420 * bits we haven't explicitly enabled so we mask the
2421 * value to insure we only process bits we requested.
2423 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2424 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2426 status &= sc->imask; /* discard unasked for bits */
2427 if (unlikely(status & AR5K_INT_FATAL)) {
2429 * Fatal errors are unrecoverable.
2430 * Typically these are caused by DMA errors.
2432 tasklet_schedule(&sc->restq);
2433 } else if (unlikely(status & AR5K_INT_RXORN)) {
2434 tasklet_schedule(&sc->restq);
2436 if (status & AR5K_INT_SWBA) {
2438 * Software beacon alert--time to send a beacon.
2439 * Handle beacon transmission directly; deferring
2440 * this is too slow to meet timing constraints
2443 * In IBSS mode we use this interrupt just to
2444 * keep track of the next TBTT (target beacon
2445 * transmission time) in order to detect wether
2446 * automatic TSF updates happened.
2448 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2449 /* XXX: only if VEOL suppported */
2450 u64 tsf = ath5k_hw_get_tsf64(ah);
2451 sc->nexttbtt += sc->bintval;
2452 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2453 "SWBA nexttbtt: %x hw_tu: %x "
2457 (unsigned long long) tsf);
2459 spin_lock(&sc->block);
2460 ath5k_beacon_send(sc);
2461 spin_unlock(&sc->block);
2464 if (status & AR5K_INT_RXEOL) {
2466 * NB: the hardware should re-read the link when
2467 * RXE bit is written, but it doesn't work at
2468 * least on older hardware revs.
2472 if (status & AR5K_INT_TXURN) {
2473 /* bump tx trigger level */
2474 ath5k_hw_update_tx_triglevel(ah, true);
2476 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2477 tasklet_schedule(&sc->rxtq);
2478 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2479 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2480 tasklet_schedule(&sc->txtq);
2481 if (status & AR5K_INT_BMISS) {
2483 if (status & AR5K_INT_MIB) {
2485 * These stats are also used for ANI i think
2486 * so how about updating them more often ?
2488 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2491 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2493 if (unlikely(!counter))
2494 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2500 ath5k_tasklet_reset(unsigned long data)
2502 struct ath5k_softc *sc = (void *)data;
2504 ath5k_reset_wake(sc);
2508 * Periodically recalibrate the PHY to account
2509 * for temperature/environment changes.
2512 ath5k_calibrate(unsigned long data)
2514 struct ath5k_softc *sc = (void *)data;
2515 struct ath5k_hw *ah = sc->ah;
2517 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2518 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2519 sc->curchan->hw_value);
2521 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2523 * Rfgain is out of bounds, reset the chip
2524 * to load new gain values.
2526 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2527 ath5k_reset_wake(sc);
2529 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2530 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2531 ieee80211_frequency_to_channel(
2532 sc->curchan->center_freq));
2534 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2535 msecs_to_jiffies(ath5k_calinterval * 1000)));
2545 ath5k_led_enable(struct ath5k_softc *sc)
2547 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2548 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2554 ath5k_led_on(struct ath5k_softc *sc)
2556 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2558 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2562 ath5k_led_off(struct ath5k_softc *sc)
2564 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2566 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2570 ath5k_led_brightness_set(struct led_classdev *led_dev,
2571 enum led_brightness brightness)
2573 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2576 if (brightness == LED_OFF)
2577 ath5k_led_off(led->sc);
2579 ath5k_led_on(led->sc);
2583 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2584 const char *name, char *trigger)
2589 strncpy(led->name, name, sizeof(led->name));
2590 led->led_dev.name = led->name;
2591 led->led_dev.default_trigger = trigger;
2592 led->led_dev.brightness_set = ath5k_led_brightness_set;
2594 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2596 ATH5K_WARN(sc, "could not register LED %s\n", name);
2603 ath5k_unregister_led(struct ath5k_led *led)
2607 led_classdev_unregister(&led->led_dev);
2608 ath5k_led_off(led->sc);
2613 ath5k_unregister_leds(struct ath5k_softc *sc)
2615 ath5k_unregister_led(&sc->rx_led);
2616 ath5k_unregister_led(&sc->tx_led);
2621 ath5k_init_leds(struct ath5k_softc *sc)
2624 struct ieee80211_hw *hw = sc->hw;
2625 struct pci_dev *pdev = sc->pdev;
2626 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2629 * Auto-enable soft led processing for IBM cards and for
2630 * 5211 minipci cards.
2632 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2633 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2634 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2636 sc->led_on = 0; /* active low */
2638 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2639 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2640 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2642 sc->led_on = 1; /* active high */
2645 * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2646 * in emachines notebooks with AMBIT subsystem.
2648 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2649 pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
2650 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2652 sc->led_on = 0; /* active low */
2655 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2658 ath5k_led_enable(sc);
2660 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2661 ret = ath5k_register_led(sc, &sc->rx_led, name,
2662 ieee80211_get_rx_led_name(hw));
2666 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2667 ret = ath5k_register_led(sc, &sc->tx_led, name,
2668 ieee80211_get_tx_led_name(hw));
2674 /********************\
2675 * Mac80211 functions *
2676 \********************/
2679 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2681 struct ath5k_softc *sc = hw->priv;
2682 struct ath5k_buf *bf;
2683 unsigned long flags;
2687 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2689 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2690 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2693 * the hardware expects the header padded to 4 byte boundaries
2694 * if this is not the case we add the padding after the header
2696 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2697 padsize = ath5k_pad_size(hdrlen);
2700 if (skb_headroom(skb) < padsize) {
2701 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2702 " headroom to pad %d\n", hdrlen, padsize);
2703 return NETDEV_TX_BUSY;
2705 skb_push(skb, padsize);
2706 memmove(skb->data, skb->data+padsize, hdrlen);
2709 spin_lock_irqsave(&sc->txbuflock, flags);
2710 if (list_empty(&sc->txbuf)) {
2711 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2712 spin_unlock_irqrestore(&sc->txbuflock, flags);
2713 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2714 return NETDEV_TX_BUSY;
2716 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2717 list_del(&bf->list);
2719 if (list_empty(&sc->txbuf))
2720 ieee80211_stop_queues(hw);
2721 spin_unlock_irqrestore(&sc->txbuflock, flags);
2725 if (ath5k_txbuf_setup(sc, bf)) {
2727 spin_lock_irqsave(&sc->txbuflock, flags);
2728 list_add_tail(&bf->list, &sc->txbuf);
2730 spin_unlock_irqrestore(&sc->txbuflock, flags);
2731 dev_kfree_skb_any(skb);
2732 return NETDEV_TX_OK;
2735 return NETDEV_TX_OK;
2739 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2741 struct ath5k_hw *ah = sc->ah;
2744 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2747 ath5k_hw_set_imr(ah, 0);
2748 ath5k_txq_cleanup(sc);
2751 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2753 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2758 * This is needed only to setup initial state
2759 * but it's best done after a reset.
2761 ath5k_hw_set_txpower_limit(sc->ah, 0);
2763 ret = ath5k_rx_start(sc);
2765 ATH5K_ERR(sc, "can't start recv logic\n");
2770 * Change channels and update the h/w rate map if we're switching;
2771 * e.g. 11a to 11b/g.
2773 * We may be doing a reset in response to an ioctl that changes the
2774 * channel so update any state that might change as a result.
2778 /* ath5k_chan_change(sc, c); */
2780 ath5k_beacon_config(sc);
2781 /* intrs are enabled by ath5k_beacon_config */
2789 ath5k_reset_wake(struct ath5k_softc *sc)
2793 ret = ath5k_reset(sc, true, true);
2795 ieee80211_wake_queues(sc->hw);
2800 static int ath5k_start(struct ieee80211_hw *hw)
2802 return ath5k_init(hw->priv);
2805 static void ath5k_stop(struct ieee80211_hw *hw)
2807 ath5k_stop_hw(hw->priv);
2810 static int ath5k_add_interface(struct ieee80211_hw *hw,
2811 struct ieee80211_if_init_conf *conf)
2813 struct ath5k_softc *sc = hw->priv;
2816 mutex_lock(&sc->lock);
2822 sc->vif = conf->vif;
2824 switch (conf->type) {
2825 case NL80211_IFTYPE_AP:
2826 case NL80211_IFTYPE_STATION:
2827 case NL80211_IFTYPE_ADHOC:
2828 case NL80211_IFTYPE_MESH_POINT:
2829 case NL80211_IFTYPE_MONITOR:
2830 sc->opmode = conf->type;
2837 /* Set to a reasonable value. Note that this will
2838 * be set to mac80211's value at ath5k_config(). */
2840 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2844 mutex_unlock(&sc->lock);
2849 ath5k_remove_interface(struct ieee80211_hw *hw,
2850 struct ieee80211_if_init_conf *conf)
2852 struct ath5k_softc *sc = hw->priv;
2853 u8 mac[ETH_ALEN] = {};
2855 mutex_lock(&sc->lock);
2856 if (sc->vif != conf->vif)
2859 ath5k_hw_set_lladdr(sc->ah, mac);
2862 mutex_unlock(&sc->lock);
2866 * TODO: Phy disable/diversity etc
2869 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2871 struct ath5k_softc *sc = hw->priv;
2872 struct ieee80211_conf *conf = &hw->conf;
2875 mutex_lock(&sc->lock);
2877 sc->bintval = conf->beacon_int;
2878 sc->power_level = conf->power_level;
2880 ret = ath5k_chan_set(sc, conf->channel);
2882 mutex_unlock(&sc->lock);
2887 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2888 struct ieee80211_if_conf *conf)
2890 struct ath5k_softc *sc = hw->priv;
2891 struct ath5k_hw *ah = sc->ah;
2894 mutex_lock(&sc->lock);
2895 if (sc->vif != vif) {
2899 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2900 /* Cache for later use during resets */
2901 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2902 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2903 * a clean way of letting us retrieve this yet. */
2904 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2907 if (conf->changed & IEEE80211_IFCC_BEACON &&
2908 (vif->type == NL80211_IFTYPE_ADHOC ||
2909 vif->type == NL80211_IFTYPE_MESH_POINT ||
2910 vif->type == NL80211_IFTYPE_AP)) {
2911 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2916 ath5k_beacon_update(sc, beacon);
2918 mutex_unlock(&sc->lock);
2920 return ath5k_reset_wake(sc);
2922 mutex_unlock(&sc->lock);
2926 #define SUPPORTED_FIF_FLAGS \
2927 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2928 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2929 FIF_BCN_PRBRESP_PROMISC
2931 * o always accept unicast, broadcast, and multicast traffic
2932 * o multicast traffic for all BSSIDs will be enabled if mac80211
2934 * o maintain current state of phy ofdm or phy cck error reception.
2935 * If the hardware detects any of these type of errors then
2936 * ath5k_hw_get_rx_filter() will pass to us the respective
2937 * hardware filters to be able to receive these type of frames.
2938 * o probe request frames are accepted only when operating in
2939 * hostap, adhoc, or monitor modes
2940 * o enable promiscuous mode according to the interface state
2942 * - when operating in adhoc mode so the 802.11 layer creates
2943 * node table entries for peers,
2944 * - when operating in station mode for collecting rssi data when
2945 * the station is otherwise quiet, or
2948 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2949 unsigned int changed_flags,
2950 unsigned int *new_flags,
2951 int mc_count, struct dev_mc_list *mclist)
2953 struct ath5k_softc *sc = hw->priv;
2954 struct ath5k_hw *ah = sc->ah;
2955 u32 mfilt[2], val, rfilt;
2962 /* Only deal with supported flags */
2963 changed_flags &= SUPPORTED_FIF_FLAGS;
2964 *new_flags &= SUPPORTED_FIF_FLAGS;
2966 /* If HW detects any phy or radar errors, leave those filters on.
2967 * Also, always enable Unicast, Broadcasts and Multicast
2968 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2969 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2970 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2971 AR5K_RX_FILTER_MCAST);
2973 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2974 if (*new_flags & FIF_PROMISC_IN_BSS) {
2975 rfilt |= AR5K_RX_FILTER_PROM;
2976 __set_bit(ATH_STAT_PROMISC, sc->status);
2978 __clear_bit(ATH_STAT_PROMISC, sc->status);
2982 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2983 if (*new_flags & FIF_ALLMULTI) {
2987 for (i = 0; i < mc_count; i++) {
2990 /* calculate XOR of eight 6-bit values */
2991 val = get_unaligned_le32(mclist->dmi_addr + 0);
2992 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2993 val = get_unaligned_le32(mclist->dmi_addr + 3);
2994 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2996 mfilt[pos / 32] |= (1 << (pos % 32));
2997 /* XXX: we might be able to just do this instead,
2998 * but not sure, needs testing, if we do use this we'd
2999 * neet to inform below to not reset the mcast */
3000 /* ath5k_hw_set_mcast_filterindex(ah,
3001 * mclist->dmi_addr[5]); */
3002 mclist = mclist->next;
3006 /* This is the best we can do */
3007 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3008 rfilt |= AR5K_RX_FILTER_PHYERR;
3010 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3011 * and probes for any BSSID, this needs testing */
3012 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3013 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3015 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3016 * set we should only pass on control frames for this
3017 * station. This needs testing. I believe right now this
3018 * enables *all* control frames, which is OK.. but
3019 * but we should see if we can improve on granularity */
3020 if (*new_flags & FIF_CONTROL)
3021 rfilt |= AR5K_RX_FILTER_CONTROL;
3023 /* Additional settings per mode -- this is per ath5k */
3025 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3027 if (sc->opmode == NL80211_IFTYPE_MONITOR)
3028 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3029 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3030 if (sc->opmode != NL80211_IFTYPE_STATION)
3031 rfilt |= AR5K_RX_FILTER_PROBEREQ;
3032 if (sc->opmode != NL80211_IFTYPE_AP &&
3033 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
3034 test_bit(ATH_STAT_PROMISC, sc->status))
3035 rfilt |= AR5K_RX_FILTER_PROM;
3036 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
3037 sc->opmode == NL80211_IFTYPE_ADHOC ||
3038 sc->opmode == NL80211_IFTYPE_AP)
3039 rfilt |= AR5K_RX_FILTER_BEACON;
3040 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3041 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3042 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3045 ath5k_hw_set_rx_filter(ah, rfilt);
3047 /* Set multicast bits */
3048 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3049 /* Set the cached hw filter flags, this will alter actually
3051 sc->filter_flags = rfilt;
3055 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3056 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3057 struct ieee80211_key_conf *key)
3059 struct ath5k_softc *sc = hw->priv;
3062 if (modparam_nohwcrypt)
3076 mutex_lock(&sc->lock);
3080 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3081 sta ? sta->addr : NULL);
3083 ATH5K_ERR(sc, "can't set the key\n");
3086 __set_bit(key->keyidx, sc->keymap);
3087 key->hw_key_idx = key->keyidx;
3088 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3089 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3092 ath5k_hw_reset_key(sc->ah, key->keyidx);
3093 __clear_bit(key->keyidx, sc->keymap);
3102 mutex_unlock(&sc->lock);
3107 ath5k_get_stats(struct ieee80211_hw *hw,
3108 struct ieee80211_low_level_stats *stats)
3110 struct ath5k_softc *sc = hw->priv;
3111 struct ath5k_hw *ah = sc->ah;
3114 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3116 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3122 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3123 struct ieee80211_tx_queue_stats *stats)
3125 struct ath5k_softc *sc = hw->priv;
3127 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3133 ath5k_get_tsf(struct ieee80211_hw *hw)
3135 struct ath5k_softc *sc = hw->priv;
3137 return ath5k_hw_get_tsf64(sc->ah);
3141 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3143 struct ath5k_softc *sc = hw->priv;
3145 ath5k_hw_set_tsf64(sc->ah, tsf);
3149 ath5k_reset_tsf(struct ieee80211_hw *hw)
3151 struct ath5k_softc *sc = hw->priv;
3154 * in IBSS mode we need to update the beacon timers too.
3155 * this will also reset the TSF if we call it with 0
3157 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3158 ath5k_beacon_update_timers(sc, 0);
3160 ath5k_hw_reset_tsf(sc->ah);
3164 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3166 unsigned long flags;
3169 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3171 spin_lock_irqsave(&sc->block, flags);
3172 ath5k_txbuf_free(sc, sc->bbuf);
3173 sc->bbuf->skb = skb;
3174 ret = ath5k_beacon_setup(sc, sc->bbuf);
3176 sc->bbuf->skb = NULL;
3177 spin_unlock_irqrestore(&sc->block, flags);
3179 ath5k_beacon_config(sc);
3186 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3188 struct ath5k_softc *sc = hw->priv;
3189 struct ath5k_hw *ah = sc->ah;
3191 rfilt = ath5k_hw_get_rx_filter(ah);
3193 rfilt |= AR5K_RX_FILTER_BEACON;
3195 rfilt &= ~AR5K_RX_FILTER_BEACON;
3196 ath5k_hw_set_rx_filter(ah, rfilt);
3197 sc->filter_flags = rfilt;
3200 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3201 struct ieee80211_vif *vif,
3202 struct ieee80211_bss_conf *bss_conf,
3205 struct ath5k_softc *sc = hw->priv;
3206 if (changes & BSS_CHANGED_ASSOC) {
3207 mutex_lock(&sc->lock);
3208 sc->assoc = bss_conf->assoc;
3209 if (sc->opmode == NL80211_IFTYPE_STATION)
3210 set_beacon_filter(hw, sc->assoc);
3211 mutex_unlock(&sc->lock);
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