git.oblomov.eu Git - linux-2.6/blob - drivers/pci/intel-iommu.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  * Author: Fenghua Yu <fenghua.yu@intel.com>
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/bitmap.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/slab.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/mempool.h>
  35 #include <linux/timer.h>
  36 #include <linux/iova.h>
  37 #include <linux/iommu.h>
  38 #include <linux/intel-iommu.h>
  39 #include <linux/sysdev.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/iommu.h>
  42 #include "pci.h"
  43
  44 #define ROOT_SIZE               VTD_PAGE_SIZE
  45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
  46
  47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
  48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
  49
  50 #define IOAPIC_RANGE_START      (0xfee00000)
  51 #define IOAPIC_RANGE_END        (0xfeefffff)
  52 #define IOVA_START_ADDR         (0x1000)
  53
  54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
  55
  56 #define MAX_AGAW_WIDTH 64
  57
  58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
  59
  60 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
  61 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
  62 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
  63
  64 #ifndef PHYSICAL_PAGE_MASK
  65 #define PHYSICAL_PAGE_MASK PAGE_MASK
  66 #endif
  67
  68 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
  69    are never going to work. */
  70 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
  71 {
  72         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
  73 }
  74
  75 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
  76 {
  77         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
  78 }
  79 static inline unsigned long page_to_dma_pfn(struct page *pg)
  80 {
  81         return mm_to_dma_pfn(page_to_pfn(pg));
  82 }
  83 static inline unsigned long virt_to_dma_pfn(void *p)
  84 {
  85         return page_to_dma_pfn(virt_to_page(p));
  86 }
  87
  88 /* global iommu list, set NULL for ignored DMAR units */
  89 static struct intel_iommu **g_iommus;
  90
  91 static int rwbf_quirk;
  92
  93 /*
  94  * 0: Present
  95  * 1-11: Reserved
  96  * 12-63: Context Ptr (12 - (haw-1))
  97  * 64-127: Reserved
  98  */
  99 struct root_entry {
 100         u64     val;
 101         u64     rsvd1;
 102 };
 103 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
 104 static inline bool root_present(struct root_entry *root)
 105 {
 106         return (root->val & 1);
 107 }
 108 static inline void set_root_present(struct root_entry *root)
 109 {
 110         root->val |= 1;
 111 }
 112 static inline void set_root_value(struct root_entry *root, unsigned long value)
 113 {
 114         root->val |= value & VTD_PAGE_MASK;
 115 }
 116
 117 static inline struct context_entry *
 118 get_context_addr_from_root(struct root_entry *root)
 119 {
 120         return (struct context_entry *)
 121                 (root_present(root)?phys_to_virt(
 122                 root->val & VTD_PAGE_MASK) :
 123                 NULL);
 124 }
 125
 126 /*
 127  * low 64 bits:
 128  * 0: present
 129  * 1: fault processing disable
 130  * 2-3: translation type
 131  * 12-63: address space root
 132  * high 64 bits:
 133  * 0-2: address width
 134  * 3-6: aval
 135  * 8-23: domain id
 136  */
 137 struct context_entry {
 138         u64 lo;
 139         u64 hi;
 140 };
 141
 142 static inline bool context_present(struct context_entry *context)
 143 {
 144         return (context->lo & 1);
 145 }
 146 static inline void context_set_present(struct context_entry *context)
 147 {
 148         context->lo |= 1;
 149 }
 150
 151 static inline void context_set_fault_enable(struct context_entry *context)
 152 {
 153         context->lo &= (((u64)-1) << 2) | 1;
 154 }
 155
 156 static inline void context_set_translation_type(struct context_entry *context,
 157                                                 unsigned long value)
 158 {
 159         context->lo &= (((u64)-1) << 4) | 3;
 160         context->lo |= (value & 3) << 2;
 161 }
 162
 163 static inline void context_set_address_root(struct context_entry *context,
 164                                             unsigned long value)
 165 {
 166         context->lo |= value & VTD_PAGE_MASK;
 167 }
 168
 169 static inline void context_set_address_width(struct context_entry *context,
 170                                              unsigned long value)
 171 {
 172         context->hi |= value & 7;
 173 }
 174
 175 static inline void context_set_domain_id(struct context_entry *context,
 176                                          unsigned long value)
 177 {
 178         context->hi |= (value & ((1 << 16) - 1)) << 8;
 179 }
 180
 181 static inline void context_clear_entry(struct context_entry *context)
 182 {
 183         context->lo = 0;
 184         context->hi = 0;
 185 }
 186
 187 /*
 188  * 0: readable
 189  * 1: writable
 190  * 2-6: reserved
 191  * 7: super page
 192  * 8-10: available
 193  * 11: snoop behavior
 194  * 12-63: Host physcial address
 195  */
 196 struct dma_pte {
 197         u64 val;
 198 };
 199
 200 static inline void dma_clear_pte(struct dma_pte *pte)
 201 {
 202         pte->val = 0;
 203 }
 204
 205 static inline void dma_set_pte_readable(struct dma_pte *pte)
 206 {
 207         pte->val |= DMA_PTE_READ;
 208 }
 209
 210 static inline void dma_set_pte_writable(struct dma_pte *pte)
 211 {
 212         pte->val |= DMA_PTE_WRITE;
 213 }
 214
 215 static inline void dma_set_pte_snp(struct dma_pte *pte)
 216 {
 217         pte->val |= DMA_PTE_SNP;
 218 }
 219
 220 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
 221 {
 222         pte->val = (pte->val & ~3) | (prot & 3);
 223 }
 224
 225 static inline u64 dma_pte_addr(struct dma_pte *pte)
 226 {
 227         return (pte->val & VTD_PAGE_MASK);
 228 }
 229
 230 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
 231 {
 232         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
 233 }
 234
 235 static inline bool dma_pte_present(struct dma_pte *pte)
 236 {
 237         return (pte->val & 3) != 0;
 238 }
 239
 240 /*
 241  * This domain is a statically identity mapping domain.
 242  *      1. This domain creats a static 1:1 mapping to all usable memory.
 243  *      2. It maps to each iommu if successful.
 244  *      3. Each iommu mapps to this domain if successful.
 245  */
 246 struct dmar_domain *si_domain;
 247
 248 /* devices under the same p2p bridge are owned in one domain */
 249 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
 250
 251 /* domain represents a virtual machine, more than one devices
 252  * across iommus may be owned in one domain, e.g. kvm guest.
 253  */
 254 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
 255
 256 /* si_domain contains mulitple devices */
 257 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
 258
 259 struct dmar_domain {
 260         int     id;                     /* domain id */
 261         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
 262
 263         struct list_head devices;       /* all devices' list */
 264         struct iova_domain iovad;       /* iova's that belong to this domain */
 265
 266         struct dma_pte  *pgd;           /* virtual address */
 267         spinlock_t      mapping_lock;   /* page table lock */
 268         int             gaw;            /* max guest address width */
 269
 270         /* adjusted guest address width, 0 is level 2 30-bit */
 271         int             agaw;
 272
 273         int             flags;          /* flags to find out type of domain */
 274
 275         int             iommu_coherency;/* indicate coherency of iommu access */
 276         int             iommu_snooping; /* indicate snooping control feature*/
 277         int             iommu_count;    /* reference count of iommu */
 278         spinlock_t      iommu_lock;     /* protect iommu set in domain */
 279         u64             max_addr;       /* maximum mapped address */
 280 };
 281
 282 /* PCI domain-device relationship */
 283 struct device_domain_info {
 284         struct list_head link;  /* link to domain siblings */
 285         struct list_head global; /* link to global list */
 286         int segment;            /* PCI domain */
 287         u8 bus;                 /* PCI bus number */
 288         u8 devfn;               /* PCI devfn number */
 289         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
 290         struct intel_iommu *iommu; /* IOMMU used by this device */
 291         struct dmar_domain *domain; /* pointer to domain */
 292 };
 293
 294 static void flush_unmaps_timeout(unsigned long data);
 295
 296 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
 297
 298 #define HIGH_WATER_MARK 250
 299 struct deferred_flush_tables {
 300         int next;
 301         struct iova *iova[HIGH_WATER_MARK];
 302         struct dmar_domain *domain[HIGH_WATER_MARK];
 303 };
 304
 305 static struct deferred_flush_tables *deferred_flush;
 306
 307 /* bitmap for indexing intel_iommus */
 308 static int g_num_of_iommus;
 309
 310 static DEFINE_SPINLOCK(async_umap_flush_lock);
 311 static LIST_HEAD(unmaps_to_do);
 312
 313 static int timer_on;
 314 static long list_size;
 315
 316 static void domain_remove_dev_info(struct dmar_domain *domain);
 317
 318 #ifdef CONFIG_DMAR_DEFAULT_ON
 319 int dmar_disabled = 0;
 320 #else
 321 int dmar_disabled = 1;
 322 #endif /*CONFIG_DMAR_DEFAULT_ON*/
 323
 324 static int __initdata dmar_map_gfx = 1;
 325 static int dmar_forcedac;
 326 static int intel_iommu_strict;
 327
 328 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
 329 static DEFINE_SPINLOCK(device_domain_lock);
 330 static LIST_HEAD(device_domain_list);
 331
 332 static struct iommu_ops intel_iommu_ops;
 333
 334 static int __init intel_iommu_setup(char *str)
 335 {
 336         if (!str)
 337                 return -EINVAL;
 338         while (*str) {
 339                 if (!strncmp(str, "on", 2)) {
 340                         dmar_disabled = 0;
 341                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
 342                 } else if (!strncmp(str, "off", 3)) {
 343                         dmar_disabled = 1;
 344                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
 345                 } else if (!strncmp(str, "igfx_off", 8)) {
 346                         dmar_map_gfx = 0;
 347                         printk(KERN_INFO
 348                                 "Intel-IOMMU: disable GFX device mapping\n");
 349                 } else if (!strncmp(str, "forcedac", 8)) {
 350                         printk(KERN_INFO
 351                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
 352                         dmar_forcedac = 1;
 353                 } else if (!strncmp(str, "strict", 6)) {
 354                         printk(KERN_INFO
 355                                 "Intel-IOMMU: disable batched IOTLB flush\n");
 356                         intel_iommu_strict = 1;
 357                 }
 358
 359                 str += strcspn(str, ",");
 360                 while (*str == ',')
 361                         str++;
 362         }
 363         return 0;
 364 }
 365 __setup("intel_iommu=", intel_iommu_setup);
 366
 367 static struct kmem_cache *iommu_domain_cache;
 368 static struct kmem_cache *iommu_devinfo_cache;
 369 static struct kmem_cache *iommu_iova_cache;
 370
 371 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
 372 {
 373         unsigned int flags;
 374         void *vaddr;
 375
 376         /* trying to avoid low memory issues */
 377         flags = current->flags & PF_MEMALLOC;
 378         current->flags |= PF_MEMALLOC;
 379         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
 380         current->flags &= (~PF_MEMALLOC | flags);
 381         return vaddr;
 382 }
 383
 384
 385 static inline void *alloc_pgtable_page(void)
 386 {
 387         unsigned int flags;
 388         void *vaddr;
 389
 390         /* trying to avoid low memory issues */
 391         flags = current->flags & PF_MEMALLOC;
 392         current->flags |= PF_MEMALLOC;
 393         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
 394         current->flags &= (~PF_MEMALLOC | flags);
 395         return vaddr;
 396 }
 397
 398 static inline void free_pgtable_page(void *vaddr)
 399 {
 400         free_page((unsigned long)vaddr);
 401 }
 402
 403 static inline void *alloc_domain_mem(void)
 404 {
 405         return iommu_kmem_cache_alloc(iommu_domain_cache);
 406 }
 407
 408 static void free_domain_mem(void *vaddr)
 409 {
 410         kmem_cache_free(iommu_domain_cache, vaddr);
 411 }
 412
 413 static inline void * alloc_devinfo_mem(void)
 414 {
 415         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
 416 }
 417
 418 static inline void free_devinfo_mem(void *vaddr)
 419 {
 420         kmem_cache_free(iommu_devinfo_cache, vaddr);
 421 }
 422
 423 struct iova *alloc_iova_mem(void)
 424 {
 425         return iommu_kmem_cache_alloc(iommu_iova_cache);
 426 }
 427
 428 void free_iova_mem(struct iova *iova)
 429 {
 430         kmem_cache_free(iommu_iova_cache, iova);
 431 }
 432
 433
 434 static inline int width_to_agaw(int width);
 435
 436 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
 437 {
 438         unsigned long sagaw;
 439         int agaw = -1;
 440
 441         sagaw = cap_sagaw(iommu->cap);
 442         for (agaw = width_to_agaw(max_gaw);
 443              agaw >= 0; agaw--) {
 444                 if (test_bit(agaw, &sagaw))
 445                         break;
 446         }
 447
 448         return agaw;
 449 }
 450
 451 /*
 452  * Calculate max SAGAW for each iommu.
 453  */
 454 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
 455 {
 456         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
 457 }
 458
 459 /*
 460  * calculate agaw for each iommu.
 461  * "SAGAW" may be different across iommus, use a default agaw, and
 462  * get a supported less agaw for iommus that don't support the default agaw.
 463  */
 464 int iommu_calculate_agaw(struct intel_iommu *iommu)
 465 {
 466         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
 467 }
 468
 469 /* This functionin only returns single iommu in a domain */
 470 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
 471 {
 472         int iommu_id;
 473
 474         /* si_domain and vm domain should not get here. */
 475         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
 476         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
 477
 478         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 479         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
 480                 return NULL;
 481
 482         return g_iommus[iommu_id];
 483 }
 484
 485 static void domain_update_iommu_coherency(struct dmar_domain *domain)
 486 {
 487         int i;
 488
 489         domain->iommu_coherency = 1;
 490
 491         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 492         for (; i < g_num_of_iommus; ) {
 493                 if (!ecap_coherent(g_iommus[i]->ecap)) {
 494                         domain->iommu_coherency = 0;
 495                         break;
 496                 }
 497                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 498         }
 499 }
 500
 501 static void domain_update_iommu_snooping(struct dmar_domain *domain)
 502 {
 503         int i;
 504
 505         domain->iommu_snooping = 1;
 506
 507         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 508         for (; i < g_num_of_iommus; ) {
 509                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
 510                         domain->iommu_snooping = 0;
 511                         break;
 512                 }
 513                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 514         }
 515 }
 516
 517 /* Some capabilities may be different across iommus */
 518 static void domain_update_iommu_cap(struct dmar_domain *domain)
 519 {
 520         domain_update_iommu_coherency(domain);
 521         domain_update_iommu_snooping(domain);
 522 }
 523
 524 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
 525 {
 526         struct dmar_drhd_unit *drhd = NULL;
 527         int i;
 528
 529         for_each_drhd_unit(drhd) {
 530                 if (drhd->ignored)
 531                         continue;
 532                 if (segment != drhd->segment)
 533                         continue;
 534
 535                 for (i = 0; i < drhd->devices_cnt; i++) {
 536                         if (drhd->devices[i] &&
 537                             drhd->devices[i]->bus->number == bus &&
 538                             drhd->devices[i]->devfn == devfn)
 539                                 return drhd->iommu;
 540                         if (drhd->devices[i] &&
 541                             drhd->devices[i]->subordinate &&
 542                             drhd->devices[i]->subordinate->number <= bus &&
 543                             drhd->devices[i]->subordinate->subordinate >= bus)
 544                                 return drhd->iommu;
 545                 }
 546
 547                 if (drhd->include_all)
 548                         return drhd->iommu;
 549         }
 550
 551         return NULL;
 552 }
 553
 554 static void domain_flush_cache(struct dmar_domain *domain,
 555                                void *addr, int size)
 556 {
 557         if (!domain->iommu_coherency)
 558                 clflush_cache_range(addr, size);
 559 }
 560
 561 /* Gets context entry for a given bus and devfn */
 562 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
 563                 u8 bus, u8 devfn)
 564 {
 565         struct root_entry *root;
 566         struct context_entry *context;
 567         unsigned long phy_addr;
 568         unsigned long flags;
 569
 570         spin_lock_irqsave(&iommu->lock, flags);
 571         root = &iommu->root_entry[bus];
 572         context = get_context_addr_from_root(root);
 573         if (!context) {
 574                 context = (struct context_entry *)alloc_pgtable_page();
 575                 if (!context) {
 576                         spin_unlock_irqrestore(&iommu->lock, flags);
 577                         return NULL;
 578                 }
 579                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
 580                 phy_addr = virt_to_phys((void *)context);
 581                 set_root_value(root, phy_addr);
 582                 set_root_present(root);
 583                 __iommu_flush_cache(iommu, root, sizeof(*root));
 584         }
 585         spin_unlock_irqrestore(&iommu->lock, flags);
 586         return &context[devfn];
 587 }
 588
 589 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
 590 {
 591         struct root_entry *root;
 592         struct context_entry *context;
 593         int ret;
 594         unsigned long flags;
 595
 596         spin_lock_irqsave(&iommu->lock, flags);
 597         root = &iommu->root_entry[bus];
 598         context = get_context_addr_from_root(root);
 599         if (!context) {
 600                 ret = 0;
 601                 goto out;
 602         }
 603         ret = context_present(&context[devfn]);
 604 out:
 605         spin_unlock_irqrestore(&iommu->lock, flags);
 606         return ret;
 607 }
 608
 609 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
 610 {
 611         struct root_entry *root;
 612         struct context_entry *context;
 613         unsigned long flags;
 614
 615         spin_lock_irqsave(&iommu->lock, flags);
 616         root = &iommu->root_entry[bus];
 617         context = get_context_addr_from_root(root);
 618         if (context) {
 619                 context_clear_entry(&context[devfn]);
 620                 __iommu_flush_cache(iommu, &context[devfn], \
 621                         sizeof(*context));
 622         }
 623         spin_unlock_irqrestore(&iommu->lock, flags);
 624 }
 625
 626 static void free_context_table(struct intel_iommu *iommu)
 627 {
 628         struct root_entry *root;
 629         int i;
 630         unsigned long flags;
 631         struct context_entry *context;
 632
 633         spin_lock_irqsave(&iommu->lock, flags);
 634         if (!iommu->root_entry) {
 635                 goto out;
 636         }
 637         for (i = 0; i < ROOT_ENTRY_NR; i++) {
 638                 root = &iommu->root_entry[i];
 639                 context = get_context_addr_from_root(root);
 640                 if (context)
 641                         free_pgtable_page(context);
 642         }
 643         free_pgtable_page(iommu->root_entry);
 644         iommu->root_entry = NULL;
 645 out:
 646         spin_unlock_irqrestore(&iommu->lock, flags);
 647 }
 648
 649 /* page table handling */
 650 #define LEVEL_STRIDE            (9)
 651 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
 652
 653 static inline int agaw_to_level(int agaw)
 654 {
 655         return agaw + 2;
 656 }
 657
 658 static inline int agaw_to_width(int agaw)
 659 {
 660         return 30 + agaw * LEVEL_STRIDE;
 661
 662 }
 663
 664 static inline int width_to_agaw(int width)
 665 {
 666         return (width - 30) / LEVEL_STRIDE;
 667 }
 668
 669 static inline unsigned int level_to_offset_bits(int level)
 670 {
 671         return (12 + (level - 1) * LEVEL_STRIDE);
 672 }
 673
 674 static inline int pfn_level_offset(unsigned long pfn, int level)
 675 {
 676         return (pfn >> (level_to_offset_bits(level) - 12)) & LEVEL_MASK;
 677 }
 678
 679 static inline u64 level_mask(int level)
 680 {
 681         return ((u64)-1 << level_to_offset_bits(level));
 682 }
 683
 684 static inline u64 level_size(int level)
 685 {
 686         return ((u64)1 << level_to_offset_bits(level));
 687 }
 688
 689 static inline u64 align_to_level(u64 addr, int level)
 690 {
 691         return ((addr + level_size(level) - 1) & level_mask(level));
 692 }
 693
 694 static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
 695 {
 696         int addr_width = agaw_to_width(domain->agaw);
 697         struct dma_pte *parent, *pte = NULL;
 698         int level = agaw_to_level(domain->agaw);
 699         int offset;
 700         unsigned long flags;
 701
 702         BUG_ON(!domain->pgd);
 703
 704         addr &= (((u64)1) << addr_width) - 1;
 705         parent = domain->pgd;
 706
 707         spin_lock_irqsave(&domain->mapping_lock, flags);
 708         while (level > 0) {
 709                 void *tmp_page;
 710
 711                 offset = pfn_level_offset(addr >> VTD_PAGE_SHIFT, level);
 712                 pte = &parent[offset];
 713                 if (level == 1)
 714                         break;
 715
 716                 if (!dma_pte_present(pte)) {
 717                         tmp_page = alloc_pgtable_page();
 718
 719                         if (!tmp_page) {
 720                                 spin_unlock_irqrestore(&domain->mapping_lock,
 721                                         flags);
 722                                 return NULL;
 723                         }
 724                         domain_flush_cache(domain, tmp_page, PAGE_SIZE);
 725                         dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page));
 726                         /*
 727                          * high level table always sets r/w, last level page
 728                          * table control read/write
 729                          */
 730                         dma_set_pte_readable(pte);
 731                         dma_set_pte_writable(pte);
 732                         domain_flush_cache(domain, pte, sizeof(*pte));
 733                 }
 734                 parent = phys_to_virt(dma_pte_addr(pte));
 735                 level--;
 736         }
 737
 738         spin_unlock_irqrestore(&domain->mapping_lock, flags);
 739         return pte;
 740 }
 741
 742 /* return address's pte at specific level */
 743 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
 744                                          unsigned long pfn,
 745                                          int level)
 746 {
 747         struct dma_pte *parent, *pte = NULL;
 748         int total = agaw_to_level(domain->agaw);
 749         int offset;
 750
 751         parent = domain->pgd;
 752         while (level <= total) {
 753                 offset = pfn_level_offset(pfn, total);
 754                 pte = &parent[offset];
 755                 if (level == total)
 756                         return pte;
 757
 758                 if (!dma_pte_present(pte))
 759                         break;
 760                 parent = phys_to_virt(dma_pte_addr(pte));
 761                 total--;
 762         }
 763         return NULL;
 764 }
 765
 766 /* clear one page's page table */
 767 static void dma_pte_clear_one(struct dmar_domain *domain, unsigned long pfn)
 768 {
 769         struct dma_pte *pte = NULL;
 770
 771         /* get last level pte */
 772         pte = dma_pfn_level_pte(domain, pfn, 1);
 773
 774         if (pte) {
 775                 dma_clear_pte(pte);
 776                 domain_flush_cache(domain, pte, sizeof(*pte));
 777         }
 778 }
 779
 780 /* clear last level pte, a tlb flush should be followed */
 781 static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
 782 {
 783         int addr_width = agaw_to_width(domain->agaw);
 784         int npages;
 785
 786         start &= (((u64)1) << addr_width) - 1;
 787         end &= (((u64)1) << addr_width) - 1;
 788         /* in case it's partial page */
 789         start &= PAGE_MASK;
 790         end = PAGE_ALIGN(end);
 791         npages = (end - start) / VTD_PAGE_SIZE;
 792
 793         /* we don't need lock here, nobody else touches the iova range */
 794         while (npages--) {
 795                 dma_pte_clear_one(domain, start >> VTD_PAGE_SHIFT);
 796                 start += VTD_PAGE_SIZE;
 797         }
 798 }
 799
 800 /* free page table pages. last level pte should already be cleared */
 801 static void dma_pte_free_pagetable(struct dmar_domain *domain,
 802         u64 start, u64 end)
 803 {
 804         int addr_width = agaw_to_width(domain->agaw);
 805         struct dma_pte *pte;
 806         int total = agaw_to_level(domain->agaw);
 807         int level;
 808         u64 tmp;
 809
 810         start &= (((u64)1) << addr_width) - 1;
 811         end &= (((u64)1) << addr_width) - 1;
 812
 813         /* we don't need lock here, nobody else touches the iova range */
 814         level = 2;
 815         while (level <= total) {
 816                 tmp = align_to_level(start, level);
 817                 if (tmp >= end || (tmp + level_size(level) > end))
 818                         return;
 819
 820                 while (tmp < end) {
 821                         pte = dma_pfn_level_pte(domain, tmp >> VTD_PAGE_SHIFT,
 822                                                 level);
 823                         if (pte) {
 824                                 free_pgtable_page(
 825                                         phys_to_virt(dma_pte_addr(pte)));
 826                                 dma_clear_pte(pte);
 827                                 domain_flush_cache(domain, pte, sizeof(*pte));
 828                         }
 829                         tmp += level_size(level);
 830                 }
 831                 level++;
 832         }
 833         /* free pgd */
 834         if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
 835                 free_pgtable_page(domain->pgd);
 836                 domain->pgd = NULL;
 837         }
 838 }
 839
 840 /* iommu handling */
 841 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
 842 {
 843         struct root_entry *root;
 844         unsigned long flags;
 845
 846         root = (struct root_entry *)alloc_pgtable_page();
 847         if (!root)
 848                 return -ENOMEM;
 849
 850         __iommu_flush_cache(iommu, root, ROOT_SIZE);
 851
 852         spin_lock_irqsave(&iommu->lock, flags);
 853         iommu->root_entry = root;
 854         spin_unlock_irqrestore(&iommu->lock, flags);
 855
 856         return 0;
 857 }
 858
 859 static void iommu_set_root_entry(struct intel_iommu *iommu)
 860 {
 861         void *addr;
 862         u32 sts;
 863         unsigned long flag;
 864
 865         addr = iommu->root_entry;
 866
 867         spin_lock_irqsave(&iommu->register_lock, flag);
 868         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 869
 870         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
 871
 872         /* Make sure hardware complete it */
 873         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 874                       readl, (sts & DMA_GSTS_RTPS), sts);
 875
 876         spin_unlock_irqrestore(&iommu->register_lock, flag);
 877 }
 878
 879 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
 880 {
 881         u32 val;
 882         unsigned long flag;
 883
 884         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
 885                 return;
 886
 887         spin_lock_irqsave(&iommu->register_lock, flag);
 888         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 889
 890         /* Make sure hardware complete it */
 891         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 892                       readl, (!(val & DMA_GSTS_WBFS)), val);
 893
 894         spin_unlock_irqrestore(&iommu->register_lock, flag);
 895 }
 896
 897 /* return value determine if we need a write buffer flush */
 898 static void __iommu_flush_context(struct intel_iommu *iommu,
 899                                   u16 did, u16 source_id, u8 function_mask,
 900                                   u64 type)
 901 {
 902         u64 val = 0;
 903         unsigned long flag;
 904
 905         switch (type) {
 906         case DMA_CCMD_GLOBAL_INVL:
 907                 val = DMA_CCMD_GLOBAL_INVL;
 908                 break;
 909         case DMA_CCMD_DOMAIN_INVL:
 910                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
 911                 break;
 912         case DMA_CCMD_DEVICE_INVL:
 913                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
 914                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
 915                 break;
 916         default:
 917                 BUG();
 918         }
 919         val |= DMA_CCMD_ICC;
 920
 921         spin_lock_irqsave(&iommu->register_lock, flag);
 922         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 923
 924         /* Make sure hardware complete it */
 925         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
 926                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 927
 928         spin_unlock_irqrestore(&iommu->register_lock, flag);
 929 }
 930
 931 /* return value determine if we need a write buffer flush */
 932 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
 933                                 u64 addr, unsigned int size_order, u64 type)
 934 {
 935         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
 936         u64 val = 0, val_iva = 0;
 937         unsigned long flag;
 938
 939         switch (type) {
 940         case DMA_TLB_GLOBAL_FLUSH:
 941                 /* global flush doesn't need set IVA_REG */
 942                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
 943                 break;
 944         case DMA_TLB_DSI_FLUSH:
 945                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 946                 break;
 947         case DMA_TLB_PSI_FLUSH:
 948                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 949                 /* Note: always flush non-leaf currently */
 950                 val_iva = size_order | addr;
 951                 break;
 952         default:
 953                 BUG();
 954         }
 955         /* Note: set drain read/write */
 956 #if 0
 957         /*
 958          * This is probably to be super secure.. Looks like we can
 959          * ignore it without any impact.
 960          */
 961         if (cap_read_drain(iommu->cap))
 962                 val |= DMA_TLB_READ_DRAIN;
 963 #endif
 964         if (cap_write_drain(iommu->cap))
 965                 val |= DMA_TLB_WRITE_DRAIN;
 966
 967         spin_lock_irqsave(&iommu->register_lock, flag);
 968         /* Note: Only uses first TLB reg currently */
 969         if (val_iva)
 970                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
 971         dmar_writeq(iommu->reg + tlb_offset + 8, val);
 972
 973         /* Make sure hardware complete it */
 974         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
 975                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
 976
 977         spin_unlock_irqrestore(&iommu->register_lock, flag);
 978
 979         /* check IOTLB invalidation granularity */
 980         if (DMA_TLB_IAIG(val) == 0)
 981                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
 982         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
 983                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
 984                         (unsigned long long)DMA_TLB_IIRG(type),
 985                         (unsigned long long)DMA_TLB_IAIG(val));
 986 }
 987
 988 static struct device_domain_info *iommu_support_dev_iotlb(
 989         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
 990 {
 991         int found = 0;
 992         unsigned long flags;
 993         struct device_domain_info *info;
 994         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
 995
 996         if (!ecap_dev_iotlb_support(iommu->ecap))
 997                 return NULL;
 998
 999         if (!iommu->qi)
1000                 return NULL;
1001
1002         spin_lock_irqsave(&device_domain_lock, flags);
1003         list_for_each_entry(info, &domain->devices, link)
1004                 if (info->bus == bus && info->devfn == devfn) {
1005                         found = 1;
1006                         break;
1007                 }
1008         spin_unlock_irqrestore(&device_domain_lock, flags);
1009
1010         if (!found || !info->dev)
1011                 return NULL;
1012
1013         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1014                 return NULL;
1015
1016         if (!dmar_find_matched_atsr_unit(info->dev))
1017                 return NULL;
1018
1019         info->iommu = iommu;
1020
1021         return info;
1022 }
1023
1024 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1025 {
1026         if (!info)
1027                 return;
1028
1029         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1030 }
1031
1032 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1033 {
1034         if (!info->dev || !pci_ats_enabled(info->dev))
1035                 return;
1036
1037         pci_disable_ats(info->dev);
1038 }
1039
1040 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1041                                   u64 addr, unsigned mask)
1042 {
1043         u16 sid, qdep;
1044         unsigned long flags;
1045         struct device_domain_info *info;
1046
1047         spin_lock_irqsave(&device_domain_lock, flags);
1048         list_for_each_entry(info, &domain->devices, link) {
1049                 if (!info->dev || !pci_ats_enabled(info->dev))
1050                         continue;
1051
1052                 sid = info->bus << 8 | info->devfn;
1053                 qdep = pci_ats_queue_depth(info->dev);
1054                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1055         }
1056         spin_unlock_irqrestore(&device_domain_lock, flags);
1057 }
1058
1059 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1060                                   u64 addr, unsigned int pages)
1061 {
1062         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1063
1064         BUG_ON(addr & (~VTD_PAGE_MASK));
1065         BUG_ON(pages == 0);
1066
1067         /*
1068          * Fallback to domain selective flush if no PSI support or the size is
1069          * too big.
1070          * PSI requires page size to be 2 ^ x, and the base address is naturally
1071          * aligned to the size
1072          */
1073         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1074                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1075                                                 DMA_TLB_DSI_FLUSH);
1076         else
1077                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1078                                                 DMA_TLB_PSI_FLUSH);
1079
1080         /*
1081          * In caching mode, domain ID 0 is reserved for non-present to present
1082          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1083          */
1084         if (!cap_caching_mode(iommu->cap) || did)
1085                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1086 }
1087
1088 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1089 {
1090         u32 pmen;
1091         unsigned long flags;
1092
1093         spin_lock_irqsave(&iommu->register_lock, flags);
1094         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1095         pmen &= ~DMA_PMEN_EPM;
1096         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1097
1098         /* wait for the protected region status bit to clear */
1099         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1100                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1101
1102         spin_unlock_irqrestore(&iommu->register_lock, flags);
1103 }
1104
1105 static int iommu_enable_translation(struct intel_iommu *iommu)
1106 {
1107         u32 sts;
1108         unsigned long flags;
1109
1110         spin_lock_irqsave(&iommu->register_lock, flags);
1111         iommu->gcmd |= DMA_GCMD_TE;
1112         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1113
1114         /* Make sure hardware complete it */
1115         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1116                       readl, (sts & DMA_GSTS_TES), sts);
1117
1118         spin_unlock_irqrestore(&iommu->register_lock, flags);
1119         return 0;
1120 }
1121
1122 static int iommu_disable_translation(struct intel_iommu *iommu)
1123 {
1124         u32 sts;
1125         unsigned long flag;
1126
1127         spin_lock_irqsave(&iommu->register_lock, flag);
1128         iommu->gcmd &= ~DMA_GCMD_TE;
1129         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1130
1131         /* Make sure hardware complete it */
1132         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1133                       readl, (!(sts & DMA_GSTS_TES)), sts);
1134
1135         spin_unlock_irqrestore(&iommu->register_lock, flag);
1136         return 0;
1137 }
1138
1139
1140 static int iommu_init_domains(struct intel_iommu *iommu)
1141 {
1142         unsigned long ndomains;
1143         unsigned long nlongs;
1144
1145         ndomains = cap_ndoms(iommu->cap);
1146         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1147         nlongs = BITS_TO_LONGS(ndomains);
1148
1149         /* TBD: there might be 64K domains,
1150          * consider other allocation for future chip
1151          */
1152         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1153         if (!iommu->domain_ids) {
1154                 printk(KERN_ERR "Allocating domain id array failed\n");
1155                 return -ENOMEM;
1156         }
1157         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1158                         GFP_KERNEL);
1159         if (!iommu->domains) {
1160                 printk(KERN_ERR "Allocating domain array failed\n");
1161                 kfree(iommu->domain_ids);
1162                 return -ENOMEM;
1163         }
1164
1165         spin_lock_init(&iommu->lock);
1166
1167         /*
1168          * if Caching mode is set, then invalid translations are tagged
1169          * with domainid 0. Hence we need to pre-allocate it.
1170          */
1171         if (cap_caching_mode(iommu->cap))
1172                 set_bit(0, iommu->domain_ids);
1173         return 0;
1174 }
1175
1176
1177 static void domain_exit(struct dmar_domain *domain);
1178 static void vm_domain_exit(struct dmar_domain *domain);
1179
1180 void free_dmar_iommu(struct intel_iommu *iommu)
1181 {
1182         struct dmar_domain *domain;
1183         int i;
1184         unsigned long flags;
1185
1186         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1187         for (; i < cap_ndoms(iommu->cap); ) {
1188                 domain = iommu->domains[i];
1189                 clear_bit(i, iommu->domain_ids);
1190
1191                 spin_lock_irqsave(&domain->iommu_lock, flags);
1192                 if (--domain->iommu_count == 0) {
1193                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1194                                 vm_domain_exit(domain);
1195                         else
1196                                 domain_exit(domain);
1197                 }
1198                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1199
1200                 i = find_next_bit(iommu->domain_ids,
1201                         cap_ndoms(iommu->cap), i+1);
1202         }
1203
1204         if (iommu->gcmd & DMA_GCMD_TE)
1205                 iommu_disable_translation(iommu);
1206
1207         if (iommu->irq) {
1208                 set_irq_data(iommu->irq, NULL);
1209                 /* This will mask the irq */
1210                 free_irq(iommu->irq, iommu);
1211                 destroy_irq(iommu->irq);
1212         }
1213
1214         kfree(iommu->domains);
1215         kfree(iommu->domain_ids);
1216
1217         g_iommus[iommu->seq_id] = NULL;
1218
1219         /* if all iommus are freed, free g_iommus */
1220         for (i = 0; i < g_num_of_iommus; i++) {
1221                 if (g_iommus[i])
1222                         break;
1223         }
1224
1225         if (i == g_num_of_iommus)
1226                 kfree(g_iommus);
1227
1228         /* free context mapping */
1229         free_context_table(iommu);
1230 }
1231
1232 static struct dmar_domain *alloc_domain(void)
1233 {
1234         struct dmar_domain *domain;
1235
1236         domain = alloc_domain_mem();
1237         if (!domain)
1238                 return NULL;
1239
1240         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1241         domain->flags = 0;
1242
1243         return domain;
1244 }
1245
1246 static int iommu_attach_domain(struct dmar_domain *domain,
1247                                struct intel_iommu *iommu)
1248 {
1249         int num;
1250         unsigned long ndomains;
1251         unsigned long flags;
1252
1253         ndomains = cap_ndoms(iommu->cap);
1254
1255         spin_lock_irqsave(&iommu->lock, flags);
1256
1257         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1258         if (num >= ndomains) {
1259                 spin_unlock_irqrestore(&iommu->lock, flags);
1260                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1261                 return -ENOMEM;
1262         }
1263
1264         domain->id = num;
1265         set_bit(num, iommu->domain_ids);
1266         set_bit(iommu->seq_id, &domain->iommu_bmp);
1267         iommu->domains[num] = domain;
1268         spin_unlock_irqrestore(&iommu->lock, flags);
1269
1270         return 0;
1271 }
1272
1273 static void iommu_detach_domain(struct dmar_domain *domain,
1274                                 struct intel_iommu *iommu)
1275 {
1276         unsigned long flags;
1277         int num, ndomains;
1278         int found = 0;
1279
1280         spin_lock_irqsave(&iommu->lock, flags);
1281         ndomains = cap_ndoms(iommu->cap);
1282         num = find_first_bit(iommu->domain_ids, ndomains);
1283         for (; num < ndomains; ) {
1284                 if (iommu->domains[num] == domain) {
1285                         found = 1;
1286                         break;
1287                 }
1288                 num = find_next_bit(iommu->domain_ids,
1289                                     cap_ndoms(iommu->cap), num+1);
1290         }
1291
1292         if (found) {
1293                 clear_bit(num, iommu->domain_ids);
1294                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1295                 iommu->domains[num] = NULL;
1296         }
1297         spin_unlock_irqrestore(&iommu->lock, flags);
1298 }
1299
1300 static struct iova_domain reserved_iova_list;
1301 static struct lock_class_key reserved_alloc_key;
1302 static struct lock_class_key reserved_rbtree_key;
1303
1304 static void dmar_init_reserved_ranges(void)
1305 {
1306         struct pci_dev *pdev = NULL;
1307         struct iova *iova;
1308         int i;
1309         u64 addr, size;
1310
1311         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1312
1313         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1314                 &reserved_alloc_key);
1315         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1316                 &reserved_rbtree_key);
1317
1318         /* IOAPIC ranges shouldn't be accessed by DMA */
1319         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1320                 IOVA_PFN(IOAPIC_RANGE_END));
1321         if (!iova)
1322                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1323
1324         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1325         for_each_pci_dev(pdev) {
1326                 struct resource *r;
1327
1328                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1329                         r = &pdev->resource[i];
1330                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1331                                 continue;
1332                         addr = r->start;
1333                         addr &= PHYSICAL_PAGE_MASK;
1334                         size = r->end - addr;
1335                         size = PAGE_ALIGN(size);
1336                         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1337                                 IOVA_PFN(size + addr) - 1);
1338                         if (!iova)
1339                                 printk(KERN_ERR "Reserve iova failed\n");
1340                 }
1341         }
1342
1343 }
1344
1345 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1346 {
1347         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1348 }
1349
1350 static inline int guestwidth_to_adjustwidth(int gaw)
1351 {
1352         int agaw;
1353         int r = (gaw - 12) % 9;
1354
1355         if (r == 0)
1356                 agaw = gaw;
1357         else
1358                 agaw = gaw + 9 - r;
1359         if (agaw > 64)
1360                 agaw = 64;
1361         return agaw;
1362 }
1363
1364 static int domain_init(struct dmar_domain *domain, int guest_width)
1365 {
1366         struct intel_iommu *iommu;
1367         int adjust_width, agaw;
1368         unsigned long sagaw;
1369
1370         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1371         spin_lock_init(&domain->mapping_lock);
1372         spin_lock_init(&domain->iommu_lock);
1373
1374         domain_reserve_special_ranges(domain);
1375
1376         /* calculate AGAW */
1377         iommu = domain_get_iommu(domain);
1378         if (guest_width > cap_mgaw(iommu->cap))
1379                 guest_width = cap_mgaw(iommu->cap);
1380         domain->gaw = guest_width;
1381         adjust_width = guestwidth_to_adjustwidth(guest_width);
1382         agaw = width_to_agaw(adjust_width);
1383         sagaw = cap_sagaw(iommu->cap);
1384         if (!test_bit(agaw, &sagaw)) {
1385                 /* hardware doesn't support it, choose a bigger one */
1386                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1387                 agaw = find_next_bit(&sagaw, 5, agaw);
1388                 if (agaw >= 5)
1389                         return -ENODEV;
1390         }
1391         domain->agaw = agaw;
1392         INIT_LIST_HEAD(&domain->devices);
1393
1394         if (ecap_coherent(iommu->ecap))
1395                 domain->iommu_coherency = 1;
1396         else
1397                 domain->iommu_coherency = 0;
1398
1399         if (ecap_sc_support(iommu->ecap))
1400                 domain->iommu_snooping = 1;
1401         else
1402                 domain->iommu_snooping = 0;
1403
1404         domain->iommu_count = 1;
1405
1406         /* always allocate the top pgd */
1407         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1408         if (!domain->pgd)
1409                 return -ENOMEM;
1410         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1411         return 0;
1412 }
1413
1414 static void domain_exit(struct dmar_domain *domain)
1415 {
1416         struct dmar_drhd_unit *drhd;
1417         struct intel_iommu *iommu;
1418         u64 end;
1419
1420         /* Domain 0 is reserved, so dont process it */
1421         if (!domain)
1422                 return;
1423
1424         domain_remove_dev_info(domain);
1425         /* destroy iovas */
1426         put_iova_domain(&domain->iovad);
1427         end = DOMAIN_MAX_ADDR(domain->gaw);
1428         end = end & (~PAGE_MASK);
1429
1430         /* clear ptes */
1431         dma_pte_clear_range(domain, 0, end);
1432
1433         /* free page tables */
1434         dma_pte_free_pagetable(domain, 0, end);
1435
1436         for_each_active_iommu(iommu, drhd)
1437                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1438                         iommu_detach_domain(domain, iommu);
1439
1440         free_domain_mem(domain);
1441 }
1442
1443 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1444                                  u8 bus, u8 devfn, int translation)
1445 {
1446         struct context_entry *context;
1447         unsigned long flags;
1448         struct intel_iommu *iommu;
1449         struct dma_pte *pgd;
1450         unsigned long num;
1451         unsigned long ndomains;
1452         int id;
1453         int agaw;
1454         struct device_domain_info *info = NULL;
1455
1456         pr_debug("Set context mapping for %02x:%02x.%d\n",
1457                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1458
1459         BUG_ON(!domain->pgd);
1460         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1461                translation != CONTEXT_TT_MULTI_LEVEL);
1462
1463         iommu = device_to_iommu(segment, bus, devfn);
1464         if (!iommu)
1465                 return -ENODEV;
1466
1467         context = device_to_context_entry(iommu, bus, devfn);
1468         if (!context)
1469                 return -ENOMEM;
1470         spin_lock_irqsave(&iommu->lock, flags);
1471         if (context_present(context)) {
1472                 spin_unlock_irqrestore(&iommu->lock, flags);
1473                 return 0;
1474         }
1475
1476         id = domain->id;
1477         pgd = domain->pgd;
1478
1479         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1480             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1481                 int found = 0;
1482
1483                 /* find an available domain id for this device in iommu */
1484                 ndomains = cap_ndoms(iommu->cap);
1485                 num = find_first_bit(iommu->domain_ids, ndomains);
1486                 for (; num < ndomains; ) {
1487                         if (iommu->domains[num] == domain) {
1488                                 id = num;
1489                                 found = 1;
1490                                 break;
1491                         }
1492                         num = find_next_bit(iommu->domain_ids,
1493                                             cap_ndoms(iommu->cap), num+1);
1494                 }
1495
1496                 if (found == 0) {
1497                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1498                         if (num >= ndomains) {
1499                                 spin_unlock_irqrestore(&iommu->lock, flags);
1500                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1501                                 return -EFAULT;
1502                         }
1503
1504                         set_bit(num, iommu->domain_ids);
1505                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1506                         iommu->domains[num] = domain;
1507                         id = num;
1508                 }
1509
1510                 /* Skip top levels of page tables for
1511                  * iommu which has less agaw than default.
1512                  */
1513                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1514                         pgd = phys_to_virt(dma_pte_addr(pgd));
1515                         if (!dma_pte_present(pgd)) {
1516                                 spin_unlock_irqrestore(&iommu->lock, flags);
1517                                 return -ENOMEM;
1518                         }
1519                 }
1520         }
1521
1522         context_set_domain_id(context, id);
1523
1524         if (translation != CONTEXT_TT_PASS_THROUGH) {
1525                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1526                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1527                                      CONTEXT_TT_MULTI_LEVEL;
1528         }
1529         /*
1530          * In pass through mode, AW must be programmed to indicate the largest
1531          * AGAW value supported by hardware. And ASR is ignored by hardware.
1532          */
1533         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1534                 context_set_address_width(context, iommu->msagaw);
1535         else {
1536                 context_set_address_root(context, virt_to_phys(pgd));
1537                 context_set_address_width(context, iommu->agaw);
1538         }
1539
1540         context_set_translation_type(context, translation);
1541         context_set_fault_enable(context);
1542         context_set_present(context);
1543         domain_flush_cache(domain, context, sizeof(*context));
1544
1545         /*
1546          * It's a non-present to present mapping. If hardware doesn't cache
1547          * non-present entry we only need to flush the write-buffer. If the
1548          * _does_ cache non-present entries, then it does so in the special
1549          * domain #0, which we have to flush:
1550          */
1551         if (cap_caching_mode(iommu->cap)) {
1552                 iommu->flush.flush_context(iommu, 0,
1553                                            (((u16)bus) << 8) | devfn,
1554                                            DMA_CCMD_MASK_NOBIT,
1555                                            DMA_CCMD_DEVICE_INVL);
1556                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1557         } else {
1558                 iommu_flush_write_buffer(iommu);
1559         }
1560         iommu_enable_dev_iotlb(info);
1561         spin_unlock_irqrestore(&iommu->lock, flags);
1562
1563         spin_lock_irqsave(&domain->iommu_lock, flags);
1564         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1565                 domain->iommu_count++;
1566                 domain_update_iommu_cap(domain);
1567         }
1568         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1569         return 0;
1570 }
1571
1572 static int
1573 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1574                         int translation)
1575 {
1576         int ret;
1577         struct pci_dev *tmp, *parent;
1578
1579         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1580                                          pdev->bus->number, pdev->devfn,
1581                                          translation);
1582         if (ret)
1583                 return ret;
1584
1585         /* dependent device mapping */
1586         tmp = pci_find_upstream_pcie_bridge(pdev);
1587         if (!tmp)
1588                 return 0;
1589         /* Secondary interface's bus number and devfn 0 */
1590         parent = pdev->bus->self;
1591         while (parent != tmp) {
1592                 ret = domain_context_mapping_one(domain,
1593                                                  pci_domain_nr(parent->bus),
1594                                                  parent->bus->number,
1595                                                  parent->devfn, translation);
1596                 if (ret)
1597                         return ret;
1598                 parent = parent->bus->self;
1599         }
1600         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1601                 return domain_context_mapping_one(domain,
1602                                         pci_domain_nr(tmp->subordinate),
1603                                         tmp->subordinate->number, 0,
1604                                         translation);
1605         else /* this is a legacy PCI bridge */
1606                 return domain_context_mapping_one(domain,
1607                                                   pci_domain_nr(tmp->bus),
1608                                                   tmp->bus->number,
1609                                                   tmp->devfn,
1610                                                   translation);
1611 }
1612
1613 static int domain_context_mapped(struct pci_dev *pdev)
1614 {
1615         int ret;
1616         struct pci_dev *tmp, *parent;
1617         struct intel_iommu *iommu;
1618
1619         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1620                                 pdev->devfn);
1621         if (!iommu)
1622                 return -ENODEV;
1623
1624         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1625         if (!ret)
1626                 return ret;
1627         /* dependent device mapping */
1628         tmp = pci_find_upstream_pcie_bridge(pdev);
1629         if (!tmp)
1630                 return ret;
1631         /* Secondary interface's bus number and devfn 0 */
1632         parent = pdev->bus->self;
1633         while (parent != tmp) {
1634                 ret = device_context_mapped(iommu, parent->bus->number,
1635                                             parent->devfn);
1636                 if (!ret)
1637                         return ret;
1638                 parent = parent->bus->self;
1639         }
1640         if (tmp->is_pcie)
1641                 return device_context_mapped(iommu, tmp->subordinate->number,
1642                                              0);
1643         else
1644                 return device_context_mapped(iommu, tmp->bus->number,
1645                                              tmp->devfn);
1646 }
1647
1648 static int
1649 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1650                         u64 hpa, size_t size, int prot)
1651 {
1652         u64 start_pfn, end_pfn;
1653         struct dma_pte *pte;
1654         int index;
1655         int addr_width = agaw_to_width(domain->agaw);
1656
1657         hpa &= (((u64)1) << addr_width) - 1;
1658
1659         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1660                 return -EINVAL;
1661         iova &= PAGE_MASK;
1662         start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1663         end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
1664         index = 0;
1665         while (start_pfn < end_pfn) {
1666                 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
1667                 if (!pte)
1668                         return -ENOMEM;
1669                 /* We don't need lock here, nobody else
1670                  * touches the iova range
1671                  */
1672                 BUG_ON(dma_pte_addr(pte));
1673                 dma_set_pte_pfn(pte, start_pfn);
1674                 dma_set_pte_prot(pte, prot);
1675                 if (prot & DMA_PTE_SNP)
1676                         dma_set_pte_snp(pte);
1677                 domain_flush_cache(domain, pte, sizeof(*pte));
1678                 start_pfn++;
1679                 index++;
1680         }
1681         return 0;
1682 }
1683
1684 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1685 {
1686         if (!iommu)
1687                 return;
1688
1689         clear_context_table(iommu, bus, devfn);
1690         iommu->flush.flush_context(iommu, 0, 0, 0,
1691                                            DMA_CCMD_GLOBAL_INVL);
1692         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1693 }
1694
1695 static void domain_remove_dev_info(struct dmar_domain *domain)
1696 {
1697         struct device_domain_info *info;
1698         unsigned long flags;
1699         struct intel_iommu *iommu;
1700
1701         spin_lock_irqsave(&device_domain_lock, flags);
1702         while (!list_empty(&domain->devices)) {
1703                 info = list_entry(domain->devices.next,
1704                         struct device_domain_info, link);
1705                 list_del(&info->link);
1706                 list_del(&info->global);
1707                 if (info->dev)
1708                         info->dev->dev.archdata.iommu = NULL;
1709                 spin_unlock_irqrestore(&device_domain_lock, flags);
1710
1711                 iommu_disable_dev_iotlb(info);
1712                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1713                 iommu_detach_dev(iommu, info->bus, info->devfn);
1714                 free_devinfo_mem(info);
1715
1716                 spin_lock_irqsave(&device_domain_lock, flags);
1717         }
1718         spin_unlock_irqrestore(&device_domain_lock, flags);
1719 }
1720
1721 /*
1722  * find_domain
1723  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1724  */
1725 static struct dmar_domain *
1726 find_domain(struct pci_dev *pdev)
1727 {
1728         struct device_domain_info *info;
1729
1730         /* No lock here, assumes no domain exit in normal case */
1731         info = pdev->dev.archdata.iommu;
1732         if (info)
1733                 return info->domain;
1734         return NULL;
1735 }
1736
1737 /* domain is initialized */
1738 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1739 {
1740         struct dmar_domain *domain, *found = NULL;
1741         struct intel_iommu *iommu;
1742         struct dmar_drhd_unit *drhd;
1743         struct device_domain_info *info, *tmp;
1744         struct pci_dev *dev_tmp;
1745         unsigned long flags;
1746         int bus = 0, devfn = 0;
1747         int segment;
1748         int ret;
1749
1750         domain = find_domain(pdev);
1751         if (domain)
1752                 return domain;
1753
1754         segment = pci_domain_nr(pdev->bus);
1755
1756         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1757         if (dev_tmp) {
1758                 if (dev_tmp->is_pcie) {
1759                         bus = dev_tmp->subordinate->number;
1760                         devfn = 0;
1761                 } else {
1762                         bus = dev_tmp->bus->number;
1763                         devfn = dev_tmp->devfn;
1764                 }
1765                 spin_lock_irqsave(&device_domain_lock, flags);
1766                 list_for_each_entry(info, &device_domain_list, global) {
1767                         if (info->segment == segment &&
1768                             info->bus == bus && info->devfn == devfn) {
1769                                 found = info->domain;
1770                                 break;
1771                         }
1772                 }
1773                 spin_unlock_irqrestore(&device_domain_lock, flags);
1774                 /* pcie-pci bridge already has a domain, uses it */
1775                 if (found) {
1776                         domain = found;
1777                         goto found_domain;
1778                 }
1779         }
1780
1781         domain = alloc_domain();
1782         if (!domain)
1783                 goto error;
1784
1785         /* Allocate new domain for the device */
1786         drhd = dmar_find_matched_drhd_unit(pdev);
1787         if (!drhd) {
1788                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1789                         pci_name(pdev));
1790                 return NULL;
1791         }
1792         iommu = drhd->iommu;
1793
1794         ret = iommu_attach_domain(domain, iommu);
1795         if (ret) {
1796                 domain_exit(domain);
1797                 goto error;
1798         }
1799
1800         if (domain_init(domain, gaw)) {
1801                 domain_exit(domain);
1802                 goto error;
1803         }
1804
1805         /* register pcie-to-pci device */
1806         if (dev_tmp) {
1807                 info = alloc_devinfo_mem();
1808                 if (!info) {
1809                         domain_exit(domain);
1810                         goto error;
1811                 }
1812                 info->segment = segment;
1813                 info->bus = bus;
1814                 info->devfn = devfn;
1815                 info->dev = NULL;
1816                 info->domain = domain;
1817                 /* This domain is shared by devices under p2p bridge */
1818                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1819
1820                 /* pcie-to-pci bridge already has a domain, uses it */
1821                 found = NULL;
1822                 spin_lock_irqsave(&device_domain_lock, flags);
1823                 list_for_each_entry(tmp, &device_domain_list, global) {
1824                         if (tmp->segment == segment &&
1825                             tmp->bus == bus && tmp->devfn == devfn) {
1826                                 found = tmp->domain;
1827                                 break;
1828                         }
1829                 }
1830                 if (found) {
1831                         free_devinfo_mem(info);
1832                         domain_exit(domain);
1833                         domain = found;
1834                 } else {
1835                         list_add(&info->link, &domain->devices);
1836                         list_add(&info->global, &device_domain_list);
1837                 }
1838                 spin_unlock_irqrestore(&device_domain_lock, flags);
1839         }
1840
1841 found_domain:
1842         info = alloc_devinfo_mem();
1843         if (!info)
1844                 goto error;
1845         info->segment = segment;
1846         info->bus = pdev->bus->number;
1847         info->devfn = pdev->devfn;
1848         info->dev = pdev;
1849         info->domain = domain;
1850         spin_lock_irqsave(&device_domain_lock, flags);
1851         /* somebody is fast */
1852         found = find_domain(pdev);
1853         if (found != NULL) {
1854                 spin_unlock_irqrestore(&device_domain_lock, flags);
1855                 if (found != domain) {
1856                         domain_exit(domain);
1857                         domain = found;
1858                 }
1859                 free_devinfo_mem(info);
1860                 return domain;
1861         }
1862         list_add(&info->link, &domain->devices);
1863         list_add(&info->global, &device_domain_list);
1864         pdev->dev.archdata.iommu = info;
1865         spin_unlock_irqrestore(&device_domain_lock, flags);
1866         return domain;
1867 error:
1868         /* recheck it here, maybe others set it */
1869         return find_domain(pdev);
1870 }
1871
1872 static int iommu_identity_mapping;
1873
1874 static int iommu_domain_identity_map(struct dmar_domain *domain,
1875                                      unsigned long long start,
1876                                      unsigned long long end)
1877 {
1878         unsigned long size;
1879         unsigned long long base;
1880
1881         /* The address might not be aligned */
1882         base = start & PAGE_MASK;
1883         size = end - base;
1884         size = PAGE_ALIGN(size);
1885         if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1886                         IOVA_PFN(base + size) - 1)) {
1887                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1888                 return -ENOMEM;
1889         }
1890
1891         pr_debug("Mapping reserved region %lx@%llx for domain %d\n",
1892                  size, base, domain->id);
1893         /*
1894          * RMRR range might have overlap with physical memory range,
1895          * clear it first
1896          */
1897         dma_pte_clear_range(domain, base, base + size);
1898
1899         return domain_page_mapping(domain, base, base, size,
1900                                    DMA_PTE_READ|DMA_PTE_WRITE);
1901 }
1902
1903 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1904                                       unsigned long long start,
1905                                       unsigned long long end)
1906 {
1907         struct dmar_domain *domain;
1908         int ret;
1909
1910         printk(KERN_INFO
1911                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1912                pci_name(pdev), start, end);
1913
1914         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1915         if (!domain)
1916                 return -ENOMEM;
1917
1918         ret = iommu_domain_identity_map(domain, start, end);
1919         if (ret)
1920                 goto error;
1921
1922         /* context entry init */
1923         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1924         if (ret)
1925                 goto error;
1926
1927         return 0;
1928
1929  error:
1930         domain_exit(domain);
1931         return ret;
1932 }
1933
1934 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1935         struct pci_dev *pdev)
1936 {
1937         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1938                 return 0;
1939         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1940                 rmrr->end_address + 1);
1941 }
1942
1943 #ifdef CONFIG_DMAR_FLOPPY_WA
1944 static inline void iommu_prepare_isa(void)
1945 {
1946         struct pci_dev *pdev;
1947         int ret;
1948
1949         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1950         if (!pdev)
1951                 return;
1952
1953         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1954         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1955
1956         if (ret)
1957                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1958                        "floppy might not work\n");
1959
1960 }
1961 #else
1962 static inline void iommu_prepare_isa(void)
1963 {
1964         return;
1965 }
1966 #endif /* !CONFIG_DMAR_FLPY_WA */
1967
1968 /* Initialize each context entry as pass through.*/
1969 static int __init init_context_pass_through(void)
1970 {
1971         struct pci_dev *pdev = NULL;
1972         struct dmar_domain *domain;
1973         int ret;
1974
1975         for_each_pci_dev(pdev) {
1976                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1977                 ret = domain_context_mapping(domain, pdev,
1978                                              CONTEXT_TT_PASS_THROUGH);
1979                 if (ret)
1980                         return ret;
1981         }
1982         return 0;
1983 }
1984
1985 static int md_domain_init(struct dmar_domain *domain, int guest_width);
1986
1987 static int __init si_domain_work_fn(unsigned long start_pfn,
1988                                     unsigned long end_pfn, void *datax)
1989 {
1990         int *ret = datax;
1991
1992         *ret = iommu_domain_identity_map(si_domain,
1993                                          (uint64_t)start_pfn << PAGE_SHIFT,
1994                                          (uint64_t)end_pfn << PAGE_SHIFT);
1995         return *ret;
1996
1997 }
1998
1999 static int si_domain_init(void)
2000 {
2001         struct dmar_drhd_unit *drhd;
2002         struct intel_iommu *iommu;
2003         int nid, ret = 0;
2004
2005         si_domain = alloc_domain();
2006         if (!si_domain)
2007                 return -EFAULT;
2008
2009         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2010
2011         for_each_active_iommu(iommu, drhd) {
2012                 ret = iommu_attach_domain(si_domain, iommu);
2013                 if (ret) {
2014                         domain_exit(si_domain);
2015                         return -EFAULT;
2016                 }
2017         }
2018
2019         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2020                 domain_exit(si_domain);
2021                 return -EFAULT;
2022         }
2023
2024         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2025
2026         for_each_online_node(nid) {
2027                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2028                 if (ret)
2029                         return ret;
2030         }
2031
2032         return 0;
2033 }
2034
2035 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2036                                           struct pci_dev *pdev);
2037 static int identity_mapping(struct pci_dev *pdev)
2038 {
2039         struct device_domain_info *info;
2040
2041         if (likely(!iommu_identity_mapping))
2042                 return 0;
2043
2044
2045         list_for_each_entry(info, &si_domain->devices, link)
2046                 if (info->dev == pdev)
2047                         return 1;
2048         return 0;
2049 }
2050
2051 static int domain_add_dev_info(struct dmar_domain *domain,
2052                                   struct pci_dev *pdev)
2053 {
2054         struct device_domain_info *info;
2055         unsigned long flags;
2056
2057         info = alloc_devinfo_mem();
2058         if (!info)
2059                 return -ENOMEM;
2060
2061         info->segment = pci_domain_nr(pdev->bus);
2062         info->bus = pdev->bus->number;
2063         info->devfn = pdev->devfn;
2064         info->dev = pdev;
2065         info->domain = domain;
2066
2067         spin_lock_irqsave(&device_domain_lock, flags);
2068         list_add(&info->link, &domain->devices);
2069         list_add(&info->global, &device_domain_list);
2070         pdev->dev.archdata.iommu = info;
2071         spin_unlock_irqrestore(&device_domain_lock, flags);
2072
2073         return 0;
2074 }
2075
2076 static int iommu_prepare_static_identity_mapping(void)
2077 {
2078         struct pci_dev *pdev = NULL;
2079         int ret;
2080
2081         ret = si_domain_init();
2082         if (ret)
2083                 return -EFAULT;
2084
2085         for_each_pci_dev(pdev) {
2086                 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2087                        pci_name(pdev));
2088
2089                 ret = domain_context_mapping(si_domain, pdev,
2090                                              CONTEXT_TT_MULTI_LEVEL);
2091                 if (ret)
2092                         return ret;
2093                 ret = domain_add_dev_info(si_domain, pdev);
2094                 if (ret)
2095                         return ret;
2096         }
2097
2098         return 0;
2099 }
2100
2101 int __init init_dmars(void)
2102 {
2103         struct dmar_drhd_unit *drhd;
2104         struct dmar_rmrr_unit *rmrr;
2105         struct pci_dev *pdev;
2106         struct intel_iommu *iommu;
2107         int i, ret;
2108         int pass_through = 1;
2109
2110         /*
2111          * In case pass through can not be enabled, iommu tries to use identity
2112          * mapping.
2113          */
2114         if (iommu_pass_through)
2115                 iommu_identity_mapping = 1;
2116
2117         /*
2118          * for each drhd
2119          *    allocate root
2120          *    initialize and program root entry to not present
2121          * endfor
2122          */
2123         for_each_drhd_unit(drhd) {
2124                 g_num_of_iommus++;
2125                 /*
2126                  * lock not needed as this is only incremented in the single
2127                  * threaded kernel __init code path all other access are read
2128                  * only
2129                  */
2130         }
2131
2132         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2133                         GFP_KERNEL);
2134         if (!g_iommus) {
2135                 printk(KERN_ERR "Allocating global iommu array failed\n");
2136                 ret = -ENOMEM;
2137                 goto error;
2138         }
2139
2140         deferred_flush = kzalloc(g_num_of_iommus *
2141                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2142         if (!deferred_flush) {
2143                 kfree(g_iommus);
2144                 ret = -ENOMEM;
2145                 goto error;
2146         }
2147
2148         for_each_drhd_unit(drhd) {
2149                 if (drhd->ignored)
2150                         continue;
2151
2152                 iommu = drhd->iommu;
2153                 g_iommus[iommu->seq_id] = iommu;
2154
2155                 ret = iommu_init_domains(iommu);
2156                 if (ret)
2157                         goto error;
2158
2159                 /*
2160                  * TBD:
2161                  * we could share the same root & context tables
2162                  * amoung all IOMMU's. Need to Split it later.
2163                  */
2164                 ret = iommu_alloc_root_entry(iommu);
2165                 if (ret) {
2166                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2167                         goto error;
2168                 }
2169                 if (!ecap_pass_through(iommu->ecap))
2170                         pass_through = 0;
2171         }
2172         if (iommu_pass_through)
2173                 if (!pass_through) {
2174                         printk(KERN_INFO
2175                                "Pass Through is not supported by hardware.\n");
2176                         iommu_pass_through = 0;
2177                 }
2178
2179         /*
2180          * Start from the sane iommu hardware state.
2181          */
2182         for_each_drhd_unit(drhd) {
2183                 if (drhd->ignored)
2184                         continue;
2185
2186                 iommu = drhd->iommu;
2187
2188                 /*
2189                  * If the queued invalidation is already initialized by us
2190                  * (for example, while enabling interrupt-remapping) then
2191                  * we got the things already rolling from a sane state.
2192                  */
2193                 if (iommu->qi)
2194                         continue;
2195
2196                 /*
2197                  * Clear any previous faults.
2198                  */
2199                 dmar_fault(-1, iommu);
2200                 /*
2201                  * Disable queued invalidation if supported and already enabled
2202                  * before OS handover.
2203                  */
2204                 dmar_disable_qi(iommu);
2205         }
2206
2207         for_each_drhd_unit(drhd) {
2208                 if (drhd->ignored)
2209                         continue;
2210
2211                 iommu = drhd->iommu;
2212
2213                 if (dmar_enable_qi(iommu)) {
2214                         /*
2215                          * Queued Invalidate not enabled, use Register Based
2216                          * Invalidate
2217                          */
2218                         iommu->flush.flush_context = __iommu_flush_context;
2219                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2220                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2221                                "invalidation\n",
2222                                (unsigned long long)drhd->reg_base_addr);
2223                 } else {
2224                         iommu->flush.flush_context = qi_flush_context;
2225                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2226                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2227                                "invalidation\n",
2228                                (unsigned long long)drhd->reg_base_addr);
2229                 }
2230         }
2231
2232         /*
2233          * If pass through is set and enabled, context entries of all pci
2234          * devices are intialized by pass through translation type.
2235          */
2236         if (iommu_pass_through) {
2237                 ret = init_context_pass_through();
2238                 if (ret) {
2239                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2240                         iommu_pass_through = 0;
2241                 }
2242         }
2243
2244         /*
2245          * If pass through is not set or not enabled, setup context entries for
2246          * identity mappings for rmrr, gfx, and isa and may fall back to static
2247          * identity mapping if iommu_identity_mapping is set.
2248          */
2249         if (!iommu_pass_through) {
2250                 if (iommu_identity_mapping)
2251                         iommu_prepare_static_identity_mapping();
2252                 /*
2253                  * For each rmrr
2254                  *   for each dev attached to rmrr
2255                  *   do
2256                  *     locate drhd for dev, alloc domain for dev
2257                  *     allocate free domain
2258                  *     allocate page table entries for rmrr
2259                  *     if context not allocated for bus
2260                  *           allocate and init context
2261                  *           set present in root table for this bus
2262                  *     init context with domain, translation etc
2263                  *    endfor
2264                  * endfor
2265                  */
2266                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2267                 for_each_rmrr_units(rmrr) {
2268                         for (i = 0; i < rmrr->devices_cnt; i++) {
2269                                 pdev = rmrr->devices[i];
2270                                 /*
2271                                  * some BIOS lists non-exist devices in DMAR
2272                                  * table.
2273                                  */
2274                                 if (!pdev)
2275                                         continue;
2276                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2277                                 if (ret)
2278                                         printk(KERN_ERR
2279                                  "IOMMU: mapping reserved region failed\n");
2280                         }
2281                 }
2282
2283                 iommu_prepare_isa();
2284         }
2285
2286         /*
2287          * for each drhd
2288          *   enable fault log
2289          *   global invalidate context cache
2290          *   global invalidate iotlb
2291          *   enable translation
2292          */
2293         for_each_drhd_unit(drhd) {
2294                 if (drhd->ignored)
2295                         continue;
2296                 iommu = drhd->iommu;
2297
2298                 iommu_flush_write_buffer(iommu);
2299
2300                 ret = dmar_set_interrupt(iommu);
2301                 if (ret)
2302                         goto error;
2303
2304                 iommu_set_root_entry(iommu);
2305
2306                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2307                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2308                 iommu_disable_protect_mem_regions(iommu);
2309
2310                 ret = iommu_enable_translation(iommu);
2311                 if (ret)
2312                         goto error;
2313         }
2314
2315         return 0;
2316 error:
2317         for_each_drhd_unit(drhd) {
2318                 if (drhd->ignored)
2319                         continue;
2320                 iommu = drhd->iommu;
2321                 free_iommu(iommu);
2322         }
2323         kfree(g_iommus);
2324         return ret;
2325 }
2326
2327 static inline u64 aligned_size(u64 host_addr, size_t size)
2328 {
2329         u64 addr;
2330         addr = (host_addr & (~PAGE_MASK)) + size;
2331         return PAGE_ALIGN(addr);
2332 }
2333
2334 struct iova *
2335 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2336 {
2337         struct iova *piova;
2338
2339         /* Make sure it's in range */
2340         end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2341         if (!size || (IOVA_START_ADDR + size > end))
2342                 return NULL;
2343
2344         piova = alloc_iova(&domain->iovad,
2345                         size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2346         return piova;
2347 }
2348
2349 static struct iova *
2350 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2351                    size_t size, u64 dma_mask)
2352 {
2353         struct pci_dev *pdev = to_pci_dev(dev);
2354         struct iova *iova = NULL;
2355
2356         if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2357                 iova = iommu_alloc_iova(domain, size, dma_mask);
2358         else {
2359                 /*
2360                  * First try to allocate an io virtual address in
2361                  * DMA_BIT_MASK(32) and if that fails then try allocating
2362                  * from higher range
2363                  */
2364                 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2365                 if (!iova)
2366                         iova = iommu_alloc_iova(domain, size, dma_mask);
2367         }
2368
2369         if (!iova) {
2370                 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2371                 return NULL;
2372         }
2373
2374         return iova;
2375 }
2376
2377 static struct dmar_domain *
2378 get_valid_domain_for_dev(struct pci_dev *pdev)
2379 {
2380         struct dmar_domain *domain;
2381         int ret;
2382
2383         domain = get_domain_for_dev(pdev,
2384                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2385         if (!domain) {
2386                 printk(KERN_ERR
2387                         "Allocating domain for %s failed", pci_name(pdev));
2388                 return NULL;
2389         }
2390
2391         /* make sure context mapping is ok */
2392         if (unlikely(!domain_context_mapped(pdev))) {
2393                 ret = domain_context_mapping(domain, pdev,
2394                                              CONTEXT_TT_MULTI_LEVEL);
2395                 if (ret) {
2396                         printk(KERN_ERR
2397                                 "Domain context map for %s failed",
2398                                 pci_name(pdev));
2399                         return NULL;
2400                 }
2401         }
2402
2403         return domain;
2404 }
2405
2406 static int iommu_dummy(struct pci_dev *pdev)
2407 {
2408         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2409 }
2410
2411 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2412 static int iommu_no_mapping(struct pci_dev *pdev)
2413 {
2414         int found;
2415
2416         if (!iommu_identity_mapping)
2417                 return iommu_dummy(pdev);
2418
2419         found = identity_mapping(pdev);
2420         if (found) {
2421                 if (pdev->dma_mask > DMA_BIT_MASK(32))
2422                         return 1;
2423                 else {
2424                         /*
2425                          * 32 bit DMA is removed from si_domain and fall back
2426                          * to non-identity mapping.
2427                          */
2428                         domain_remove_one_dev_info(si_domain, pdev);
2429                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2430                                pci_name(pdev));
2431                         return 0;
2432                 }
2433         } else {
2434                 /*
2435                  * In case of a detached 64 bit DMA device from vm, the device
2436                  * is put into si_domain for identity mapping.
2437                  */
2438                 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2439                         int ret;
2440                         ret = domain_add_dev_info(si_domain, pdev);
2441                         if (!ret) {
2442                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2443                                        pci_name(pdev));
2444                                 return 1;
2445                         }
2446                 }
2447         }
2448
2449         return iommu_dummy(pdev);
2450 }
2451
2452 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2453                                      size_t size, int dir, u64 dma_mask)
2454 {
2455         struct pci_dev *pdev = to_pci_dev(hwdev);
2456         struct dmar_domain *domain;
2457         phys_addr_t start_paddr;
2458         struct iova *iova;
2459         int prot = 0;
2460         int ret;
2461         struct intel_iommu *iommu;
2462
2463         BUG_ON(dir == DMA_NONE);
2464
2465         if (iommu_no_mapping(pdev))
2466                 return paddr;
2467
2468         domain = get_valid_domain_for_dev(pdev);
2469         if (!domain)
2470                 return 0;
2471
2472         iommu = domain_get_iommu(domain);
2473         size = aligned_size((u64)paddr, size);
2474
2475         iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2476         if (!iova)
2477                 goto error;
2478
2479         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2480
2481         /*
2482          * Check if DMAR supports zero-length reads on write only
2483          * mappings..
2484          */
2485         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2486                         !cap_zlr(iommu->cap))
2487                 prot |= DMA_PTE_READ;
2488         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2489                 prot |= DMA_PTE_WRITE;
2490         /*
2491          * paddr - (paddr + size) might be partial page, we should map the whole
2492          * page.  Note: if two part of one page are separately mapped, we
2493          * might have two guest_addr mapping to the same host paddr, but this
2494          * is not a big problem
2495          */
2496         ret = domain_page_mapping(domain, start_paddr,
2497                                   ((u64)paddr) & PHYSICAL_PAGE_MASK,
2498                                   size, prot);
2499         if (ret)
2500                 goto error;
2501
2502         /* it's a non-present to present mapping. Only flush if caching mode */
2503         if (cap_caching_mode(iommu->cap))
2504                 iommu_flush_iotlb_psi(iommu, 0, start_paddr,
2505                                       size >> VTD_PAGE_SHIFT);
2506         else
2507                 iommu_flush_write_buffer(iommu);
2508
2509         return start_paddr + ((u64)paddr & (~PAGE_MASK));
2510
2511 error:
2512         if (iova)
2513                 __free_iova(&domain->iovad, iova);
2514         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2515                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2516         return 0;
2517 }
2518
2519 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2520                                  unsigned long offset, size_t size,
2521                                  enum dma_data_direction dir,
2522                                  struct dma_attrs *attrs)
2523 {
2524         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2525                                   dir, to_pci_dev(dev)->dma_mask);
2526 }
2527
2528 static void flush_unmaps(void)
2529 {
2530         int i, j;
2531
2532         timer_on = 0;
2533
2534         /* just flush them all */
2535         for (i = 0; i < g_num_of_iommus; i++) {
2536                 struct intel_iommu *iommu = g_iommus[i];
2537                 if (!iommu)
2538                         continue;
2539
2540                 if (!deferred_flush[i].next)
2541                         continue;
2542
2543                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2544                                          DMA_TLB_GLOBAL_FLUSH);
2545                 for (j = 0; j < deferred_flush[i].next; j++) {
2546                         unsigned long mask;
2547                         struct iova *iova = deferred_flush[i].iova[j];
2548
2549                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2550                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2551                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2552                                         iova->pfn_lo << PAGE_SHIFT, mask);
2553                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2554                 }
2555                 deferred_flush[i].next = 0;
2556         }
2557
2558         list_size = 0;
2559 }
2560
2561 static void flush_unmaps_timeout(unsigned long data)
2562 {
2563         unsigned long flags;
2564
2565         spin_lock_irqsave(&async_umap_flush_lock, flags);
2566         flush_unmaps();
2567         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2568 }
2569
2570 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2571 {
2572         unsigned long flags;
2573         int next, iommu_id;
2574         struct intel_iommu *iommu;
2575
2576         spin_lock_irqsave(&async_umap_flush_lock, flags);
2577         if (list_size == HIGH_WATER_MARK)
2578                 flush_unmaps();
2579
2580         iommu = domain_get_iommu(dom);
2581         iommu_id = iommu->seq_id;
2582
2583         next = deferred_flush[iommu_id].next;
2584         deferred_flush[iommu_id].domain[next] = dom;
2585         deferred_flush[iommu_id].iova[next] = iova;
2586         deferred_flush[iommu_id].next++;
2587
2588         if (!timer_on) {
2589                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2590                 timer_on = 1;
2591         }
2592         list_size++;
2593         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2594 }
2595
2596 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2597                              size_t size, enum dma_data_direction dir,
2598                              struct dma_attrs *attrs)
2599 {
2600         struct pci_dev *pdev = to_pci_dev(dev);
2601         struct dmar_domain *domain;
2602         unsigned long start_addr;
2603         struct iova *iova;
2604         struct intel_iommu *iommu;
2605
2606         if (iommu_no_mapping(pdev))
2607                 return;
2608
2609         domain = find_domain(pdev);
2610         BUG_ON(!domain);
2611
2612         iommu = domain_get_iommu(domain);
2613
2614         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2615         if (!iova)
2616                 return;
2617
2618         start_addr = iova->pfn_lo << PAGE_SHIFT;
2619         size = aligned_size((u64)dev_addr, size);
2620
2621         pr_debug("Device %s unmapping: %zx@%llx\n",
2622                 pci_name(pdev), size, (unsigned long long)start_addr);
2623
2624         /*  clear the whole page */
2625         dma_pte_clear_range(domain, start_addr, start_addr + size);
2626         /* free page tables */
2627         dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2628         if (intel_iommu_strict) {
2629                 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2630                                       size >> VTD_PAGE_SHIFT);
2631                 /* free iova */
2632                 __free_iova(&domain->iovad, iova);
2633         } else {
2634                 add_unmap(domain, iova);
2635                 /*
2636                  * queue up the release of the unmap to save the 1/6th of the
2637                  * cpu used up by the iotlb flush operation...
2638                  */
2639         }
2640 }
2641
2642 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2643                                int dir)
2644 {
2645         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2646 }
2647
2648 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2649                                   dma_addr_t *dma_handle, gfp_t flags)
2650 {
2651         void *vaddr;
2652         int order;
2653
2654         size = PAGE_ALIGN(size);
2655         order = get_order(size);
2656         flags &= ~(GFP_DMA | GFP_DMA32);
2657
2658         vaddr = (void *)__get_free_pages(flags, order);
2659         if (!vaddr)
2660                 return NULL;
2661         memset(vaddr, 0, size);
2662
2663         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2664                                          DMA_BIDIRECTIONAL,
2665                                          hwdev->coherent_dma_mask);
2666         if (*dma_handle)
2667                 return vaddr;
2668         free_pages((unsigned long)vaddr, order);
2669         return NULL;
2670 }
2671
2672 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2673                                 dma_addr_t dma_handle)
2674 {
2675         int order;
2676
2677         size = PAGE_ALIGN(size);
2678         order = get_order(size);
2679
2680         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2681         free_pages((unsigned long)vaddr, order);
2682 }
2683
2684 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2685                            int nelems, enum dma_data_direction dir,
2686                            struct dma_attrs *attrs)
2687 {
2688         int i;
2689         struct pci_dev *pdev = to_pci_dev(hwdev);
2690         struct dmar_domain *domain;
2691         unsigned long start_addr;
2692         struct iova *iova;
2693         size_t size = 0;
2694         phys_addr_t addr;
2695         struct scatterlist *sg;
2696         struct intel_iommu *iommu;
2697
2698         if (iommu_no_mapping(pdev))
2699                 return;
2700
2701         domain = find_domain(pdev);
2702         BUG_ON(!domain);
2703
2704         iommu = domain_get_iommu(domain);
2705
2706         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2707         if (!iova)
2708                 return;
2709         for_each_sg(sglist, sg, nelems, i) {
2710                 addr = page_to_phys(sg_page(sg)) + sg->offset;
2711                 size += aligned_size((u64)addr, sg->length);
2712         }
2713
2714         start_addr = iova->pfn_lo << PAGE_SHIFT;
2715
2716         /*  clear the whole page */
2717         dma_pte_clear_range(domain, start_addr, start_addr + size);
2718         /* free page tables */
2719         dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2720
2721         iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2722                               size >> VTD_PAGE_SHIFT);
2723
2724         /* free iova */
2725         __free_iova(&domain->iovad, iova);
2726 }
2727
2728 static int intel_nontranslate_map_sg(struct device *hddev,
2729         struct scatterlist *sglist, int nelems, int dir)
2730 {
2731         int i;
2732         struct scatterlist *sg;
2733
2734         for_each_sg(sglist, sg, nelems, i) {
2735                 BUG_ON(!sg_page(sg));
2736                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2737                 sg->dma_length = sg->length;
2738         }
2739         return nelems;
2740 }
2741
2742 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2743                         enum dma_data_direction dir, struct dma_attrs *attrs)
2744 {
2745         phys_addr_t addr;
2746         int i;
2747         struct pci_dev *pdev = to_pci_dev(hwdev);
2748         struct dmar_domain *domain;
2749         size_t size = 0;
2750         int prot = 0;
2751         size_t offset = 0;
2752         struct iova *iova = NULL;
2753         int ret;
2754         struct scatterlist *sg;
2755         unsigned long start_addr;
2756         struct intel_iommu *iommu;
2757
2758         BUG_ON(dir == DMA_NONE);
2759         if (iommu_no_mapping(pdev))
2760                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2761
2762         domain = get_valid_domain_for_dev(pdev);
2763         if (!domain)
2764                 return 0;
2765
2766         iommu = domain_get_iommu(domain);
2767
2768         for_each_sg(sglist, sg, nelems, i) {
2769                 addr = page_to_phys(sg_page(sg)) + sg->offset;
2770                 size += aligned_size((u64)addr, sg->length);
2771         }
2772
2773         iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2774         if (!iova) {
2775                 sglist->dma_length = 0;
2776                 return 0;
2777         }
2778
2779         /*
2780          * Check if DMAR supports zero-length reads on write only
2781          * mappings..
2782          */
2783         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2784                         !cap_zlr(iommu->cap))
2785                 prot |= DMA_PTE_READ;
2786         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2787                 prot |= DMA_PTE_WRITE;
2788
2789         start_addr = iova->pfn_lo << PAGE_SHIFT;
2790         offset = 0;
2791         for_each_sg(sglist, sg, nelems, i) {
2792                 addr = page_to_phys(sg_page(sg)) + sg->offset;
2793                 size = aligned_size((u64)addr, sg->length);
2794                 ret = domain_page_mapping(domain, start_addr + offset,
2795                                           ((u64)addr) & PHYSICAL_PAGE_MASK,
2796                                           size, prot);
2797                 if (ret) {
2798                         /*  clear the page */
2799                         dma_pte_clear_range(domain, start_addr,
2800                                   start_addr + offset);
2801                         /* free page tables */
2802                         dma_pte_free_pagetable(domain, start_addr,
2803                                   start_addr + offset);
2804                         /* free iova */
2805                         __free_iova(&domain->iovad, iova);
2806                         return 0;
2807                 }
2808                 sg->dma_address = start_addr + offset +
2809                                 ((u64)addr & (~PAGE_MASK));
2810                 sg->dma_length = sg->length;
2811                 offset += size;
2812         }
2813
2814         /* it's a non-present to present mapping. Only flush if caching mode */
2815         if (cap_caching_mode(iommu->cap))
2816                 iommu_flush_iotlb_psi(iommu, 0, start_addr,
2817                                       offset >> VTD_PAGE_SHIFT);
2818         else
2819                 iommu_flush_write_buffer(iommu);
2820
2821         return nelems;
2822 }
2823
2824 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2825 {
2826         return !dma_addr;
2827 }
2828
2829 struct dma_map_ops intel_dma_ops = {
2830         .alloc_coherent = intel_alloc_coherent,
2831         .free_coherent = intel_free_coherent,
2832         .map_sg = intel_map_sg,
2833         .unmap_sg = intel_unmap_sg,
2834         .map_page = intel_map_page,
2835         .unmap_page = intel_unmap_page,
2836         .mapping_error = intel_mapping_error,
2837 };
2838
2839 static inline int iommu_domain_cache_init(void)
2840 {
2841         int ret = 0;
2842
2843         iommu_domain_cache = kmem_cache_create("iommu_domain",
2844                                          sizeof(struct dmar_domain),
2845                                          0,
2846                                          SLAB_HWCACHE_ALIGN,
2847
2848                                          NULL);
2849         if (!iommu_domain_cache) {
2850                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2851                 ret = -ENOMEM;
2852         }
2853
2854         return ret;
2855 }
2856
2857 static inline int iommu_devinfo_cache_init(void)
2858 {
2859         int ret = 0;
2860
2861         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2862                                          sizeof(struct device_domain_info),
2863                                          0,
2864                                          SLAB_HWCACHE_ALIGN,
2865                                          NULL);
2866         if (!iommu_devinfo_cache) {
2867                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2868                 ret = -ENOMEM;
2869         }
2870
2871         return ret;
2872 }
2873
2874 static inline int iommu_iova_cache_init(void)
2875 {
2876         int ret = 0;
2877
2878         iommu_iova_cache = kmem_cache_create("iommu_iova",
2879                                          sizeof(struct iova),
2880                                          0,
2881                                          SLAB_HWCACHE_ALIGN,
2882                                          NULL);
2883         if (!iommu_iova_cache) {
2884                 printk(KERN_ERR "Couldn't create iova cache\n");
2885                 ret = -ENOMEM;
2886         }
2887
2888         return ret;
2889 }
2890
2891 static int __init iommu_init_mempool(void)
2892 {
2893         int ret;
2894         ret = iommu_iova_cache_init();
2895         if (ret)
2896                 return ret;
2897
2898         ret = iommu_domain_cache_init();
2899         if (ret)
2900                 goto domain_error;
2901
2902         ret = iommu_devinfo_cache_init();
2903         if (!ret)
2904                 return ret;
2905
2906         kmem_cache_destroy(iommu_domain_cache);
2907 domain_error:
2908         kmem_cache_destroy(iommu_iova_cache);
2909
2910         return -ENOMEM;
2911 }
2912
2913 static void __init iommu_exit_mempool(void)
2914 {
2915         kmem_cache_destroy(iommu_devinfo_cache);
2916         kmem_cache_destroy(iommu_domain_cache);
2917         kmem_cache_destroy(iommu_iova_cache);
2918
2919 }
2920
2921 static void __init init_no_remapping_devices(void)
2922 {
2923         struct dmar_drhd_unit *drhd;
2924
2925         for_each_drhd_unit(drhd) {
2926                 if (!drhd->include_all) {
2927                         int i;
2928                         for (i = 0; i < drhd->devices_cnt; i++)
2929                                 if (drhd->devices[i] != NULL)
2930                                         break;
2931                         /* ignore DMAR unit if no pci devices exist */
2932                         if (i == drhd->devices_cnt)
2933                                 drhd->ignored = 1;
2934                 }
2935         }
2936
2937         if (dmar_map_gfx)
2938                 return;
2939
2940         for_each_drhd_unit(drhd) {
2941                 int i;
2942                 if (drhd->ignored || drhd->include_all)
2943                         continue;
2944
2945                 for (i = 0; i < drhd->devices_cnt; i++)
2946                         if (drhd->devices[i] &&
2947                                 !IS_GFX_DEVICE(drhd->devices[i]))
2948                                 break;
2949
2950                 if (i < drhd->devices_cnt)
2951                         continue;
2952
2953                 /* bypass IOMMU if it is just for gfx devices */
2954                 drhd->ignored = 1;
2955                 for (i = 0; i < drhd->devices_cnt; i++) {
2956                         if (!drhd->devices[i])
2957                                 continue;
2958                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2959                 }
2960         }
2961 }
2962
2963 #ifdef CONFIG_SUSPEND
2964 static int init_iommu_hw(void)
2965 {
2966         struct dmar_drhd_unit *drhd;
2967         struct intel_iommu *iommu = NULL;
2968
2969         for_each_active_iommu(iommu, drhd)
2970                 if (iommu->qi)
2971                         dmar_reenable_qi(iommu);
2972
2973         for_each_active_iommu(iommu, drhd) {
2974                 iommu_flush_write_buffer(iommu);
2975
2976                 iommu_set_root_entry(iommu);
2977
2978                 iommu->flush.flush_context(iommu, 0, 0, 0,
2979                                            DMA_CCMD_GLOBAL_INVL);
2980                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2981                                          DMA_TLB_GLOBAL_FLUSH);
2982                 iommu_disable_protect_mem_regions(iommu);
2983                 iommu_enable_translation(iommu);
2984         }
2985
2986         return 0;
2987 }
2988
2989 static void iommu_flush_all(void)
2990 {
2991         struct dmar_drhd_unit *drhd;
2992         struct intel_iommu *iommu;
2993
2994         for_each_active_iommu(iommu, drhd) {
2995                 iommu->flush.flush_context(iommu, 0, 0, 0,
2996                                            DMA_CCMD_GLOBAL_INVL);
2997                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2998                                          DMA_TLB_GLOBAL_FLUSH);
2999         }
3000 }
3001
3002 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3003 {
3004         struct dmar_drhd_unit *drhd;
3005         struct intel_iommu *iommu = NULL;
3006         unsigned long flag;
3007
3008         for_each_active_iommu(iommu, drhd) {
3009                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3010                                                  GFP_ATOMIC);
3011                 if (!iommu->iommu_state)
3012                         goto nomem;
3013         }
3014
3015         iommu_flush_all();
3016
3017         for_each_active_iommu(iommu, drhd) {
3018                 iommu_disable_translation(iommu);
3019
3020                 spin_lock_irqsave(&iommu->register_lock, flag);
3021
3022                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3023                         readl(iommu->reg + DMAR_FECTL_REG);
3024                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3025                         readl(iommu->reg + DMAR_FEDATA_REG);
3026                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3027                         readl(iommu->reg + DMAR_FEADDR_REG);
3028                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3029                         readl(iommu->reg + DMAR_FEUADDR_REG);
3030
3031                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3032         }
3033         return 0;
3034
3035 nomem:
3036         for_each_active_iommu(iommu, drhd)
3037                 kfree(iommu->iommu_state);
3038
3039         return -ENOMEM;
3040 }
3041
3042 static int iommu_resume(struct sys_device *dev)
3043 {
3044         struct dmar_drhd_unit *drhd;
3045         struct intel_iommu *iommu = NULL;
3046         unsigned long flag;
3047
3048         if (init_iommu_hw()) {
3049                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3050                 return -EIO;
3051         }
3052
3053         for_each_active_iommu(iommu, drhd) {
3054
3055                 spin_lock_irqsave(&iommu->register_lock, flag);
3056
3057                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3058                         iommu->reg + DMAR_FECTL_REG);
3059                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3060                         iommu->reg + DMAR_FEDATA_REG);
3061                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3062                         iommu->reg + DMAR_FEADDR_REG);
3063                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3064                         iommu->reg + DMAR_FEUADDR_REG);
3065
3066                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3067         }
3068
3069         for_each_active_iommu(iommu, drhd)
3070                 kfree(iommu->iommu_state);
3071
3072         return 0;
3073 }
3074
3075 static struct sysdev_class iommu_sysclass = {
3076         .name           = "iommu",
3077         .resume         = iommu_resume,
3078         .suspend        = iommu_suspend,
3079 };
3080
3081 static struct sys_device device_iommu = {
3082         .cls    = &iommu_sysclass,
3083 };
3084
3085 static int __init init_iommu_sysfs(void)
3086 {
3087         int error;
3088
3089         error = sysdev_class_register(&iommu_sysclass);
3090         if (error)
3091                 return error;
3092
3093         error = sysdev_register(&device_iommu);
3094         if (error)
3095                 sysdev_class_unregister(&iommu_sysclass);
3096
3097         return error;
3098 }
3099
3100 #else
3101 static int __init init_iommu_sysfs(void)
3102 {
3103         return 0;
3104 }
3105 #endif  /* CONFIG_PM */
3106
3107 int __init intel_iommu_init(void)
3108 {
3109         int ret = 0;
3110
3111         if (dmar_table_init())
3112                 return  -ENODEV;
3113
3114         if (dmar_dev_scope_init())
3115                 return  -ENODEV;
3116
3117         /*
3118          * Check the need for DMA-remapping initialization now.
3119          * Above initialization will also be used by Interrupt-remapping.
3120          */
3121         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3122                 return -ENODEV;
3123
3124         iommu_init_mempool();
3125         dmar_init_reserved_ranges();
3126
3127         init_no_remapping_devices();
3128
3129         ret = init_dmars();
3130         if (ret) {
3131                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3132                 put_iova_domain(&reserved_iova_list);
3133                 iommu_exit_mempool();
3134                 return ret;
3135         }
3136         printk(KERN_INFO
3137         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3138
3139         init_timer(&unmap_timer);
3140         force_iommu = 1;
3141
3142         if (!iommu_pass_through) {
3143                 printk(KERN_INFO
3144                        "Multi-level page-table translation for DMAR.\n");
3145                 dma_ops = &intel_dma_ops;
3146         } else
3147                 printk(KERN_INFO
3148                        "DMAR: Pass through translation for DMAR.\n");
3149
3150         init_iommu_sysfs();
3151
3152         register_iommu(&intel_iommu_ops);
3153
3154         return 0;
3155 }
3156
3157 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3158                                            struct pci_dev *pdev)
3159 {
3160         struct pci_dev *tmp, *parent;
3161
3162         if (!iommu || !pdev)
3163                 return;
3164
3165         /* dependent device detach */
3166         tmp = pci_find_upstream_pcie_bridge(pdev);
3167         /* Secondary interface's bus number and devfn 0 */
3168         if (tmp) {
3169                 parent = pdev->bus->self;
3170                 while (parent != tmp) {
3171                         iommu_detach_dev(iommu, parent->bus->number,
3172                                          parent->devfn);
3173                         parent = parent->bus->self;
3174                 }
3175                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3176                         iommu_detach_dev(iommu,
3177                                 tmp->subordinate->number, 0);
3178                 else /* this is a legacy PCI bridge */
3179                         iommu_detach_dev(iommu, tmp->bus->number,
3180                                          tmp->devfn);
3181         }
3182 }
3183
3184 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3185                                           struct pci_dev *pdev)
3186 {
3187         struct device_domain_info *info;
3188         struct intel_iommu *iommu;
3189         unsigned long flags;
3190         int found = 0;
3191         struct list_head *entry, *tmp;
3192
3193         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3194                                 pdev->devfn);
3195         if (!iommu)
3196                 return;
3197
3198         spin_lock_irqsave(&device_domain_lock, flags);
3199         list_for_each_safe(entry, tmp, &domain->devices) {
3200                 info = list_entry(entry, struct device_domain_info, link);
3201                 /* No need to compare PCI domain; it has to be the same */
3202                 if (info->bus == pdev->bus->number &&
3203                     info->devfn == pdev->devfn) {
3204                         list_del(&info->link);
3205                         list_del(&info->global);
3206                         if (info->dev)
3207                                 info->dev->dev.archdata.iommu = NULL;
3208                         spin_unlock_irqrestore(&device_domain_lock, flags);
3209
3210                         iommu_disable_dev_iotlb(info);
3211                         iommu_detach_dev(iommu, info->bus, info->devfn);
3212                         iommu_detach_dependent_devices(iommu, pdev);
3213                         free_devinfo_mem(info);
3214
3215                         spin_lock_irqsave(&device_domain_lock, flags);
3216
3217                         if (found)
3218                                 break;
3219                         else
3220                                 continue;
3221                 }
3222
3223                 /* if there is no other devices under the same iommu
3224                  * owned by this domain, clear this iommu in iommu_bmp
3225                  * update iommu count and coherency
3226                  */
3227                 if (iommu == device_to_iommu(info->segment, info->bus,
3228                                             info->devfn))
3229                         found = 1;
3230         }
3231
3232         if (found == 0) {
3233                 unsigned long tmp_flags;
3234                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3235                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3236                 domain->iommu_count--;
3237                 domain_update_iommu_cap(domain);
3238                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3239         }
3240
3241         spin_unlock_irqrestore(&device_domain_lock, flags);
3242 }
3243
3244 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3245 {
3246         struct device_domain_info *info;
3247         struct intel_iommu *iommu;
3248         unsigned long flags1, flags2;
3249
3250         spin_lock_irqsave(&device_domain_lock, flags1);
3251         while (!list_empty(&domain->devices)) {
3252                 info = list_entry(domain->devices.next,
3253                         struct device_domain_info, link);
3254                 list_del(&info->link);
3255                 list_del(&info->global);
3256                 if (info->dev)
3257                         info->dev->dev.archdata.iommu = NULL;
3258
3259                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3260
3261                 iommu_disable_dev_iotlb(info);
3262                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3263                 iommu_detach_dev(iommu, info->bus, info->devfn);
3264                 iommu_detach_dependent_devices(iommu, info->dev);
3265
3266                 /* clear this iommu in iommu_bmp, update iommu count
3267                  * and capabilities
3268                  */
3269                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3270                 if (test_and_clear_bit(iommu->seq_id,
3271                                        &domain->iommu_bmp)) {
3272                         domain->iommu_count--;
3273                         domain_update_iommu_cap(domain);
3274                 }
3275                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3276
3277                 free_devinfo_mem(info);
3278                 spin_lock_irqsave(&device_domain_lock, flags1);
3279         }
3280         spin_unlock_irqrestore(&device_domain_lock, flags1);
3281 }
3282
3283 /* domain id for virtual machine, it won't be set in context */
3284 static unsigned long vm_domid;
3285
3286 static int vm_domain_min_agaw(struct dmar_domain *domain)
3287 {
3288         int i;
3289         int min_agaw = domain->agaw;
3290
3291         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3292         for (; i < g_num_of_iommus; ) {
3293                 if (min_agaw > g_iommus[i]->agaw)
3294                         min_agaw = g_iommus[i]->agaw;
3295
3296                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3297         }
3298
3299         return min_agaw;
3300 }
3301
3302 static struct dmar_domain *iommu_alloc_vm_domain(void)
3303 {
3304         struct dmar_domain *domain;
3305
3306         domain = alloc_domain_mem();
3307         if (!domain)
3308                 return NULL;
3309
3310         domain->id = vm_domid++;
3311         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3312         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3313
3314         return domain;
3315 }
3316
3317 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3318 {
3319         int adjust_width;
3320
3321         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3322         spin_lock_init(&domain->mapping_lock);
3323         spin_lock_init(&domain->iommu_lock);
3324
3325         domain_reserve_special_ranges(domain);
3326
3327         /* calculate AGAW */
3328         domain->gaw = guest_width;
3329         adjust_width = guestwidth_to_adjustwidth(guest_width);
3330         domain->agaw = width_to_agaw(adjust_width);
3331
3332         INIT_LIST_HEAD(&domain->devices);
3333
3334         domain->iommu_count = 0;
3335         domain->iommu_coherency = 0;
3336         domain->max_addr = 0;
3337
3338         /* always allocate the top pgd */
3339         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3340         if (!domain->pgd)
3341                 return -ENOMEM;
3342         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3343         return 0;
3344 }
3345
3346 static void iommu_free_vm_domain(struct dmar_domain *domain)
3347 {
3348         unsigned long flags;
3349         struct dmar_drhd_unit *drhd;
3350         struct intel_iommu *iommu;
3351         unsigned long i;
3352         unsigned long ndomains;
3353
3354         for_each_drhd_unit(drhd) {
3355                 if (drhd->ignored)
3356                         continue;
3357                 iommu = drhd->iommu;
3358
3359                 ndomains = cap_ndoms(iommu->cap);
3360                 i = find_first_bit(iommu->domain_ids, ndomains);
3361                 for (; i < ndomains; ) {
3362                         if (iommu->domains[i] == domain) {
3363                                 spin_lock_irqsave(&iommu->lock, flags);
3364                                 clear_bit(i, iommu->domain_ids);
3365                                 iommu->domains[i] = NULL;
3366                                 spin_unlock_irqrestore(&iommu->lock, flags);
3367                                 break;
3368                         }
3369                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3370                 }
3371         }
3372 }
3373
3374 static void vm_domain_exit(struct dmar_domain *domain)
3375 {
3376         u64 end;
3377
3378         /* Domain 0 is reserved, so dont process it */
3379         if (!domain)
3380                 return;
3381
3382         vm_domain_remove_all_dev_info(domain);
3383         /* destroy iovas */
3384         put_iova_domain(&domain->iovad);
3385         end = DOMAIN_MAX_ADDR(domain->gaw);
3386         end = end & (~VTD_PAGE_MASK);
3387
3388         /* clear ptes */
3389         dma_pte_clear_range(domain, 0, end);
3390
3391         /* free page tables */
3392         dma_pte_free_pagetable(domain, 0, end);
3393
3394         iommu_free_vm_domain(domain);
3395         free_domain_mem(domain);
3396 }
3397
3398 static int intel_iommu_domain_init(struct iommu_domain *domain)
3399 {
3400         struct dmar_domain *dmar_domain;
3401
3402         dmar_domain = iommu_alloc_vm_domain();
3403         if (!dmar_domain) {
3404                 printk(KERN_ERR
3405                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3406                 return -ENOMEM;
3407         }
3408         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3409                 printk(KERN_ERR
3410                         "intel_iommu_domain_init() failed\n");
3411                 vm_domain_exit(dmar_domain);
3412                 return -ENOMEM;
3413         }
3414         domain->priv = dmar_domain;
3415
3416         return 0;
3417 }
3418
3419 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3420 {
3421         struct dmar_domain *dmar_domain = domain->priv;
3422
3423         domain->priv = NULL;
3424         vm_domain_exit(dmar_domain);
3425 }
3426
3427 static int intel_iommu_attach_device(struct iommu_domain *domain,
3428                                      struct device *dev)
3429 {
3430         struct dmar_domain *dmar_domain = domain->priv;
3431         struct pci_dev *pdev = to_pci_dev(dev);
3432         struct intel_iommu *iommu;
3433         int addr_width;
3434         u64 end;
3435         int ret;
3436
3437         /* normally pdev is not mapped */
3438         if (unlikely(domain_context_mapped(pdev))) {
3439                 struct dmar_domain *old_domain;
3440
3441                 old_domain = find_domain(pdev);
3442                 if (old_domain) {
3443                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3444                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3445                                 domain_remove_one_dev_info(old_domain, pdev);
3446                         else
3447                                 domain_remove_dev_info(old_domain);
3448                 }
3449         }
3450
3451         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3452                                 pdev->devfn);
3453         if (!iommu)
3454                 return -ENODEV;
3455
3456         /* check if this iommu agaw is sufficient for max mapped address */
3457         addr_width = agaw_to_width(iommu->agaw);
3458         end = DOMAIN_MAX_ADDR(addr_width);
3459         end = end & VTD_PAGE_MASK;
3460         if (end < dmar_domain->max_addr) {
3461                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3462                        "sufficient for the mapped address (%llx)\n",
3463                        __func__, iommu->agaw, dmar_domain->max_addr);
3464                 return -EFAULT;
3465         }
3466
3467         ret = domain_add_dev_info(dmar_domain, pdev);
3468         if (ret)
3469                 return ret;
3470
3471         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3472         return ret;
3473 }
3474
3475 static void intel_iommu_detach_device(struct iommu_domain *domain,
3476                                       struct device *dev)
3477 {
3478         struct dmar_domain *dmar_domain = domain->priv;
3479         struct pci_dev *pdev = to_pci_dev(dev);
3480
3481         domain_remove_one_dev_info(dmar_domain, pdev);
3482 }
3483
3484 static int intel_iommu_map_range(struct iommu_domain *domain,
3485                                  unsigned long iova, phys_addr_t hpa,
3486                                  size_t size, int iommu_prot)
3487 {
3488         struct dmar_domain *dmar_domain = domain->priv;
3489         u64 max_addr;
3490         int addr_width;
3491         int prot = 0;
3492         int ret;
3493
3494         if (iommu_prot & IOMMU_READ)
3495                 prot |= DMA_PTE_READ;
3496         if (iommu_prot & IOMMU_WRITE)
3497                 prot |= DMA_PTE_WRITE;
3498         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3499                 prot |= DMA_PTE_SNP;
3500
3501         max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
3502         if (dmar_domain->max_addr < max_addr) {
3503                 int min_agaw;
3504                 u64 end;
3505
3506                 /* check if minimum agaw is sufficient for mapped address */
3507                 min_agaw = vm_domain_min_agaw(dmar_domain);
3508                 addr_width = agaw_to_width(min_agaw);
3509                 end = DOMAIN_MAX_ADDR(addr_width);
3510                 end = end & VTD_PAGE_MASK;
3511                 if (end < max_addr) {
3512                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3513                                "sufficient for the mapped address (%llx)\n",
3514                                __func__, min_agaw, max_addr);
3515                         return -EFAULT;
3516                 }
3517                 dmar_domain->max_addr = max_addr;
3518         }
3519
3520         ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3521         return ret;
3522 }
3523
3524 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3525                                     unsigned long iova, size_t size)
3526 {
3527         struct dmar_domain *dmar_domain = domain->priv;
3528         dma_addr_t base;
3529
3530         /* The address might not be aligned */
3531         base = iova & VTD_PAGE_MASK;
3532         size = VTD_PAGE_ALIGN(size);
3533         dma_pte_clear_range(dmar_domain, base, base + size);
3534
3535         if (dmar_domain->max_addr == base + size)
3536                 dmar_domain->max_addr = base;
3537 }
3538
3539 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3540                                             unsigned long iova)
3541 {
3542         struct dmar_domain *dmar_domain = domain->priv;
3543         struct dma_pte *pte;
3544         u64 phys = 0;
3545
3546         pte = addr_to_dma_pte(dmar_domain, iova);
3547         if (pte)
3548                 phys = dma_pte_addr(pte);
3549
3550         return phys;
3551 }
3552
3553 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3554                                       unsigned long cap)
3555 {
3556         struct dmar_domain *dmar_domain = domain->priv;
3557
3558         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3559                 return dmar_domain->iommu_snooping;
3560
3561         return 0;
3562 }
3563
3564 static struct iommu_ops intel_iommu_ops = {
3565         .domain_init    = intel_iommu_domain_init,
3566         .domain_destroy = intel_iommu_domain_destroy,
3567         .attach_dev     = intel_iommu_attach_device,
3568         .detach_dev     = intel_iommu_detach_device,
3569         .map            = intel_iommu_map_range,
3570         .unmap          = intel_iommu_unmap_range,
3571         .iova_to_phys   = intel_iommu_iova_to_phys,
3572         .domain_has_cap = intel_iommu_domain_has_cap,
3573 };
3574
3575 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3576 {
3577         /*
3578          * Mobile 4 Series Chipset neglects to set RWBF capability,
3579          * but needs it:
3580          */
3581         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3582         rwbf_quirk = 1;
3583 }
3584
3585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);