git.oblomov.eu Git - linux-2.6/blob - drivers/serial/sunzilog.c

   1 /*
   2  * sunzilog.c
   3  *
   4  * Driver for Zilog serial chips found on Sun workstations and
   5  * servers.  This driver could actually be made more generic.
   6  *
   7  * This is based on the old drivers/sbus/char/zs.c code.  A lot
   8  * of code has been simply moved over directly from there but
   9  * much has been rewritten.  Credits therefore go out to Eddie
  10  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  11  * work there.
  12  *
  13  *  Copyright (C) 2002 David S. Miller (davem@redhat.com)
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/sched.h>
  20 #include <linux/errno.h>
  21 #include <linux/delay.h>
  22 #include <linux/tty.h>
  23 #include <linux/tty_flip.h>
  24 #include <linux/major.h>
  25 #include <linux/string.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/circ_buf.h>
  30 #include <linux/serial.h>
  31 #include <linux/sysrq.h>
  32 #include <linux/console.h>
  33 #include <linux/spinlock.h>
  34 #ifdef CONFIG_SERIO
  35 #include <linux/serio.h>
  36 #endif
  37 #include <linux/init.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41 #ifdef CONFIG_SPARC64
  42 #include <asm/fhc.h>
  43 #endif
  44 #include <asm/sbus.h>
  45
  46 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  47 #define SUPPORT_SYSRQ
  48 #endif
  49
  50 #include <linux/serial_core.h>
  51
  52 #include "suncore.h"
  53 #include "sunzilog.h"
  54
  55 /* On 32-bit sparcs we need to delay after register accesses
  56  * to accommodate sun4 systems, but we do not need to flush writes.
  57  * On 64-bit sparc we only need to flush single writes to ensure
  58  * completion.
  59  */
  60 #ifndef CONFIG_SPARC64
  61 #define ZSDELAY()               udelay(5)
  62 #define ZSDELAY_LONG()          udelay(20)
  63 #define ZS_WSYNC(channel)       do { } while (0)
  64 #else
  65 #define ZSDELAY()
  66 #define ZSDELAY_LONG()
  67 #define ZS_WSYNC(__channel) \
  68         sbus_readb(&((__channel)->control))
  69 #endif
  70
  71 static int num_sunzilog;
  72 #define NUM_SUNZILOG    num_sunzilog
  73 #define NUM_CHANNELS    (NUM_SUNZILOG * 2)
  74
  75 #define KEYBOARD_LINE 0x2
  76 #define MOUSE_LINE    0x3
  77
  78 #define ZS_CLOCK                4915200 /* Zilog input clock rate. */
  79 #define ZS_CLOCK_DIVISOR        16      /* Divisor this driver uses. */
  80
  81 /*
  82  * We wrap our port structure around the generic uart_port.
  83  */
  84 struct uart_sunzilog_port {
  85         struct uart_port                port;
  86
  87         /* IRQ servicing chain.  */
  88         struct uart_sunzilog_port       *next;
  89
  90         /* Current values of Zilog write registers.  */
  91         unsigned char                   curregs[NUM_ZSREGS];
  92
  93         unsigned int                    flags;
  94 #define SUNZILOG_FLAG_CONS_KEYB         0x00000001
  95 #define SUNZILOG_FLAG_CONS_MOUSE        0x00000002
  96 #define SUNZILOG_FLAG_IS_CONS           0x00000004
  97 #define SUNZILOG_FLAG_IS_KGDB           0x00000008
  98 #define SUNZILOG_FLAG_MODEM_STATUS      0x00000010
  99 #define SUNZILOG_FLAG_IS_CHANNEL_A      0x00000020
 100 #define SUNZILOG_FLAG_REGS_HELD         0x00000040
 101 #define SUNZILOG_FLAG_TX_STOPPED        0x00000080
 102 #define SUNZILOG_FLAG_TX_ACTIVE         0x00000100
 103
 104         unsigned int cflag;
 105
 106         unsigned char                   parity_mask;
 107         unsigned char                   prev_status;
 108
 109 #ifdef CONFIG_SERIO
 110         struct serio                    *serio;
 111         int                             serio_open;
 112 #endif
 113 };
 114
 115 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel __iomem *)((PORT)->membase))
 116 #define UART_ZILOG(PORT)                ((struct uart_sunzilog_port *)(PORT))
 117
 118 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
 119 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
 120 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
 121 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
 122 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
 123 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
 124 #define ZS_REGS_HELD(UP)        ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
 125 #define ZS_TX_STOPPED(UP)       ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
 126 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
 127
 128 /* Reading and writing Zilog8530 registers.  The delays are to make this
 129  * driver work on the Sun4 which needs a settling delay after each chip
 130  * register access, other machines handle this in hardware via auxiliary
 131  * flip-flops which implement the settle time we do in software.
 132  *
 133  * The port lock must be held and local IRQs must be disabled
 134  * when {read,write}_zsreg is invoked.
 135  */
 136 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
 137                                 unsigned char reg)
 138 {
 139         unsigned char retval;
 140
 141         sbus_writeb(reg, &channel->control);
 142         ZSDELAY();
 143         retval = sbus_readb(&channel->control);
 144         ZSDELAY();
 145
 146         return retval;
 147 }
 148
 149 static void write_zsreg(struct zilog_channel __iomem *channel,
 150                         unsigned char reg, unsigned char value)
 151 {
 152         sbus_writeb(reg, &channel->control);
 153         ZSDELAY();
 154         sbus_writeb(value, &channel->control);
 155         ZSDELAY();
 156 }
 157
 158 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
 159 {
 160         int i;
 161
 162         for (i = 0; i < 32; i++) {
 163                 unsigned char regval;
 164
 165                 regval = sbus_readb(&channel->control);
 166                 ZSDELAY();
 167                 if (regval & Rx_CH_AV)
 168                         break;
 169
 170                 regval = read_zsreg(channel, R1);
 171                 sbus_readb(&channel->data);
 172                 ZSDELAY();
 173
 174                 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 175                         sbus_writeb(ERR_RES, &channel->control);
 176                         ZSDELAY();
 177                         ZS_WSYNC(channel);
 178                 }
 179         }
 180 }
 181
 182 /* This function must only be called when the TX is not busy.  The UART
 183  * port lock must be held and local interrupts disabled.
 184  */
 185 static void __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
 186 {
 187         int i;
 188
 189         /* Let pending transmits finish.  */
 190         for (i = 0; i < 1000; i++) {
 191                 unsigned char stat = read_zsreg(channel, R1);
 192                 if (stat & ALL_SNT)
 193                         break;
 194                 udelay(100);
 195         }
 196
 197         sbus_writeb(ERR_RES, &channel->control);
 198         ZSDELAY();
 199         ZS_WSYNC(channel);
 200
 201         sunzilog_clear_fifo(channel);
 202
 203         /* Disable all interrupts.  */
 204         write_zsreg(channel, R1,
 205                     regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
 206
 207         /* Set parity, sync config, stop bits, and clock divisor.  */
 208         write_zsreg(channel, R4, regs[R4]);
 209
 210         /* Set misc. TX/RX control bits.  */
 211         write_zsreg(channel, R10, regs[R10]);
 212
 213         /* Set TX/RX controls sans the enable bits.  */
 214         write_zsreg(channel, R3, regs[R3] & ~RxENAB);
 215         write_zsreg(channel, R5, regs[R5] & ~TxENAB);
 216
 217         /* Synchronous mode config.  */
 218         write_zsreg(channel, R6, regs[R6]);
 219         write_zsreg(channel, R7, regs[R7]);
 220
 221         /* Don't mess with the interrupt vector (R2, unused by us) and
 222          * master interrupt control (R9).  We make sure this is setup
 223          * properly at probe time then never touch it again.
 224          */
 225
 226         /* Disable baud generator.  */
 227         write_zsreg(channel, R14, regs[R14] & ~BRENAB);
 228
 229         /* Clock mode control.  */
 230         write_zsreg(channel, R11, regs[R11]);
 231
 232         /* Lower and upper byte of baud rate generator divisor.  */
 233         write_zsreg(channel, R12, regs[R12]);
 234         write_zsreg(channel, R13, regs[R13]);
 235
 236         /* Now rewrite R14, with BRENAB (if set).  */
 237         write_zsreg(channel, R14, regs[R14]);
 238
 239         /* External status interrupt control.  */
 240         write_zsreg(channel, R15, regs[R15]);
 241
 242         /* Reset external status interrupts.  */
 243         write_zsreg(channel, R0, RES_EXT_INT);
 244         write_zsreg(channel, R0, RES_EXT_INT);
 245
 246         /* Rewrite R3/R5, this time without enables masked.  */
 247         write_zsreg(channel, R3, regs[R3]);
 248         write_zsreg(channel, R5, regs[R5]);
 249
 250         /* Rewrite R1, this time without IRQ enabled masked.  */
 251         write_zsreg(channel, R1, regs[R1]);
 252 }
 253
 254 /* Reprogram the Zilog channel HW registers with the copies found in the
 255  * software state struct.  If the transmitter is busy, we defer this update
 256  * until the next TX complete interrupt.  Else, we do it right now.
 257  *
 258  * The UART port lock must be held and local interrupts disabled.
 259  */
 260 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
 261                                        struct zilog_channel __iomem *channel)
 262 {
 263         if (!ZS_REGS_HELD(up)) {
 264                 if (ZS_TX_ACTIVE(up)) {
 265                         up->flags |= SUNZILOG_FLAG_REGS_HELD;
 266                 } else {
 267                         __load_zsregs(channel, up->curregs);
 268                 }
 269         }
 270 }
 271
 272 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
 273 {
 274         unsigned int cur_cflag = up->cflag;
 275         int brg, new_baud;
 276
 277         up->cflag &= ~CBAUD;
 278         up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
 279
 280         brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 281         up->curregs[R12] = (brg & 0xff);
 282         up->curregs[R13] = (brg >> 8) & 0xff;
 283         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
 284 }
 285
 286 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
 287                                          unsigned char ch, int is_break,
 288                                          struct pt_regs *regs)
 289 {
 290         if (ZS_IS_KEYB(up)) {
 291                 /* Stop-A is handled by drivers/char/keyboard.c now. */
 292 #ifdef CONFIG_SERIO
 293                 if (up->serio_open)
 294                         serio_interrupt(up->serio, ch, 0, regs);
 295 #endif
 296         } else if (ZS_IS_MOUSE(up)) {
 297                 int ret = suncore_mouse_baud_detection(ch, is_break);
 298
 299                 switch (ret) {
 300                 case 2:
 301                         sunzilog_change_mouse_baud(up);
 302                         /* fallthru */
 303                 case 1:
 304                         break;
 305
 306                 case 0:
 307 #ifdef CONFIG_SERIO
 308                         if (up->serio_open)
 309                                 serio_interrupt(up->serio, ch, 0, regs);
 310 #endif
 311                         break;
 312                 };
 313         }
 314 }
 315
 316 static struct tty_struct *
 317 sunzilog_receive_chars(struct uart_sunzilog_port *up,
 318                        struct zilog_channel __iomem *channel,
 319                        struct pt_regs *regs)
 320 {
 321         struct tty_struct *tty;
 322         unsigned char ch, r1, flag;
 323
 324         tty = NULL;
 325         if (up->port.info != NULL &&            /* Unopened serial console */
 326             up->port.info->tty != NULL)         /* Keyboard || mouse */
 327                 tty = up->port.info->tty;
 328
 329         for (;;) {
 330
 331                 r1 = read_zsreg(channel, R1);
 332                 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 333                         sbus_writeb(ERR_RES, &channel->control);
 334                         ZSDELAY();
 335                         ZS_WSYNC(channel);
 336                 }
 337
 338                 ch = sbus_readb(&channel->control);
 339                 ZSDELAY();
 340
 341                 /* This funny hack depends upon BRK_ABRT not interfering
 342                  * with the other bits we care about in R1.
 343                  */
 344                 if (ch & BRK_ABRT)
 345                         r1 |= BRK_ABRT;
 346
 347                 if (!(ch & Rx_CH_AV))
 348                         break;
 349
 350                 ch = sbus_readb(&channel->data);
 351                 ZSDELAY();
 352
 353                 ch &= up->parity_mask;
 354
 355                 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
 356                         sunzilog_kbdms_receive_chars(up, ch, 0, regs);
 357                         continue;
 358                 }
 359
 360                 if (tty == NULL) {
 361                         uart_handle_sysrq_char(&up->port, ch, regs);
 362                         continue;
 363                 }
 364
 365                 /* A real serial line, record the character and status.  */
 366                 flag = TTY_NORMAL;
 367                 up->port.icount.rx++;
 368                 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
 369                         if (r1 & BRK_ABRT) {
 370                                 r1 &= ~(PAR_ERR | CRC_ERR);
 371                                 up->port.icount.brk++;
 372                                 if (uart_handle_break(&up->port))
 373                                         continue;
 374                         }
 375                         else if (r1 & PAR_ERR)
 376                                 up->port.icount.parity++;
 377                         else if (r1 & CRC_ERR)
 378                                 up->port.icount.frame++;
 379                         if (r1 & Rx_OVR)
 380                                 up->port.icount.overrun++;
 381                         r1 &= up->port.read_status_mask;
 382                         if (r1 & BRK_ABRT)
 383                                 flag = TTY_BREAK;
 384                         else if (r1 & PAR_ERR)
 385                                 flag = TTY_PARITY;
 386                         else if (r1 & CRC_ERR)
 387                                 flag = TTY_FRAME;
 388                 }
 389                 if (uart_handle_sysrq_char(&up->port, ch, regs))
 390                         continue;
 391
 392                 if (up->port.ignore_status_mask == 0xff ||
 393                     (r1 & up->port.ignore_status_mask) == 0) {
 394                         tty_insert_flip_char(tty, ch, flag);
 395                 }
 396                 if (r1 & Rx_OVR)
 397                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 398         }
 399
 400         return tty;
 401 }
 402
 403 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
 404                                    struct zilog_channel __iomem *channel,
 405                                    struct pt_regs *regs)
 406 {
 407         unsigned char status;
 408
 409         status = sbus_readb(&channel->control);
 410         ZSDELAY();
 411
 412         sbus_writeb(RES_EXT_INT, &channel->control);
 413         ZSDELAY();
 414         ZS_WSYNC(channel);
 415
 416         if (status & BRK_ABRT) {
 417                 if (ZS_IS_MOUSE(up))
 418                         sunzilog_kbdms_receive_chars(up, 0, 1, regs);
 419                 if (ZS_IS_CONS(up)) {
 420                         /* Wait for BREAK to deassert to avoid potentially
 421                          * confusing the PROM.
 422                          */
 423                         while (1) {
 424                                 status = sbus_readb(&channel->control);
 425                                 ZSDELAY();
 426                                 if (!(status & BRK_ABRT))
 427                                         break;
 428                         }
 429                         sun_do_break();
 430                         return;
 431                 }
 432         }
 433
 434         if (ZS_WANTS_MODEM_STATUS(up)) {
 435                 if (status & SYNC)
 436                         up->port.icount.dsr++;
 437
 438                 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
 439                  * But it does not tell us which bit has changed, we have to keep
 440                  * track of this ourselves.
 441                  */
 442                 if ((status ^ up->prev_status) ^ DCD)
 443                         uart_handle_dcd_change(&up->port,
 444                                                (status & DCD));
 445                 if ((status ^ up->prev_status) ^ CTS)
 446                         uart_handle_cts_change(&up->port,
 447                                                (status & CTS));
 448
 449                 wake_up_interruptible(&up->port.info->delta_msr_wait);
 450         }
 451
 452         up->prev_status = status;
 453 }
 454
 455 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
 456                                     struct zilog_channel __iomem *channel)
 457 {
 458         struct circ_buf *xmit;
 459
 460         if (ZS_IS_CONS(up)) {
 461                 unsigned char status = sbus_readb(&channel->control);
 462                 ZSDELAY();
 463
 464                 /* TX still busy?  Just wait for the next TX done interrupt.
 465                  *
 466                  * It can occur because of how we do serial console writes.  It would
 467                  * be nice to transmit console writes just like we normally would for
 468                  * a TTY line. (ie. buffered and TX interrupt driven).  That is not
 469                  * easy because console writes cannot sleep.  One solution might be
 470                  * to poll on enough port->xmit space becomming free.  -DaveM
 471                  */
 472                 if (!(status & Tx_BUF_EMP))
 473                         return;
 474         }
 475
 476         up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
 477
 478         if (ZS_REGS_HELD(up)) {
 479                 __load_zsregs(channel, up->curregs);
 480                 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
 481         }
 482
 483         if (ZS_TX_STOPPED(up)) {
 484                 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 485                 goto ack_tx_int;
 486         }
 487
 488         if (up->port.x_char) {
 489                 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 490                 sbus_writeb(up->port.x_char, &channel->data);
 491                 ZSDELAY();
 492                 ZS_WSYNC(channel);
 493
 494                 up->port.icount.tx++;
 495                 up->port.x_char = 0;
 496                 return;
 497         }
 498
 499         if (up->port.info == NULL)
 500                 goto ack_tx_int;
 501         xmit = &up->port.info->xmit;
 502         if (uart_circ_empty(xmit))
 503                 goto ack_tx_int;
 504
 505         if (uart_tx_stopped(&up->port))
 506                 goto ack_tx_int;
 507
 508         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 509         sbus_writeb(xmit->buf[xmit->tail], &channel->data);
 510         ZSDELAY();
 511         ZS_WSYNC(channel);
 512
 513         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 514         up->port.icount.tx++;
 515
 516         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 517                 uart_write_wakeup(&up->port);
 518
 519         return;
 520
 521 ack_tx_int:
 522         sbus_writeb(RES_Tx_P, &channel->control);
 523         ZSDELAY();
 524         ZS_WSYNC(channel);
 525 }
 526
 527 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 528 {
 529         struct uart_sunzilog_port *up = dev_id;
 530
 531         while (up) {
 532                 struct zilog_channel __iomem *channel
 533                         = ZILOG_CHANNEL_FROM_PORT(&up->port);
 534                 struct tty_struct *tty;
 535                 unsigned char r3;
 536
 537                 spin_lock(&up->port.lock);
 538                 r3 = read_zsreg(channel, R3);
 539
 540                 /* Channel A */
 541                 tty = NULL;
 542                 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 543                         sbus_writeb(RES_H_IUS, &channel->control);
 544                         ZSDELAY();
 545                         ZS_WSYNC(channel);
 546
 547                         if (r3 & CHARxIP)
 548                                 tty = sunzilog_receive_chars(up, channel, regs);
 549                         if (r3 & CHAEXT)
 550                                 sunzilog_status_handle(up, channel, regs);
 551                         if (r3 & CHATxIP)
 552                                 sunzilog_transmit_chars(up, channel);
 553                 }
 554                 spin_unlock(&up->port.lock);
 555
 556                 if (tty)
 557                         tty_flip_buffer_push(tty);
 558
 559                 /* Channel B */
 560                 up = up->next;
 561                 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 562
 563                 spin_lock(&up->port.lock);
 564                 tty = NULL;
 565                 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
 566                         sbus_writeb(RES_H_IUS, &channel->control);
 567                         ZSDELAY();
 568                         ZS_WSYNC(channel);
 569
 570                         if (r3 & CHBRxIP)
 571                                 tty = sunzilog_receive_chars(up, channel, regs);
 572                         if (r3 & CHBEXT)
 573                                 sunzilog_status_handle(up, channel, regs);
 574                         if (r3 & CHBTxIP)
 575                                 sunzilog_transmit_chars(up, channel);
 576                 }
 577                 spin_unlock(&up->port.lock);
 578
 579                 if (tty)
 580                         tty_flip_buffer_push(tty);
 581
 582                 up = up->next;
 583         }
 584
 585         return IRQ_HANDLED;
 586 }
 587
 588 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
 589  * port lock, it is acquired here.
 590  */
 591 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
 592 {
 593         struct zilog_channel __iomem *channel;
 594         unsigned char status;
 595
 596         channel = ZILOG_CHANNEL_FROM_PORT(port);
 597         status = sbus_readb(&channel->control);
 598         ZSDELAY();
 599
 600         return status;
 601 }
 602
 603 /* The port lock is not held.  */
 604 static unsigned int sunzilog_tx_empty(struct uart_port *port)
 605 {
 606         unsigned long flags;
 607         unsigned char status;
 608         unsigned int ret;
 609
 610         spin_lock_irqsave(&port->lock, flags);
 611
 612         status = sunzilog_read_channel_status(port);
 613
 614         spin_unlock_irqrestore(&port->lock, flags);
 615
 616         if (status & Tx_BUF_EMP)
 617                 ret = TIOCSER_TEMT;
 618         else
 619                 ret = 0;
 620
 621         return ret;
 622 }
 623
 624 /* The port lock is held and interrupts are disabled.  */
 625 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
 626 {
 627         unsigned char status;
 628         unsigned int ret;
 629
 630         status = sunzilog_read_channel_status(port);
 631
 632         ret = 0;
 633         if (status & DCD)
 634                 ret |= TIOCM_CAR;
 635         if (status & SYNC)
 636                 ret |= TIOCM_DSR;
 637         if (status & CTS)
 638                 ret |= TIOCM_CTS;
 639
 640         return ret;
 641 }
 642
 643 /* The port lock is held and interrupts are disabled.  */
 644 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 645 {
 646         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 647         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 648         unsigned char set_bits, clear_bits;
 649
 650         set_bits = clear_bits = 0;
 651
 652         if (mctrl & TIOCM_RTS)
 653                 set_bits |= RTS;
 654         else
 655                 clear_bits |= RTS;
 656         if (mctrl & TIOCM_DTR)
 657                 set_bits |= DTR;
 658         else
 659                 clear_bits |= DTR;
 660
 661         /* NOTE: Not subject to 'transmitter active' rule.  */
 662         up->curregs[R5] |= set_bits;
 663         up->curregs[R5] &= ~clear_bits;
 664         write_zsreg(channel, R5, up->curregs[R5]);
 665 }
 666
 667 /* The port lock is held and interrupts are disabled.  */
 668 static void sunzilog_stop_tx(struct uart_port *port)
 669 {
 670         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 671
 672         up->flags |= SUNZILOG_FLAG_TX_STOPPED;
 673 }
 674
 675 /* The port lock is held and interrupts are disabled.  */
 676 static void sunzilog_start_tx(struct uart_port *port)
 677 {
 678         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 679         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 680         unsigned char status;
 681
 682         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 683         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 684
 685         status = sbus_readb(&channel->control);
 686         ZSDELAY();
 687
 688         /* TX busy?  Just wait for the TX done interrupt.  */
 689         if (!(status & Tx_BUF_EMP))
 690                 return;
 691
 692         /* Send the first character to jump-start the TX done
 693          * IRQ sending engine.
 694          */
 695         if (port->x_char) {
 696                 sbus_writeb(port->x_char, &channel->data);
 697                 ZSDELAY();
 698                 ZS_WSYNC(channel);
 699
 700                 port->icount.tx++;
 701                 port->x_char = 0;
 702         } else {
 703                 struct circ_buf *xmit = &port->info->xmit;
 704
 705                 sbus_writeb(xmit->buf[xmit->tail], &channel->data);
 706                 ZSDELAY();
 707                 ZS_WSYNC(channel);
 708
 709                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 710                 port->icount.tx++;
 711
 712                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 713                         uart_write_wakeup(&up->port);
 714         }
 715 }
 716
 717 /* The port lock is held.  */
 718 static void sunzilog_stop_rx(struct uart_port *port)
 719 {
 720         struct uart_sunzilog_port *up = UART_ZILOG(port);
 721         struct zilog_channel __iomem *channel;
 722
 723         if (ZS_IS_CONS(up))
 724                 return;
 725
 726         channel = ZILOG_CHANNEL_FROM_PORT(port);
 727
 728         /* Disable all RX interrupts.  */
 729         up->curregs[R1] &= ~RxINT_MASK;
 730         sunzilog_maybe_update_regs(up, channel);
 731 }
 732
 733 /* The port lock is held.  */
 734 static void sunzilog_enable_ms(struct uart_port *port)
 735 {
 736         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 737         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 738         unsigned char new_reg;
 739
 740         new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
 741         if (new_reg != up->curregs[R15]) {
 742                 up->curregs[R15] = new_reg;
 743
 744                 /* NOTE: Not subject to 'transmitter active' rule.  */
 745                 write_zsreg(channel, R15, up->curregs[R15]);
 746         }
 747 }
 748
 749 /* The port lock is not held.  */
 750 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
 751 {
 752         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 753         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 754         unsigned char set_bits, clear_bits, new_reg;
 755         unsigned long flags;
 756
 757         set_bits = clear_bits = 0;
 758
 759         if (break_state)
 760                 set_bits |= SND_BRK;
 761         else
 762                 clear_bits |= SND_BRK;
 763
 764         spin_lock_irqsave(&port->lock, flags);
 765
 766         new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
 767         if (new_reg != up->curregs[R5]) {
 768                 up->curregs[R5] = new_reg;
 769
 770                 /* NOTE: Not subject to 'transmitter active' rule.  */
 771                 write_zsreg(channel, R5, up->curregs[R5]);
 772         }
 773
 774         spin_unlock_irqrestore(&port->lock, flags);
 775 }
 776
 777 static void __sunzilog_startup(struct uart_sunzilog_port *up)
 778 {
 779         struct zilog_channel __iomem *channel;
 780
 781         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 782         up->prev_status = sbus_readb(&channel->control);
 783
 784         /* Enable receiver and transmitter.  */
 785         up->curregs[R3] |= RxENAB;
 786         up->curregs[R5] |= TxENAB;
 787
 788         up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
 789         sunzilog_maybe_update_regs(up, channel);
 790 }
 791
 792 static int sunzilog_startup(struct uart_port *port)
 793 {
 794         struct uart_sunzilog_port *up = UART_ZILOG(port);
 795         unsigned long flags;
 796
 797         if (ZS_IS_CONS(up))
 798                 return 0;
 799
 800         spin_lock_irqsave(&port->lock, flags);
 801         __sunzilog_startup(up);
 802         spin_unlock_irqrestore(&port->lock, flags);
 803         return 0;
 804 }
 805
 806 /*
 807  * The test for ZS_IS_CONS is explained by the following e-mail:
 808  *****
 809  * From: Russell King <rmk@arm.linux.org.uk>
 810  * Date: Sun, 8 Dec 2002 10:18:38 +0000
 811  *
 812  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
 813  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
 814  * > and I noticed that something is not right with reference
 815  * > counting in this case. It seems that when the console
 816  * > is open by kernel initially, this is not accounted
 817  * > as an open, and uart_startup is not called.
 818  *
 819  * That is correct.  We are unable to call uart_startup when the serial
 820  * console is initialised because it may need to allocate memory (as
 821  * request_irq does) and the memory allocators may not have been
 822  * initialised.
 823  *
 824  * 1. initialise the port into a state where it can send characters in the
 825  *    console write method.
 826  *
 827  * 2. don't do the actual hardware shutdown in your shutdown() method (but
 828  *    do the normal software shutdown - ie, free irqs etc)
 829  *****
 830  */
 831 static void sunzilog_shutdown(struct uart_port *port)
 832 {
 833         struct uart_sunzilog_port *up = UART_ZILOG(port);
 834         struct zilog_channel __iomem *channel;
 835         unsigned long flags;
 836
 837         if (ZS_IS_CONS(up))
 838                 return;
 839
 840         spin_lock_irqsave(&port->lock, flags);
 841
 842         channel = ZILOG_CHANNEL_FROM_PORT(port);
 843
 844         /* Disable receiver and transmitter.  */
 845         up->curregs[R3] &= ~RxENAB;
 846         up->curregs[R5] &= ~TxENAB;
 847
 848         /* Disable all interrupts and BRK assertion.  */
 849         up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
 850         up->curregs[R5] &= ~SND_BRK;
 851         sunzilog_maybe_update_regs(up, channel);
 852
 853         spin_unlock_irqrestore(&port->lock, flags);
 854 }
 855
 856 /* Shared by TTY driver and serial console setup.  The port lock is held
 857  * and local interrupts are disabled.
 858  */
 859 static void
 860 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
 861                        unsigned int iflag, int brg)
 862 {
 863
 864         up->curregs[R10] = NRZ;
 865         up->curregs[R11] = TCBR | RCBR;
 866
 867         /* Program BAUD and clock source. */
 868         up->curregs[R4] &= ~XCLK_MASK;
 869         up->curregs[R4] |= X16CLK;
 870         up->curregs[R12] = brg & 0xff;
 871         up->curregs[R13] = (brg >> 8) & 0xff;
 872         up->curregs[R14] = BRSRC | BRENAB;
 873
 874         /* Character size, stop bits, and parity. */
 875         up->curregs[3] &= ~RxN_MASK;
 876         up->curregs[5] &= ~TxN_MASK;
 877         switch (cflag & CSIZE) {
 878         case CS5:
 879                 up->curregs[3] |= Rx5;
 880                 up->curregs[5] |= Tx5;
 881                 up->parity_mask = 0x1f;
 882                 break;
 883         case CS6:
 884                 up->curregs[3] |= Rx6;
 885                 up->curregs[5] |= Tx6;
 886                 up->parity_mask = 0x3f;
 887                 break;
 888         case CS7:
 889                 up->curregs[3] |= Rx7;
 890                 up->curregs[5] |= Tx7;
 891                 up->parity_mask = 0x7f;
 892                 break;
 893         case CS8:
 894         default:
 895                 up->curregs[3] |= Rx8;
 896                 up->curregs[5] |= Tx8;
 897                 up->parity_mask = 0xff;
 898                 break;
 899         };
 900         up->curregs[4] &= ~0x0c;
 901         if (cflag & CSTOPB)
 902                 up->curregs[4] |= SB2;
 903         else
 904                 up->curregs[4] |= SB1;
 905         if (cflag & PARENB)
 906                 up->curregs[4] |= PAR_ENAB;
 907         else
 908                 up->curregs[4] &= ~PAR_ENAB;
 909         if (!(cflag & PARODD))
 910                 up->curregs[4] |= PAR_EVEN;
 911         else
 912                 up->curregs[4] &= ~PAR_EVEN;
 913
 914         up->port.read_status_mask = Rx_OVR;
 915         if (iflag & INPCK)
 916                 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
 917         if (iflag & (BRKINT | PARMRK))
 918                 up->port.read_status_mask |= BRK_ABRT;
 919
 920         up->port.ignore_status_mask = 0;
 921         if (iflag & IGNPAR)
 922                 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
 923         if (iflag & IGNBRK) {
 924                 up->port.ignore_status_mask |= BRK_ABRT;
 925                 if (iflag & IGNPAR)
 926                         up->port.ignore_status_mask |= Rx_OVR;
 927         }
 928
 929         if ((cflag & CREAD) == 0)
 930                 up->port.ignore_status_mask = 0xff;
 931 }
 932
 933 /* The port lock is not held.  */
 934 static void
 935 sunzilog_set_termios(struct uart_port *port, struct termios *termios,
 936                      struct termios *old)
 937 {
 938         struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
 939         unsigned long flags;
 940         int baud, brg;
 941
 942         baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
 943
 944         spin_lock_irqsave(&up->port.lock, flags);
 945
 946         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 947
 948         sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
 949
 950         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 951                 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
 952         else
 953                 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
 954
 955         up->cflag = termios->c_cflag;
 956
 957         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
 958
 959         uart_update_timeout(port, termios->c_cflag, baud);
 960
 961         spin_unlock_irqrestore(&up->port.lock, flags);
 962 }
 963
 964 static const char *sunzilog_type(struct uart_port *port)
 965 {
 966         return "SunZilog";
 967 }
 968
 969 /* We do not request/release mappings of the registers here, this
 970  * happens at early serial probe time.
 971  */
 972 static void sunzilog_release_port(struct uart_port *port)
 973 {
 974 }
 975
 976 static int sunzilog_request_port(struct uart_port *port)
 977 {
 978         return 0;
 979 }
 980
 981 /* These do not need to do anything interesting either.  */
 982 static void sunzilog_config_port(struct uart_port *port, int flags)
 983 {
 984 }
 985
 986 /* We do not support letting the user mess with the divisor, IRQ, etc. */
 987 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
 988 {
 989         return -EINVAL;
 990 }
 991
 992 static struct uart_ops sunzilog_pops = {
 993         .tx_empty       =       sunzilog_tx_empty,
 994         .set_mctrl      =       sunzilog_set_mctrl,
 995         .get_mctrl      =       sunzilog_get_mctrl,
 996         .stop_tx        =       sunzilog_stop_tx,
 997         .start_tx       =       sunzilog_start_tx,
 998         .stop_rx        =       sunzilog_stop_rx,
 999         .enable_ms      =       sunzilog_enable_ms,
1000         .break_ctl      =       sunzilog_break_ctl,
1001         .startup        =       sunzilog_startup,
1002         .shutdown       =       sunzilog_shutdown,
1003         .set_termios    =       sunzilog_set_termios,
1004         .type           =       sunzilog_type,
1005         .release_port   =       sunzilog_release_port,
1006         .request_port   =       sunzilog_request_port,
1007         .config_port    =       sunzilog_config_port,
1008         .verify_port    =       sunzilog_verify_port,
1009 };
1010
1011 static struct uart_sunzilog_port *sunzilog_port_table;
1012 static struct zilog_layout __iomem **sunzilog_chip_regs;
1013
1014 static struct uart_sunzilog_port *sunzilog_irq_chain;
1015 static int zilog_irq = -1;
1016
1017 static struct uart_driver sunzilog_reg = {
1018         .owner          =       THIS_MODULE,
1019         .driver_name    =       "ttyS",
1020         .devfs_name     =       "tts/",
1021         .dev_name       =       "ttyS",
1022         .major          =       TTY_MAJOR,
1023 };
1024
1025 static void * __init alloc_one_table(unsigned long size)
1026 {
1027         void *ret;
1028
1029         ret = kmalloc(size, GFP_KERNEL);
1030         if (ret != NULL)
1031                 memset(ret, 0, size);
1032
1033         return ret;
1034 }
1035
1036 static void __init sunzilog_alloc_tables(void)
1037 {
1038         sunzilog_port_table =
1039                 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_sunzilog_port));
1040         sunzilog_chip_regs =
1041                 alloc_one_table(NUM_SUNZILOG * sizeof(struct zilog_layout __iomem *));
1042
1043         if (sunzilog_port_table == NULL || sunzilog_chip_regs == NULL) {
1044                 prom_printf("SunZilog: Cannot allocate tables.\n");
1045                 prom_halt();
1046         }
1047 }
1048
1049 #ifdef CONFIG_SPARC64
1050
1051 /* We used to attempt to use the address property of the Zilog device node
1052  * but that totally is not necessary on sparc64.
1053  */
1054 static struct zilog_layout __iomem * __init get_zs_sun4u(int chip, int zsnode)
1055 {
1056         void __iomem *mapped_addr;
1057         unsigned int sun4u_ino;
1058         struct sbus_bus *sbus = NULL;
1059         struct sbus_dev *sdev = NULL;
1060         int err;
1061
1062         if (central_bus == NULL) {
1063                 for_each_sbus(sbus) {
1064                         for_each_sbusdev(sdev, sbus) {
1065                                 if (sdev->prom_node == zsnode)
1066                                         goto found;
1067                         }
1068                 }
1069         }
1070  found:
1071         if (sdev == NULL && central_bus == NULL) {
1072                 prom_printf("SunZilog: sdev&&central == NULL for "
1073                             "Zilog %d in get_zs_sun4u.\n", chip);
1074                 prom_halt();
1075         }
1076         if (central_bus == NULL) {
1077                 mapped_addr =
1078                         sbus_ioremap(&sdev->resource[0], 0,
1079                                      PAGE_SIZE,
1080                                      "Zilog Registers");
1081         } else {
1082                 struct linux_prom_registers zsregs[1];
1083
1084                 err = prom_getproperty(zsnode, "reg",
1085                                        (char *) &zsregs[0],
1086                                        sizeof(zsregs));
1087                 if (err == -1) {
1088                         prom_printf("SunZilog: Cannot map "
1089                                     "Zilog %d regs on "
1090                                     "central bus.\n", chip);
1091                         prom_halt();
1092                 }
1093                 apply_fhc_ranges(central_bus->child,
1094                                  &zsregs[0], 1);
1095                 apply_central_ranges(central_bus, &zsregs[0], 1);
1096                 mapped_addr = (void __iomem *)
1097                         ((((u64)zsregs[0].which_io)<<32UL) |
1098                         ((u64)zsregs[0].phys_addr));
1099         }
1100
1101         if (zilog_irq == -1) {
1102                 if (central_bus) {
1103                         unsigned long iclr, imap;
1104
1105                         iclr = central_bus->child->fhc_regs.uregs
1106                                 + FHC_UREGS_ICLR;
1107                         imap = central_bus->child->fhc_regs.uregs
1108                                 + FHC_UREGS_IMAP;
1109                         zilog_irq = build_irq(0, iclr, imap);
1110                 } else {
1111                         err = prom_getproperty(zsnode, "interrupts",
1112                                                (char *) &sun4u_ino,
1113                                                sizeof(sun4u_ino));
1114                         zilog_irq = sbus_build_irq(sbus_root, sun4u_ino);
1115                 }
1116         }
1117
1118         return (struct zilog_layout __iomem *) mapped_addr;
1119 }
1120 #else /* CONFIG_SPARC64 */
1121
1122 /*
1123  * XXX The sun4d case is utterly screwed: it tries to re-walk the tree
1124  * (for the 3rd time) in order to find bootbus and cpu. Streamline it.
1125  */
1126 static struct zilog_layout __iomem * __init get_zs_sun4cmd(int chip, int node)
1127 {
1128         struct linux_prom_irqs irq_info[2];
1129         void __iomem *mapped_addr = NULL;
1130         int zsnode, cpunode, bbnode;
1131         struct linux_prom_registers zsreg[4];
1132         struct resource res;
1133
1134         if (sparc_cpu_model == sun4d) {
1135                 int walk;
1136
1137                 zsnode = 0;
1138                 bbnode = 0;
1139                 cpunode = 0;
1140                 for (walk = prom_getchild(prom_root_node);
1141                      (walk = prom_searchsiblings(walk, "cpu-unit")) != 0;
1142                      walk = prom_getsibling(walk)) {
1143                         bbnode = prom_getchild(walk);
1144                         if (bbnode &&
1145                             (bbnode = prom_searchsiblings(bbnode, "bootbus"))) {
1146                                 if ((zsnode = prom_getchild(bbnode)) == node) {
1147                                         cpunode = walk;
1148                                         break;
1149                                 }
1150                         }
1151                 }
1152                 if (!walk) {
1153                         prom_printf("SunZilog: Cannot find the %d'th bootbus on sun4d.\n",
1154                                     (chip / 2));
1155                         prom_halt();
1156                 }
1157
1158                 if (prom_getproperty(zsnode, "reg",
1159                                      (char *) zsreg, sizeof(zsreg)) == -1) {
1160                         prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1161                         prom_halt();
1162                 }
1163                 /* XXX Looks like an off by one? */
1164                 prom_apply_generic_ranges(bbnode, cpunode, zsreg, 1);
1165                 res.start = zsreg[0].phys_addr;
1166                 res.end = res.start + (8 - 1);
1167                 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1168                 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1169
1170         } else {
1171                 zsnode = node;
1172
1173 #if 0 /* XXX When was this used? */
1174                 if (prom_getintdefault(zsnode, "slave", -1) != chipid) {
1175                         zsnode = prom_getsibling(zsnode);
1176                         continue;
1177                 }
1178 #endif
1179
1180                 /*
1181                  * "address" is only present on ports that OBP opened
1182                  * (from Mitch Bradley's "Hitchhiker's Guide to OBP").
1183                  * We do not use it.
1184                  */
1185
1186                 if (prom_getproperty(zsnode, "reg",
1187                                      (char *) zsreg, sizeof(zsreg)) == -1) {
1188                         prom_printf("SunZilog: Cannot map Zilog %d\n", chip);
1189                         prom_halt();
1190                 }
1191                 if (sparc_cpu_model == sun4m)   /* Crude. Pass parent. XXX */
1192                         prom_apply_obio_ranges(zsreg, 1);
1193                 res.start = zsreg[0].phys_addr;
1194                 res.end = res.start + (8 - 1);
1195                 res.flags = zsreg[0].which_io | IORESOURCE_IO;
1196                 mapped_addr = sbus_ioremap(&res, 0, 8, "Zilog Serial");
1197         }
1198
1199         if (prom_getproperty(zsnode, "intr",
1200                              (char *) irq_info, sizeof(irq_info))
1201                     % sizeof(struct linux_prom_irqs)) {
1202                 prom_printf("SunZilog: Cannot get IRQ property for Zilog %d.\n",
1203                             chip);
1204                 prom_halt();
1205         }
1206         if (zilog_irq == -1) {
1207                 zilog_irq = irq_info[0].pri;
1208         } else if (zilog_irq != irq_info[0].pri) {
1209                 /* XXX. Dumb. Should handle per-chip IRQ, for add-ons. */
1210                 prom_printf("SunZilog: Inconsistent IRQ layout for Zilog %d.\n",
1211                             chip);
1212                 prom_halt();
1213         }
1214
1215         return (struct zilog_layout __iomem *) mapped_addr;
1216 }
1217 #endif /* !(CONFIG_SPARC64) */
1218
1219 /* Get the address of the registers for SunZilog instance CHIP.  */
1220 static struct zilog_layout __iomem * __init get_zs(int chip, int node)
1221 {
1222         if (chip < 0 || chip >= NUM_SUNZILOG) {
1223                 prom_printf("SunZilog: Illegal chip number %d in get_zs.\n", chip);
1224                 prom_halt();
1225         }
1226
1227 #ifdef CONFIG_SPARC64
1228         return get_zs_sun4u(chip, node);
1229 #else
1230
1231         if (sparc_cpu_model == sun4) {
1232                 struct resource res;
1233
1234                 /* Not probe-able, hard code it. */
1235                 switch (chip) {
1236                 case 0:
1237                         res.start = 0xf1000000;
1238                         break;
1239                 case 1:
1240                         res.start = 0xf0000000;
1241                         break;
1242                 };
1243                 zilog_irq = 12;
1244                 res.end = (res.start + (8 - 1));
1245                 res.flags = IORESOURCE_IO;
1246                 return sbus_ioremap(&res, 0, 8, "SunZilog");
1247         }
1248
1249         return get_zs_sun4cmd(chip, node);
1250 #endif
1251 }
1252
1253 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1254
1255 static void sunzilog_putchar(struct uart_port *port, int ch)
1256 {
1257         struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
1258         int loops = ZS_PUT_CHAR_MAX_DELAY;
1259
1260         /* This is a timed polling loop so do not switch the explicit
1261          * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1262          */
1263         do {
1264                 unsigned char val = sbus_readb(&channel->control);
1265                 if (val & Tx_BUF_EMP) {
1266                         ZSDELAY();
1267                         break;
1268                 }
1269                 udelay(5);
1270         } while (--loops);
1271
1272         sbus_writeb(ch, &channel->data);
1273         ZSDELAY();
1274         ZS_WSYNC(channel);
1275 }
1276
1277 #ifdef CONFIG_SERIO
1278
1279 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1280
1281 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1282 {
1283         struct uart_sunzilog_port *up = serio->port_data;
1284         unsigned long flags;
1285
1286         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1287
1288         sunzilog_putchar(&up->port, ch);
1289
1290         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1291
1292         return 0;
1293 }
1294
1295 static int sunzilog_serio_open(struct serio *serio)
1296 {
1297         struct uart_sunzilog_port *up = serio->port_data;
1298         unsigned long flags;
1299         int ret;
1300
1301         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1302         if (!up->serio_open) {
1303                 up->serio_open = 1;
1304                 ret = 0;
1305         } else
1306                 ret = -EBUSY;
1307         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1308
1309         return ret;
1310 }
1311
1312 static void sunzilog_serio_close(struct serio *serio)
1313 {
1314         struct uart_sunzilog_port *up = serio->port_data;
1315         unsigned long flags;
1316
1317         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1318         up->serio_open = 0;
1319         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1320 }
1321
1322 #endif /* CONFIG_SERIO */
1323
1324 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1325 static void
1326 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1327 {
1328         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1329         unsigned long flags;
1330
1331         spin_lock_irqsave(&up->port.lock, flags);
1332         uart_console_write(&up->port, s, count, sunzilog_putchar);
1333         udelay(2);
1334         spin_unlock_irqrestore(&up->port.lock, flags);
1335 }
1336
1337 static int __init sunzilog_console_setup(struct console *con, char *options)
1338 {
1339         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1340         unsigned long flags;
1341         int baud, brg;
1342
1343         printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1344                (sunzilog_reg.minor - 64) + con->index, con->index);
1345
1346         /* Get firmware console settings.  */
1347         sunserial_console_termios(con);
1348
1349         /* Firmware console speed is limited to 150-->38400 baud so
1350          * this hackish cflag thing is OK.
1351          */
1352         switch (con->cflag & CBAUD) {
1353         case B150: baud = 150; break;
1354         case B300: baud = 300; break;
1355         case B600: baud = 600; break;
1356         case B1200: baud = 1200; break;
1357         case B2400: baud = 2400; break;
1358         case B4800: baud = 4800; break;
1359         default: case B9600: baud = 9600; break;
1360         case B19200: baud = 19200; break;
1361         case B38400: baud = 38400; break;
1362         };
1363
1364         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1365
1366         spin_lock_irqsave(&up->port.lock, flags);
1367
1368         up->curregs[R15] = BRKIE;
1369         sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1370
1371         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1372         __sunzilog_startup(up);
1373
1374         spin_unlock_irqrestore(&up->port.lock, flags);
1375
1376         return 0;
1377 }
1378
1379 static struct console sunzilog_console = {
1380         .name   =       "ttyS",
1381         .write  =       sunzilog_console_write,
1382         .device =       uart_console_device,
1383         .setup  =       sunzilog_console_setup,
1384         .flags  =       CON_PRINTBUFFER,
1385         .index  =       -1,
1386         .data   =       &sunzilog_reg,
1387 };
1388
1389 static int __init sunzilog_console_init(void)
1390 {
1391         int i;
1392
1393         if (con_is_present())
1394                 return 0;
1395
1396         for (i = 0; i < NUM_CHANNELS; i++) {
1397                 int this_minor = sunzilog_reg.minor + i;
1398
1399                 if ((this_minor - 64) == (serial_console - 1))
1400                         break;
1401         }
1402         if (i == NUM_CHANNELS)
1403                 return 0;
1404
1405         sunzilog_console.index = i;
1406         sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1407         register_console(&sunzilog_console);
1408         return 0;
1409 }
1410
1411 static inline struct console *SUNZILOG_CONSOLE(void)
1412 {
1413         int i;
1414
1415         if (con_is_present())
1416                 return NULL;
1417
1418         for (i = 0; i < NUM_CHANNELS; i++) {
1419                 int this_minor = sunzilog_reg.minor + i;
1420
1421                 if ((this_minor - 64) == (serial_console - 1))
1422                         break;
1423         }
1424         if (i == NUM_CHANNELS)
1425                 return NULL;
1426
1427         sunzilog_console.index = i;
1428         sunzilog_port_table[i].flags |= SUNZILOG_FLAG_IS_CONS;
1429
1430         return &sunzilog_console;
1431 }
1432
1433 #else
1434 #define SUNZILOG_CONSOLE()      (NULL)
1435 #define sunzilog_console_init() do { } while (0)
1436 #endif
1437
1438 /*
1439  * We scan the PROM tree recursively. This is the most reliable way
1440  * to find Zilog nodes on various platforms. However, we face an extreme
1441  * shortage of kernel stack, so we must be very careful. To that end,
1442  * we scan only to a certain depth, and we use a common property buffer
1443  * in the scan structure.
1444  */
1445 #define ZS_PROPSIZE  128
1446 #define ZS_SCAN_DEPTH   5
1447
1448 struct zs_probe_scan {
1449         int depth;
1450         void (*scanner)(struct zs_probe_scan *t, int node);
1451
1452         int devices;
1453         char prop[ZS_PROPSIZE];
1454 };
1455
1456 static int __inline__ sunzilog_node_ok(int node, const char *name, int len)
1457 {
1458         if (strncmp(name, "zs", len) == 0)
1459                 return 1;
1460         /* Don't fold this procedure just yet. Compare to su_node_ok(). */
1461         return 0;
1462 }
1463
1464 static void __init sunzilog_scan(struct zs_probe_scan *t, int node)
1465 {
1466         int len;
1467
1468         for (; node != 0; node = prom_getsibling(node)) {
1469                 len = prom_getproperty(node, "name", t->prop, ZS_PROPSIZE);
1470                 if (len <= 1)
1471                         continue;               /* Broken PROM node */
1472                 if (sunzilog_node_ok(node, t->prop, len)) {
1473                         (*t->scanner)(t, node);
1474                 } else {
1475                         if (t->depth < ZS_SCAN_DEPTH) {
1476                                 t->depth++;
1477                                 sunzilog_scan(t, prom_getchild(node));
1478                                 --t->depth;
1479                         }
1480                 }
1481         }
1482 }
1483
1484 static void __init sunzilog_prepare(void)
1485 {
1486         struct uart_sunzilog_port *up;
1487         struct zilog_layout __iomem *rp;
1488         int channel, chip;
1489
1490         /*
1491          * Temporary fix.
1492          */
1493         for (channel = 0; channel < NUM_CHANNELS; channel++)
1494                 spin_lock_init(&sunzilog_port_table[channel].port.lock);
1495
1496         sunzilog_irq_chain = up = &sunzilog_port_table[0];
1497         for (channel = 0; channel < NUM_CHANNELS - 1; channel++)
1498                 up[channel].next = &up[channel + 1];
1499         up[channel].next = NULL;
1500
1501         for (chip = 0; chip < NUM_SUNZILOG; chip++) {
1502                 rp = sunzilog_chip_regs[chip];
1503                 up[(chip * 2) + 0].port.membase = (void __iomem *)&rp->channelA;
1504                 up[(chip * 2) + 1].port.membase = (void __iomem *)&rp->channelB;
1505
1506                 /* Channel A */
1507                 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1508                 up[(chip * 2) + 0].port.irq = zilog_irq;
1509                 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1510                 up[(chip * 2) + 0].port.fifosize = 1;
1511                 up[(chip * 2) + 0].port.ops = &sunzilog_pops;
1512                 up[(chip * 2) + 0].port.type = PORT_SUNZILOG;
1513                 up[(chip * 2) + 0].port.flags = 0;
1514                 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1515                 up[(chip * 2) + 0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1516
1517                 /* Channel B */
1518                 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1519                 up[(chip * 2) + 1].port.irq = zilog_irq;
1520                 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1521                 up[(chip * 2) + 1].port.fifosize = 1;
1522                 up[(chip * 2) + 1].port.ops = &sunzilog_pops;
1523                 up[(chip * 2) + 1].port.type = PORT_SUNZILOG;
1524                 up[(chip * 2) + 1].port.flags = 0;
1525                 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1526                 up[(chip * 2) + 1].flags |= 0;
1527         }
1528 }
1529
1530 static void __init sunzilog_init_kbdms(struct uart_sunzilog_port *up, int channel)
1531 {
1532         int baud, brg;
1533
1534         if (channel == KEYBOARD_LINE) {
1535                 up->flags |= SUNZILOG_FLAG_CONS_KEYB;
1536                 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1537                 baud = 1200;
1538         } else {
1539                 up->flags |= SUNZILOG_FLAG_CONS_MOUSE;
1540                 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1541                 baud = 4800;
1542         }
1543         printk(KERN_INFO "zs%d at 0x%p (irq = %d) is a SunZilog\n",
1544                channel, up->port.membase, zilog_irq);
1545
1546         up->curregs[R15] = BRKIE;
1547         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1548         sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1549         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1550         __sunzilog_startup(up);
1551 }
1552
1553 #ifdef CONFIG_SERIO
1554 static void __init sunzilog_register_serio(struct uart_sunzilog_port *up, int channel)
1555 {
1556         struct serio *serio;
1557
1558         up->serio = serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1559         if (serio) {
1560                 memset(serio, 0, sizeof(*serio));
1561
1562                 serio->port_data = up;
1563
1564                 serio->id.type = SERIO_RS232;
1565                 if (channel == KEYBOARD_LINE) {
1566                         serio->id.proto = SERIO_SUNKBD;
1567                         strlcpy(serio->name, "zskbd", sizeof(serio->name));
1568                 } else {
1569                         serio->id.proto = SERIO_SUN;
1570                         serio->id.extra = 1;
1571                         strlcpy(serio->name, "zsms", sizeof(serio->name));
1572                 }
1573                 strlcpy(serio->phys,
1574                         (channel == KEYBOARD_LINE ? "zs/serio0" : "zs/serio1"),
1575                         sizeof(serio->phys));
1576
1577                 serio->write = sunzilog_serio_write;
1578                 serio->open = sunzilog_serio_open;
1579                 serio->close = sunzilog_serio_close;
1580
1581                 serio_register_port(serio);
1582         } else {
1583                 printk(KERN_WARNING "zs%d: not enough memory for serio port\n",
1584                         channel);
1585         }
1586 }
1587 #endif
1588
1589 static void __init sunzilog_init_hw(void)
1590 {
1591         int i;
1592
1593         for (i = 0; i < NUM_CHANNELS; i++) {
1594                 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1595                 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1596                 unsigned long flags;
1597                 int baud, brg;
1598
1599                 spin_lock_irqsave(&up->port.lock, flags);
1600
1601                 if (ZS_IS_CHANNEL_A(up)) {
1602                         write_zsreg(channel, R9, FHWRES);
1603                         ZSDELAY_LONG();
1604                         (void) read_zsreg(channel, R0);
1605                 }
1606
1607                 if (i == KEYBOARD_LINE || i == MOUSE_LINE) {
1608                         sunzilog_init_kbdms(up, i);
1609                         up->curregs[R9] |= (NV | MIE);
1610                         write_zsreg(channel, R9, up->curregs[R9]);
1611                 } else {
1612                         /* Normal serial TTY. */
1613                         up->parity_mask = 0xff;
1614                         up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1615                         up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1616                         up->curregs[R3] = RxENAB | Rx8;
1617                         up->curregs[R5] = TxENAB | Tx8;
1618                         up->curregs[R9] = NV | MIE;
1619                         up->curregs[R10] = NRZ;
1620                         up->curregs[R11] = TCBR | RCBR;
1621                         baud = 9600;
1622                         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1623                         up->curregs[R12] = (brg & 0xff);
1624                         up->curregs[R13] = (brg >> 8) & 0xff;
1625                         up->curregs[R14] = BRSRC | BRENAB;
1626                         __load_zsregs(channel, up->curregs);
1627                         write_zsreg(channel, R9, up->curregs[R9]);
1628                 }
1629
1630                 spin_unlock_irqrestore(&up->port.lock, flags);
1631
1632 #ifdef CONFIG_SERIO
1633                 if (i == KEYBOARD_LINE || i == MOUSE_LINE)
1634                         sunzilog_register_serio(up, i);
1635 #endif
1636         }
1637 }
1638
1639 static struct zilog_layout __iomem * __init get_zs(int chip, int node);
1640
1641 static void __init sunzilog_scan_probe(struct zs_probe_scan *t, int node)
1642 {
1643         sunzilog_chip_regs[t->devices] = get_zs(t->devices, node);
1644         t->devices++;
1645 }
1646
1647 static int __init sunzilog_ports_init(void)
1648 {
1649         struct zs_probe_scan scan;
1650         int ret;
1651         int uart_count;
1652         int i;
1653
1654         printk(KERN_DEBUG "SunZilog: %d chips.\n", NUM_SUNZILOG);
1655
1656         scan.scanner = sunzilog_scan_probe;
1657         scan.depth = 0;
1658         scan.devices = 0;
1659         sunzilog_scan(&scan, prom_getchild(prom_root_node));
1660
1661         sunzilog_prepare();
1662
1663         if (request_irq(zilog_irq, sunzilog_interrupt, SA_SHIRQ,
1664                         "SunZilog", sunzilog_irq_chain)) {
1665                 prom_printf("SunZilog: Unable to register zs interrupt handler.\n");
1666                 prom_halt();
1667         }
1668
1669         sunzilog_init_hw();
1670
1671         /* We can only init this once we have probed the Zilogs
1672          * in the system. Do not count channels assigned to keyboards
1673          * or mice when we are deciding how many ports to register.
1674          */
1675         uart_count = 0;
1676         for (i = 0; i < NUM_CHANNELS; i++) {
1677                 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1678
1679                 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1680                         continue;
1681
1682                 uart_count++;
1683         }
1684
1685         sunzilog_reg.nr = uart_count;
1686         sunzilog_reg.minor = sunserial_current_minor;
1687
1688         ret = uart_register_driver(&sunzilog_reg);
1689         if (ret == 0) {
1690                 sunzilog_reg.tty_driver->name_base = sunzilog_reg.minor - 64;
1691                 sunzilog_reg.cons = SUNZILOG_CONSOLE();
1692
1693                 sunserial_current_minor += uart_count;
1694
1695                 for (i = 0; i < NUM_CHANNELS; i++) {
1696                         struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1697
1698                         if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up))
1699                                 continue;
1700
1701                         if (uart_add_one_port(&sunzilog_reg, &up->port)) {
1702                                 printk(KERN_ERR
1703                                     "SunZilog: failed to add port zs%d\n", i);
1704                         }
1705                 }
1706         }
1707
1708         return ret;
1709 }
1710
1711 static void __init sunzilog_scan_count(struct zs_probe_scan *t, int node)
1712 {
1713         t->devices++;
1714 }
1715
1716 static int __init sunzilog_ports_count(void)
1717 {
1718         struct zs_probe_scan scan;
1719
1720         /* Sun4 Zilog setup is hard coded, no probing to do.  */
1721         if (sparc_cpu_model == sun4)
1722                 return 2;
1723
1724         scan.scanner = sunzilog_scan_count;
1725         scan.depth = 0;
1726         scan.devices = 0;
1727
1728         sunzilog_scan(&scan, prom_getchild(prom_root_node));
1729
1730         return scan.devices;
1731 }
1732
1733 static int __init sunzilog_init(void)
1734 {
1735
1736         NUM_SUNZILOG = sunzilog_ports_count();
1737         if (NUM_SUNZILOG == 0)
1738                 return -ENODEV;
1739
1740         sunzilog_alloc_tables();
1741
1742         sunzilog_ports_init();
1743
1744         return 0;
1745 }
1746
1747 static void __exit sunzilog_exit(void)
1748 {
1749         int i;
1750
1751         for (i = 0; i < NUM_CHANNELS; i++) {
1752                 struct uart_sunzilog_port *up = &sunzilog_port_table[i];
1753
1754                 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1755 #ifdef CONFIG_SERIO
1756                         if (up->serio) {
1757                                 serio_unregister_port(up->serio);
1758                                 up->serio = NULL;
1759                         }
1760 #endif
1761                 } else
1762                         uart_remove_one_port(&sunzilog_reg, &up->port);
1763         }
1764
1765         uart_unregister_driver(&sunzilog_reg);
1766 }
1767
1768 module_init(sunzilog_init);
1769 module_exit(sunzilog_exit);
1770
1771 MODULE_AUTHOR("David S. Miller");
1772 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1773 MODULE_LICENSE("GPL");