git.oblomov.eu Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *
 105  * Known bugs:
 106  * We suspect that on some hardware no TX done interrupts are generated.
 107  * This means recovery from netif_stop_queue only happens if the hw timer
 108  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 109  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 110  * If your hardware reliably generates tx done interrupts, then you can remove
 111  * DEV_NEED_TIMERIRQ from the driver_data flags.
 112  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 113  * superfluous timer interrupts from the nic.
 114  */
 115 #define FORCEDETH_VERSION               "0.48"
 116 #define DRV_NAME                        "forcedeth"
 117
 118 #include <linux/module.h>
 119 #include <linux/types.h>
 120 #include <linux/pci.h>
 121 #include <linux/interrupt.h>
 122 #include <linux/netdevice.h>
 123 #include <linux/etherdevice.h>
 124 #include <linux/delay.h>
 125 #include <linux/spinlock.h>
 126 #include <linux/ethtool.h>
 127 #include <linux/timer.h>
 128 #include <linux/skbuff.h>
 129 #include <linux/mii.h>
 130 #include <linux/random.h>
 131 #include <linux/init.h>
 132 #include <linux/if_vlan.h>
 133
 134 #include <asm/irq.h>
 135 #include <asm/io.h>
 136 #include <asm/uaccess.h>
 137 #include <asm/system.h>
 138
 139 #if 0
 140 #define dprintk                 printk
 141 #else
 142 #define dprintk(x...)           do { } while (0)
 143 #endif
 144
 145
 146 /*
 147  * Hardware access:
 148  */
 149
 150 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 151 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 152 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 153 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 154 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 155
 156 enum {
 157         NvRegIrqStatus = 0x000,
 158 #define NVREG_IRQSTAT_MIIEVENT  0x040
 159 #define NVREG_IRQSTAT_MASK              0x1ff
 160         NvRegIrqMask = 0x004,
 161 #define NVREG_IRQ_RX_ERROR              0x0001
 162 #define NVREG_IRQ_RX                    0x0002
 163 #define NVREG_IRQ_RX_NOBUF              0x0004
 164 #define NVREG_IRQ_TX_ERR                0x0008
 165 #define NVREG_IRQ_TX_OK                 0x0010
 166 #define NVREG_IRQ_TIMER                 0x0020
 167 #define NVREG_IRQ_LINK                  0x0040
 168 #define NVREG_IRQ_TX_ERROR              0x0080
 169 #define NVREG_IRQ_TX1                   0x0100
 170 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 171 #define NVREG_IRQMASK_CPU               0x0040
 172
 173 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 174                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 175                                         NVREG_IRQ_TX1))
 176
 177         NvRegUnknownSetupReg6 = 0x008,
 178 #define NVREG_UNKSETUP6_VAL             3
 179
 180 /*
 181  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 182  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 183  */
 184         NvRegPollingInterval = 0x00c,
 185 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 186 #define NVREG_POLL_DEFAULT_CPU  13
 187         NvRegMisc1 = 0x080,
 188 #define NVREG_MISC1_HD          0x02
 189 #define NVREG_MISC1_FORCE       0x3b0f3c
 190
 191         NvRegTransmitterControl = 0x084,
 192 #define NVREG_XMITCTL_START     0x01
 193         NvRegTransmitterStatus = 0x088,
 194 #define NVREG_XMITSTAT_BUSY     0x01
 195
 196         NvRegPacketFilterFlags = 0x8c,
 197 #define NVREG_PFF_ALWAYS        0x7F0008
 198 #define NVREG_PFF_PROMISC       0x80
 199 #define NVREG_PFF_MYADDR        0x20
 200
 201         NvRegOffloadConfig = 0x90,
 202 #define NVREG_OFFLOAD_HOMEPHY   0x601
 203 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 204         NvRegReceiverControl = 0x094,
 205 #define NVREG_RCVCTL_START      0x01
 206         NvRegReceiverStatus = 0x98,
 207 #define NVREG_RCVSTAT_BUSY      0x01
 208
 209         NvRegRandomSeed = 0x9c,
 210 #define NVREG_RNDSEED_MASK      0x00ff
 211 #define NVREG_RNDSEED_FORCE     0x7f00
 212 #define NVREG_RNDSEED_FORCE2    0x2d00
 213 #define NVREG_RNDSEED_FORCE3    0x7400
 214
 215         NvRegUnknownSetupReg1 = 0xA0,
 216 #define NVREG_UNKSETUP1_VAL     0x16070f
 217         NvRegUnknownSetupReg2 = 0xA4,
 218 #define NVREG_UNKSETUP2_VAL     0x16
 219         NvRegMacAddrA = 0xA8,
 220         NvRegMacAddrB = 0xAC,
 221         NvRegMulticastAddrA = 0xB0,
 222 #define NVREG_MCASTADDRA_FORCE  0x01
 223         NvRegMulticastAddrB = 0xB4,
 224         NvRegMulticastMaskA = 0xB8,
 225         NvRegMulticastMaskB = 0xBC,
 226
 227         NvRegPhyInterface = 0xC0,
 228 #define PHY_RGMII               0x10000000
 229
 230         NvRegTxRingPhysAddr = 0x100,
 231         NvRegRxRingPhysAddr = 0x104,
 232         NvRegRingSizes = 0x108,
 233 #define NVREG_RINGSZ_TXSHIFT 0
 234 #define NVREG_RINGSZ_RXSHIFT 16
 235         NvRegUnknownTransmitterReg = 0x10c,
 236         NvRegLinkSpeed = 0x110,
 237 #define NVREG_LINKSPEED_FORCE 0x10000
 238 #define NVREG_LINKSPEED_10      1000
 239 #define NVREG_LINKSPEED_100     100
 240 #define NVREG_LINKSPEED_1000    50
 241 #define NVREG_LINKSPEED_MASK    (0xFFF)
 242         NvRegUnknownSetupReg5 = 0x130,
 243 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 244         NvRegUnknownSetupReg3 = 0x13c,
 245 #define NVREG_UNKSETUP3_VAL1    0x200010
 246         NvRegTxRxControl = 0x144,
 247 #define NVREG_TXRXCTL_KICK      0x0001
 248 #define NVREG_TXRXCTL_BIT1      0x0002
 249 #define NVREG_TXRXCTL_BIT2      0x0004
 250 #define NVREG_TXRXCTL_IDLE      0x0008
 251 #define NVREG_TXRXCTL_RESET     0x0010
 252 #define NVREG_TXRXCTL_RXCHECK   0x0400
 253 #define NVREG_TXRXCTL_DESC_1    0
 254 #define NVREG_TXRXCTL_DESC_2    0x02100
 255 #define NVREG_TXRXCTL_DESC_3    0x02200
 256         NvRegMIIStatus = 0x180,
 257 #define NVREG_MIISTAT_ERROR             0x0001
 258 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 259 #define NVREG_MIISTAT_MASK              0x000f
 260 #define NVREG_MIISTAT_MASK2             0x000f
 261         NvRegUnknownSetupReg4 = 0x184,
 262 #define NVREG_UNKSETUP4_VAL     8
 263
 264         NvRegAdapterControl = 0x188,
 265 #define NVREG_ADAPTCTL_START    0x02
 266 #define NVREG_ADAPTCTL_LINKUP   0x04
 267 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 268 #define NVREG_ADAPTCTL_RUNNING  0x100000
 269 #define NVREG_ADAPTCTL_PHYSHIFT 24
 270         NvRegMIISpeed = 0x18c,
 271 #define NVREG_MIISPEED_BIT8     (1<<8)
 272 #define NVREG_MIIDELAY  5
 273         NvRegMIIControl = 0x190,
 274 #define NVREG_MIICTL_INUSE      0x08000
 275 #define NVREG_MIICTL_WRITE      0x00400
 276 #define NVREG_MIICTL_ADDRSHIFT  5
 277         NvRegMIIData = 0x194,
 278         NvRegWakeUpFlags = 0x200,
 279 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 280 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 281 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 282 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 283 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 284 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 285 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 286 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 287 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 288 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 289 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 290
 291         NvRegPatternCRC = 0x204,
 292         NvRegPatternMask = 0x208,
 293         NvRegPowerCap = 0x268,
 294 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 295 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 296 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 297         NvRegPowerState = 0x26c,
 298 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 299 #define NVREG_POWERSTATE_VALID          0x0100
 300 #define NVREG_POWERSTATE_MASK           0x0003
 301 #define NVREG_POWERSTATE_D0             0x0000
 302 #define NVREG_POWERSTATE_D1             0x0001
 303 #define NVREG_POWERSTATE_D2             0x0002
 304 #define NVREG_POWERSTATE_D3             0x0003
 305 };
 306
 307 /* Big endian: should work, but is untested */
 308 struct ring_desc {
 309         u32 PacketBuffer;
 310         u32 FlagLen;
 311 };
 312
 313 struct ring_desc_ex {
 314         u32 PacketBufferHigh;
 315         u32 PacketBufferLow;
 316         u32 Reserved;
 317         u32 FlagLen;
 318 };
 319
 320 typedef union _ring_type {
 321         struct ring_desc* orig;
 322         struct ring_desc_ex* ex;
 323 } ring_type;
 324
 325 #define FLAG_MASK_V1 0xffff0000
 326 #define FLAG_MASK_V2 0xffffc000
 327 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 328 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 329
 330 #define NV_TX_LASTPACKET        (1<<16)
 331 #define NV_TX_RETRYERROR        (1<<19)
 332 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 333 #define NV_TX_DEFERRED          (1<<26)
 334 #define NV_TX_CARRIERLOST       (1<<27)
 335 #define NV_TX_LATECOLLISION     (1<<28)
 336 #define NV_TX_UNDERFLOW         (1<<29)
 337 #define NV_TX_ERROR             (1<<30)
 338 #define NV_TX_VALID             (1<<31)
 339
 340 #define NV_TX2_LASTPACKET       (1<<29)
 341 #define NV_TX2_RETRYERROR       (1<<18)
 342 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 343 #define NV_TX2_DEFERRED         (1<<25)
 344 #define NV_TX2_CARRIERLOST      (1<<26)
 345 #define NV_TX2_LATECOLLISION    (1<<27)
 346 #define NV_TX2_UNDERFLOW        (1<<28)
 347 /* error and valid are the same for both */
 348 #define NV_TX2_ERROR            (1<<30)
 349 #define NV_TX2_VALID            (1<<31)
 350 #define NV_TX2_TSO              (1<<28)
 351 #define NV_TX2_TSO_SHIFT        14
 352 #define NV_TX2_CHECKSUM_L3      (1<<27)
 353 #define NV_TX2_CHECKSUM_L4      (1<<26)
 354
 355 #define NV_RX_DESCRIPTORVALID   (1<<16)
 356 #define NV_RX_MISSEDFRAME       (1<<17)
 357 #define NV_RX_SUBSTRACT1        (1<<18)
 358 #define NV_RX_ERROR1            (1<<23)
 359 #define NV_RX_ERROR2            (1<<24)
 360 #define NV_RX_ERROR3            (1<<25)
 361 #define NV_RX_ERROR4            (1<<26)
 362 #define NV_RX_CRCERR            (1<<27)
 363 #define NV_RX_OVERFLOW          (1<<28)
 364 #define NV_RX_FRAMINGERR        (1<<29)
 365 #define NV_RX_ERROR             (1<<30)
 366 #define NV_RX_AVAIL             (1<<31)
 367
 368 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 369 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 370 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 371 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 372 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 373 #define NV_RX2_SUBSTRACT1       (1<<25)
 374 #define NV_RX2_ERROR1           (1<<18)
 375 #define NV_RX2_ERROR2           (1<<19)
 376 #define NV_RX2_ERROR3           (1<<20)
 377 #define NV_RX2_ERROR4           (1<<21)
 378 #define NV_RX2_CRCERR           (1<<22)
 379 #define NV_RX2_OVERFLOW         (1<<23)
 380 #define NV_RX2_FRAMINGERR       (1<<24)
 381 /* error and avail are the same for both */
 382 #define NV_RX2_ERROR            (1<<30)
 383 #define NV_RX2_AVAIL            (1<<31)
 384
 385 /* Miscelaneous hardware related defines: */
 386 #define NV_PCI_REGSZ            0x270
 387
 388 /* various timeout delays: all in usec */
 389 #define NV_TXRX_RESET_DELAY     4
 390 #define NV_TXSTOP_DELAY1        10
 391 #define NV_TXSTOP_DELAY1MAX     500000
 392 #define NV_TXSTOP_DELAY2        100
 393 #define NV_RXSTOP_DELAY1        10
 394 #define NV_RXSTOP_DELAY1MAX     500000
 395 #define NV_RXSTOP_DELAY2        100
 396 #define NV_SETUP5_DELAY         5
 397 #define NV_SETUP5_DELAYMAX      50000
 398 #define NV_POWERUP_DELAY        5
 399 #define NV_POWERUP_DELAYMAX     5000
 400 #define NV_MIIBUSY_DELAY        50
 401 #define NV_MIIPHY_DELAY 10
 402 #define NV_MIIPHY_DELAYMAX      10000
 403
 404 #define NV_WAKEUPPATTERNS       5
 405 #define NV_WAKEUPMASKENTRIES    4
 406
 407 /* General driver defaults */
 408 #define NV_WATCHDOG_TIMEO       (5*HZ)
 409
 410 #define RX_RING         128
 411 #define TX_RING         64
 412 /*
 413  * If your nic mysteriously hangs then try to reduce the limits
 414  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 415  * last valid ring entry. But this would be impossible to
 416  * implement - probably a disassembly error.
 417  */
 418 #define TX_LIMIT_STOP   63
 419 #define TX_LIMIT_START  62
 420
 421 /* rx/tx mac addr + type + vlan + align + slack*/
 422 #define NV_RX_HEADERS           (64)
 423 /* even more slack. */
 424 #define NV_RX_ALLOC_PAD         (64)
 425
 426 /* maximum mtu size */
 427 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 428 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 429
 430 #define OOM_REFILL      (1+HZ/20)
 431 #define POLL_WAIT       (1+HZ/100)
 432 #define LINK_TIMEOUT    (3*HZ)
 433
 434 /*
 435  * desc_ver values:
 436  * The nic supports three different descriptor types:
 437  * - DESC_VER_1: Original
 438  * - DESC_VER_2: support for jumbo frames.
 439  * - DESC_VER_3: 64-bit format.
 440  */
 441 #define DESC_VER_1      1
 442 #define DESC_VER_2      2
 443 #define DESC_VER_3      3
 444
 445 /* PHY defines */
 446 #define PHY_OUI_MARVELL 0x5043
 447 #define PHY_OUI_CICADA  0x03f1
 448 #define PHYID1_OUI_MASK 0x03ff
 449 #define PHYID1_OUI_SHFT 6
 450 #define PHYID2_OUI_MASK 0xfc00
 451 #define PHYID2_OUI_SHFT 10
 452 #define PHY_INIT1       0x0f000
 453 #define PHY_INIT2       0x0e00
 454 #define PHY_INIT3       0x01000
 455 #define PHY_INIT4       0x0200
 456 #define PHY_INIT5       0x0004
 457 #define PHY_INIT6       0x02000
 458 #define PHY_GIGABIT     0x0100
 459
 460 #define PHY_TIMEOUT     0x1
 461 #define PHY_ERROR       0x2
 462
 463 #define PHY_100 0x1
 464 #define PHY_1000        0x2
 465 #define PHY_HALF        0x100
 466
 467 /* FIXME: MII defines that should be added to <linux/mii.h> */
 468 #define MII_1000BT_CR   0x09
 469 #define MII_1000BT_SR   0x0a
 470 #define ADVERTISE_1000FULL      0x0200
 471 #define ADVERTISE_1000HALF      0x0100
 472 #define LPA_1000FULL    0x0800
 473 #define LPA_1000HALF    0x0400
 474
 475
 476 /*
 477  * SMP locking:
 478  * All hardware access under dev->priv->lock, except the performance
 479  * critical parts:
 480  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 481  *      by the arch code for interrupts.
 482  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 483  *      needs dev->priv->lock :-(
 484  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 485  */
 486
 487 /* in dev: base, irq */
 488 struct fe_priv {
 489         spinlock_t lock;
 490
 491         /* General data:
 492          * Locking: spin_lock(&np->lock); */
 493         struct net_device_stats stats;
 494         int in_shutdown;
 495         u32 linkspeed;
 496         int duplex;
 497         int autoneg;
 498         int fixed_mode;
 499         int phyaddr;
 500         int wolenabled;
 501         unsigned int phy_oui;
 502         u16 gigabit;
 503
 504         /* General data: RO fields */
 505         dma_addr_t ring_addr;
 506         struct pci_dev *pci_dev;
 507         u32 orig_mac[2];
 508         u32 irqmask;
 509         u32 desc_ver;
 510         u32 txrxctl_bits;
 511
 512         void __iomem *base;
 513
 514         /* rx specific fields.
 515          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 516          */
 517         ring_type rx_ring;
 518         unsigned int cur_rx, refill_rx;
 519         struct sk_buff *rx_skbuff[RX_RING];
 520         dma_addr_t rx_dma[RX_RING];
 521         unsigned int rx_buf_sz;
 522         unsigned int pkt_limit;
 523         struct timer_list oom_kick;
 524         struct timer_list nic_poll;
 525
 526         /* media detection workaround.
 527          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 528          */
 529         int need_linktimer;
 530         unsigned long link_timeout;
 531         /*
 532          * tx specific fields.
 533          */
 534         ring_type tx_ring;
 535         unsigned int next_tx, nic_tx;
 536         struct sk_buff *tx_skbuff[TX_RING];
 537         dma_addr_t tx_dma[TX_RING];
 538         u32 tx_flags;
 539 };
 540
 541 /*
 542  * Maximum number of loops until we assume that a bit in the irq mask
 543  * is stuck. Overridable with module param.
 544  */
 545 static int max_interrupt_work = 5;
 546
 547 /*
 548  * Optimization can be either throuput mode or cpu mode
 549  *
 550  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 551  * CPU Mode: Interrupts are controlled by a timer.
 552  */
 553 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
 554 #define NV_OPTIMIZATION_MODE_CPU        1
 555 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 556
 557 /*
 558  * Poll interval for timer irq
 559  *
 560  * This interval determines how frequent an interrupt is generated.
 561  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 562  * Min = 0, and Max = 65535
 563  */
 564 static int poll_interval = -1;
 565
 566 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 567 {
 568         return netdev_priv(dev);
 569 }
 570
 571 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 572 {
 573         return ((struct fe_priv *)netdev_priv(dev))->base;
 574 }
 575
 576 static inline void pci_push(u8 __iomem *base)
 577 {
 578         /* force out pending posted writes */
 579         readl(base);
 580 }
 581
 582 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 583 {
 584         return le32_to_cpu(prd->FlagLen)
 585                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 586 }
 587
 588 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 589 {
 590         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 591 }
 592
 593 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 594                                 int delay, int delaymax, const char *msg)
 595 {
 596         u8 __iomem *base = get_hwbase(dev);
 597
 598         pci_push(base);
 599         do {
 600                 udelay(delay);
 601                 delaymax -= delay;
 602                 if (delaymax < 0) {
 603                         if (msg)
 604                                 printk(msg);
 605                         return 1;
 606                 }
 607         } while ((readl(base + offset) & mask) != target);
 608         return 0;
 609 }
 610
 611 #define MII_READ        (-1)
 612 /* mii_rw: read/write a register on the PHY.
 613  *
 614  * Caller must guarantee serialization
 615  */
 616 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 617 {
 618         u8 __iomem *base = get_hwbase(dev);
 619         u32 reg;
 620         int retval;
 621
 622         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 623
 624         reg = readl(base + NvRegMIIControl);
 625         if (reg & NVREG_MIICTL_INUSE) {
 626                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 627                 udelay(NV_MIIBUSY_DELAY);
 628         }
 629
 630         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 631         if (value != MII_READ) {
 632                 writel(value, base + NvRegMIIData);
 633                 reg |= NVREG_MIICTL_WRITE;
 634         }
 635         writel(reg, base + NvRegMIIControl);
 636
 637         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 638                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 639                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 640                                 dev->name, miireg, addr);
 641                 retval = -1;
 642         } else if (value != MII_READ) {
 643                 /* it was a write operation - fewer failures are detectable */
 644                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 645                                 dev->name, value, miireg, addr);
 646                 retval = 0;
 647         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 648                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 649                                 dev->name, miireg, addr);
 650                 retval = -1;
 651         } else {
 652                 retval = readl(base + NvRegMIIData);
 653                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 654                                 dev->name, miireg, addr, retval);
 655         }
 656
 657         return retval;
 658 }
 659
 660 static int phy_reset(struct net_device *dev)
 661 {
 662         struct fe_priv *np = netdev_priv(dev);
 663         u32 miicontrol;
 664         unsigned int tries = 0;
 665
 666         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 667         miicontrol |= BMCR_RESET;
 668         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 669                 return -1;
 670         }
 671
 672         /* wait for 500ms */
 673         msleep(500);
 674
 675         /* must wait till reset is deasserted */
 676         while (miicontrol & BMCR_RESET) {
 677                 msleep(10);
 678                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 679                 /* FIXME: 100 tries seem excessive */
 680                 if (tries++ > 100)
 681                         return -1;
 682         }
 683         return 0;
 684 }
 685
 686 static int phy_init(struct net_device *dev)
 687 {
 688         struct fe_priv *np = get_nvpriv(dev);
 689         u8 __iomem *base = get_hwbase(dev);
 690         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 691
 692         /* set advertise register */
 693         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 694         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 695         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 696                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 697                 return PHY_ERROR;
 698         }
 699
 700         /* get phy interface type */
 701         phyinterface = readl(base + NvRegPhyInterface);
 702
 703         /* see if gigabit phy */
 704         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 705         if (mii_status & PHY_GIGABIT) {
 706                 np->gigabit = PHY_GIGABIT;
 707                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 708                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 709                 if (phyinterface & PHY_RGMII)
 710                         mii_control_1000 |= ADVERTISE_1000FULL;
 711                 else
 712                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 713
 714                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 715                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 716                         return PHY_ERROR;
 717                 }
 718         }
 719         else
 720                 np->gigabit = 0;
 721
 722         /* reset the phy */
 723         if (phy_reset(dev)) {
 724                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 725                 return PHY_ERROR;
 726         }
 727
 728         /* phy vendor specific configuration */
 729         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 730                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 731                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 732                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 733                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 734                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 735                         return PHY_ERROR;
 736                 }
 737                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 738                 phy_reserved |= PHY_INIT5;
 739                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 740                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 741                         return PHY_ERROR;
 742                 }
 743         }
 744         if (np->phy_oui == PHY_OUI_CICADA) {
 745                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 746                 phy_reserved |= PHY_INIT6;
 747                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 748                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 749                         return PHY_ERROR;
 750                 }
 751         }
 752
 753         /* restart auto negotiation */
 754         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 755         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 756         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 757                 return PHY_ERROR;
 758         }
 759
 760         return 0;
 761 }
 762
 763 static void nv_start_rx(struct net_device *dev)
 764 {
 765         struct fe_priv *np = netdev_priv(dev);
 766         u8 __iomem *base = get_hwbase(dev);
 767
 768         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 769         /* Already running? Stop it. */
 770         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 771                 writel(0, base + NvRegReceiverControl);
 772                 pci_push(base);
 773         }
 774         writel(np->linkspeed, base + NvRegLinkSpeed);
 775         pci_push(base);
 776         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 777         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 778                                 dev->name, np->duplex, np->linkspeed);
 779         pci_push(base);
 780 }
 781
 782 static void nv_stop_rx(struct net_device *dev)
 783 {
 784         u8 __iomem *base = get_hwbase(dev);
 785
 786         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 787         writel(0, base + NvRegReceiverControl);
 788         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 789                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 790                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 791
 792         udelay(NV_RXSTOP_DELAY2);
 793         writel(0, base + NvRegLinkSpeed);
 794 }
 795
 796 static void nv_start_tx(struct net_device *dev)
 797 {
 798         u8 __iomem *base = get_hwbase(dev);
 799
 800         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 801         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 802         pci_push(base);
 803 }
 804
 805 static void nv_stop_tx(struct net_device *dev)
 806 {
 807         u8 __iomem *base = get_hwbase(dev);
 808
 809         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 810         writel(0, base + NvRegTransmitterControl);
 811         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 812                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 813                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 814
 815         udelay(NV_TXSTOP_DELAY2);
 816         writel(0, base + NvRegUnknownTransmitterReg);
 817 }
 818
 819 static void nv_txrx_reset(struct net_device *dev)
 820 {
 821         struct fe_priv *np = netdev_priv(dev);
 822         u8 __iomem *base = get_hwbase(dev);
 823
 824         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 825         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
 826         pci_push(base);
 827         udelay(NV_TXRX_RESET_DELAY);
 828         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
 829         pci_push(base);
 830 }
 831
 832 /*
 833  * nv_get_stats: dev->get_stats function
 834  * Get latest stats value from the nic.
 835  * Called with read_lock(&dev_base_lock) held for read -
 836  * only synchronized against unregister_netdevice.
 837  */
 838 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 839 {
 840         struct fe_priv *np = netdev_priv(dev);
 841
 842         /* It seems that the nic always generates interrupts and doesn't
 843          * accumulate errors internally. Thus the current values in np->stats
 844          * are already up to date.
 845          */
 846         return &np->stats;
 847 }
 848
 849 /*
 850  * nv_alloc_rx: fill rx ring entries.
 851  * Return 1 if the allocations for the skbs failed and the
 852  * rx engine is without Available descriptors
 853  */
 854 static int nv_alloc_rx(struct net_device *dev)
 855 {
 856         struct fe_priv *np = netdev_priv(dev);
 857         unsigned int refill_rx = np->refill_rx;
 858         int nr;
 859
 860         while (np->cur_rx != refill_rx) {
 861                 struct sk_buff *skb;
 862
 863                 nr = refill_rx % RX_RING;
 864                 if (np->rx_skbuff[nr] == NULL) {
 865
 866                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 867                         if (!skb)
 868                                 break;
 869
 870                         skb->dev = dev;
 871                         np->rx_skbuff[nr] = skb;
 872                 } else {
 873                         skb = np->rx_skbuff[nr];
 874                 }
 875                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
 876                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
 877                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 878                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 879                         wmb();
 880                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 881                 } else {
 882                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
 883                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
 884                         wmb();
 885                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
 886                 }
 887                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 888                                         dev->name, refill_rx);
 889                 refill_rx++;
 890         }
 891         np->refill_rx = refill_rx;
 892         if (np->cur_rx - refill_rx == RX_RING)
 893                 return 1;
 894         return 0;
 895 }
 896
 897 static void nv_do_rx_refill(unsigned long data)
 898 {
 899         struct net_device *dev = (struct net_device *) data;
 900         struct fe_priv *np = netdev_priv(dev);
 901
 902         disable_irq(dev->irq);
 903         if (nv_alloc_rx(dev)) {
 904                 spin_lock(&np->lock);
 905                 if (!np->in_shutdown)
 906                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 907                 spin_unlock(&np->lock);
 908         }
 909         enable_irq(dev->irq);
 910 }
 911
 912 static void nv_init_rx(struct net_device *dev)
 913 {
 914         struct fe_priv *np = netdev_priv(dev);
 915         int i;
 916
 917         np->cur_rx = RX_RING;
 918         np->refill_rx = 0;
 919         for (i = 0; i < RX_RING; i++)
 920                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 921                         np->rx_ring.orig[i].FlagLen = 0;
 922                 else
 923                         np->rx_ring.ex[i].FlagLen = 0;
 924 }
 925
 926 static void nv_init_tx(struct net_device *dev)
 927 {
 928         struct fe_priv *np = netdev_priv(dev);
 929         int i;
 930
 931         np->next_tx = np->nic_tx = 0;
 932         for (i = 0; i < TX_RING; i++) {
 933                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 934                         np->tx_ring.orig[i].FlagLen = 0;
 935                 else
 936                         np->tx_ring.ex[i].FlagLen = 0;
 937                 np->tx_skbuff[i] = NULL;
 938         }
 939 }
 940
 941 static int nv_init_ring(struct net_device *dev)
 942 {
 943         nv_init_tx(dev);
 944         nv_init_rx(dev);
 945         return nv_alloc_rx(dev);
 946 }
 947
 948 static void nv_release_txskb(struct net_device *dev, unsigned int skbnr)
 949 {
 950         struct fe_priv *np = netdev_priv(dev);
 951         struct sk_buff *skb = np->tx_skbuff[skbnr];
 952         unsigned int j, entry, fragments;
 953
 954         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n",
 955                 dev->name, skbnr, np->tx_skbuff[skbnr]);
 956
 957         entry = skbnr;
 958         if ((fragments = skb_shinfo(skb)->nr_frags) != 0) {
 959                 for (j = fragments; j >= 1; j--) {
 960                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1];
 961                         pci_unmap_page(np->pci_dev, np->tx_dma[entry],
 962                                        frag->size,
 963                                        PCI_DMA_TODEVICE);
 964                         entry = (entry - 1) % TX_RING;
 965                 }
 966         }
 967         pci_unmap_single(np->pci_dev, np->tx_dma[entry],
 968                          skb->len - skb->data_len,
 969                          PCI_DMA_TODEVICE);
 970         dev_kfree_skb_irq(skb);
 971         np->tx_skbuff[skbnr] = NULL;
 972 }
 973
 974 static void nv_drain_tx(struct net_device *dev)
 975 {
 976         struct fe_priv *np = netdev_priv(dev);
 977         unsigned int i;
 978
 979         for (i = 0; i < TX_RING; i++) {
 980                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 981                         np->tx_ring.orig[i].FlagLen = 0;
 982                 else
 983                         np->tx_ring.ex[i].FlagLen = 0;
 984                 if (np->tx_skbuff[i]) {
 985                         nv_release_txskb(dev, i);
 986                         np->stats.tx_dropped++;
 987                 }
 988         }
 989 }
 990
 991 static void nv_drain_rx(struct net_device *dev)
 992 {
 993         struct fe_priv *np = netdev_priv(dev);
 994         int i;
 995         for (i = 0; i < RX_RING; i++) {
 996                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 997                         np->rx_ring.orig[i].FlagLen = 0;
 998                 else
 999                         np->rx_ring.ex[i].FlagLen = 0;
1000                 wmb();
1001                 if (np->rx_skbuff[i]) {
1002                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1003                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1004                                                 PCI_DMA_FROMDEVICE);
1005                         dev_kfree_skb(np->rx_skbuff[i]);
1006                         np->rx_skbuff[i] = NULL;
1007                 }
1008         }
1009 }
1010
1011 static void drain_ring(struct net_device *dev)
1012 {
1013         nv_drain_tx(dev);
1014         nv_drain_rx(dev);
1015 }
1016
1017 /*
1018  * nv_start_xmit: dev->hard_start_xmit function
1019  * Called with dev->xmit_lock held.
1020  */
1021 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1022 {
1023         struct fe_priv *np = netdev_priv(dev);
1024         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1025         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1026         unsigned int nr = (np->next_tx + fragments) % TX_RING;
1027         unsigned int i;
1028
1029         spin_lock_irq(&np->lock);
1030
1031         if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) {
1032                 spin_unlock_irq(&np->lock);
1033                 netif_stop_queue(dev);
1034                 return NETDEV_TX_BUSY;
1035         }
1036
1037         np->tx_skbuff[nr] = skb;
1038
1039         if (fragments) {
1040                 dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments);
1041                 /* setup descriptors in reverse order */
1042                 for (i = fragments; i >= 1; i--) {
1043                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1];
1044                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size,
1045                                                         PCI_DMA_TODEVICE);
1046
1047                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1048                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1049                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1050                         } else {
1051                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1052                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1053                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1054                         }
1055
1056                         nr = (nr - 1) % TX_RING;
1057
1058                         if (np->desc_ver == DESC_VER_1)
1059                                 tx_flags_extra &= ~NV_TX_LASTPACKET;
1060                         else
1061                                 tx_flags_extra &= ~NV_TX2_LASTPACKET;
1062                 }
1063         }
1064
1065 #ifdef NETIF_F_TSO
1066         if (skb_shinfo(skb)->tso_size)
1067                 tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1068         else
1069 #endif
1070         tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1071
1072         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len,
1073                                         PCI_DMA_TODEVICE);
1074
1075         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1076                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1077                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1078         } else {
1079                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1080                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1081                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1082         }
1083
1084         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n",
1085                                 dev->name, np->next_tx, tx_flags_extra);
1086         {
1087                 int j;
1088                 for (j=0; j<64; j++) {
1089                         if ((j%16) == 0)
1090                                 dprintk("\n%03x:", j);
1091                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1092                 }
1093                 dprintk("\n");
1094         }
1095
1096         np->next_tx += 1 + fragments;
1097
1098         dev->trans_start = jiffies;
1099         spin_unlock_irq(&np->lock);
1100         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1101         pci_push(get_hwbase(dev));
1102         return NETDEV_TX_OK;
1103 }
1104
1105 /*
1106  * nv_tx_done: check for completed packets, release the skbs.
1107  *
1108  * Caller must own np->lock.
1109  */
1110 static void nv_tx_done(struct net_device *dev)
1111 {
1112         struct fe_priv *np = netdev_priv(dev);
1113         u32 Flags;
1114         unsigned int i;
1115         struct sk_buff *skb;
1116
1117         while (np->nic_tx != np->next_tx) {
1118                 i = np->nic_tx % TX_RING;
1119
1120                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1121                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1122                 else
1123                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1124
1125                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1126                                         dev->name, np->nic_tx, Flags);
1127                 if (Flags & NV_TX_VALID)
1128                         break;
1129                 if (np->desc_ver == DESC_VER_1) {
1130                         if (Flags & NV_TX_LASTPACKET) {
1131                                 skb = np->tx_skbuff[i];
1132                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1133                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1134                                         if (Flags & NV_TX_UNDERFLOW)
1135                                                 np->stats.tx_fifo_errors++;
1136                                         if (Flags & NV_TX_CARRIERLOST)
1137                                                 np->stats.tx_carrier_errors++;
1138                                         np->stats.tx_errors++;
1139                                 } else {
1140                                         np->stats.tx_packets++;
1141                                         np->stats.tx_bytes += skb->len;
1142                                 }
1143                                 nv_release_txskb(dev, i);
1144                         }
1145                 } else {
1146                         if (Flags & NV_TX2_LASTPACKET) {
1147                                 skb = np->tx_skbuff[i];
1148                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1149                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1150                                         if (Flags & NV_TX2_UNDERFLOW)
1151                                                 np->stats.tx_fifo_errors++;
1152                                         if (Flags & NV_TX2_CARRIERLOST)
1153                                                 np->stats.tx_carrier_errors++;
1154                                         np->stats.tx_errors++;
1155                                 } else {
1156                                         np->stats.tx_packets++;
1157                                         np->stats.tx_bytes += skb->len;
1158                                 }
1159                                 nv_release_txskb(dev, i);
1160                         }
1161                 }
1162                 np->nic_tx++;
1163         }
1164         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1165                 netif_wake_queue(dev);
1166 }
1167
1168 /*
1169  * nv_tx_timeout: dev->tx_timeout function
1170  * Called with dev->xmit_lock held.
1171  */
1172 static void nv_tx_timeout(struct net_device *dev)
1173 {
1174         struct fe_priv *np = netdev_priv(dev);
1175         u8 __iomem *base = get_hwbase(dev);
1176
1177         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1178                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1179
1180         {
1181                 int i;
1182
1183                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1184                                 dev->name, (unsigned long)np->ring_addr,
1185                                 np->next_tx, np->nic_tx);
1186                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1187                 for (i=0;i<0x400;i+= 32) {
1188                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1189                                         i,
1190                                         readl(base + i + 0), readl(base + i + 4),
1191                                         readl(base + i + 8), readl(base + i + 12),
1192                                         readl(base + i + 16), readl(base + i + 20),
1193                                         readl(base + i + 24), readl(base + i + 28));
1194                 }
1195                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1196                 for (i=0;i<TX_RING;i+= 4) {
1197                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1198                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1199                                        i,
1200                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1201                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1202                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1203                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1204                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1205                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1206                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1207                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1208                         } else {
1209                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1210                                        i,
1211                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1212                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1213                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1214                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1215                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1216                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1217                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1218                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1219                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1220                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1221                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1222                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1223                         }
1224                 }
1225         }
1226
1227         spin_lock_irq(&np->lock);
1228
1229         /* 1) stop tx engine */
1230         nv_stop_tx(dev);
1231
1232         /* 2) check that the packets were not sent already: */
1233         nv_tx_done(dev);
1234
1235         /* 3) if there are dead entries: clear everything */
1236         if (np->next_tx != np->nic_tx) {
1237                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1238                 nv_drain_tx(dev);
1239                 np->next_tx = np->nic_tx = 0;
1240                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1241                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1242                 else
1243                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1244                 netif_wake_queue(dev);
1245         }
1246
1247         /* 4) restart tx engine */
1248         nv_start_tx(dev);
1249         spin_unlock_irq(&np->lock);
1250 }
1251
1252 /*
1253  * Called when the nic notices a mismatch between the actual data len on the
1254  * wire and the len indicated in the 802 header
1255  */
1256 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1257 {
1258         int hdrlen;     /* length of the 802 header */
1259         int protolen;   /* length as stored in the proto field */
1260
1261         /* 1) calculate len according to header */
1262         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1263                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1264                 hdrlen = VLAN_HLEN;
1265         } else {
1266                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1267                 hdrlen = ETH_HLEN;
1268         }
1269         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1270                                 dev->name, datalen, protolen, hdrlen);
1271         if (protolen > ETH_DATA_LEN)
1272                 return datalen; /* Value in proto field not a len, no checks possible */
1273
1274         protolen += hdrlen;
1275         /* consistency checks: */
1276         if (datalen > ETH_ZLEN) {
1277                 if (datalen >= protolen) {
1278                         /* more data on wire than in 802 header, trim of
1279                          * additional data.
1280                          */
1281                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1282                                         dev->name, protolen);
1283                         return protolen;
1284                 } else {
1285                         /* less data on wire than mentioned in header.
1286                          * Discard the packet.
1287                          */
1288                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1289                                         dev->name);
1290                         return -1;
1291                 }
1292         } else {
1293                 /* short packet. Accept only if 802 values are also short */
1294                 if (protolen > ETH_ZLEN) {
1295                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1296                                         dev->name);
1297                         return -1;
1298                 }
1299                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1300                                 dev->name, datalen);
1301                 return datalen;
1302         }
1303 }
1304
1305 static void nv_rx_process(struct net_device *dev)
1306 {
1307         struct fe_priv *np = netdev_priv(dev);
1308         u32 Flags;
1309
1310         for (;;) {
1311                 struct sk_buff *skb;
1312                 int len;
1313                 int i;
1314                 if (np->cur_rx - np->refill_rx >= RX_RING)
1315                         break;  /* we scanned the whole ring - do not continue */
1316
1317                 i = np->cur_rx % RX_RING;
1318                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1319                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1320                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1321                 } else {
1322                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1323                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1324                 }
1325
1326                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1327                                         dev->name, np->cur_rx, Flags);
1328
1329                 if (Flags & NV_RX_AVAIL)
1330                         break;  /* still owned by hardware, */
1331
1332                 /*
1333                  * the packet is for us - immediately tear down the pci mapping.
1334                  * TODO: check if a prefetch of the first cacheline improves
1335                  * the performance.
1336                  */
1337                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1338                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1339                                 PCI_DMA_FROMDEVICE);
1340
1341                 {
1342                         int j;
1343                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1344                         for (j=0; j<64; j++) {
1345                                 if ((j%16) == 0)
1346                                         dprintk("\n%03x:", j);
1347                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1348                         }
1349                         dprintk("\n");
1350                 }
1351                 /* look at what we actually got: */
1352                 if (np->desc_ver == DESC_VER_1) {
1353                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1354                                 goto next_pkt;
1355
1356                         if (Flags & NV_RX_ERROR) {
1357                                 if (Flags & NV_RX_MISSEDFRAME) {
1358                                         np->stats.rx_missed_errors++;
1359                                         np->stats.rx_errors++;
1360                                         goto next_pkt;
1361                                 }
1362                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1363                                         np->stats.rx_errors++;
1364                                         goto next_pkt;
1365                                 }
1366                                 if (Flags & NV_RX_CRCERR) {
1367                                         np->stats.rx_crc_errors++;
1368                                         np->stats.rx_errors++;
1369                                         goto next_pkt;
1370                                 }
1371                                 if (Flags & NV_RX_OVERFLOW) {
1372                                         np->stats.rx_over_errors++;
1373                                         np->stats.rx_errors++;
1374                                         goto next_pkt;
1375                                 }
1376                                 if (Flags & NV_RX_ERROR4) {
1377                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1378                                         if (len < 0) {
1379                                                 np->stats.rx_errors++;
1380                                                 goto next_pkt;
1381                                         }
1382                                 }
1383                                 /* framing errors are soft errors. */
1384                                 if (Flags & NV_RX_FRAMINGERR) {
1385                                         if (Flags & NV_RX_SUBSTRACT1) {
1386                                                 len--;
1387                                         }
1388                                 }
1389                         }
1390                 } else {
1391                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1392                                 goto next_pkt;
1393
1394                         if (Flags & NV_RX2_ERROR) {
1395                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1396                                         np->stats.rx_errors++;
1397                                         goto next_pkt;
1398                                 }
1399                                 if (Flags & NV_RX2_CRCERR) {
1400                                         np->stats.rx_crc_errors++;
1401                                         np->stats.rx_errors++;
1402                                         goto next_pkt;
1403                                 }
1404                                 if (Flags & NV_RX2_OVERFLOW) {
1405                                         np->stats.rx_over_errors++;
1406                                         np->stats.rx_errors++;
1407                                         goto next_pkt;
1408                                 }
1409                                 if (Flags & NV_RX2_ERROR4) {
1410                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1411                                         if (len < 0) {
1412                                                 np->stats.rx_errors++;
1413                                                 goto next_pkt;
1414                                         }
1415                                 }
1416                                 /* framing errors are soft errors */
1417                                 if (Flags & NV_RX2_FRAMINGERR) {
1418                                         if (Flags & NV_RX2_SUBSTRACT1) {
1419                                                 len--;
1420                                         }
1421                                 }
1422                         }
1423                         Flags &= NV_RX2_CHECKSUMMASK;
1424                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1425                                         Flags == NV_RX2_CHECKSUMOK2 ||
1426                                         Flags == NV_RX2_CHECKSUMOK3) {
1427                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1428                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1429                         } else {
1430                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1431                         }
1432                 }
1433                 /* got a valid packet - forward it to the network core */
1434                 skb = np->rx_skbuff[i];
1435                 np->rx_skbuff[i] = NULL;
1436
1437                 skb_put(skb, len);
1438                 skb->protocol = eth_type_trans(skb, dev);
1439                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1440                                         dev->name, np->cur_rx, len, skb->protocol);
1441                 netif_rx(skb);
1442                 dev->last_rx = jiffies;
1443                 np->stats.rx_packets++;
1444                 np->stats.rx_bytes += len;
1445 next_pkt:
1446                 np->cur_rx++;
1447         }
1448 }
1449
1450 static void set_bufsize(struct net_device *dev)
1451 {
1452         struct fe_priv *np = netdev_priv(dev);
1453
1454         if (dev->mtu <= ETH_DATA_LEN)
1455                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1456         else
1457                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1458 }
1459
1460 /*
1461  * nv_change_mtu: dev->change_mtu function
1462  * Called with dev_base_lock held for read.
1463  */
1464 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1465 {
1466         struct fe_priv *np = netdev_priv(dev);
1467         int old_mtu;
1468
1469         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1470                 return -EINVAL;
1471
1472         old_mtu = dev->mtu;
1473         dev->mtu = new_mtu;
1474
1475         /* return early if the buffer sizes will not change */
1476         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1477                 return 0;
1478         if (old_mtu == new_mtu)
1479                 return 0;
1480
1481         /* synchronized against open : rtnl_lock() held by caller */
1482         if (netif_running(dev)) {
1483                 u8 __iomem *base = get_hwbase(dev);
1484                 /*
1485                  * It seems that the nic preloads valid ring entries into an
1486                  * internal buffer. The procedure for flushing everything is
1487                  * guessed, there is probably a simpler approach.
1488                  * Changing the MTU is a rare event, it shouldn't matter.
1489                  */
1490                 disable_irq(dev->irq);
1491                 spin_lock_bh(&dev->xmit_lock);
1492                 spin_lock(&np->lock);
1493                 /* stop engines */
1494                 nv_stop_rx(dev);
1495                 nv_stop_tx(dev);
1496                 nv_txrx_reset(dev);
1497                 /* drain rx queue */
1498                 nv_drain_rx(dev);
1499                 nv_drain_tx(dev);
1500                 /* reinit driver view of the rx queue */
1501                 nv_init_rx(dev);
1502                 nv_init_tx(dev);
1503                 /* alloc new rx buffers */
1504                 set_bufsize(dev);
1505                 if (nv_alloc_rx(dev)) {
1506                         if (!np->in_shutdown)
1507                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1508                 }
1509                 /* reinit nic view of the rx queue */
1510                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1511                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1512                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1513                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1514                 else
1515                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1516                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1517                         base + NvRegRingSizes);
1518                 pci_push(base);
1519                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1520                 pci_push(base);
1521
1522                 /* restart rx engine */
1523                 nv_start_rx(dev);
1524                 nv_start_tx(dev);
1525                 spin_unlock(&np->lock);
1526                 spin_unlock_bh(&dev->xmit_lock);
1527                 enable_irq(dev->irq);
1528         }
1529         return 0;
1530 }
1531
1532 static void nv_copy_mac_to_hw(struct net_device *dev)
1533 {
1534         u8 __iomem *base = get_hwbase(dev);
1535         u32 mac[2];
1536
1537         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1538                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1539         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1540
1541         writel(mac[0], base + NvRegMacAddrA);
1542         writel(mac[1], base + NvRegMacAddrB);
1543 }
1544
1545 /*
1546  * nv_set_mac_address: dev->set_mac_address function
1547  * Called with rtnl_lock() held.
1548  */
1549 static int nv_set_mac_address(struct net_device *dev, void *addr)
1550 {
1551         struct fe_priv *np = netdev_priv(dev);
1552         struct sockaddr *macaddr = (struct sockaddr*)addr;
1553
1554         if(!is_valid_ether_addr(macaddr->sa_data))
1555                 return -EADDRNOTAVAIL;
1556
1557         /* synchronized against open : rtnl_lock() held by caller */
1558         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1559
1560         if (netif_running(dev)) {
1561                 spin_lock_bh(&dev->xmit_lock);
1562                 spin_lock_irq(&np->lock);
1563
1564                 /* stop rx engine */
1565                 nv_stop_rx(dev);
1566
1567                 /* set mac address */
1568                 nv_copy_mac_to_hw(dev);
1569
1570                 /* restart rx engine */
1571                 nv_start_rx(dev);
1572                 spin_unlock_irq(&np->lock);
1573                 spin_unlock_bh(&dev->xmit_lock);
1574         } else {
1575                 nv_copy_mac_to_hw(dev);
1576         }
1577         return 0;
1578 }
1579
1580 /*
1581  * nv_set_multicast: dev->set_multicast function
1582  * Called with dev->xmit_lock held.
1583  */
1584 static void nv_set_multicast(struct net_device *dev)
1585 {
1586         struct fe_priv *np = netdev_priv(dev);
1587         u8 __iomem *base = get_hwbase(dev);
1588         u32 addr[2];
1589         u32 mask[2];
1590         u32 pff;
1591
1592         memset(addr, 0, sizeof(addr));
1593         memset(mask, 0, sizeof(mask));
1594
1595         if (dev->flags & IFF_PROMISC) {
1596                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1597                 pff = NVREG_PFF_PROMISC;
1598         } else {
1599                 pff = NVREG_PFF_MYADDR;
1600
1601                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1602                         u32 alwaysOff[2];
1603                         u32 alwaysOn[2];
1604
1605                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1606                         if (dev->flags & IFF_ALLMULTI) {
1607                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1608                         } else {
1609                                 struct dev_mc_list *walk;
1610
1611                                 walk = dev->mc_list;
1612                                 while (walk != NULL) {
1613                                         u32 a, b;
1614                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1615                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1616                                         alwaysOn[0] &= a;
1617                                         alwaysOff[0] &= ~a;
1618                                         alwaysOn[1] &= b;
1619                                         alwaysOff[1] &= ~b;
1620                                         walk = walk->next;
1621                                 }
1622                         }
1623                         addr[0] = alwaysOn[0];
1624                         addr[1] = alwaysOn[1];
1625                         mask[0] = alwaysOn[0] | alwaysOff[0];
1626                         mask[1] = alwaysOn[1] | alwaysOff[1];
1627                 }
1628         }
1629         addr[0] |= NVREG_MCASTADDRA_FORCE;
1630         pff |= NVREG_PFF_ALWAYS;
1631         spin_lock_irq(&np->lock);
1632         nv_stop_rx(dev);
1633         writel(addr[0], base + NvRegMulticastAddrA);
1634         writel(addr[1], base + NvRegMulticastAddrB);
1635         writel(mask[0], base + NvRegMulticastMaskA);
1636         writel(mask[1], base + NvRegMulticastMaskB);
1637         writel(pff, base + NvRegPacketFilterFlags);
1638         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1639                 dev->name);
1640         nv_start_rx(dev);
1641         spin_unlock_irq(&np->lock);
1642 }
1643
1644 /**
1645  * nv_update_linkspeed: Setup the MAC according to the link partner
1646  * @dev: Network device to be configured
1647  *
1648  * The function queries the PHY and checks if there is a link partner.
1649  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1650  * set to 10 MBit HD.
1651  *
1652  * The function returns 0 if there is no link partner and 1 if there is
1653  * a good link partner.
1654  */
1655 static int nv_update_linkspeed(struct net_device *dev)
1656 {
1657         struct fe_priv *np = netdev_priv(dev);
1658         u8 __iomem *base = get_hwbase(dev);
1659         int adv, lpa;
1660         int newls = np->linkspeed;
1661         int newdup = np->duplex;
1662         int mii_status;
1663         int retval = 0;
1664         u32 control_1000, status_1000, phyreg;
1665
1666         /* BMSR_LSTATUS is latched, read it twice:
1667          * we want the current value.
1668          */
1669         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1670         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1671
1672         if (!(mii_status & BMSR_LSTATUS)) {
1673                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1674                                 dev->name);
1675                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1676                 newdup = 0;
1677                 retval = 0;
1678                 goto set_speed;
1679         }
1680
1681         if (np->autoneg == 0) {
1682                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1683                                 dev->name, np->fixed_mode);
1684                 if (np->fixed_mode & LPA_100FULL) {
1685                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1686                         newdup = 1;
1687                 } else if (np->fixed_mode & LPA_100HALF) {
1688                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1689                         newdup = 0;
1690                 } else if (np->fixed_mode & LPA_10FULL) {
1691                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1692                         newdup = 1;
1693                 } else {
1694                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1695                         newdup = 0;
1696                 }
1697                 retval = 1;
1698                 goto set_speed;
1699         }
1700         /* check auto negotiation is complete */
1701         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1702                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1703                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1704                 newdup = 0;
1705                 retval = 0;
1706                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1707                 goto set_speed;
1708         }
1709
1710         retval = 1;
1711         if (np->gigabit == PHY_GIGABIT) {
1712                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1713                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1714
1715                 if ((control_1000 & ADVERTISE_1000FULL) &&
1716                         (status_1000 & LPA_1000FULL)) {
1717                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1718                                 dev->name);
1719                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1720                         newdup = 1;
1721                         goto set_speed;
1722                 }
1723         }
1724
1725         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1726         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1727         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1728                                 dev->name, adv, lpa);
1729
1730         /* FIXME: handle parallel detection properly */
1731         lpa = lpa & adv;
1732         if (lpa & LPA_100FULL) {
1733                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1734                 newdup = 1;
1735         } else if (lpa & LPA_100HALF) {
1736                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1737                 newdup = 0;
1738         } else if (lpa & LPA_10FULL) {
1739                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1740                 newdup = 1;
1741         } else if (lpa & LPA_10HALF) {
1742                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1743                 newdup = 0;
1744         } else {
1745                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1746                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1747                 newdup = 0;
1748         }
1749
1750 set_speed:
1751         if (np->duplex == newdup && np->linkspeed == newls)
1752                 return retval;
1753
1754         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1755                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1756
1757         np->duplex = newdup;
1758         np->linkspeed = newls;
1759
1760         if (np->gigabit == PHY_GIGABIT) {
1761                 phyreg = readl(base + NvRegRandomSeed);
1762                 phyreg &= ~(0x3FF00);
1763                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1764                         phyreg |= NVREG_RNDSEED_FORCE3;
1765                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1766                         phyreg |= NVREG_RNDSEED_FORCE2;
1767                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1768                         phyreg |= NVREG_RNDSEED_FORCE;
1769                 writel(phyreg, base + NvRegRandomSeed);
1770         }
1771
1772         phyreg = readl(base + NvRegPhyInterface);
1773         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1774         if (np->duplex == 0)
1775                 phyreg |= PHY_HALF;
1776         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1777                 phyreg |= PHY_100;
1778         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1779                 phyreg |= PHY_1000;
1780         writel(phyreg, base + NvRegPhyInterface);
1781
1782         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1783                 base + NvRegMisc1);
1784         pci_push(base);
1785         writel(np->linkspeed, base + NvRegLinkSpeed);
1786         pci_push(base);
1787
1788         return retval;
1789 }
1790
1791 static void nv_linkchange(struct net_device *dev)
1792 {
1793         if (nv_update_linkspeed(dev)) {
1794                 if (!netif_carrier_ok(dev)) {
1795                         netif_carrier_on(dev);
1796                         printk(KERN_INFO "%s: link up.\n", dev->name);
1797                         nv_start_rx(dev);
1798                 }
1799         } else {
1800                 if (netif_carrier_ok(dev)) {
1801                         netif_carrier_off(dev);
1802                         printk(KERN_INFO "%s: link down.\n", dev->name);
1803                         nv_stop_rx(dev);
1804                 }
1805         }
1806 }
1807
1808 static void nv_link_irq(struct net_device *dev)
1809 {
1810         u8 __iomem *base = get_hwbase(dev);
1811         u32 miistat;
1812
1813         miistat = readl(base + NvRegMIIStatus);
1814         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1815         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1816
1817         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1818                 nv_linkchange(dev);
1819         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1820 }
1821
1822 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1823 {
1824         struct net_device *dev = (struct net_device *) data;
1825         struct fe_priv *np = netdev_priv(dev);
1826         u8 __iomem *base = get_hwbase(dev);
1827         u32 events;
1828         int i;
1829
1830         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1831
1832         for (i=0; ; i++) {
1833                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1834                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1835                 pci_push(base);
1836                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1837                 if (!(events & np->irqmask))
1838                         break;
1839
1840                 spin_lock(&np->lock);
1841                 nv_tx_done(dev);
1842                 spin_unlock(&np->lock);
1843
1844                 nv_rx_process(dev);
1845                 if (nv_alloc_rx(dev)) {
1846                         spin_lock(&np->lock);
1847                         if (!np->in_shutdown)
1848                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1849                         spin_unlock(&np->lock);
1850                 }
1851
1852                 if (events & NVREG_IRQ_LINK) {
1853                         spin_lock(&np->lock);
1854                         nv_link_irq(dev);
1855                         spin_unlock(&np->lock);
1856                 }
1857                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1858                         spin_lock(&np->lock);
1859                         nv_linkchange(dev);
1860                         spin_unlock(&np->lock);
1861                         np->link_timeout = jiffies + LINK_TIMEOUT;
1862                 }
1863                 if (events & (NVREG_IRQ_TX_ERR)) {
1864                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1865                                                 dev->name, events);
1866                 }
1867                 if (events & (NVREG_IRQ_UNKNOWN)) {
1868                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1869                                                 dev->name, events);
1870                 }
1871                 if (i > max_interrupt_work) {
1872                         spin_lock(&np->lock);
1873                         /* disable interrupts on the nic */
1874                         writel(0, base + NvRegIrqMask);
1875                         pci_push(base);
1876
1877                         if (!np->in_shutdown)
1878                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1879                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1880                         spin_unlock(&np->lock);
1881                         break;
1882                 }
1883
1884         }
1885         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1886
1887         return IRQ_RETVAL(i);
1888 }
1889
1890 static void nv_do_nic_poll(unsigned long data)
1891 {
1892         struct net_device *dev = (struct net_device *) data;
1893         struct fe_priv *np = netdev_priv(dev);
1894         u8 __iomem *base = get_hwbase(dev);
1895
1896         disable_irq(dev->irq);
1897         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1898         /*
1899          * reenable interrupts on the nic, we have to do this before calling
1900          * nv_nic_irq because that may decide to do otherwise
1901          */
1902         writel(np->irqmask, base + NvRegIrqMask);
1903         pci_push(base);
1904         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1905         enable_irq(dev->irq);
1906 }
1907
1908 #ifdef CONFIG_NET_POLL_CONTROLLER
1909 static void nv_poll_controller(struct net_device *dev)
1910 {
1911         nv_do_nic_poll((unsigned long) dev);
1912 }
1913 #endif
1914
1915 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1916 {
1917         struct fe_priv *np = netdev_priv(dev);
1918         strcpy(info->driver, "forcedeth");
1919         strcpy(info->version, FORCEDETH_VERSION);
1920         strcpy(info->bus_info, pci_name(np->pci_dev));
1921 }
1922
1923 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1924 {
1925         struct fe_priv *np = netdev_priv(dev);
1926         wolinfo->supported = WAKE_MAGIC;
1927
1928         spin_lock_irq(&np->lock);
1929         if (np->wolenabled)
1930                 wolinfo->wolopts = WAKE_MAGIC;
1931         spin_unlock_irq(&np->lock);
1932 }
1933
1934 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1935 {
1936         struct fe_priv *np = netdev_priv(dev);
1937         u8 __iomem *base = get_hwbase(dev);
1938
1939         spin_lock_irq(&np->lock);
1940         if (wolinfo->wolopts == 0) {
1941                 writel(0, base + NvRegWakeUpFlags);
1942                 np->wolenabled = 0;
1943         }
1944         if (wolinfo->wolopts & WAKE_MAGIC) {
1945                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1946                 np->wolenabled = 1;
1947         }
1948         spin_unlock_irq(&np->lock);
1949         return 0;
1950 }
1951
1952 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1953 {
1954         struct fe_priv *np = netdev_priv(dev);
1955         int adv;
1956
1957         spin_lock_irq(&np->lock);
1958         ecmd->port = PORT_MII;
1959         if (!netif_running(dev)) {
1960                 /* We do not track link speed / duplex setting if the
1961                  * interface is disabled. Force a link check */
1962                 nv_update_linkspeed(dev);
1963         }
1964         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1965                 case NVREG_LINKSPEED_10:
1966                         ecmd->speed = SPEED_10;
1967                         break;
1968                 case NVREG_LINKSPEED_100:
1969                         ecmd->speed = SPEED_100;
1970                         break;
1971                 case NVREG_LINKSPEED_1000:
1972                         ecmd->speed = SPEED_1000;
1973                         break;
1974         }
1975         ecmd->duplex = DUPLEX_HALF;
1976         if (np->duplex)
1977                 ecmd->duplex = DUPLEX_FULL;
1978
1979         ecmd->autoneg = np->autoneg;
1980
1981         ecmd->advertising = ADVERTISED_MII;
1982         if (np->autoneg) {
1983                 ecmd->advertising |= ADVERTISED_Autoneg;
1984                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1985         } else {
1986                 adv = np->fixed_mode;
1987         }
1988         if (adv & ADVERTISE_10HALF)
1989                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1990         if (adv & ADVERTISE_10FULL)
1991                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1992         if (adv & ADVERTISE_100HALF)
1993                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1994         if (adv & ADVERTISE_100FULL)
1995                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1996         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1997                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1998                 if (adv & ADVERTISE_1000FULL)
1999                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
2000         }
2001
2002         ecmd->supported = (SUPPORTED_Autoneg |
2003                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2004                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2005                 SUPPORTED_MII);
2006         if (np->gigabit == PHY_GIGABIT)
2007                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2008
2009         ecmd->phy_address = np->phyaddr;
2010         ecmd->transceiver = XCVR_EXTERNAL;
2011
2012         /* ignore maxtxpkt, maxrxpkt for now */
2013         spin_unlock_irq(&np->lock);
2014         return 0;
2015 }
2016
2017 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2018 {
2019         struct fe_priv *np = netdev_priv(dev);
2020
2021         if (ecmd->port != PORT_MII)
2022                 return -EINVAL;
2023         if (ecmd->transceiver != XCVR_EXTERNAL)
2024                 return -EINVAL;
2025         if (ecmd->phy_address != np->phyaddr) {
2026                 /* TODO: support switching between multiple phys. Should be
2027                  * trivial, but not enabled due to lack of test hardware. */
2028                 return -EINVAL;
2029         }
2030         if (ecmd->autoneg == AUTONEG_ENABLE) {
2031                 u32 mask;
2032
2033                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2034                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2035                 if (np->gigabit == PHY_GIGABIT)
2036                         mask |= ADVERTISED_1000baseT_Full;
2037
2038                 if ((ecmd->advertising & mask) == 0)
2039                         return -EINVAL;
2040
2041         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2042                 /* Note: autonegotiation disable, speed 1000 intentionally
2043                  * forbidden - noone should need that. */
2044
2045                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2046                         return -EINVAL;
2047                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2048                         return -EINVAL;
2049         } else {
2050                 return -EINVAL;
2051         }
2052
2053         spin_lock_irq(&np->lock);
2054         if (ecmd->autoneg == AUTONEG_ENABLE) {
2055                 int adv, bmcr;
2056
2057                 np->autoneg = 1;
2058
2059                 /* advertise only what has been requested */
2060                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2061                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2062                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2063                         adv |= ADVERTISE_10HALF;
2064                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2065                         adv |= ADVERTISE_10FULL;
2066                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2067                         adv |= ADVERTISE_100HALF;
2068                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2069                         adv |= ADVERTISE_100FULL;
2070                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2071
2072                 if (np->gigabit == PHY_GIGABIT) {
2073                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2074                         adv &= ~ADVERTISE_1000FULL;
2075                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2076                                 adv |= ADVERTISE_1000FULL;
2077                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2078                 }
2079
2080                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2081                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2082                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2083
2084         } else {
2085                 int adv, bmcr;
2086
2087                 np->autoneg = 0;
2088
2089                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2090                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2091                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2092                         adv |= ADVERTISE_10HALF;
2093                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2094                         adv |= ADVERTISE_10FULL;
2095                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2096                         adv |= ADVERTISE_100HALF;
2097                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2098                         adv |= ADVERTISE_100FULL;
2099                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2100                 np->fixed_mode = adv;
2101
2102                 if (np->gigabit == PHY_GIGABIT) {
2103                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2104                         adv &= ~ADVERTISE_1000FULL;
2105                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2106                 }
2107
2108                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2109                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2110                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2111                         bmcr |= BMCR_FULLDPLX;
2112                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2113                         bmcr |= BMCR_SPEED100;
2114                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2115
2116                 if (netif_running(dev)) {
2117                         /* Wait a bit and then reconfigure the nic. */
2118                         udelay(10);
2119                         nv_linkchange(dev);
2120                 }
2121         }
2122         spin_unlock_irq(&np->lock);
2123
2124         return 0;
2125 }
2126
2127 #define FORCEDETH_REGS_VER      1
2128 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
2129
2130 static int nv_get_regs_len(struct net_device *dev)
2131 {
2132         return FORCEDETH_REGS_SIZE;
2133 }
2134
2135 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2136 {
2137         struct fe_priv *np = netdev_priv(dev);
2138         u8 __iomem *base = get_hwbase(dev);
2139         u32 *rbuf = buf;
2140         int i;
2141
2142         regs->version = FORCEDETH_REGS_VER;
2143         spin_lock_irq(&np->lock);
2144         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2145                 rbuf[i] = readl(base + i*sizeof(u32));
2146         spin_unlock_irq(&np->lock);
2147 }
2148
2149 static int nv_nway_reset(struct net_device *dev)
2150 {
2151         struct fe_priv *np = netdev_priv(dev);
2152         int ret;
2153
2154         spin_lock_irq(&np->lock);
2155         if (np->autoneg) {
2156                 int bmcr;
2157
2158                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2159                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2160                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2161
2162                 ret = 0;
2163         } else {
2164                 ret = -EINVAL;
2165         }
2166         spin_unlock_irq(&np->lock);
2167
2168         return ret;
2169 }
2170
2171 static struct ethtool_ops ops = {
2172         .get_drvinfo = nv_get_drvinfo,
2173         .get_link = ethtool_op_get_link,
2174         .get_wol = nv_get_wol,
2175         .set_wol = nv_set_wol,
2176         .get_settings = nv_get_settings,
2177         .set_settings = nv_set_settings,
2178         .get_regs_len = nv_get_regs_len,
2179         .get_regs = nv_get_regs,
2180         .nway_reset = nv_nway_reset,
2181         .get_perm_addr = ethtool_op_get_perm_addr,
2182 };
2183
2184 static int nv_open(struct net_device *dev)
2185 {
2186         struct fe_priv *np = netdev_priv(dev);
2187         u8 __iomem *base = get_hwbase(dev);
2188         int ret, oom, i;
2189
2190         dprintk(KERN_DEBUG "nv_open: begin\n");
2191
2192         /* 1) erase previous misconfiguration */
2193         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2194         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2195         writel(0, base + NvRegMulticastAddrB);
2196         writel(0, base + NvRegMulticastMaskA);
2197         writel(0, base + NvRegMulticastMaskB);
2198         writel(0, base + NvRegPacketFilterFlags);
2199
2200         writel(0, base + NvRegTransmitterControl);
2201         writel(0, base + NvRegReceiverControl);
2202
2203         writel(0, base + NvRegAdapterControl);
2204
2205         /* 2) initialize descriptor rings */
2206         set_bufsize(dev);
2207         oom = nv_init_ring(dev);
2208
2209         writel(0, base + NvRegLinkSpeed);
2210         writel(0, base + NvRegUnknownTransmitterReg);
2211         nv_txrx_reset(dev);
2212         writel(0, base + NvRegUnknownSetupReg6);
2213
2214         np->in_shutdown = 0;
2215
2216         /* 3) set mac address */
2217         nv_copy_mac_to_hw(dev);
2218
2219         /* 4) give hw rings */
2220         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2221         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2222                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2223         else
2224                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2225         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2226                 base + NvRegRingSizes);
2227
2228         /* 5) continue setup */
2229         writel(np->linkspeed, base + NvRegLinkSpeed);
2230         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2231         writel(np->txrxctl_bits, base + NvRegTxRxControl);
2232         pci_push(base);
2233         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2234         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2235                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2236                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2237
2238         writel(0, base + NvRegUnknownSetupReg4);
2239         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2240         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2241
2242         /* 6) continue setup */
2243         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2244         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2245         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2246         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2247
2248         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2249         get_random_bytes(&i, sizeof(i));
2250         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2251         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2252         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2253         if (poll_interval == -1) {
2254                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2255                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
2256                 else
2257                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
2258         }
2259         else
2260                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
2261         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2262         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2263                         base + NvRegAdapterControl);
2264         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2265         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2266         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2267
2268         i = readl(base + NvRegPowerState);
2269         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2270                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2271
2272         pci_push(base);
2273         udelay(10);
2274         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2275
2276         writel(0, base + NvRegIrqMask);
2277         pci_push(base);
2278         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2279         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2280         pci_push(base);
2281
2282         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2283         if (ret)
2284                 goto out_drain;
2285
2286         /* ask for interrupts */
2287         writel(np->irqmask, base + NvRegIrqMask);
2288
2289         spin_lock_irq(&np->lock);
2290         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2291         writel(0, base + NvRegMulticastAddrB);
2292         writel(0, base + NvRegMulticastMaskA);
2293         writel(0, base + NvRegMulticastMaskB);
2294         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2295         /* One manual link speed update: Interrupts are enabled, future link
2296          * speed changes cause interrupts and are handled by nv_link_irq().
2297          */
2298         {
2299                 u32 miistat;
2300                 miistat = readl(base + NvRegMIIStatus);
2301                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2302                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2303         }
2304         /* set linkspeed to invalid value, thus force nv_update_linkspeed
2305          * to init hw */
2306         np->linkspeed = 0;
2307         ret = nv_update_linkspeed(dev);
2308         nv_start_rx(dev);
2309         nv_start_tx(dev);
2310         netif_start_queue(dev);
2311         if (ret) {
2312                 netif_carrier_on(dev);
2313         } else {
2314                 printk("%s: no link during initialization.\n", dev->name);
2315                 netif_carrier_off(dev);
2316         }
2317         if (oom)
2318                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2319         spin_unlock_irq(&np->lock);
2320
2321         return 0;
2322 out_drain:
2323         drain_ring(dev);
2324         return ret;
2325 }
2326
2327 static int nv_close(struct net_device *dev)
2328 {
2329         struct fe_priv *np = netdev_priv(dev);
2330         u8 __iomem *base;
2331
2332         spin_lock_irq(&np->lock);
2333         np->in_shutdown = 1;
2334         spin_unlock_irq(&np->lock);
2335         synchronize_irq(dev->irq);
2336
2337         del_timer_sync(&np->oom_kick);
2338         del_timer_sync(&np->nic_poll);
2339
2340         netif_stop_queue(dev);
2341         spin_lock_irq(&np->lock);
2342         nv_stop_tx(dev);
2343         nv_stop_rx(dev);
2344         nv_txrx_reset(dev);
2345
2346         /* disable interrupts on the nic or we will lock up */
2347         base = get_hwbase(dev);
2348         writel(0, base + NvRegIrqMask);
2349         pci_push(base);
2350         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2351
2352         spin_unlock_irq(&np->lock);
2353
2354         free_irq(dev->irq, dev);
2355
2356         drain_ring(dev);
2357
2358         if (np->wolenabled)
2359                 nv_start_rx(dev);
2360
2361         /* special op: write back the misordered MAC address - otherwise
2362          * the next nv_probe would see a wrong address.
2363          */
2364         writel(np->orig_mac[0], base + NvRegMacAddrA);
2365         writel(np->orig_mac[1], base + NvRegMacAddrB);
2366
2367         /* FIXME: power down nic */
2368
2369         return 0;
2370 }
2371
2372 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2373 {
2374         struct net_device *dev;
2375         struct fe_priv *np;
2376         unsigned long addr;
2377         u8 __iomem *base;
2378         int err, i;
2379
2380         dev = alloc_etherdev(sizeof(struct fe_priv));
2381         err = -ENOMEM;
2382         if (!dev)
2383                 goto out;
2384
2385         np = netdev_priv(dev);
2386         np->pci_dev = pci_dev;
2387         spin_lock_init(&np->lock);
2388         SET_MODULE_OWNER(dev);
2389         SET_NETDEV_DEV(dev, &pci_dev->dev);
2390
2391         init_timer(&np->oom_kick);
2392         np->oom_kick.data = (unsigned long) dev;
2393         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2394         init_timer(&np->nic_poll);
2395         np->nic_poll.data = (unsigned long) dev;
2396         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2397
2398         err = pci_enable_device(pci_dev);
2399         if (err) {
2400                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2401                                 err, pci_name(pci_dev));
2402                 goto out_free;
2403         }
2404
2405         pci_set_master(pci_dev);
2406
2407         err = pci_request_regions(pci_dev, DRV_NAME);
2408         if (err < 0)
2409                 goto out_disable;
2410
2411         err = -EINVAL;
2412         addr = 0;
2413         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2414                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2415                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2416                                 pci_resource_len(pci_dev, i),
2417                                 pci_resource_flags(pci_dev, i));
2418                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2419                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2420                         addr = pci_resource_start(pci_dev, i);
2421                         break;
2422                 }
2423         }
2424         if (i == DEVICE_COUNT_RESOURCE) {
2425                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2426                                         pci_name(pci_dev));
2427                 goto out_relreg;
2428         }
2429
2430         /* handle different descriptor versions */
2431         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2432                 /* packet format 3: supports 40-bit addressing */
2433                 np->desc_ver = DESC_VER_3;
2434                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2435                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2436                                         pci_name(pci_dev));
2437                 } else {
2438                         dev->features |= NETIF_F_HIGHDMA;
2439                 }
2440                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2441         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2442                 /* packet format 2: supports jumbo frames */
2443                 np->desc_ver = DESC_VER_2;
2444                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2445         } else {
2446                 /* original packet format */
2447                 np->desc_ver = DESC_VER_1;
2448                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2449         }
2450
2451         np->pkt_limit = NV_PKTLIMIT_1;
2452         if (id->driver_data & DEV_HAS_LARGEDESC)
2453                 np->pkt_limit = NV_PKTLIMIT_2;
2454
2455         if (id->driver_data & DEV_HAS_CHECKSUM) {
2456                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2457                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2458 #ifdef NETIF_F_TSO
2459                 /* disabled dev->features |= NETIF_F_TSO; */
2460 #endif
2461         }
2462
2463         err = -ENOMEM;
2464         np->base = ioremap(addr, NV_PCI_REGSZ);
2465         if (!np->base)
2466                 goto out_relreg;
2467         dev->base_addr = (unsigned long)np->base;
2468
2469         dev->irq = pci_dev->irq;
2470
2471         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2472                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2473                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2474                                         &np->ring_addr);
2475                 if (!np->rx_ring.orig)
2476                         goto out_unmap;
2477                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2478         } else {
2479                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2480                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2481                                         &np->ring_addr);
2482                 if (!np->rx_ring.ex)
2483                         goto out_unmap;
2484                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2485         }
2486
2487         dev->open = nv_open;
2488         dev->stop = nv_close;
2489         dev->hard_start_xmit = nv_start_xmit;
2490         dev->get_stats = nv_get_stats;
2491         dev->change_mtu = nv_change_mtu;
2492         dev->set_mac_address = nv_set_mac_address;
2493         dev->set_multicast_list = nv_set_multicast;
2494 #ifdef CONFIG_NET_POLL_CONTROLLER
2495         dev->poll_controller = nv_poll_controller;
2496 #endif
2497         SET_ETHTOOL_OPS(dev, &ops);
2498         dev->tx_timeout = nv_tx_timeout;
2499         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2500
2501         pci_set_drvdata(pci_dev, dev);
2502
2503         /* read the mac address */
2504         base = get_hwbase(dev);
2505         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2506         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2507
2508         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2509         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2510         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2511         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2512         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2513         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2514         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2515
2516         if (!is_valid_ether_addr(dev->perm_addr)) {
2517                 /*
2518                  * Bad mac address. At least one bios sets the mac address
2519                  * to 01:23:45:67:89:ab
2520                  */
2521                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2522                         pci_name(pci_dev),
2523                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2524                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2525                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2526                 dev->dev_addr[0] = 0x00;
2527                 dev->dev_addr[1] = 0x00;
2528                 dev->dev_addr[2] = 0x6c;
2529                 get_random_bytes(&dev->dev_addr[3], 3);
2530         }
2531
2532         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2533                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2534                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2535
2536         /* disable WOL */
2537         writel(0, base + NvRegWakeUpFlags);
2538         np->wolenabled = 0;
2539
2540         if (np->desc_ver == DESC_VER_1) {
2541                 np->tx_flags = NV_TX_VALID;
2542         } else {
2543                 np->tx_flags = NV_TX2_VALID;
2544         }
2545         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2546                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
2547         else
2548                 np->irqmask = NVREG_IRQMASK_CPU;
2549
2550         if (id->driver_data & DEV_NEED_TIMERIRQ)
2551                 np->irqmask |= NVREG_IRQ_TIMER;
2552         if (id->driver_data & DEV_NEED_LINKTIMER) {
2553                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2554                 np->need_linktimer = 1;
2555                 np->link_timeout = jiffies + LINK_TIMEOUT;
2556         } else {
2557                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2558                 np->need_linktimer = 0;
2559         }
2560
2561         /* find a suitable phy */
2562         for (i = 1; i <= 32; i++) {
2563                 int id1, id2;
2564                 int phyaddr = i & 0x1F;
2565
2566                 spin_lock_irq(&np->lock);
2567                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
2568                 spin_unlock_irq(&np->lock);
2569                 if (id1 < 0 || id1 == 0xffff)
2570                         continue;
2571                 spin_lock_irq(&np->lock);
2572                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
2573                 spin_unlock_irq(&np->lock);
2574                 if (id2 < 0 || id2 == 0xffff)
2575                         continue;
2576
2577                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2578                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2579                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2580                         pci_name(pci_dev), id1, id2, phyaddr);
2581                 np->phyaddr = phyaddr;
2582                 np->phy_oui = id1 | id2;
2583                 break;
2584         }
2585         if (i == 33) {
2586                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2587                        pci_name(pci_dev));
2588                 goto out_freering;
2589         }
2590
2591         /* reset it */
2592         phy_init(dev);
2593
2594         /* set default link speed settings */
2595         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2596         np->duplex = 0;
2597         np->autoneg = 1;
2598
2599         err = register_netdev(dev);
2600         if (err) {
2601                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2602                 goto out_freering;
2603         }
2604         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2605                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2606                         pci_name(pci_dev));
2607
2608         return 0;
2609
2610 out_freering:
2611         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2612                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2613                                     np->rx_ring.orig, np->ring_addr);
2614         else
2615                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2616                                     np->rx_ring.ex, np->ring_addr);
2617         pci_set_drvdata(pci_dev, NULL);
2618 out_unmap:
2619         iounmap(get_hwbase(dev));
2620 out_relreg:
2621         pci_release_regions(pci_dev);
2622 out_disable:
2623         pci_disable_device(pci_dev);
2624 out_free:
2625         free_netdev(dev);
2626 out:
2627         return err;
2628 }
2629
2630 static void __devexit nv_remove(struct pci_dev *pci_dev)
2631 {
2632         struct net_device *dev = pci_get_drvdata(pci_dev);
2633         struct fe_priv *np = netdev_priv(dev);
2634
2635         unregister_netdev(dev);
2636
2637         /* free all structures */
2638         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2639                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2640         else
2641                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2642         iounmap(get_hwbase(dev));
2643         pci_release_regions(pci_dev);
2644         pci_disable_device(pci_dev);
2645         free_netdev(dev);
2646         pci_set_drvdata(pci_dev, NULL);
2647 }
2648
2649 static struct pci_device_id pci_tbl[] = {
2650         {       /* nForce Ethernet Controller */
2651                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2652                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2653         },
2654         {       /* nForce2 Ethernet Controller */
2655                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2656                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2657         },
2658         {       /* nForce3 Ethernet Controller */
2659                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2660                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2661         },
2662         {       /* nForce3 Ethernet Controller */
2663                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2664                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2665         },
2666         {       /* nForce3 Ethernet Controller */
2667                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2668                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2669         },
2670         {       /* nForce3 Ethernet Controller */
2671                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2672                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2673         },
2674         {       /* nForce3 Ethernet Controller */
2675                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2676                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2677         },
2678         {       /* CK804 Ethernet Controller */
2679                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2680                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2681         },
2682         {       /* CK804 Ethernet Controller */
2683                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2684                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2685         },
2686         {       /* MCP04 Ethernet Controller */
2687                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2688                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2689         },
2690         {       /* MCP04 Ethernet Controller */
2691                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2692                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2693         },
2694         {       /* MCP51 Ethernet Controller */
2695                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2696                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2697         },
2698         {       /* MCP51 Ethernet Controller */
2699                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2700                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2701         },
2702         {       /* MCP55 Ethernet Controller */
2703                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2704                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2705         },
2706         {       /* MCP55 Ethernet Controller */
2707                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2708                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2709         },
2710         {0,},
2711 };
2712
2713 static struct pci_driver driver = {
2714         .name = "forcedeth",
2715         .id_table = pci_tbl,
2716         .probe = nv_probe,
2717         .remove = __devexit_p(nv_remove),
2718 };
2719
2720
2721 static int __init init_nic(void)
2722 {
2723         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2724         return pci_module_init(&driver);
2725 }
2726
2727 static void __exit exit_nic(void)
2728 {
2729         pci_unregister_driver(&driver);
2730 }
2731
2732 module_param(max_interrupt_work, int, 0);
2733 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2734 module_param(optimization_mode, int, 0);
2735 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
2736 module_param(poll_interval, int, 0);
2737 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
2738
2739 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2740 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2741 MODULE_LICENSE("GPL");
2742
2743 MODULE_DEVICE_TABLE(pci, pci_tbl);
2744
2745 module_init(init_nic);
2746 module_exit(exit_nic);