git.oblomov.eu Git - linux-2.6/blob - drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/dma.h>
  24 #include <asm/ecard.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct icside_state *state = hwif->hwif_data;
 213         struct scatterlist *sg = hwif->sg_table;
 214
 215         ide_map_sg(drive, rq);
 216
 217         if (rq_data_dir(rq) == READ)
 218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 219         else
 220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 221
 222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 223                                     hwif->sg_dma_direction);
 224 }
 225
 226 /*
 227  * Configure the IOMD to give the appropriate timings for the transfer
 228  * mode being requested.  We take the advice of the ATA standards, and
 229  * calculate the cycle time based on the transfer mode, and the EIDE
 230  * MW DMA specs that the drive provides in the IDENTIFY command.
 231  *
 232  * We have the following IOMD DMA modes to choose from:
 233  *
 234  *      Type    Active          Recovery        Cycle
 235  *      A       250 (250)       312 (550)       562 (800)
 236  *      B       187             250             437
 237  *      C       125 (125)       125 (375)       250 (500)
 238  *      D       62              125             187
 239  *
 240  * (figures in brackets are actual measured timings)
 241  *
 242  * However, we also need to take care of the read/write active and
 243  * recovery timings:
 244  *
 245  *                      Read    Write
 246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 247  *      MW0     215     50      215     480     A
 248  *      MW1     80      50      50      150     C
 249  *      MW2     70      25      25      120     C
 250  */
 251 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
 252 {
 253         int on = 0, cycle_time = 0, use_dma_info = 0;
 254
 255         /*
 256          * Limit the transfer speed to MW_DMA_2.
 257          */
 258         xfer_mode = ide_rate_filter(drive, xfer_mode);
 259
 260         switch (xfer_mode) {
 261         case XFER_MW_DMA_2:
 262                 cycle_time = 250;
 263                 use_dma_info = 1;
 264                 break;
 265
 266         case XFER_MW_DMA_1:
 267                 cycle_time = 250;
 268                 use_dma_info = 1;
 269                 break;
 270
 271         case XFER_MW_DMA_0:
 272                 cycle_time = 480;
 273                 break;
 274
 275         case XFER_SW_DMA_2:
 276         case XFER_SW_DMA_1:
 277         case XFER_SW_DMA_0:
 278                 cycle_time = 480;
 279                 break;
 280         }
 281
 282         /*
 283          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 284          * take care to note the values in the ID...
 285          */
 286         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 287                 cycle_time = drive->id->eide_dma_time;
 288
 289         drive->drive_data = cycle_time;
 290
 291         if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
 292                 on = 1;
 293         else
 294                 drive->drive_data = 480;
 295
 296         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 297                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 298
 299         drive->current_speed = xfer_mode;
 300
 301         return on;
 302 }
 303
 304 static void icside_dma_host_off(ide_drive_t *drive)
 305 {
 306 }
 307
 308 static void icside_dma_off_quietly(ide_drive_t *drive)
 309 {
 310         drive->using_dma = 0;
 311 }
 312
 313 static void icside_dma_host_on(ide_drive_t *drive)
 314 {
 315 }
 316
 317 static int icside_dma_on(ide_drive_t *drive)
 318 {
 319         drive->using_dma = 1;
 320
 321         return 0;
 322 }
 323
 324 static int icside_dma_check(ide_drive_t *drive)
 325 {
 326         struct hd_driveid *id = drive->id;
 327         ide_hwif_t *hwif = HWIF(drive);
 328         int xfer_mode = XFER_PIO_2;
 329         int on;
 330
 331         if (!(id->capability & 1) || !hwif->autodma)
 332                 goto out;
 333
 334         /*
 335          * Consult the list of known "bad" drives
 336          */
 337         if (__ide_dma_bad_drive(drive))
 338                 goto out;
 339
 340         /*
 341          * Enable DMA on any drive that has multiword DMA
 342          */
 343         if (id->field_valid & 2) {
 344                 xfer_mode = ide_max_dma_mode(drive);
 345                 goto out;
 346         }
 347
 348         /*
 349          * Consult the list of known "good" drives
 350          */
 351         if (__ide_dma_good_drive(drive)) {
 352                 if (id->eide_dma_time > 150)
 353                         goto out;
 354                 xfer_mode = XFER_MW_DMA_1;
 355         }
 356
 357 out:
 358         on = icside_set_speed(drive, xfer_mode);
 359
 360         return on ? 0 : -1;
 361 }
 362
 363 static int icside_dma_end(ide_drive_t *drive)
 364 {
 365         ide_hwif_t *hwif = HWIF(drive);
 366         struct icside_state *state = hwif->hwif_data;
 367
 368         drive->waiting_for_dma = 0;
 369
 370         disable_dma(hwif->hw.dma);
 371
 372         /* Teardown mappings after DMA has completed. */
 373         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 374                      hwif->sg_dma_direction);
 375
 376         return get_dma_residue(hwif->hw.dma) != 0;
 377 }
 378
 379 static void icside_dma_start(ide_drive_t *drive)
 380 {
 381         ide_hwif_t *hwif = HWIF(drive);
 382
 383         /* We can not enable DMA on both channels simultaneously. */
 384         BUG_ON(dma_channel_active(hwif->hw.dma));
 385         enable_dma(hwif->hw.dma);
 386 }
 387
 388 static int icside_dma_setup(ide_drive_t *drive)
 389 {
 390         ide_hwif_t *hwif = HWIF(drive);
 391         struct request *rq = hwif->hwgroup->rq;
 392         unsigned int dma_mode;
 393
 394         if (rq_data_dir(rq))
 395                 dma_mode = DMA_MODE_WRITE;
 396         else
 397                 dma_mode = DMA_MODE_READ;
 398
 399         /*
 400          * We can not enable DMA on both channels.
 401          */
 402         BUG_ON(dma_channel_active(hwif->hw.dma));
 403
 404         icside_build_sglist(drive, rq);
 405
 406         /*
 407          * Ensure that we have the right interrupt routed.
 408          */
 409         icside_maskproc(drive, 0);
 410
 411         /*
 412          * Route the DMA signals to the correct interface.
 413          */
 414         writeb(hwif->select_data, hwif->config_data);
 415
 416         /*
 417          * Select the correct timing for this drive.
 418          */
 419         set_dma_speed(hwif->hw.dma, drive->drive_data);
 420
 421         /*
 422          * Tell the DMA engine about the SG table and
 423          * data direction.
 424          */
 425         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 426         set_dma_mode(hwif->hw.dma, dma_mode);
 427
 428         drive->waiting_for_dma = 1;
 429
 430         return 0;
 431 }
 432
 433 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 434 {
 435         /* issue cmd to drive */
 436         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 437 }
 438
 439 static int icside_dma_test_irq(ide_drive_t *drive)
 440 {
 441         ide_hwif_t *hwif = HWIF(drive);
 442         struct icside_state *state = hwif->hwif_data;
 443
 444         return readb(state->irq_port +
 445                      (hwif->channel ?
 446                         ICS_ARCIN_V6_INTRSTAT_2 :
 447                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 448 }
 449
 450 static void icside_dma_timeout(ide_drive_t *drive)
 451 {
 452         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 453
 454         if (icside_dma_test_irq(drive))
 455                 return;
 456
 457         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 458
 459         icside_dma_end(drive);
 460 }
 461
 462 static void icside_dma_lost_irq(ide_drive_t *drive)
 463 {
 464         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 465 }
 466
 467 static void icside_dma_init(ide_hwif_t *hwif)
 468 {
 469         printk("    %s: SG-DMA", hwif->name);
 470
 471         hwif->atapi_dma         = 1;
 472         hwif->mwdma_mask        = 7; /* MW0..2 */
 473         hwif->swdma_mask        = 7; /* SW0..2 */
 474
 475         hwif->dmatable_cpu      = NULL;
 476         hwif->dmatable_dma      = 0;
 477         hwif->speedproc         = icside_set_speed;
 478         hwif->autodma           = 1;
 479
 480         hwif->ide_dma_check     = icside_dma_check;
 481         hwif->dma_host_off      = icside_dma_host_off;
 482         hwif->dma_off_quietly   = icside_dma_off_quietly;
 483         hwif->dma_host_on       = icside_dma_host_on;
 484         hwif->ide_dma_on        = icside_dma_on;
 485         hwif->dma_setup         = icside_dma_setup;
 486         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 487         hwif->dma_start         = icside_dma_start;
 488         hwif->ide_dma_end       = icside_dma_end;
 489         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 490         hwif->dma_timeout       = icside_dma_timeout;
 491         hwif->dma_lost_irq      = icside_dma_lost_irq;
 492
 493         hwif->drives[0].autodma = hwif->autodma;
 494         hwif->drives[1].autodma = hwif->autodma;
 495
 496         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 497 }
 498 #else
 499 #define icside_dma_init(hwif)   (0)
 500 #endif
 501
 502 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 503 {
 504         ide_hwif_t *hwif;
 505         int index;
 506
 507         for (index = 0; index < MAX_HWIFS; ++index) {
 508                 hwif = &ide_hwifs[index];
 509                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 510                         goto found;
 511         }
 512
 513         for (index = 0; index < MAX_HWIFS; ++index) {
 514                 hwif = &ide_hwifs[index];
 515                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 516                         goto found;
 517         }
 518
 519         hwif = NULL;
 520 found:
 521         return hwif;
 522 }
 523
 524 static ide_hwif_t *
 525 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 526 {
 527         unsigned long port = (unsigned long)base + info->dataoffset;
 528         ide_hwif_t *hwif;
 529
 530         hwif = icside_find_hwif(port);
 531         if (hwif) {
 532                 int i;
 533
 534                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 535
 536                 /*
 537                  * Ensure we're using MMIO
 538                  */
 539                 default_hwif_mmiops(hwif);
 540                 hwif->mmio = 1;
 541
 542                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 543                         hwif->hw.io_ports[i] = port;
 544                         hwif->io_ports[i] = port;
 545                         port += 1 << info->stepping;
 546                 }
 547                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 548                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 549                 hwif->hw.irq  = ec->irq;
 550                 hwif->irq     = ec->irq;
 551                 hwif->noprobe = 0;
 552                 hwif->chipset = ide_acorn;
 553                 hwif->gendev.parent = &ec->dev;
 554         }
 555
 556         return hwif;
 557 }
 558
 559 static int __init
 560 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 561 {
 562         ide_hwif_t *hwif;
 563         void __iomem *base;
 564
 565         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 566         if (!base)
 567                 return -ENOMEM;
 568
 569         state->irq_port = base;
 570
 571         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 572         ec->irqmask  = 1;
 573
 574         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 575
 576         /*
 577          * Be on the safe side - disable interrupts
 578          */
 579         icside_irqdisable_arcin_v5(ec, 0);
 580
 581         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 582         if (!hwif)
 583                 return -ENODEV;
 584
 585         state->hwif[0] = hwif;
 586
 587         probe_hwif_init(hwif);
 588
 589         ide_proc_register_port(hwif);
 590
 591         return 0;
 592 }
 593
 594 static int __init
 595 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 596 {
 597         ide_hwif_t *hwif, *mate;
 598         void __iomem *ioc_base, *easi_base;
 599         unsigned int sel = 0;
 600         int ret;
 601
 602         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 603         if (!ioc_base) {
 604                 ret = -ENOMEM;
 605                 goto out;
 606         }
 607
 608         easi_base = ioc_base;
 609
 610         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 611                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 612                 if (!easi_base) {
 613                         ret = -ENOMEM;
 614                         goto out;
 615                 }
 616
 617                 /*
 618                  * Enable access to the EASI region.
 619                  */
 620                 sel = 1 << 5;
 621         }
 622
 623         writeb(sel, ioc_base);
 624
 625         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 626
 627         state->irq_port   = easi_base;
 628         state->ioc_base   = ioc_base;
 629
 630         /*
 631          * Be on the safe side - disable interrupts
 632          */
 633         icside_irqdisable_arcin_v6(ec, 0);
 634
 635         /*
 636          * Find and register the interfaces.
 637          */
 638         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 639         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 640
 641         if (!hwif || !mate) {
 642                 ret = -ENODEV;
 643                 goto out;
 644         }
 645
 646         state->hwif[0]    = hwif;
 647         state->hwif[1]    = mate;
 648
 649         hwif->maskproc    = icside_maskproc;
 650         hwif->channel     = 0;
 651         hwif->hwif_data   = state;
 652         hwif->mate        = mate;
 653         hwif->serialized  = 1;
 654         hwif->config_data = (unsigned long)ioc_base;
 655         hwif->select_data = sel;
 656         hwif->hw.dma      = ec->dma;
 657
 658         mate->maskproc    = icside_maskproc;
 659         mate->channel     = 1;
 660         mate->hwif_data   = state;
 661         mate->mate        = hwif;
 662         mate->serialized  = 1;
 663         mate->config_data = (unsigned long)ioc_base;
 664         mate->select_data = sel | 1;
 665         mate->hw.dma      = ec->dma;
 666
 667         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 668                 icside_dma_init(hwif);
 669                 icside_dma_init(mate);
 670         }
 671
 672         probe_hwif_init(hwif);
 673         probe_hwif_init(mate);
 674
 675         ide_proc_register_port(hwif);
 676         ide_proc_register_port(mate);
 677
 678         return 0;
 679
 680  out:
 681         return ret;
 682 }
 683
 684 static int __devinit
 685 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 686 {
 687         struct icside_state *state;
 688         void __iomem *idmem;
 689         int ret;
 690
 691         ret = ecard_request_resources(ec);
 692         if (ret)
 693                 goto out;
 694
 695         state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
 696         if (!state) {
 697                 ret = -ENOMEM;
 698                 goto release;
 699         }
 700
 701         state->type     = ICS_TYPE_NOTYPE;
 702         state->dev      = &ec->dev;
 703
 704         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 705         if (idmem) {
 706                 unsigned int type;
 707
 708                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 709                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 710                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 711                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 712                 ecardm_iounmap(ec, idmem);
 713
 714                 state->type = type;
 715         }
 716
 717         switch (state->type) {
 718         case ICS_TYPE_A3IN:
 719                 dev_warn(&ec->dev, "A3IN unsupported\n");
 720                 ret = -ENODEV;
 721                 break;
 722
 723         case ICS_TYPE_A3USER:
 724                 dev_warn(&ec->dev, "A3USER unsupported\n");
 725                 ret = -ENODEV;
 726                 break;
 727
 728         case ICS_TYPE_V5:
 729                 ret = icside_register_v5(state, ec);
 730                 break;
 731
 732         case ICS_TYPE_V6:
 733                 ret = icside_register_v6(state, ec);
 734                 break;
 735
 736         default:
 737                 dev_warn(&ec->dev, "unknown interface type\n");
 738                 ret = -ENODEV;
 739                 break;
 740         }
 741
 742         if (ret == 0) {
 743                 ecard_set_drvdata(ec, state);
 744                 goto out;
 745         }
 746
 747         kfree(state);
 748  release:
 749         ecard_release_resources(ec);
 750  out:
 751         return ret;
 752 }
 753
 754 static void __devexit icside_remove(struct expansion_card *ec)
 755 {
 756         struct icside_state *state = ecard_get_drvdata(ec);
 757
 758         switch (state->type) {
 759         case ICS_TYPE_V5:
 760                 /* FIXME: tell IDE to stop using the interface */
 761
 762                 /* Disable interrupts */
 763                 icside_irqdisable_arcin_v5(ec, 0);
 764                 break;
 765
 766         case ICS_TYPE_V6:
 767                 /* FIXME: tell IDE to stop using the interface */
 768                 if (ec->dma != NO_DMA)
 769                         free_dma(ec->dma);
 770
 771                 /* Disable interrupts */
 772                 icside_irqdisable_arcin_v6(ec, 0);
 773
 774                 /* Reset the ROM pointer/EASI selection */
 775                 writeb(0, state->ioc_base);
 776                 break;
 777         }
 778
 779         ecard_set_drvdata(ec, NULL);
 780
 781         kfree(state);
 782         ecard_release_resources(ec);
 783 }
 784
 785 static void icside_shutdown(struct expansion_card *ec)
 786 {
 787         struct icside_state *state = ecard_get_drvdata(ec);
 788         unsigned long flags;
 789
 790         /*
 791          * Disable interrupts from this card.  We need to do
 792          * this before disabling EASI since we may be accessing
 793          * this register via that region.
 794          */
 795         local_irq_save(flags);
 796         ec->ops->irqdisable(ec, 0);
 797         local_irq_restore(flags);
 798
 799         /*
 800          * Reset the ROM pointer so that we can read the ROM
 801          * after a soft reboot.  This also disables access to
 802          * the IDE taskfile via the EASI region.
 803          */
 804         if (state->ioc_base)
 805                 writeb(0, state->ioc_base);
 806 }
 807
 808 static const struct ecard_id icside_ids[] = {
 809         { MANU_ICS,  PROD_ICS_IDE  },
 810         { MANU_ICS2, PROD_ICS2_IDE },
 811         { 0xffff, 0xffff }
 812 };
 813
 814 static struct ecard_driver icside_driver = {
 815         .probe          = icside_probe,
 816         .remove         = __devexit_p(icside_remove),
 817         .shutdown       = icside_shutdown,
 818         .id_table       = icside_ids,
 819         .drv = {
 820                 .name   = "icside",
 821         },
 822 };
 823
 824 static int __init icside_init(void)
 825 {
 826         return ecard_register_driver(&icside_driver);
 827 }
 828
 829 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 830 MODULE_LICENSE("GPL");
 831 MODULE_DESCRIPTION("ICS IDE driver");
 832
 833 module_init(icside_init);