2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#134 $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
55 /****************************** Softc Data ************************************/
56 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
58 /***************************** Lookup Tables **********************************/
59 char *ahc_chip_names[] =
76 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
79 * Hardware error codes.
81 struct ahc_hard_error_entry {
86 static struct ahc_hard_error_entry ahc_hard_errors[] = {
87 { ILLHADDR, "Illegal Host Access" },
88 { ILLSADDR, "Illegal Sequencer Address referrenced" },
89 { ILLOPCODE, "Illegal Opcode in sequencer program" },
90 { SQPARERR, "Sequencer Parity Error" },
91 { DPARERR, "Data-path Parity Error" },
92 { MPARERR, "Scratch or SCB Memory Parity Error" },
93 { PCIERRSTAT, "PCI Error detected" },
94 { CIOPARERR, "CIOBUS Parity Error" },
96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
98 static struct ahc_phase_table_entry ahc_phase_table[] =
100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
104 { P_COMMAND, MSG_NOOP, "in Command phase" },
105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
108 { P_BUSFREE, MSG_NOOP, "while idle" },
109 { 0, MSG_NOOP, "in unknown phase" }
113 * In most cases we only wish to itterate over real phases, so
114 * exclude the last element from the count.
116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
119 * Valid SCSIRATE values. (p. 3-17)
120 * Provides a mapping of tranfer periods in ns to the proper value to
121 * stick in the scsixfer reg.
123 static struct ahc_syncrate ahc_syncrates[] =
125 /* ultra2 fast/ultra period rate */
126 { 0x42, 0x000, 9, "80.0" },
127 { 0x03, 0x000, 10, "40.0" },
128 { 0x04, 0x000, 11, "33.0" },
129 { 0x05, 0x100, 12, "20.0" },
130 { 0x06, 0x110, 15, "16.0" },
131 { 0x07, 0x120, 18, "13.4" },
132 { 0x08, 0x000, 25, "10.0" },
133 { 0x19, 0x010, 31, "8.0" },
134 { 0x1a, 0x020, 37, "6.67" },
135 { 0x1b, 0x030, 43, "5.7" },
136 { 0x1c, 0x040, 50, "5.0" },
137 { 0x00, 0x050, 56, "4.4" },
138 { 0x00, 0x060, 62, "4.0" },
139 { 0x00, 0x070, 68, "3.6" },
140 { 0x00, 0x000, 0, NULL }
143 /* Our Sequencer Program */
144 #include "aic7xxx_seq.h"
146 /**************************** Function Declarations ***************************/
147 static void ahc_force_renegotiation(struct ahc_softc *ahc,
148 struct ahc_devinfo *devinfo);
149 static struct ahc_tmode_tstate*
150 ahc_alloc_tstate(struct ahc_softc *ahc,
151 u_int scsi_id, char channel);
152 #ifdef AHC_TARGET_MODE
153 static void ahc_free_tstate(struct ahc_softc *ahc,
154 u_int scsi_id, char channel, int force);
156 static struct ahc_syncrate*
157 ahc_devlimited_syncrate(struct ahc_softc *ahc,
158 struct ahc_initiator_tinfo *,
162 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
163 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
164 struct ahc_devinfo *devinfo);
165 static void ahc_scb_devinfo(struct ahc_softc *ahc,
166 struct ahc_devinfo *devinfo,
168 static void ahc_assert_atn(struct ahc_softc *ahc);
169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
172 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo);
174 static void ahc_construct_sdtr(struct ahc_softc *ahc,
175 struct ahc_devinfo *devinfo,
176 u_int period, u_int offset);
177 static void ahc_construct_wdtr(struct ahc_softc *ahc,
178 struct ahc_devinfo *devinfo,
180 static void ahc_construct_ppr(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo,
182 u_int period, u_int offset,
183 u_int bus_width, u_int ppr_options);
184 static void ahc_clear_msg_state(struct ahc_softc *ahc);
185 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
186 static void ahc_handle_message_phase(struct ahc_softc *ahc);
192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
193 u_int msgval, int full);
194 static int ahc_parse_msg(struct ahc_softc *ahc,
195 struct ahc_devinfo *devinfo);
196 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo);
198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
199 struct ahc_devinfo *devinfo);
200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
201 static void ahc_handle_devreset(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
203 cam_status status, char *message,
205 #ifdef AHC_TARGET_MODE
206 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
207 struct ahc_devinfo *devinfo,
211 static bus_dmamap_callback_t ahc_dmamap_cb;
212 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
213 static int ahc_init_scbdata(struct ahc_softc *ahc);
214 static void ahc_fini_scbdata(struct ahc_softc *ahc);
215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
216 struct scb *prev_scb,
218 static int ahc_qinfifo_count(struct ahc_softc *ahc);
219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
220 u_int prev, u_int scbptr);
221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
222 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
223 u_int scbpos, u_int prev);
224 static void ahc_reset_current_bus(struct ahc_softc *ahc);
226 static void ahc_dumpseq(struct ahc_softc *ahc);
228 static int ahc_loadseq(struct ahc_softc *ahc);
229 static int ahc_check_patch(struct ahc_softc *ahc,
230 struct patch **start_patch,
231 u_int start_instr, u_int *skip_addr);
232 static void ahc_download_instr(struct ahc_softc *ahc,
233 u_int instrptr, uint8_t *dconsts);
234 #ifdef AHC_TARGET_MODE
235 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
236 struct ahc_tmode_lstate *lstate,
240 static void ahc_update_scsiid(struct ahc_softc *ahc,
242 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
243 struct target_cmd *cmd);
245 /************************* Sequencer Execution Control ************************/
247 * Restart the sequencer program from address zero
250 ahc_restart(struct ahc_softc *ahc)
255 /* No more pending messages. */
256 ahc_clear_msg_state(ahc);
258 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
259 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
260 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
261 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
262 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
263 ahc_outb(ahc, SAVED_LUN, 0xFF);
266 * Ensure that the sequencer's idea of TQINPOS
267 * matches our own. The sequencer increments TQINPOS
268 * only after it sees a DMA complete and a reset could
269 * occur before the increment leaving the kernel to believe
270 * the command arrived but the sequencer to not.
272 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
274 /* Always allow reselection */
275 ahc_outb(ahc, SCSISEQ,
276 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
277 if ((ahc->features & AHC_CMD_CHAN) != 0) {
278 /* Ensure that no DMA operations are in progress */
279 ahc_outb(ahc, CCSCBCNT, 0);
280 ahc_outb(ahc, CCSGCTL, 0);
281 ahc_outb(ahc, CCSCBCTL, 0);
284 * If we were in the process of DMA'ing SCB data into
285 * an SCB, replace that SCB on the free list. This prevents
288 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
289 ahc_add_curscb_to_free_list(ahc);
290 ahc_outb(ahc, SEQ_FLAGS2,
291 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
293 ahc_outb(ahc, MWI_RESIDUAL, 0);
294 ahc_outb(ahc, SEQCTL, ahc->seqctl);
295 ahc_outb(ahc, SEQADDR0, 0);
296 ahc_outb(ahc, SEQADDR1, 0);
300 /************************* Input/Output Queues ********************************/
302 ahc_run_qoutfifo(struct ahc_softc *ahc)
307 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
308 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
310 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
311 if ((ahc->qoutfifonext & 0x03) == 0x03) {
315 * Clear 32bits of QOUTFIFO at a time
316 * so that we don't clobber an incoming
317 * byte DMA to the array on architectures
318 * that only support 32bit load and store
321 modnext = ahc->qoutfifonext & ~0x3;
322 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
323 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
324 ahc->shared_data_dmamap,
325 /*offset*/modnext, /*len*/4,
326 BUS_DMASYNC_PREREAD);
330 scb = ahc_lookup_scb(ahc, scb_index);
332 printf("%s: WARNING no command for scb %d "
333 "(cmdcmplt)\nQOUTPOS = %d\n",
334 ahc_name(ahc), scb_index,
335 (ahc->qoutfifonext - 1) & 0xFF);
340 * Save off the residual
343 ahc_update_residual(ahc, scb);
349 ahc_run_untagged_queues(struct ahc_softc *ahc)
353 for (i = 0; i < 16; i++)
354 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
358 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
362 if (ahc->untagged_queue_lock != 0)
365 if ((scb = TAILQ_FIRST(queue)) != NULL
366 && (scb->flags & SCB_ACTIVE) == 0) {
367 scb->flags |= SCB_ACTIVE;
368 ahc_queue_scb(ahc, scb);
372 /************************* Interrupt Handling *********************************/
374 ahc_handle_brkadrint(struct ahc_softc *ahc)
377 * We upset the sequencer :-(
378 * Lookup the error message
383 error = ahc_inb(ahc, ERROR);
384 for (i = 0; error != 1 && i < num_errors; i++)
386 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
387 ahc_name(ahc), ahc_hard_errors[i].errmesg,
388 ahc_inb(ahc, SEQADDR0) |
389 (ahc_inb(ahc, SEQADDR1) << 8));
391 ahc_dump_card_state(ahc);
393 /* Tell everyone that this HBA is no longer available */
394 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
395 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
398 /* Disable all interrupt sources by resetting the controller */
403 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
406 struct ahc_devinfo devinfo;
408 ahc_fetch_devinfo(ahc, &devinfo);
411 * Clear the upper byte that holds SEQINT status
412 * codes and clear the SEQINT bit. We will unpause
413 * the sequencer, if appropriate, after servicing
416 ahc_outb(ahc, CLRINT, CLRSEQINT);
417 switch (intstat & SEQINT_MASK) {
421 struct hardware_scb *hscb;
424 * Set the default return value to 0 (don't
425 * send sense). The sense code will change
428 ahc_outb(ahc, RETURN_1, 0);
431 * The sequencer will notify us when a command
432 * has an error that would be of interest to
433 * the kernel. This allows us to leave the sequencer
434 * running in the common case of command completes
435 * without error. The sequencer will already have
436 * dma'd the SCB back up to us, so we can reference
437 * the in kernel copy directly.
439 scb_index = ahc_inb(ahc, SCB_TAG);
440 scb = ahc_lookup_scb(ahc, scb_index);
442 ahc_print_devinfo(ahc, &devinfo);
443 printf("ahc_intr - referenced scb "
444 "not valid during seqint 0x%x scb(%d)\n",
446 ahc_dump_card_state(ahc);
453 /* Don't want to clobber the original sense code */
454 if ((scb->flags & SCB_SENSE) != 0) {
456 * Clear the SCB_SENSE Flag and have
457 * the sequencer do a normal command
460 scb->flags &= ~SCB_SENSE;
461 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
464 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
465 /* Freeze the queue until the client sees the error. */
466 ahc_freeze_devq(ahc, scb);
468 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
469 switch (hscb->shared_data.status.scsi_status) {
471 printf("%s: Interrupted for staus of 0???\n",
474 case SCSI_STATUS_CMD_TERMINATED:
475 case SCSI_STATUS_CHECK_COND:
477 struct ahc_dma_seg *sg;
478 struct scsi_sense *sc;
479 struct ahc_initiator_tinfo *targ_info;
480 struct ahc_tmode_tstate *tstate;
481 struct ahc_transinfo *tinfo;
483 if (ahc_debug & AHC_SHOW_SENSE) {
484 ahc_print_path(ahc, scb);
485 printf("SCB %d: requests Check Status\n",
490 if (ahc_perform_autosense(scb) == 0)
493 targ_info = ahc_fetch_transinfo(ahc,
498 tinfo = &targ_info->curr;
500 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
502 * Save off the residual if there is one.
504 ahc_update_residual(ahc, scb);
506 if (ahc_debug & AHC_SHOW_SENSE) {
507 ahc_print_path(ahc, scb);
508 printf("Sending Sense\n");
511 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
512 sg->len = ahc_get_sense_bufsize(ahc, scb);
513 sg->len |= AHC_DMA_LAST_SEG;
515 /* Fixup byte order */
516 sg->addr = ahc_htole32(sg->addr);
517 sg->len = ahc_htole32(sg->len);
519 sc->opcode = REQUEST_SENSE;
521 if (tinfo->protocol_version <= SCSI_REV_2
522 && SCB_GET_LUN(scb) < 8)
523 sc->byte2 = SCB_GET_LUN(scb) << 5;
526 sc->length = sg->len;
530 * We can't allow the target to disconnect.
531 * This will be an untagged transaction and
532 * having the target disconnect will make this
533 * transaction indestinguishable from outstanding
534 * tagged transactions.
539 * This request sense could be because the
540 * the device lost power or in some other
541 * way has lost our transfer negotiations.
542 * Renegotiate if appropriate. Unit attention
543 * errors will be reported before any data
546 if (ahc_get_residual(scb)
547 == ahc_get_transfer_length(scb)) {
548 ahc_update_neg_request(ahc, &devinfo,
550 AHC_NEG_IF_NON_ASYNC);
552 if (tstate->auto_negotiate & devinfo.target_mask) {
553 hscb->control |= MK_MESSAGE;
554 scb->flags &= ~SCB_NEGOTIATE;
555 scb->flags |= SCB_AUTO_NEGOTIATE;
557 hscb->cdb_len = sizeof(*sc);
558 hscb->dataptr = sg->addr;
559 hscb->datacnt = sg->len;
560 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
561 hscb->sgptr = ahc_htole32(hscb->sgptr);
563 scb->flags |= SCB_SENSE;
564 ahc_qinfifo_requeue_tail(ahc, scb);
565 ahc_outb(ahc, RETURN_1, SEND_SENSE);
567 * Ensure we have enough time to actually
568 * retrieve the sense.
570 ahc_scb_timer_reset(scb, 5 * 1000000);
580 /* Ensure we don't leave the selection hardware on */
581 ahc_outb(ahc, SCSISEQ,
582 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
584 printf("%s:%c:%d: no active SCB for reconnecting "
585 "target - issuing BUS DEVICE RESET\n",
586 ahc_name(ahc), devinfo.channel, devinfo.target);
587 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
588 "ARG_1 == 0x%x ACCUM = 0x%x\n",
589 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
590 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
591 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
593 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
594 ahc_index_busy_tcl(ahc,
595 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
596 ahc_inb(ahc, SAVED_LUN))),
597 ahc_inb(ahc, SINDEX));
598 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
599 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
600 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
601 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
602 ahc_inb(ahc, SCB_CONTROL));
603 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
604 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
605 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
606 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
607 ahc_dump_card_state(ahc);
608 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
610 ahc->msgout_index = 0;
611 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
612 ahc_outb(ahc, MSG_OUT, HOST_MSG);
618 u_int rejbyte = ahc_inb(ahc, ACCUM);
619 printf("%s:%c:%d: Warning - unknown message received from "
620 "target (0x%x). Rejecting\n",
621 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
624 case PROTO_VIOLATION:
626 ahc_handle_proto_violation(ahc);
630 ahc_handle_ign_wide_residue(ahc, &devinfo);
633 ahc_reinitialize_dataptrs(ahc);
639 lastphase = ahc_inb(ahc, LASTPHASE);
640 printf("%s:%c:%d: unknown scsi bus phase %x, "
641 "lastphase = 0x%x. Attempting to continue\n",
642 ahc_name(ahc), devinfo.channel, devinfo.target,
643 lastphase, ahc_inb(ahc, SCSISIGI));
650 lastphase = ahc_inb(ahc, LASTPHASE);
651 printf("%s:%c:%d: Missed busfree. "
652 "Lastphase = 0x%x, Curphase = 0x%x\n",
653 ahc_name(ahc), devinfo.channel, devinfo.target,
654 lastphase, ahc_inb(ahc, SCSISIGI));
661 * The sequencer has encountered a message phase
662 * that requires host assistance for completion.
663 * While handling the message phase(s), we will be
664 * notified by the sequencer after each byte is
665 * transfered so we can track bus phase changes.
667 * If this is the first time we've seen a HOST_MSG_LOOP
668 * interrupt, initialize the state of the host message
671 if (ahc->msg_type == MSG_TYPE_NONE) {
676 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
677 if (bus_phase != P_MESGIN
678 && bus_phase != P_MESGOUT) {
679 printf("ahc_intr: HOST_MSG_LOOP bad "
683 * Probably transitioned to bus free before
684 * we got here. Just punt the message.
686 ahc_clear_intstat(ahc);
691 scb_index = ahc_inb(ahc, SCB_TAG);
692 scb = ahc_lookup_scb(ahc, scb_index);
693 if (devinfo.role == ROLE_INITIATOR) {
695 panic("HOST_MSG_LOOP with "
696 "invalid SCB %x\n", scb_index);
698 if (bus_phase == P_MESGOUT)
699 ahc_setup_initiator_msgout(ahc,
704 MSG_TYPE_INITIATOR_MSGIN;
705 ahc->msgin_index = 0;
708 #ifdef AHC_TARGET_MODE
710 if (bus_phase == P_MESGOUT) {
712 MSG_TYPE_TARGET_MSGOUT;
713 ahc->msgin_index = 0;
716 ahc_setup_target_msgin(ahc,
723 ahc_handle_message_phase(ahc);
729 * If we've cleared the parity error interrupt
730 * but the sequencer still believes that SCSIPERR
731 * is true, it must be that the parity error is
732 * for the currently presented byte on the bus,
733 * and we are not in a phase (data-in) where we will
734 * eventually ack this byte. Ack the byte and
735 * throw it away in the hope that the target will
736 * take us to message out to deliver the appropriate
739 if ((intstat & SCSIINT) == 0
740 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
742 if ((ahc->features & AHC_DT) == 0) {
746 * The hardware will only let you ack bytes
747 * if the expected phase in SCSISIGO matches
748 * the current phase. Make sure this is
749 * currently the case.
751 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
752 ahc_outb(ahc, LASTPHASE, curphase);
753 ahc_outb(ahc, SCSISIGO, curphase);
755 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
759 * In a data phase. Faster to bitbucket
760 * the data than to individually ack each
761 * byte. This is also the only strategy
762 * that will work with AUTOACK enabled.
764 ahc_outb(ahc, SXFRCTL1,
765 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
767 while (--wait != 0) {
768 if ((ahc_inb(ahc, SCSISIGI)
773 ahc_outb(ahc, SXFRCTL1,
774 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
779 ahc_print_devinfo(ahc, &devinfo);
780 printf("Unable to clear parity error. "
782 scb_index = ahc_inb(ahc, SCB_TAG);
783 scb = ahc_lookup_scb(ahc, scb_index);
785 ahc_set_transaction_status(scb,
787 ahc_reset_channel(ahc, devinfo.channel,
791 ahc_inb(ahc, SCSIDATL);
799 * When the sequencer detects an overrun, it
800 * places the controller in "BITBUCKET" mode
801 * and allows the target to complete its transfer.
802 * Unfortunately, none of the counters get updated
803 * when the controller is in this mode, so we have
804 * no way of knowing how large the overrun was.
806 u_int scbindex = ahc_inb(ahc, SCB_TAG);
807 u_int lastphase = ahc_inb(ahc, LASTPHASE);
810 scb = ahc_lookup_scb(ahc, scbindex);
811 for (i = 0; i < num_phases; i++) {
812 if (lastphase == ahc_phase_table[i].phase)
815 ahc_print_path(ahc, scb);
816 printf("data overrun detected %s."
818 ahc_phase_table[i].phasemsg,
820 ahc_print_path(ahc, scb);
821 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
822 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
823 ahc_get_transfer_length(scb), scb->sg_count);
824 if (scb->sg_count > 0) {
825 for (i = 0; i < scb->sg_count; i++) {
827 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
829 (ahc_le32toh(scb->sg_list[i].len) >> 24
830 & SG_HIGH_ADDR_BITS),
831 ahc_le32toh(scb->sg_list[i].addr),
832 ahc_le32toh(scb->sg_list[i].len)
837 * Set this and it will take effect when the
838 * target does a command complete.
840 ahc_freeze_devq(ahc, scb);
841 if ((scb->flags & SCB_SENSE) == 0) {
842 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
844 scb->flags &= ~SCB_SENSE;
845 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
849 if ((ahc->features & AHC_ULTRA2) != 0) {
851 * Clear the channel in case we return
852 * to data phase later.
854 ahc_outb(ahc, SXFRCTL0,
855 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
856 ahc_outb(ahc, SXFRCTL0,
857 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
859 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
862 /* Ensure HHADDR is 0 for future DMA operations. */
863 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
864 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
865 ahc_outb(ahc, HADDR, 0);
866 ahc_outb(ahc, DSCOMMAND1, dscommand1);
874 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
875 ahc_name(ahc), devinfo.channel, devinfo.target,
877 scbindex = ahc_inb(ahc, SCB_TAG);
878 scb = ahc_lookup_scb(ahc, scbindex);
880 && (scb->flags & SCB_RECOVERY_SCB) != 0)
882 * Ensure that we didn't put a second instance of this
883 * SCB into the QINFIFO.
885 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
886 SCB_GET_CHANNEL(ahc, scb),
887 SCB_GET_LUN(scb), scb->hscb->tag,
888 ROLE_INITIATOR, /*status*/0,
894 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
895 ahc_dump_card_state(ahc);
903 scbptr = ahc_inb(ahc, SCBPTR);
904 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
905 scbptr, ahc_inb(ahc, ARG_1),
906 ahc->scb_data->hscbs[scbptr].tag);
907 ahc_dump_card_state(ahc);
913 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
914 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
915 "ARG_1 == 0x%x ACCUM = 0x%x\n",
916 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
917 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
918 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
919 "SINDEX == 0x%x\n, A == 0x%x\n",
920 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
921 ahc_index_busy_tcl(ahc,
922 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
923 ahc_inb(ahc, SAVED_LUN))),
924 ahc_inb(ahc, SINDEX),
925 ahc_inb(ahc, ACCUM));
926 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
927 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
928 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
929 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
930 ahc_inb(ahc, SCB_CONTROL));
931 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
932 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
933 ahc_dump_card_state(ahc);
938 printf("ahc_intr: seqint, "
939 "intstat == 0x%x, scsisigi = 0x%x\n",
940 intstat, ahc_inb(ahc, SCSISIGI));
945 * The sequencer is paused immediately on
946 * a SEQINT, so we should restart it when
953 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
962 if ((ahc->features & AHC_TWIN) != 0
963 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
967 intr_channel = cur_channel;
969 if ((ahc->features & AHC_ULTRA2) != 0)
970 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
973 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
974 if (status == 0 && status0 == 0) {
975 if ((ahc->features & AHC_TWIN) != 0) {
976 /* Try the other channel */
977 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
978 status = ahc_inb(ahc, SSTAT1)
979 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
980 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
983 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
984 ahc_outb(ahc, CLRINT, CLRSCSIINT);
990 /* Make sure the sequencer is in a safe location. */
991 ahc_clear_critical_section(ahc);
993 scb_index = ahc_inb(ahc, SCB_TAG);
994 scb = ahc_lookup_scb(ahc, scb_index);
996 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
999 if ((ahc->features & AHC_ULTRA2) != 0
1000 && (status0 & IOERR) != 0) {
1003 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1004 printf("%s: Transceiver State Has Changed to %s mode\n",
1005 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1006 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1008 * When transitioning to SE mode, the reset line
1009 * glitches, triggering an arbitration bug in some
1010 * Ultra2 controllers. This bug is cleared when we
1011 * assert the reset line. Since a reset glitch has
1012 * already occurred with this transition and a
1013 * transceiver state change is handled just like
1014 * a bus reset anyway, asserting the reset line
1015 * ourselves is safe.
1017 ahc_reset_channel(ahc, intr_channel,
1018 /*Initiate Reset*/now_lvd == 0);
1019 } else if ((status & SCSIRSTI) != 0) {
1020 printf("%s: Someone reset channel %c\n",
1021 ahc_name(ahc), intr_channel);
1022 if (intr_channel != cur_channel)
1023 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1024 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1025 } else if ((status & SCSIPERR) != 0) {
1027 * Determine the bus phase and queue an appropriate message.
1028 * SCSIPERR is latched true as soon as a parity error
1029 * occurs. If the sequencer acked the transfer that
1030 * caused the parity error and the currently presented
1031 * transfer on the bus has correct parity, SCSIPERR will
1032 * be cleared by CLRSCSIPERR. Use this to determine if
1033 * we should look at the last phase the sequencer recorded,
1034 * or the current phase presented on the bus.
1036 struct ahc_devinfo devinfo;
1046 lastphase = ahc_inb(ahc, LASTPHASE);
1047 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1048 sstat2 = ahc_inb(ahc, SSTAT2);
1049 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1051 * For all phases save DATA, the sequencer won't
1052 * automatically ack a byte that has a parity error
1053 * in it. So the only way that the current phase
1054 * could be 'data-in' is if the parity error is for
1055 * an already acked byte in the data phase. During
1056 * synchronous data-in transfers, we may actually
1057 * ack bytes before latching the current phase in
1058 * LASTPHASE, leading to the discrepancy between
1059 * curphase and lastphase.
1061 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1062 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1063 errorphase = curphase;
1065 errorphase = lastphase;
1067 for (i = 0; i < num_phases; i++) {
1068 if (errorphase == ahc_phase_table[i].phase)
1071 mesg_out = ahc_phase_table[i].mesg_out;
1074 if (SCB_IS_SILENT(scb))
1077 ahc_print_path(ahc, scb);
1078 scb->flags |= SCB_TRANSMISSION_ERROR;
1080 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1081 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1082 scsirate = ahc_inb(ahc, SCSIRATE);
1083 if (silent == FALSE) {
1084 printf("parity error detected %s. "
1085 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1086 ahc_phase_table[i].phasemsg,
1087 ahc_inw(ahc, SEQADDR0),
1089 if ((ahc->features & AHC_DT) != 0) {
1090 if ((sstat2 & CRCVALERR) != 0)
1091 printf("\tCRC Value Mismatch\n");
1092 if ((sstat2 & CRCENDERR) != 0)
1093 printf("\tNo terminal CRC packet "
1095 if ((sstat2 & CRCREQERR) != 0)
1096 printf("\tIllegal CRC packet "
1098 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1099 printf("\tUnexpected %sDT Data Phase\n",
1100 (scsirate & SINGLE_EDGE)
1105 if ((ahc->features & AHC_DT) != 0
1106 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1108 * This error applies regardless of
1109 * data direction, so ignore the value
1110 * in the phase table.
1112 mesg_out = MSG_INITIATOR_DET_ERR;
1116 * We've set the hardware to assert ATN if we
1117 * get a parity error on "in" phases, so all we
1118 * need to do is stuff the message buffer with
1119 * the appropriate message. "In" phases have set
1120 * mesg_out to something other than MSG_NOP.
1122 if (mesg_out != MSG_NOOP) {
1123 if (ahc->msg_type != MSG_TYPE_NONE)
1124 ahc->send_msg_perror = TRUE;
1126 ahc_outb(ahc, MSG_OUT, mesg_out);
1129 * Force a renegotiation with this target just in
1130 * case we are out of sync for some external reason
1131 * unknown (or unreported) by the target.
1133 ahc_fetch_devinfo(ahc, &devinfo);
1134 ahc_force_renegotiation(ahc, &devinfo);
1136 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1138 } else if ((status & SELTO) != 0) {
1141 /* Stop the selection */
1142 ahc_outb(ahc, SCSISEQ, 0);
1144 /* No more pending messages */
1145 ahc_clear_msg_state(ahc);
1147 /* Clear interrupt state */
1148 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1149 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1152 * Although the driver does not care about the
1153 * 'Selection in Progress' status bit, the busy
1154 * LED does. SELINGO is only cleared by a sucessfull
1155 * selection, so we must manually clear it to insure
1156 * the LED turns off just incase no future successful
1157 * selections occur (e.g. no devices on the bus).
1159 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1161 scbptr = ahc_inb(ahc, WAITING_SCBH);
1162 ahc_outb(ahc, SCBPTR, scbptr);
1163 scb_index = ahc_inb(ahc, SCB_TAG);
1165 scb = ahc_lookup_scb(ahc, scb_index);
1167 printf("%s: ahc_intr - referenced scb not "
1168 "valid during SELTO scb(%d, %d)\n",
1169 ahc_name(ahc), scbptr, scb_index);
1170 ahc_dump_card_state(ahc);
1172 struct ahc_devinfo devinfo;
1174 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1175 ahc_print_path(ahc, scb);
1176 printf("Saw Selection Timeout for SCB 0x%x\n",
1181 * Force a renegotiation with this target just in
1182 * case the cable was pulled and will later be
1183 * re-attached. The target may forget its negotiation
1184 * settings with us should it attempt to reselect
1185 * during the interruption. The target will not issue
1186 * a unit attention in this case, so we must always
1189 ahc_scb_devinfo(ahc, &devinfo, scb);
1190 ahc_force_renegotiation(ahc, &devinfo);
1191 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1192 ahc_freeze_devq(ahc, scb);
1194 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1196 } else if ((status & BUSFREE) != 0
1197 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1198 struct ahc_devinfo devinfo;
1203 u_int initiator_role_id;
1208 * Clear our selection hardware as soon as possible.
1209 * We may have an entry in the waiting Q for this target,
1210 * that is affected by this busfree and we don't want to
1211 * go about selecting the target while we handle the event.
1213 ahc_outb(ahc, SCSISEQ,
1214 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1217 * Disable busfree interrupts and clear the busfree
1218 * interrupt status. We do this here so that several
1219 * bus transactions occur prior to clearing the SCSIINT
1220 * latch. It can take a bit for the clearing to take effect.
1222 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1223 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1226 * Look at what phase we were last in.
1227 * If its message out, chances are pretty good
1228 * that the busfree was in response to one of
1229 * our abort requests.
1231 lastphase = ahc_inb(ahc, LASTPHASE);
1232 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1233 saved_lun = ahc_inb(ahc, SAVED_LUN);
1234 target = SCSIID_TARGET(ahc, saved_scsiid);
1235 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1236 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1237 ahc_compile_devinfo(&devinfo, initiator_role_id,
1238 target, saved_lun, channel, ROLE_INITIATOR);
1241 if (lastphase == P_MESGOUT) {
1244 tag = SCB_LIST_NULL;
1245 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1246 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1247 if (ahc->msgout_buf[ahc->msgout_index - 1]
1249 tag = scb->hscb->tag;
1250 ahc_print_path(ahc, scb);
1251 printf("SCB %d - Abort%s Completed.\n",
1252 scb->hscb->tag, tag == SCB_LIST_NULL ?
1254 ahc_abort_scbs(ahc, target, channel,
1259 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1260 MSG_BUS_DEV_RESET, TRUE)) {
1263 * Don't mark the user's request for this BDR
1264 * as completing with CAM_BDR_SENT. CAM3
1265 * specifies CAM_REQ_CMP.
1268 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1269 && ahc_match_scb(ahc, scb, target, channel,
1273 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1276 ahc_compile_devinfo(&devinfo,
1282 ahc_handle_devreset(ahc, &devinfo,
1285 /*verbose_level*/0);
1287 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1288 MSG_EXT_PPR, FALSE)) {
1289 struct ahc_initiator_tinfo *tinfo;
1290 struct ahc_tmode_tstate *tstate;
1293 * PPR Rejected. Try non-ppr negotiation
1294 * and retry command.
1296 tinfo = ahc_fetch_transinfo(ahc,
1301 tinfo->curr.transport_version = 2;
1302 tinfo->goal.transport_version = 2;
1303 tinfo->goal.ppr_options = 0;
1304 ahc_qinfifo_requeue_tail(ahc, scb);
1306 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1307 MSG_EXT_WDTR, FALSE)) {
1309 * Negotiation Rejected. Go-narrow and
1312 ahc_set_width(ahc, &devinfo,
1313 MSG_EXT_WDTR_BUS_8_BIT,
1314 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1316 ahc_qinfifo_requeue_tail(ahc, scb);
1318 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1319 MSG_EXT_SDTR, FALSE)) {
1321 * Negotiation Rejected. Go-async and
1324 ahc_set_syncrate(ahc, &devinfo,
1326 /*period*/0, /*offset*/0,
1328 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1330 ahc_qinfifo_requeue_tail(ahc, scb);
1334 if (printerror != 0) {
1340 if ((scb->hscb->control & TAG_ENB) != 0)
1341 tag = scb->hscb->tag;
1343 tag = SCB_LIST_NULL;
1344 ahc_print_path(ahc, scb);
1345 ahc_abort_scbs(ahc, target, channel,
1346 SCB_GET_LUN(scb), tag,
1351 * We had not fully identified this connection,
1352 * so we cannot abort anything.
1354 printf("%s: ", ahc_name(ahc));
1356 for (i = 0; i < num_phases; i++) {
1357 if (lastphase == ahc_phase_table[i].phase)
1360 if (lastphase != P_BUSFREE) {
1362 * Renegotiate with this device at the
1363 * next oportunity just in case this busfree
1364 * is due to a negotiation mismatch with the
1367 ahc_force_renegotiation(ahc, &devinfo);
1369 printf("Unexpected busfree %s\n"
1370 "SEQADDR == 0x%x\n",
1371 ahc_phase_table[i].phasemsg,
1372 ahc_inb(ahc, SEQADDR0)
1373 | (ahc_inb(ahc, SEQADDR1) << 8));
1375 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1378 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1379 ahc_name(ahc), status);
1380 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1385 * Force renegotiation to occur the next time we initiate
1386 * a command to the current device.
1389 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1391 struct ahc_initiator_tinfo *targ_info;
1392 struct ahc_tmode_tstate *tstate;
1394 targ_info = ahc_fetch_transinfo(ahc,
1396 devinfo->our_scsiid,
1399 ahc_update_neg_request(ahc, devinfo, tstate,
1400 targ_info, AHC_NEG_IF_NON_ASYNC);
1403 #define AHC_MAX_STEPS 2000
1405 ahc_clear_critical_section(struct ahc_softc *ahc)
1412 if (ahc->num_critical_sections == 0)
1424 seqaddr = ahc_inb(ahc, SEQADDR0)
1425 | (ahc_inb(ahc, SEQADDR1) << 8);
1428 * Seqaddr represents the next instruction to execute,
1429 * so we are really executing the instruction just
1434 cs = ahc->critical_sections;
1435 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1437 if (cs->begin < seqaddr && cs->end >= seqaddr)
1441 if (i == ahc->num_critical_sections)
1444 if (steps > AHC_MAX_STEPS) {
1445 printf("%s: Infinite loop in critical section\n",
1447 ahc_dump_card_state(ahc);
1448 panic("critical section loop");
1452 if (stepping == FALSE) {
1455 * Disable all interrupt sources so that the
1456 * sequencer will not be stuck by a pausing
1457 * interrupt condition while we attempt to
1458 * leave a critical section.
1460 simode0 = ahc_inb(ahc, SIMODE0);
1461 ahc_outb(ahc, SIMODE0, 0);
1462 simode1 = ahc_inb(ahc, SIMODE1);
1463 if ((ahc->features & AHC_DT) != 0)
1465 * On DT class controllers, we
1466 * use the enhanced busfree logic.
1467 * Unfortunately we cannot re-enable
1468 * busfree detection within the
1469 * current connection, so we must
1470 * leave it on while single stepping.
1472 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1474 ahc_outb(ahc, SIMODE1, 0);
1475 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1476 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1479 if ((ahc->features & AHC_DT) != 0) {
1480 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1481 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1483 ahc_outb(ahc, HCNTRL, ahc->unpause);
1484 while (!ahc_is_paused(ahc))
1488 ahc_outb(ahc, SIMODE0, simode0);
1489 ahc_outb(ahc, SIMODE1, simode1);
1490 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1495 * Clear any pending interrupt status.
1498 ahc_clear_intstat(struct ahc_softc *ahc)
1500 /* Clear any interrupt conditions this may have caused */
1501 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1502 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1504 ahc_flush_device_writes(ahc);
1505 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1506 ahc_flush_device_writes(ahc);
1507 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1508 ahc_flush_device_writes(ahc);
1511 /**************************** Debugging Routines ******************************/
1513 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1517 ahc_print_scb(struct scb *scb)
1521 struct hardware_scb *hscb = scb->hscb;
1523 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1529 printf("Shared Data: ");
1530 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1531 printf("%#02x", hscb->shared_data.cdb[i]);
1532 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1533 ahc_le32toh(hscb->dataptr),
1534 ahc_le32toh(hscb->datacnt),
1535 ahc_le32toh(hscb->sgptr),
1537 if (scb->sg_count > 0) {
1538 for (i = 0; i < scb->sg_count; i++) {
1539 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1541 (ahc_le32toh(scb->sg_list[i].len) >> 24
1542 & SG_HIGH_ADDR_BITS),
1543 ahc_le32toh(scb->sg_list[i].addr),
1544 ahc_le32toh(scb->sg_list[i].len));
1549 /************************* Transfer Negotiation *******************************/
1551 * Allocate per target mode instance (ID we respond to as a target)
1552 * transfer negotiation data structures.
1554 static struct ahc_tmode_tstate *
1555 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1557 struct ahc_tmode_tstate *master_tstate;
1558 struct ahc_tmode_tstate *tstate;
1561 master_tstate = ahc->enabled_targets[ahc->our_id];
1562 if (channel == 'B') {
1564 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1566 if (ahc->enabled_targets[scsi_id] != NULL
1567 && ahc->enabled_targets[scsi_id] != master_tstate)
1568 panic("%s: ahc_alloc_tstate - Target already allocated",
1570 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1571 M_DEVBUF, M_NOWAIT);
1576 * If we have allocated a master tstate, copy user settings from
1577 * the master tstate (taken from SRAM or the EEPROM) for this
1578 * channel, but reset our current and goal settings to async/narrow
1579 * until an initiator talks to us.
1581 if (master_tstate != NULL) {
1582 memcpy(tstate, master_tstate, sizeof(*tstate));
1583 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1584 tstate->ultraenb = 0;
1585 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1586 memset(&tstate->transinfo[i].curr, 0,
1587 sizeof(tstate->transinfo[i].curr));
1588 memset(&tstate->transinfo[i].goal, 0,
1589 sizeof(tstate->transinfo[i].goal));
1592 memset(tstate, 0, sizeof(*tstate));
1593 ahc->enabled_targets[scsi_id] = tstate;
1597 #ifdef AHC_TARGET_MODE
1599 * Free per target mode instance (ID we respond to as a target)
1600 * transfer negotiation data structures.
1603 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1605 struct ahc_tmode_tstate *tstate;
1608 * Don't clean up our "master" tstate.
1609 * It has our default user settings.
1611 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1612 || (channel == 'A' && scsi_id == ahc->our_id))
1618 tstate = ahc->enabled_targets[scsi_id];
1620 free(tstate, M_DEVBUF);
1621 ahc->enabled_targets[scsi_id] = NULL;
1626 * Called when we have an active connection to a target on the bus,
1627 * this function finds the nearest syncrate to the input period limited
1628 * by the capabilities of the bus connectivity of and sync settings for
1631 struct ahc_syncrate *
1632 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1633 struct ahc_initiator_tinfo *tinfo,
1634 u_int *period, u_int *ppr_options, role_t role)
1636 struct ahc_transinfo *transinfo;
1639 if ((ahc->features & AHC_ULTRA2) != 0) {
1640 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1641 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1642 maxsync = AHC_SYNCRATE_DT;
1644 maxsync = AHC_SYNCRATE_ULTRA;
1645 /* Can't do DT on an SE bus */
1646 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1648 } else if ((ahc->features & AHC_ULTRA) != 0) {
1649 maxsync = AHC_SYNCRATE_ULTRA;
1651 maxsync = AHC_SYNCRATE_FAST;
1654 * Never allow a value higher than our current goal
1655 * period otherwise we may allow a target initiated
1656 * negotiation to go above the limit as set by the
1657 * user. In the case of an initiator initiated
1658 * sync negotiation, we limit based on the user
1659 * setting. This allows the system to still accept
1660 * incoming negotiations even if target initiated
1661 * negotiation is not performed.
1663 if (role == ROLE_TARGET)
1664 transinfo = &tinfo->user;
1666 transinfo = &tinfo->goal;
1667 *ppr_options &= transinfo->ppr_options;
1668 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1669 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1670 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1672 if (transinfo->period == 0) {
1677 *period = MAX(*period, transinfo->period);
1678 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1682 * Look up the valid period to SCSIRATE conversion in our table.
1683 * Return the period and offset that should be sent to the target
1684 * if this was the beginning of an SDTR.
1686 struct ahc_syncrate *
1687 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1688 u_int *ppr_options, u_int maxsync)
1690 struct ahc_syncrate *syncrate;
1692 if ((ahc->features & AHC_DT) == 0)
1693 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1695 /* Skip all DT only entries if DT is not available */
1696 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1697 && maxsync < AHC_SYNCRATE_ULTRA2)
1698 maxsync = AHC_SYNCRATE_ULTRA2;
1700 for (syncrate = &ahc_syncrates[maxsync];
1701 syncrate->rate != NULL;
1705 * The Ultra2 table doesn't go as low
1706 * as for the Fast/Ultra cards.
1708 if ((ahc->features & AHC_ULTRA2) != 0
1709 && (syncrate->sxfr_u2 == 0))
1712 if (*period <= syncrate->period) {
1714 * When responding to a target that requests
1715 * sync, the requested rate may fall between
1716 * two rates that we can output, but still be
1717 * a rate that we can receive. Because of this,
1718 * we want to respond to the target with
1719 * the same rate that it sent to us even
1720 * if the period we use to send data to it
1721 * is lower. Only lower the response period
1724 if (syncrate == &ahc_syncrates[maxsync])
1725 *period = syncrate->period;
1728 * At some speeds, we only support
1731 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1732 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1738 || (syncrate->rate == NULL)
1739 || ((ahc->features & AHC_ULTRA2) != 0
1740 && (syncrate->sxfr_u2 == 0))) {
1741 /* Use asynchronous transfers. */
1744 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1750 * Convert from an entry in our syncrate table to the SCSI equivalent
1751 * sync "period" factor.
1754 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1756 struct ahc_syncrate *syncrate;
1758 if ((ahc->features & AHC_ULTRA2) != 0)
1759 scsirate &= SXFR_ULTRA2;
1763 syncrate = &ahc_syncrates[maxsync];
1764 while (syncrate->rate != NULL) {
1766 if ((ahc->features & AHC_ULTRA2) != 0) {
1767 if (syncrate->sxfr_u2 == 0)
1769 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1770 return (syncrate->period);
1771 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1772 return (syncrate->period);
1776 return (0); /* async */
1780 * Truncate the given synchronous offset to a value the
1781 * current adapter type and syncrate are capable of.
1784 ahc_validate_offset(struct ahc_softc *ahc,
1785 struct ahc_initiator_tinfo *tinfo,
1786 struct ahc_syncrate *syncrate,
1787 u_int *offset, int wide, role_t role)
1791 /* Limit offset to what we can do */
1792 if (syncrate == NULL) {
1794 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1795 maxoffset = MAX_OFFSET_ULTRA2;
1798 maxoffset = MAX_OFFSET_16BIT;
1800 maxoffset = MAX_OFFSET_8BIT;
1802 *offset = MIN(*offset, maxoffset);
1803 if (tinfo != NULL) {
1804 if (role == ROLE_TARGET)
1805 *offset = MIN(*offset, tinfo->user.offset);
1807 *offset = MIN(*offset, tinfo->goal.offset);
1812 * Truncate the given transfer width parameter to a value the
1813 * current adapter type is capable of.
1816 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1817 u_int *bus_width, role_t role)
1819 switch (*bus_width) {
1821 if (ahc->features & AHC_WIDE) {
1823 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1827 case MSG_EXT_WDTR_BUS_8_BIT:
1828 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1831 if (tinfo != NULL) {
1832 if (role == ROLE_TARGET)
1833 *bus_width = MIN(tinfo->user.width, *bus_width);
1835 *bus_width = MIN(tinfo->goal.width, *bus_width);
1840 * Update the bitmask of targets for which the controller should
1841 * negotiate with at the next convenient oportunity. This currently
1842 * means the next time we send the initial identify messages for
1843 * a new transaction.
1846 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1847 struct ahc_tmode_tstate *tstate,
1848 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1850 u_int auto_negotiate_orig;
1852 auto_negotiate_orig = tstate->auto_negotiate;
1853 if (neg_type == AHC_NEG_ALWAYS) {
1855 * Force our "current" settings to be
1856 * unknown so that unless a bus reset
1857 * occurs the need to renegotiate is
1858 * recorded persistently.
1860 if ((ahc->features & AHC_WIDE) != 0)
1861 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1862 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1863 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1865 if (tinfo->curr.period != tinfo->goal.period
1866 || tinfo->curr.width != tinfo->goal.width
1867 || tinfo->curr.offset != tinfo->goal.offset
1868 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1869 || (neg_type == AHC_NEG_IF_NON_ASYNC
1870 && (tinfo->goal.offset != 0
1871 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1872 || tinfo->goal.ppr_options != 0)))
1873 tstate->auto_negotiate |= devinfo->target_mask;
1875 tstate->auto_negotiate &= ~devinfo->target_mask;
1877 return (auto_negotiate_orig != tstate->auto_negotiate);
1881 * Update the user/goal/curr tables of synchronous negotiation
1882 * parameters as well as, in the case of a current or active update,
1883 * any data structures on the host controller. In the case of an
1884 * active update, the specified target is currently talking to us on
1885 * the bus, so the transfer parameter update must take effect
1889 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1890 struct ahc_syncrate *syncrate, u_int period,
1891 u_int offset, u_int ppr_options, u_int type, int paused)
1893 struct ahc_initiator_tinfo *tinfo;
1894 struct ahc_tmode_tstate *tstate;
1901 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1904 if (syncrate == NULL) {
1909 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1910 devinfo->target, &tstate);
1912 if ((type & AHC_TRANS_USER) != 0) {
1913 tinfo->user.period = period;
1914 tinfo->user.offset = offset;
1915 tinfo->user.ppr_options = ppr_options;
1918 if ((type & AHC_TRANS_GOAL) != 0) {
1919 tinfo->goal.period = period;
1920 tinfo->goal.offset = offset;
1921 tinfo->goal.ppr_options = ppr_options;
1924 old_period = tinfo->curr.period;
1925 old_offset = tinfo->curr.offset;
1926 old_ppr = tinfo->curr.ppr_options;
1928 if ((type & AHC_TRANS_CUR) != 0
1929 && (old_period != period
1930 || old_offset != offset
1931 || old_ppr != ppr_options)) {
1935 scsirate = tinfo->scsirate;
1936 if ((ahc->features & AHC_ULTRA2) != 0) {
1938 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1939 if (syncrate != NULL) {
1940 scsirate |= syncrate->sxfr_u2;
1941 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1942 scsirate |= ENABLE_CRC;
1944 scsirate |= SINGLE_EDGE;
1948 scsirate &= ~(SXFR|SOFS);
1950 * Ensure Ultra mode is set properly for
1953 tstate->ultraenb &= ~devinfo->target_mask;
1954 if (syncrate != NULL) {
1955 if (syncrate->sxfr & ULTRA_SXFR) {
1957 devinfo->target_mask;
1959 scsirate |= syncrate->sxfr & SXFR;
1960 scsirate |= offset & SOFS;
1965 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1966 sxfrctl0 &= ~FAST20;
1967 if (tstate->ultraenb & devinfo->target_mask)
1969 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1973 ahc_outb(ahc, SCSIRATE, scsirate);
1974 if ((ahc->features & AHC_ULTRA2) != 0)
1975 ahc_outb(ahc, SCSIOFFSET, offset);
1978 tinfo->scsirate = scsirate;
1979 tinfo->curr.period = period;
1980 tinfo->curr.offset = offset;
1981 tinfo->curr.ppr_options = ppr_options;
1983 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1984 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1987 printf("%s: target %d synchronous at %sMHz%s, "
1988 "offset = 0x%x\n", ahc_name(ahc),
1989 devinfo->target, syncrate->rate,
1990 (ppr_options & MSG_EXT_PPR_DT_REQ)
1991 ? " DT" : "", offset);
1993 printf("%s: target %d using "
1994 "asynchronous transfers\n",
1995 ahc_name(ahc), devinfo->target);
2000 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2001 tinfo, AHC_NEG_TO_GOAL);
2004 ahc_update_pending_scbs(ahc);
2008 * Update the user/goal/curr tables of wide negotiation
2009 * parameters as well as, in the case of a current or active update,
2010 * any data structures on the host controller. In the case of an
2011 * active update, the specified target is currently talking to us on
2012 * the bus, so the transfer parameter update must take effect
2016 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2017 u_int width, u_int type, int paused)
2019 struct ahc_initiator_tinfo *tinfo;
2020 struct ahc_tmode_tstate *tstate;
2025 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2027 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2028 devinfo->target, &tstate);
2030 if ((type & AHC_TRANS_USER) != 0)
2031 tinfo->user.width = width;
2033 if ((type & AHC_TRANS_GOAL) != 0)
2034 tinfo->goal.width = width;
2036 oldwidth = tinfo->curr.width;
2037 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2041 scsirate = tinfo->scsirate;
2042 scsirate &= ~WIDEXFER;
2043 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2044 scsirate |= WIDEXFER;
2046 tinfo->scsirate = scsirate;
2049 ahc_outb(ahc, SCSIRATE, scsirate);
2051 tinfo->curr.width = width;
2053 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2054 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2056 printf("%s: target %d using %dbit transfers\n",
2057 ahc_name(ahc), devinfo->target,
2058 8 * (0x01 << width));
2062 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2063 tinfo, AHC_NEG_TO_GOAL);
2065 ahc_update_pending_scbs(ahc);
2069 * Update the current state of tagged queuing for a given target.
2072 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2075 ahc_platform_set_tags(ahc, devinfo, alg);
2076 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2077 devinfo->lun, AC_TRANSFER_NEG, &alg);
2081 * When the transfer settings for a connection change, update any
2082 * in-transit SCBs to contain the new data so the hardware will
2083 * be set correctly during future (re)selections.
2086 ahc_update_pending_scbs(struct ahc_softc *ahc)
2088 struct scb *pending_scb;
2089 int pending_scb_count;
2095 * Traverse the pending SCB list and ensure that all of the
2096 * SCBs there have the proper settings.
2098 pending_scb_count = 0;
2099 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2100 struct ahc_devinfo devinfo;
2101 struct hardware_scb *pending_hscb;
2102 struct ahc_initiator_tinfo *tinfo;
2103 struct ahc_tmode_tstate *tstate;
2105 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2106 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2108 devinfo.target, &tstate);
2109 pending_hscb = pending_scb->hscb;
2110 pending_hscb->control &= ~ULTRAENB;
2111 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2112 pending_hscb->control |= ULTRAENB;
2113 pending_hscb->scsirate = tinfo->scsirate;
2114 pending_hscb->scsioffset = tinfo->curr.offset;
2115 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2116 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2117 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2118 pending_hscb->control &= ~MK_MESSAGE;
2120 ahc_sync_scb(ahc, pending_scb,
2121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2122 pending_scb_count++;
2125 if (pending_scb_count == 0)
2128 if (ahc_is_paused(ahc)) {
2135 saved_scbptr = ahc_inb(ahc, SCBPTR);
2136 /* Ensure that the hscbs down on the card match the new information */
2137 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2138 struct hardware_scb *pending_hscb;
2142 ahc_outb(ahc, SCBPTR, i);
2143 scb_tag = ahc_inb(ahc, SCB_TAG);
2144 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2145 if (pending_scb == NULL)
2148 pending_hscb = pending_scb->hscb;
2149 control = ahc_inb(ahc, SCB_CONTROL);
2150 control &= ~(ULTRAENB|MK_MESSAGE);
2151 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2152 ahc_outb(ahc, SCB_CONTROL, control);
2153 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2154 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2156 ahc_outb(ahc, SCBPTR, saved_scbptr);
2162 /**************************** Pathing Information *****************************/
2164 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2170 if (ahc_inb(ahc, SSTAT0) & TARGET)
2173 role = ROLE_INITIATOR;
2175 if (role == ROLE_TARGET
2176 && (ahc->features & AHC_MULTI_TID) != 0
2177 && (ahc_inb(ahc, SEQ_FLAGS)
2178 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2179 /* We were selected, so pull our id from TARGIDIN */
2180 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2181 } else if ((ahc->features & AHC_ULTRA2) != 0)
2182 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2184 our_id = ahc_inb(ahc, SCSIID) & OID;
2186 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2187 ahc_compile_devinfo(devinfo,
2189 SCSIID_TARGET(ahc, saved_scsiid),
2190 ahc_inb(ahc, SAVED_LUN),
2191 SCSIID_CHANNEL(ahc, saved_scsiid),
2195 struct ahc_phase_table_entry*
2196 ahc_lookup_phase_entry(int phase)
2198 struct ahc_phase_table_entry *entry;
2199 struct ahc_phase_table_entry *last_entry;
2202 * num_phases doesn't include the default entry which
2203 * will be returned if the phase doesn't match.
2205 last_entry = &ahc_phase_table[num_phases];
2206 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2207 if (phase == entry->phase)
2214 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2215 u_int lun, char channel, role_t role)
2217 devinfo->our_scsiid = our_id;
2218 devinfo->target = target;
2220 devinfo->target_offset = target;
2221 devinfo->channel = channel;
2222 devinfo->role = role;
2224 devinfo->target_offset += 8;
2225 devinfo->target_mask = (0x01 << devinfo->target_offset);
2229 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2231 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2232 devinfo->target, devinfo->lun);
2236 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2242 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2243 role = ROLE_INITIATOR;
2244 if ((scb->flags & SCB_TARGET_SCB) != 0)
2246 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2247 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2251 /************************ Message Phase Processing ****************************/
2253 ahc_assert_atn(struct ahc_softc *ahc)
2258 if ((ahc->features & AHC_DT) == 0)
2259 scsisigo |= ahc_inb(ahc, SCSISIGI);
2260 ahc_outb(ahc, SCSISIGO, scsisigo);
2264 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2265 * or enters the initial message out phase, we are interrupted. Fill our
2266 * outgoing message buffer with the appropriate message and beging handing
2267 * the message phase(s) manually.
2270 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2274 * To facilitate adding multiple messages together,
2275 * each routine should increment the index and len
2276 * variables instead of setting them explicitly.
2278 ahc->msgout_index = 0;
2279 ahc->msgout_len = 0;
2281 if ((scb->flags & SCB_DEVICE_RESET) == 0
2282 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2285 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2286 if ((scb->hscb->control & DISCENB) != 0)
2287 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2288 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2291 if ((scb->hscb->control & TAG_ENB) != 0) {
2292 ahc->msgout_buf[ahc->msgout_index++] =
2293 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2294 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2295 ahc->msgout_len += 2;
2299 if (scb->flags & SCB_DEVICE_RESET) {
2300 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2302 ahc_print_path(ahc, scb);
2303 printf("Bus Device Reset Message Sent\n");
2305 * Clear our selection hardware in advance of
2306 * the busfree. We may have an entry in the waiting
2307 * Q for this target, and we don't want to go about
2308 * selecting while we handle the busfree and blow it
2311 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2312 } else if ((scb->flags & SCB_ABORT) != 0) {
2313 if ((scb->hscb->control & TAG_ENB) != 0)
2314 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2316 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2318 ahc_print_path(ahc, scb);
2319 printf("Abort%s Message Sent\n",
2320 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2322 * Clear our selection hardware in advance of
2323 * the busfree. We may have an entry in the waiting
2324 * Q for this target, and we don't want to go about
2325 * selecting while we handle the busfree and blow it
2328 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2329 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2330 ahc_build_transfer_msg(ahc, devinfo);
2332 printf("ahc_intr: AWAITING_MSG for an SCB that "
2333 "does not have a waiting message\n");
2334 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2335 devinfo->target_mask);
2336 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2337 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2338 ahc_inb(ahc, MSG_OUT), scb->flags);
2342 * Clear the MK_MESSAGE flag from the SCB so we aren't
2343 * asked to send this message again.
2345 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2346 scb->hscb->control &= ~MK_MESSAGE;
2347 ahc->msgout_index = 0;
2348 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2352 * Build an appropriate transfer negotiation message for the
2353 * currently active target.
2356 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2359 * We need to initiate transfer negotiations.
2360 * If our current and goal settings are identical,
2361 * we want to renegotiate due to a check condition.
2363 struct ahc_initiator_tinfo *tinfo;
2364 struct ahc_tmode_tstate *tstate;
2365 struct ahc_syncrate *rate;
2373 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2374 devinfo->target, &tstate);
2376 * Filter our period based on the current connection.
2377 * If we can't perform DT transfers on this segment (not in LVD
2378 * mode for instance), then our decision to issue a PPR message
2381 period = tinfo->goal.period;
2382 offset = tinfo->goal.offset;
2383 ppr_options = tinfo->goal.ppr_options;
2384 /* Target initiated PPR is not allowed in the SCSI spec */
2385 if (devinfo->role == ROLE_TARGET)
2387 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2388 &ppr_options, devinfo->role);
2389 dowide = tinfo->curr.width != tinfo->goal.width;
2390 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2392 * Only use PPR if we have options that need it, even if the device
2393 * claims to support it. There might be an expander in the way
2396 doppr = ppr_options != 0;
2398 if (!dowide && !dosync && !doppr) {
2399 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2400 dosync = tinfo->goal.offset != 0;
2403 if (!dowide && !dosync && !doppr) {
2405 * Force async with a WDTR message if we have a wide bus,
2406 * or just issue an SDTR with a 0 offset.
2408 if ((ahc->features & AHC_WIDE) != 0)
2414 ahc_print_devinfo(ahc, devinfo);
2415 printf("Ensuring async\n");
2419 /* Target initiated PPR is not allowed in the SCSI spec */
2420 if (devinfo->role == ROLE_TARGET)
2424 * Both the PPR message and SDTR message require the
2425 * goal syncrate to be limited to what the target device
2426 * is capable of handling (based on whether an LVD->SE
2427 * expander is on the bus), so combine these two cases.
2428 * Regardless, guarantee that if we are using WDTR and SDTR
2429 * messages that WDTR comes first.
2431 if (doppr || (dosync && !dowide)) {
2433 offset = tinfo->goal.offset;
2434 ahc_validate_offset(ahc, tinfo, rate, &offset,
2435 doppr ? tinfo->goal.width
2436 : tinfo->curr.width,
2439 ahc_construct_ppr(ahc, devinfo, period, offset,
2440 tinfo->goal.width, ppr_options);
2442 ahc_construct_sdtr(ahc, devinfo, period, offset);
2445 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2450 * Build a synchronous negotiation message in our message
2451 * buffer based on the input parameters.
2454 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2455 u_int period, u_int offset)
2458 period = AHC_ASYNC_XFER_PERIOD;
2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2462 ahc->msgout_buf[ahc->msgout_index++] = period;
2463 ahc->msgout_buf[ahc->msgout_index++] = offset;
2464 ahc->msgout_len += 5;
2466 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2467 ahc_name(ahc), devinfo->channel, devinfo->target,
2468 devinfo->lun, period, offset);
2473 * Build a wide negotiation message in our message
2474 * buffer based on the input parameters.
2477 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2483 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2484 ahc->msgout_len += 4;
2486 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2487 ahc_name(ahc), devinfo->channel, devinfo->target,
2488 devinfo->lun, bus_width);
2493 * Build a parallel protocol request message in our message
2494 * buffer based on the input parameters.
2497 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2498 u_int period, u_int offset, u_int bus_width,
2502 period = AHC_ASYNC_XFER_PERIOD;
2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2505 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2506 ahc->msgout_buf[ahc->msgout_index++] = period;
2507 ahc->msgout_buf[ahc->msgout_index++] = 0;
2508 ahc->msgout_buf[ahc->msgout_index++] = offset;
2509 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2510 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2511 ahc->msgout_len += 8;
2513 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2514 "offset %x, ppr_options %x\n", ahc_name(ahc),
2515 devinfo->channel, devinfo->target, devinfo->lun,
2516 bus_width, period, offset, ppr_options);
2521 * Clear any active message state.
2524 ahc_clear_msg_state(struct ahc_softc *ahc)
2526 ahc->msgout_len = 0;
2527 ahc->msgin_index = 0;
2528 ahc->msg_type = MSG_TYPE_NONE;
2529 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2531 * The target didn't care to respond to our
2532 * message request, so clear ATN.
2534 ahc_outb(ahc, CLRSINT1, CLRATNO);
2536 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2537 ahc_outb(ahc, SEQ_FLAGS2,
2538 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2542 ahc_handle_proto_violation(struct ahc_softc *ahc)
2544 struct ahc_devinfo devinfo;
2552 ahc_fetch_devinfo(ahc, &devinfo);
2553 scbid = ahc_inb(ahc, SCB_TAG);
2554 scb = ahc_lookup_scb(ahc, scbid);
2555 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2556 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2557 lastphase = ahc_inb(ahc, LASTPHASE);
2558 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2561 * The reconnecting target either did not send an
2562 * identify message, or did, but we didn't find an SCB
2565 ahc_print_devinfo(ahc, &devinfo);
2566 printf("Target did not send an IDENTIFY message. "
2567 "LASTPHASE = 0x%x.\n", lastphase);
2569 } else if (scb == NULL) {
2571 * We don't seem to have an SCB active for this
2572 * transaction. Print an error and reset the bus.
2574 ahc_print_devinfo(ahc, &devinfo);
2575 printf("No SCB found during protocol violation\n");
2576 goto proto_violation_reset;
2578 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2579 if ((seq_flags & NO_CDB_SENT) != 0) {
2580 ahc_print_path(ahc, scb);
2581 printf("No or incomplete CDB sent to device.\n");
2582 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2584 * The target never bothered to provide status to
2585 * us prior to completing the command. Since we don't
2586 * know the disposition of this command, we must attempt
2587 * to abort it. Assert ATN and prepare to send an abort
2590 ahc_print_path(ahc, scb);
2591 printf("Completed command without status.\n");
2593 ahc_print_path(ahc, scb);
2594 printf("Unknown protocol violation.\n");
2595 ahc_dump_card_state(ahc);
2598 if ((lastphase & ~P_DATAIN_DT) == 0
2599 || lastphase == P_COMMAND) {
2600 proto_violation_reset:
2602 * Target either went directly to data/command
2603 * phase or didn't respond to our ATN.
2604 * The only safe thing to do is to blow
2605 * it away with a bus reset.
2607 found = ahc_reset_channel(ahc, 'A', TRUE);
2608 printf("%s: Issued Channel %c Bus Reset. "
2609 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2612 * Leave the selection hardware off in case
2613 * this abort attempt will affect yet to
2616 ahc_outb(ahc, SCSISEQ,
2617 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2618 ahc_assert_atn(ahc);
2619 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2621 ahc_print_devinfo(ahc, &devinfo);
2622 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2623 ahc->msgout_len = 1;
2624 ahc->msgout_index = 0;
2625 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2627 ahc_print_path(ahc, scb);
2628 scb->flags |= SCB_ABORT;
2630 printf("Protocol violation %s. Attempting to abort.\n",
2631 ahc_lookup_phase_entry(curphase)->phasemsg);
2636 * Manual message loop handler.
2639 ahc_handle_message_phase(struct ahc_softc *ahc)
2641 struct ahc_devinfo devinfo;
2645 ahc_fetch_devinfo(ahc, &devinfo);
2646 end_session = FALSE;
2647 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2650 switch (ahc->msg_type) {
2651 case MSG_TYPE_INITIATOR_MSGOUT:
2657 if (ahc->msgout_len == 0)
2658 panic("HOST_MSG_LOOP interrupt with no active message");
2661 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2662 ahc_print_devinfo(ahc, &devinfo);
2663 printf("INITIATOR_MSG_OUT");
2666 phasemis = bus_phase != P_MESGOUT;
2669 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2670 printf(" PHASEMIS %s\n",
2671 ahc_lookup_phase_entry(bus_phase)
2675 if (bus_phase == P_MESGIN) {
2677 * Change gears and see if
2678 * this messages is of interest to
2679 * us or should be passed back to
2682 ahc_outb(ahc, CLRSINT1, CLRATNO);
2683 ahc->send_msg_perror = FALSE;
2684 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2685 ahc->msgin_index = 0;
2692 if (ahc->send_msg_perror) {
2693 ahc_outb(ahc, CLRSINT1, CLRATNO);
2694 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2696 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2697 printf(" byte 0x%x\n", ahc->send_msg_perror);
2699 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2703 msgdone = ahc->msgout_index == ahc->msgout_len;
2706 * The target has requested a retry.
2707 * Re-assert ATN, reset our message index to
2710 ahc->msgout_index = 0;
2711 ahc_assert_atn(ahc);
2714 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2716 /* Last byte is signified by dropping ATN */
2717 ahc_outb(ahc, CLRSINT1, CLRATNO);
2721 * Clear our interrupt status and present
2722 * the next byte on the bus.
2724 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2726 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2727 printf(" byte 0x%x\n",
2728 ahc->msgout_buf[ahc->msgout_index]);
2730 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2733 case MSG_TYPE_INITIATOR_MSGIN:
2739 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2740 ahc_print_devinfo(ahc, &devinfo);
2741 printf("INITIATOR_MSG_IN");
2744 phasemis = bus_phase != P_MESGIN;
2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2748 printf(" PHASEMIS %s\n",
2749 ahc_lookup_phase_entry(bus_phase)
2753 ahc->msgin_index = 0;
2754 if (bus_phase == P_MESGOUT
2755 && (ahc->send_msg_perror == TRUE
2756 || (ahc->msgout_len != 0
2757 && ahc->msgout_index == 0))) {
2758 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2765 /* Pull the byte in without acking it */
2766 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2769 printf(" byte 0x%x\n",
2770 ahc->msgin_buf[ahc->msgin_index]);
2773 message_done = ahc_parse_msg(ahc, &devinfo);
2777 * Clear our incoming message buffer in case there
2778 * is another message following this one.
2780 ahc->msgin_index = 0;
2783 * If this message illicited a response,
2784 * assert ATN so the target takes us to the
2785 * message out phase.
2787 if (ahc->msgout_len != 0) {
2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2790 ahc_print_devinfo(ahc, &devinfo);
2791 printf("Asserting ATN for response\n");
2794 ahc_assert_atn(ahc);
2799 if (message_done == MSGLOOP_TERMINATED) {
2803 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2804 ahc_inb(ahc, SCSIDATL);
2808 case MSG_TYPE_TARGET_MSGIN:
2813 if (ahc->msgout_len == 0)
2814 panic("Target MSGIN with no active message");
2817 * If we interrupted a mesgout session, the initiator
2818 * will not know this until our first REQ. So, we
2819 * only honor mesgout requests after we've sent our
2822 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2823 && ahc->msgout_index > 0)
2824 msgout_request = TRUE;
2826 msgout_request = FALSE;
2828 if (msgout_request) {
2831 * Change gears and see if
2832 * this messages is of interest to
2833 * us or should be passed back to
2836 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2837 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2838 ahc->msgin_index = 0;
2839 /* Dummy read to REQ for first byte */
2840 ahc_inb(ahc, SCSIDATL);
2841 ahc_outb(ahc, SXFRCTL0,
2842 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2846 msgdone = ahc->msgout_index == ahc->msgout_len;
2848 ahc_outb(ahc, SXFRCTL0,
2849 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2855 * Present the next byte on the bus.
2857 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2858 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2861 case MSG_TYPE_TARGET_MSGOUT:
2867 * The initiator signals that this is
2868 * the last byte by dropping ATN.
2870 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2873 * Read the latched byte, but turn off SPIOEN first
2874 * so that we don't inadvertently cause a REQ for the
2877 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2878 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2879 msgdone = ahc_parse_msg(ahc, &devinfo);
2880 if (msgdone == MSGLOOP_TERMINATED) {
2882 * The message is *really* done in that it caused
2883 * us to go to bus free. The sequencer has already
2884 * been reset at this point, so pull the ejection
2893 * XXX Read spec about initiator dropping ATN too soon
2894 * and use msgdone to detect it.
2896 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2897 ahc->msgin_index = 0;
2900 * If this message illicited a response, transition
2901 * to the Message in phase and send it.
2903 if (ahc->msgout_len != 0) {
2904 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2905 ahc_outb(ahc, SXFRCTL0,
2906 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2907 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2908 ahc->msgin_index = 0;
2916 /* Ask for the next byte. */
2917 ahc_outb(ahc, SXFRCTL0,
2918 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2924 panic("Unknown REQINIT message type");
2928 ahc_clear_msg_state(ahc);
2929 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2931 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2935 * See if we sent a particular extended message to the target.
2936 * If "full" is true, return true only if the target saw the full
2937 * message. If "full" is false, return true if the target saw at
2938 * least the first byte of the message.
2941 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2949 while (index < ahc->msgout_len) {
2950 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2953 end_index = index + 1 + ahc->msgout_buf[index + 1];
2954 if (ahc->msgout_buf[index+2] == msgval
2955 && type == AHCMSG_EXT) {
2958 if (ahc->msgout_index > end_index)
2960 } else if (ahc->msgout_index > index)
2964 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2965 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2967 /* Skip tag type and tag id or residue param*/
2970 /* Single byte message */
2971 if (type == AHCMSG_1B
2972 && ahc->msgout_buf[index] == msgval
2973 && ahc->msgout_index > index)
2985 * Wait for a complete incoming message, parse it, and respond accordingly.
2988 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2990 struct ahc_initiator_tinfo *tinfo;
2991 struct ahc_tmode_tstate *tstate;
2995 u_int targ_scsirate;
2997 done = MSGLOOP_IN_PROG;
3000 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3001 devinfo->target, &tstate);
3002 targ_scsirate = tinfo->scsirate;
3005 * Parse as much of the message as is available,
3006 * rejecting it if we don't support it. When
3007 * the entire message is available and has been
3008 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3009 * that we have parsed an entire message.
3011 * In the case of extended messages, we accept the length
3012 * byte outright and perform more checking once we know the
3013 * extended message type.
3015 switch (ahc->msgin_buf[0]) {
3016 case MSG_DISCONNECT:
3017 case MSG_SAVEDATAPOINTER:
3018 case MSG_CMDCOMPLETE:
3019 case MSG_RESTOREPOINTERS:
3020 case MSG_IGN_WIDE_RESIDUE:
3022 * End our message loop as these are messages
3023 * the sequencer handles on its own.
3025 done = MSGLOOP_TERMINATED;
3027 case MSG_MESSAGE_REJECT:
3028 response = ahc_handle_msg_reject(ahc, devinfo);
3031 done = MSGLOOP_MSGCOMPLETE;
3035 /* Wait for enough of the message to begin validation */
3036 if (ahc->msgin_index < 2)
3038 switch (ahc->msgin_buf[2]) {
3041 struct ahc_syncrate *syncrate;
3047 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3053 * Wait until we have both args before validating
3054 * and acting on this message.
3056 * Add one to MSG_EXT_SDTR_LEN to account for
3057 * the extended message preamble.
3059 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3062 period = ahc->msgin_buf[3];
3064 saved_offset = offset = ahc->msgin_buf[4];
3065 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3068 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3069 targ_scsirate & WIDEXFER,
3072 printf("(%s:%c:%d:%d): Received "
3073 "SDTR period %x, offset %x\n\t"
3074 "Filtered to period %x, offset %x\n",
3075 ahc_name(ahc), devinfo->channel,
3076 devinfo->target, devinfo->lun,
3077 ahc->msgin_buf[3], saved_offset,
3080 ahc_set_syncrate(ahc, devinfo,
3082 offset, ppr_options,
3083 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3087 * See if we initiated Sync Negotiation
3088 * and didn't have to fall down to async
3091 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3093 if (saved_offset != offset) {
3094 /* Went too low - force async */
3099 * Send our own SDTR in reply
3102 && devinfo->role == ROLE_INITIATOR) {
3103 printf("(%s:%c:%d:%d): Target "
3105 ahc_name(ahc), devinfo->channel,
3106 devinfo->target, devinfo->lun);
3108 ahc->msgout_index = 0;
3109 ahc->msgout_len = 0;
3110 ahc_construct_sdtr(ahc, devinfo,
3112 ahc->msgout_index = 0;
3115 done = MSGLOOP_MSGCOMPLETE;
3122 u_int sending_reply;
3124 sending_reply = FALSE;
3125 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3131 * Wait until we have our arg before validating
3132 * and acting on this message.
3134 * Add one to MSG_EXT_WDTR_LEN to account for
3135 * the extended message preamble.
3137 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3140 bus_width = ahc->msgin_buf[3];
3141 saved_width = bus_width;
3142 ahc_validate_width(ahc, tinfo, &bus_width,
3145 printf("(%s:%c:%d:%d): Received WDTR "
3146 "%x filtered to %x\n",
3147 ahc_name(ahc), devinfo->channel,
3148 devinfo->target, devinfo->lun,
3149 saved_width, bus_width);
3152 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3154 * Don't send a WDTR back to the
3155 * target, since we asked first.
3156 * If the width went higher than our
3157 * request, reject it.
3159 if (saved_width > bus_width) {
3161 printf("(%s:%c:%d:%d): requested %dBit "
3162 "transfers. Rejecting...\n",
3163 ahc_name(ahc), devinfo->channel,
3164 devinfo->target, devinfo->lun,
3165 8 * (0x01 << bus_width));
3170 * Send our own WDTR in reply
3173 && devinfo->role == ROLE_INITIATOR) {
3174 printf("(%s:%c:%d:%d): Target "
3176 ahc_name(ahc), devinfo->channel,
3177 devinfo->target, devinfo->lun);
3179 ahc->msgout_index = 0;
3180 ahc->msgout_len = 0;
3181 ahc_construct_wdtr(ahc, devinfo, bus_width);
3182 ahc->msgout_index = 0;
3184 sending_reply = TRUE;
3187 * After a wide message, we are async, but
3188 * some devices don't seem to honor this portion
3189 * of the spec. Force a renegotiation of the
3190 * sync component of our transfer agreement even
3191 * if our goal is async. By updating our width
3192 * after forcing the negotiation, we avoid
3193 * renegotiating for width.
3195 ahc_update_neg_request(ahc, devinfo, tstate,
3196 tinfo, AHC_NEG_ALWAYS);
3197 ahc_set_width(ahc, devinfo, bus_width,
3198 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3200 if (sending_reply == FALSE && reject == FALSE) {
3203 * We will always have an SDTR to send.
3205 ahc->msgout_index = 0;
3206 ahc->msgout_len = 0;
3207 ahc_build_transfer_msg(ahc, devinfo);
3208 ahc->msgout_index = 0;
3211 done = MSGLOOP_MSGCOMPLETE;
3216 struct ahc_syncrate *syncrate;
3223 u_int saved_ppr_options;
3225 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3231 * Wait until we have all args before validating
3232 * and acting on this message.
3234 * Add one to MSG_EXT_PPR_LEN to account for
3235 * the extended message preamble.
3237 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3240 period = ahc->msgin_buf[3];
3241 offset = ahc->msgin_buf[5];
3242 bus_width = ahc->msgin_buf[6];
3243 saved_width = bus_width;
3244 ppr_options = ahc->msgin_buf[7];
3246 * According to the spec, a DT only
3247 * period factor with no DT option
3248 * set implies async.
3250 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3253 saved_ppr_options = ppr_options;
3254 saved_offset = offset;
3257 * Mask out any options we don't support
3258 * on any controller. Transfer options are
3259 * only available if we are negotiating wide.
3261 ppr_options &= MSG_EXT_PPR_DT_REQ;
3265 ahc_validate_width(ahc, tinfo, &bus_width,
3267 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3270 ahc_validate_offset(ahc, tinfo, syncrate,
3274 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3276 * If we are unable to do any of the
3277 * requested options (we went too low),
3278 * then we'll have to reject the message.
3280 if (saved_width > bus_width
3281 || saved_offset != offset
3282 || saved_ppr_options != ppr_options) {
3291 if (devinfo->role != ROLE_TARGET)
3292 printf("(%s:%c:%d:%d): Target "
3294 ahc_name(ahc), devinfo->channel,
3295 devinfo->target, devinfo->lun);
3297 printf("(%s:%c:%d:%d): Initiator "
3299 ahc_name(ahc), devinfo->channel,
3300 devinfo->target, devinfo->lun);
3301 ahc->msgout_index = 0;
3302 ahc->msgout_len = 0;
3303 ahc_construct_ppr(ahc, devinfo, period, offset,
3304 bus_width, ppr_options);
3305 ahc->msgout_index = 0;
3309 printf("(%s:%c:%d:%d): Received PPR width %x, "
3310 "period %x, offset %x,options %x\n"
3311 "\tFiltered to width %x, period %x, "
3312 "offset %x, options %x\n",
3313 ahc_name(ahc), devinfo->channel,
3314 devinfo->target, devinfo->lun,
3315 saved_width, ahc->msgin_buf[3],
3316 saved_offset, saved_ppr_options,
3317 bus_width, period, offset, ppr_options);
3319 ahc_set_width(ahc, devinfo, bus_width,
3320 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3322 ahc_set_syncrate(ahc, devinfo,
3324 offset, ppr_options,
3325 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3327 done = MSGLOOP_MSGCOMPLETE;
3331 /* Unknown extended message. Reject it. */
3337 #ifdef AHC_TARGET_MODE
3338 case MSG_BUS_DEV_RESET:
3339 ahc_handle_devreset(ahc, devinfo,
3341 "Bus Device Reset Received",
3342 /*verbose_level*/0);
3344 done = MSGLOOP_TERMINATED;
3348 case MSG_CLEAR_QUEUE:
3352 /* Target mode messages */
3353 if (devinfo->role != ROLE_TARGET) {
3357 tag = SCB_LIST_NULL;
3358 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3359 tag = ahc_inb(ahc, INITIATOR_TAG);
3360 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3361 devinfo->lun, tag, ROLE_TARGET,
3364 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3365 if (tstate != NULL) {
3366 struct ahc_tmode_lstate* lstate;
3368 lstate = tstate->enabled_luns[devinfo->lun];
3369 if (lstate != NULL) {
3370 ahc_queue_lstate_event(ahc, lstate,
3371 devinfo->our_scsiid,
3374 ahc_send_lstate_events(ahc, lstate);
3378 done = MSGLOOP_TERMINATED;
3382 case MSG_TERM_IO_PROC:
3390 * Setup to reject the message.
3392 ahc->msgout_index = 0;
3393 ahc->msgout_len = 1;
3394 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3395 done = MSGLOOP_MSGCOMPLETE;
3399 if (done != MSGLOOP_IN_PROG && !response)
3400 /* Clear the outgoing message buffer */
3401 ahc->msgout_len = 0;
3407 * Process a message reject message.
3410 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3413 * What we care about here is if we had an
3414 * outstanding SDTR or WDTR message for this
3415 * target. If we did, this is a signal that
3416 * the target is refusing negotiation.
3419 struct ahc_initiator_tinfo *tinfo;
3420 struct ahc_tmode_tstate *tstate;
3425 scb_index = ahc_inb(ahc, SCB_TAG);
3426 scb = ahc_lookup_scb(ahc, scb_index);
3427 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3428 devinfo->our_scsiid,
3429 devinfo->target, &tstate);
3430 /* Might be necessary */
3431 last_msg = ahc_inb(ahc, LAST_MSG);
3433 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3435 * Target does not support the PPR message.
3436 * Attempt to negotiate SPI-2 style.
3439 printf("(%s:%c:%d:%d): PPR Rejected. "
3440 "Trying WDTR/SDTR\n",
3441 ahc_name(ahc), devinfo->channel,
3442 devinfo->target, devinfo->lun);
3444 tinfo->goal.ppr_options = 0;
3445 tinfo->curr.transport_version = 2;
3446 tinfo->goal.transport_version = 2;
3447 ahc->msgout_index = 0;
3448 ahc->msgout_len = 0;
3449 ahc_build_transfer_msg(ahc, devinfo);
3450 ahc->msgout_index = 0;
3452 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3454 /* note 8bit xfers */
3455 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3456 "8bit transfers\n", ahc_name(ahc),
3457 devinfo->channel, devinfo->target, devinfo->lun);
3458 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3459 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3462 * No need to clear the sync rate. If the target
3463 * did not accept the command, our syncrate is
3464 * unaffected. If the target started the negotiation,
3465 * but rejected our response, we already cleared the
3466 * sync rate before sending our WDTR.
3468 if (tinfo->goal.offset != tinfo->curr.offset) {
3470 /* Start the sync negotiation */
3471 ahc->msgout_index = 0;
3472 ahc->msgout_len = 0;
3473 ahc_build_transfer_msg(ahc, devinfo);
3474 ahc->msgout_index = 0;
3477 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3478 /* note asynch xfers and clear flag */
3479 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3480 /*offset*/0, /*ppr_options*/0,
3481 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3483 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3484 "Using asynchronous transfers\n",
3485 ahc_name(ahc), devinfo->channel,
3486 devinfo->target, devinfo->lun);
3487 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3491 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3493 if (tag_type == MSG_SIMPLE_TASK) {
3494 printf("(%s:%c:%d:%d): refuses tagged commands. "
3495 "Performing non-tagged I/O\n", ahc_name(ahc),
3496 devinfo->channel, devinfo->target, devinfo->lun);
3497 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3500 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3501 "Performing simple queue tagged I/O only\n",
3502 ahc_name(ahc), devinfo->channel, devinfo->target,
3503 devinfo->lun, tag_type == MSG_ORDERED_TASK
3504 ? "ordered" : "head of queue");
3505 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3510 * Resend the identify for this CCB as the target
3511 * may believe that the selection is invalid otherwise.
3513 ahc_outb(ahc, SCB_CONTROL,
3514 ahc_inb(ahc, SCB_CONTROL) & mask);
3515 scb->hscb->control &= mask;
3516 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3517 /*type*/MSG_SIMPLE_TASK);
3518 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3519 ahc_assert_atn(ahc);
3522 * This transaction is now at the head of
3523 * the untagged queue for this target.
3525 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3526 struct scb_tailq *untagged_q;
3529 &(ahc->untagged_queues[devinfo->target_offset]);
3530 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3531 scb->flags |= SCB_UNTAGGEDQ;
3533 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3537 * Requeue all tagged commands for this target
3538 * currently in our posession so they can be
3539 * converted to untagged commands.
3541 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3542 SCB_GET_CHANNEL(ahc, scb),
3543 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3544 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3548 * Otherwise, we ignore it.
3550 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3551 ahc_name(ahc), devinfo->channel, devinfo->target,
3558 * Process an ingnore wide residue message.
3561 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3566 scb_index = ahc_inb(ahc, SCB_TAG);
3567 scb = ahc_lookup_scb(ahc, scb_index);
3569 * XXX Actually check data direction in the sequencer?
3570 * Perhaps add datadir to some spare bits in the hscb?
3572 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3573 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3575 * Ignore the message if we haven't
3576 * seen an appropriate data phase yet.
3580 * If the residual occurred on the last
3581 * transfer and the transfer request was
3582 * expected to end on an odd count, do
3583 * nothing. Otherwise, subtract a byte
3584 * and update the residual count accordingly.
3588 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3589 if ((sgptr & SG_LIST_NULL) != 0
3590 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3592 * If the residual occurred on the last
3593 * transfer and the transfer request was
3594 * expected to end on an odd count, do
3598 struct ahc_dma_seg *sg;
3603 /* Pull in all of the sgptr */
3604 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3605 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3607 if ((sgptr & SG_LIST_NULL) != 0) {
3609 * The residual data count is not updated
3610 * for the command run to completion case.
3611 * Explicitly zero the count.
3613 data_cnt &= ~AHC_SG_LEN_MASK;
3616 data_addr = ahc_inl(ahc, SHADDR);
3620 sgptr &= SG_PTR_MASK;
3622 sg = ahc_sg_bus_to_virt(scb, sgptr);
3625 * The residual sg ptr points to the next S/G
3626 * to load so we must go back one.
3629 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3630 if (sg != scb->sg_list
3631 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3634 sglen = ahc_le32toh(sg->len);
3636 * Preserve High Address and SG_LIST bits
3637 * while setting the count to 1.
3639 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3640 data_addr = ahc_le32toh(sg->addr)
3641 + (sglen & AHC_SG_LEN_MASK) - 1;
3644 * Increment sg so it points to the
3648 sgptr = ahc_sg_virt_to_bus(scb, sg);
3650 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3651 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3653 * Toggle the "oddness" of the transfer length
3654 * to handle this mid-transfer ignore wide
3655 * residue. This ensures that the oddness is
3656 * correct for subsequent data transfers.
3658 ahc_outb(ahc, SCB_LUN,
3659 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3666 * Reinitialize the data pointers for the active transfer
3667 * based on its current residual.
3670 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3673 struct ahc_dma_seg *sg;
3679 scb_index = ahc_inb(ahc, SCB_TAG);
3680 scb = ahc_lookup_scb(ahc, scb_index);
3681 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3682 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3683 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3684 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3686 sgptr &= SG_PTR_MASK;
3687 sg = ahc_sg_bus_to_virt(scb, sgptr);
3689 /* The residual sg_ptr always points to the next sg */
3692 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3693 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3694 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3696 dataptr = ahc_le32toh(sg->addr)
3697 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3699 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3702 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3703 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3704 ahc_outb(ahc, HADDR,
3705 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3706 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3708 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3709 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3710 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3711 ahc_outb(ahc, HADDR, dataptr);
3712 ahc_outb(ahc, HCNT + 2, resid >> 16);
3713 ahc_outb(ahc, HCNT + 1, resid >> 8);
3714 ahc_outb(ahc, HCNT, resid);
3715 if ((ahc->features & AHC_ULTRA2) == 0) {
3716 ahc_outb(ahc, STCNT + 2, resid >> 16);
3717 ahc_outb(ahc, STCNT + 1, resid >> 8);
3718 ahc_outb(ahc, STCNT, resid);
3723 * Handle the effects of issuing a bus device reset message.
3726 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3727 cam_status status, char *message, int verbose_level)
3729 #ifdef AHC_TARGET_MODE
3730 struct ahc_tmode_tstate* tstate;
3735 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3736 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3739 #ifdef AHC_TARGET_MODE
3741 * Send an immediate notify ccb to all target mord peripheral
3742 * drivers affected by this action.
3744 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3745 if (tstate != NULL) {
3746 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3747 struct ahc_tmode_lstate* lstate;
3749 lstate = tstate->enabled_luns[lun];
3753 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3754 MSG_BUS_DEV_RESET, /*arg*/0);
3755 ahc_send_lstate_events(ahc, lstate);
3761 * Go back to async/narrow transfers and renegotiate.
3763 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3764 AHC_TRANS_CUR, /*paused*/TRUE);
3765 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3766 /*period*/0, /*offset*/0, /*ppr_options*/0,
3767 AHC_TRANS_CUR, /*paused*/TRUE);
3769 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3770 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3773 && (verbose_level <= bootverbose))
3774 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3775 message, devinfo->channel, devinfo->target, found);
3778 #ifdef AHC_TARGET_MODE
3780 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3785 * To facilitate adding multiple messages together,
3786 * each routine should increment the index and len
3787 * variables instead of setting them explicitly.
3789 ahc->msgout_index = 0;
3790 ahc->msgout_len = 0;
3792 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3793 ahc_build_transfer_msg(ahc, devinfo);
3795 panic("ahc_intr: AWAITING target message with no message");
3797 ahc->msgout_index = 0;
3798 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3801 /**************************** Initialization **********************************/
3803 * Allocate a controller structure for a new device
3804 * and perform initial initializion.
3807 ahc_alloc(void *platform_arg, char *name)
3809 struct ahc_softc *ahc;
3813 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3815 printf("aic7xxx: cannot malloc softc!\n");
3816 free(name, M_DEVBUF);
3820 ahc = device_get_softc((device_t)platform_arg);
3822 memset(ahc, 0, sizeof(*ahc));
3823 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3824 M_DEVBUF, M_NOWAIT);
3825 if (ahc->seep_config == NULL) {
3827 free(ahc, M_DEVBUF);
3829 free(name, M_DEVBUF);
3832 LIST_INIT(&ahc->pending_scbs);
3833 /* We don't know our unit number until the OSM sets it */
3836 ahc->description = NULL;
3838 ahc->channel_b = 'B';
3839 ahc->chip = AHC_NONE;
3840 ahc->features = AHC_FENONE;
3841 ahc->bugs = AHC_BUGNONE;
3842 ahc->flags = AHC_FNONE;
3844 * Default to all error reporting enabled with the
3845 * sequencer operating at its fastest speed.
3846 * The bus attach code may modify this.
3848 ahc->seqctl = FASTMODE;
3850 for (i = 0; i < AHC_NUM_TARGETS; i++)
3851 TAILQ_INIT(&ahc->untagged_queues[i]);
3852 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3860 ahc_softc_init(struct ahc_softc *ahc)
3863 /* The IRQMS bit is only valid on VL and EISA chips */
3864 if ((ahc->chip & AHC_PCI) == 0)
3865 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3868 ahc->pause = ahc->unpause | PAUSE;
3869 /* XXX The shared scb data stuff should be deprecated */
3870 if (ahc->scb_data == NULL) {
3871 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3872 M_DEVBUF, M_NOWAIT);
3873 if (ahc->scb_data == NULL)
3875 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3882 ahc_softc_insert(struct ahc_softc *ahc)
3884 struct ahc_softc *list_ahc;
3886 #if AHC_PCI_CONFIG > 0
3888 * Second Function PCI devices need to inherit some
3889 * settings from function 0.
3891 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3892 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3893 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3894 ahc_dev_softc_t list_pci;
3895 ahc_dev_softc_t pci;
3897 list_pci = list_ahc->dev_softc;
3898 pci = ahc->dev_softc;
3899 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3900 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
3901 struct ahc_softc *master;
3902 struct ahc_softc *slave;
3904 if (ahc_get_pci_function(list_pci) == 0) {
3911 slave->flags &= ~AHC_BIOS_ENABLED;
3913 master->flags & AHC_BIOS_ENABLED;
3914 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3916 master->flags & AHC_PRIMARY_CHANNEL;
3924 * Insertion sort into our list of softcs.
3926 list_ahc = TAILQ_FIRST(&ahc_tailq);
3927 while (list_ahc != NULL
3928 && ahc_softc_comp(ahc, list_ahc) <= 0)
3929 list_ahc = TAILQ_NEXT(list_ahc, links);
3930 if (list_ahc != NULL)
3931 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
3933 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
3938 * Verify that the passed in softc pointer is for a
3939 * controller that is still configured.
3942 ahc_find_softc(struct ahc_softc *ahc)
3944 struct ahc_softc *list_ahc;
3946 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3947 if (list_ahc == ahc)
3954 ahc_set_unit(struct ahc_softc *ahc, int unit)
3960 ahc_set_name(struct ahc_softc *ahc, char *name)
3962 if (ahc->name != NULL)
3963 free(ahc->name, M_DEVBUF);
3968 ahc_free(struct ahc_softc *ahc)
3972 switch (ahc->init_level) {
3978 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3979 ahc->shared_data_dmamap);
3982 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3983 ahc->shared_data_dmamap);
3984 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3985 ahc->shared_data_dmamap);
3988 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3991 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3999 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
4001 ahc_platform_free(ahc);
4002 ahc_fini_scbdata(ahc);
4003 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4004 struct ahc_tmode_tstate *tstate;
4006 tstate = ahc->enabled_targets[i];
4007 if (tstate != NULL) {
4008 #ifdef AHC_TARGET_MODE
4011 for (j = 0; j < AHC_NUM_LUNS; j++) {
4012 struct ahc_tmode_lstate *lstate;
4014 lstate = tstate->enabled_luns[j];
4015 if (lstate != NULL) {
4016 xpt_free_path(lstate->path);
4017 free(lstate, M_DEVBUF);
4021 free(tstate, M_DEVBUF);
4024 #ifdef AHC_TARGET_MODE
4025 if (ahc->black_hole != NULL) {
4026 xpt_free_path(ahc->black_hole->path);
4027 free(ahc->black_hole, M_DEVBUF);
4030 if (ahc->name != NULL)
4031 free(ahc->name, M_DEVBUF);
4032 if (ahc->seep_config != NULL)
4033 free(ahc->seep_config, M_DEVBUF);
4035 free(ahc, M_DEVBUF);
4041 ahc_shutdown(void *arg)
4043 struct ahc_softc *ahc;
4046 ahc = (struct ahc_softc *)arg;
4048 /* This will reset most registers to 0, but not all */
4049 ahc_reset(ahc, /*reinit*/FALSE);
4050 ahc_outb(ahc, SCSISEQ, 0);
4051 ahc_outb(ahc, SXFRCTL0, 0);
4052 ahc_outb(ahc, DSPCISTATUS, 0);
4054 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4055 ahc_outb(ahc, i, 0);
4059 * Reset the controller and record some information about it
4060 * that is only available just after a reset. If "reinit" is
4061 * non-zero, this reset occured after initial configuration
4062 * and the caller requests that the chip be fully reinitialized
4063 * to a runable state. Chip interrupts are *not* enabled after
4064 * a reinitialization. The caller must enable interrupts via
4065 * ahc_intr_enable().
4068 ahc_reset(struct ahc_softc *ahc, int reinit)
4071 u_int sxfrctl1_a, sxfrctl1_b;
4076 * Preserve the value of the SXFRCTL1 register for all channels.
4077 * It contains settings that affect termination and we don't want
4078 * to disturb the integrity of the bus.
4081 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) {
4083 * The chip has not been initialized since
4084 * PCI/EISA/VLB bus reset. Don't trust
4085 * "left over BIOS data".
4087 ahc->flags |= AHC_NO_BIOS_INIT;
4090 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4094 * Save channel B's settings in case this chip
4095 * is setup for TWIN channel operation.
4097 sblkctl = ahc_inb(ahc, SBLKCTL);
4098 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4099 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4100 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4102 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4104 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4107 * Ensure that the reset has finished. We delay 1000us
4108 * prior to reading the register to make sure the chip
4109 * has sufficiently completed its reset to handle register
4115 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4118 printf("%s: WARNING - Failed chip reset! "
4119 "Trying to initialize anyway.\n", ahc_name(ahc));
4121 ahc_outb(ahc, HCNTRL, ahc->pause);
4123 /* Determine channel configuration */
4124 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4125 /* No Twin Channel PCI cards */
4126 if ((ahc->chip & AHC_PCI) != 0)
4127 sblkctl &= ~SELBUSB;
4130 /* Single Narrow Channel */
4134 ahc->features |= AHC_WIDE;
4138 ahc->features |= AHC_TWIN;
4141 printf(" Unsupported adapter type. Ignoring\n");
4148 * We must always initialize STPWEN to 1 before we
4149 * restore the saved values. STPWEN is initialized
4150 * to a tri-state condition which can only be cleared
4153 if ((ahc->features & AHC_TWIN) != 0) {
4156 sblkctl = ahc_inb(ahc, SBLKCTL);
4157 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4158 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4159 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4161 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4166 * If a recovery action has forced a chip reset,
4167 * re-initialize the chip to our liking.
4169 error = ahc->bus_chip_init(ahc);
4179 * Determine the number of SCBs available on the controller
4182 ahc_probe_scbs(struct ahc_softc *ahc) {
4185 for (i = 0; i < AHC_SCB_MAX; i++) {
4187 ahc_outb(ahc, SCBPTR, i);
4188 ahc_outb(ahc, SCB_BASE, i);
4189 if (ahc_inb(ahc, SCB_BASE) != i)
4191 ahc_outb(ahc, SCBPTR, 0);
4192 if (ahc_inb(ahc, SCB_BASE) != 0)
4199 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4203 baddr = (dma_addr_t *)arg;
4204 *baddr = segs->ds_addr;
4208 ahc_build_free_scb_list(struct ahc_softc *ahc)
4214 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4217 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4220 ahc_outb(ahc, SCBPTR, i);
4223 * Touch all SCB bytes to avoid parity errors
4224 * should one of our debugging routines read
4225 * an otherwise uninitiatlized byte.
4227 for (j = 0; j < scbsize; j++)
4228 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4230 /* Clear the control byte. */
4231 ahc_outb(ahc, SCB_CONTROL, 0);
4233 /* Set the next pointer */
4234 if ((ahc->flags & AHC_PAGESCBS) != 0)
4235 ahc_outb(ahc, SCB_NEXT, i+1);
4237 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4239 /* Make the tag number, SCSIID, and lun invalid */
4240 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4241 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4242 ahc_outb(ahc, SCB_LUN, 0xFF);
4245 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4246 /* SCB 0 heads the free list. */
4247 ahc_outb(ahc, FREE_SCBH, 0);
4250 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4253 /* Make sure that the last SCB terminates the free list */
4254 ahc_outb(ahc, SCBPTR, i-1);
4255 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4259 ahc_init_scbdata(struct ahc_softc *ahc)
4261 struct scb_data *scb_data;
4263 scb_data = ahc->scb_data;
4264 SLIST_INIT(&scb_data->free_scbs);
4265 SLIST_INIT(&scb_data->sg_maps);
4267 /* Allocate SCB resources */
4268 scb_data->scbarray =
4269 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4270 M_DEVBUF, M_NOWAIT);
4271 if (scb_data->scbarray == NULL)
4273 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4275 /* Determine the number of hardware SCBs and initialize them */
4277 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4278 if (ahc->scb_data->maxhscbs == 0) {
4279 printf("%s: No SCB space found\n", ahc_name(ahc));
4284 * Create our DMA tags. These tags define the kinds of device
4285 * accessible memory allocations and memory mappings we will
4286 * need to perform during normal operation.
4288 * Unless we need to further restrict the allocation, we rely
4289 * on the restrictions of the parent dmat, hence the common
4290 * use of MAXADDR and MAXSIZE.
4293 /* DMA tag for our hardware scb structures */
4294 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4295 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4296 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4297 /*highaddr*/BUS_SPACE_MAXADDR,
4298 /*filter*/NULL, /*filterarg*/NULL,
4299 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4301 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4302 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4306 scb_data->init_level++;
4308 /* Allocation for our hscbs */
4309 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4310 (void **)&scb_data->hscbs,
4311 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4315 scb_data->init_level++;
4317 /* And permanently map them */
4318 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4320 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4321 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4323 scb_data->init_level++;
4325 /* DMA tag for our sense buffers */
4326 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4327 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4328 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4329 /*highaddr*/BUS_SPACE_MAXADDR,
4330 /*filter*/NULL, /*filterarg*/NULL,
4331 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4333 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4334 /*flags*/0, &scb_data->sense_dmat) != 0) {
4338 scb_data->init_level++;
4341 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4342 (void **)&scb_data->sense,
4343 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4347 scb_data->init_level++;
4349 /* And permanently map them */
4350 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4352 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4353 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4355 scb_data->init_level++;
4357 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4358 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4359 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4360 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4361 /*highaddr*/BUS_SPACE_MAXADDR,
4362 /*filter*/NULL, /*filterarg*/NULL,
4363 PAGE_SIZE, /*nsegments*/1,
4364 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4365 /*flags*/0, &scb_data->sg_dmat) != 0) {
4369 scb_data->init_level++;
4371 /* Perform initial CCB allocation */
4372 memset(scb_data->hscbs, 0,
4373 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4374 ahc_alloc_scbs(ahc);
4376 if (scb_data->numscbs == 0) {
4377 printf("%s: ahc_init_scbdata - "
4378 "Unable to allocate initial scbs\n",
4384 * Reserve the next queued SCB.
4386 ahc->next_queued_scb = ahc_get_scb(ahc);
4389 * Note that we were successfull
4399 ahc_fini_scbdata(struct ahc_softc *ahc)
4401 struct scb_data *scb_data;
4403 scb_data = ahc->scb_data;
4404 if (scb_data == NULL)
4407 switch (scb_data->init_level) {
4411 struct sg_map_node *sg_map;
4413 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4414 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4415 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4417 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4420 free(sg_map, M_DEVBUF);
4422 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4425 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4426 scb_data->sense_dmamap);
4428 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4429 scb_data->sense_dmamap);
4430 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4431 scb_data->sense_dmamap);
4433 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4435 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4436 scb_data->hscb_dmamap);
4438 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4439 scb_data->hscb_dmamap);
4440 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4441 scb_data->hscb_dmamap);
4443 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4448 if (scb_data->scbarray != NULL)
4449 free(scb_data->scbarray, M_DEVBUF);
4453 ahc_alloc_scbs(struct ahc_softc *ahc)
4455 struct scb_data *scb_data;
4456 struct scb *next_scb;
4457 struct sg_map_node *sg_map;
4458 dma_addr_t physaddr;
4459 struct ahc_dma_seg *segs;
4463 scb_data = ahc->scb_data;
4464 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4465 /* Can't allocate any more */
4468 next_scb = &scb_data->scbarray[scb_data->numscbs];
4470 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4475 /* Allocate S/G space for the next batch of SCBS */
4476 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4477 (void **)&sg_map->sg_vaddr,
4478 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4479 free(sg_map, M_DEVBUF);
4483 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4485 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4486 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4487 &sg_map->sg_physaddr, /*flags*/0);
4489 segs = sg_map->sg_vaddr;
4490 physaddr = sg_map->sg_physaddr;
4492 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4493 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4494 for (i = 0; i < newcount; i++) {
4495 struct scb_platform_data *pdata;
4499 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4500 M_DEVBUF, M_NOWAIT);
4503 next_scb->platform_data = pdata;
4504 next_scb->sg_map = sg_map;
4505 next_scb->sg_list = segs;
4507 * The sequencer always starts with the second entry.
4508 * The first entry is embedded in the scb.
4510 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4511 next_scb->ahc_softc = ahc;
4512 next_scb->flags = SCB_FREE;
4514 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4519 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4520 next_scb->hscb->tag = ahc->scb_data->numscbs;
4521 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4522 next_scb, links.sle);
4524 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4526 ahc->scb_data->numscbs++;
4531 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4535 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4537 if ((ahc->features & AHC_TWIN) != 0)
4538 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4539 "B SCSI Id=%d, primary %c, ",
4540 ahc->our_id, ahc->our_id_b,
4541 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4547 if ((ahc->features & AHC_ULTRA) != 0) {
4549 } else if ((ahc->features & AHC_DT) != 0) {
4550 speed = "Ultra160 ";
4551 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4554 if ((ahc->features & AHC_WIDE) != 0) {
4559 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4560 speed, type, ahc->channel, ahc->our_id);
4564 if ((ahc->flags & AHC_PAGESCBS) != 0)
4565 sprintf(buf, "%d/%d SCBs",
4566 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4568 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4572 ahc_chip_init(struct ahc_softc *ahc)
4578 u_int scsiseq_template;
4581 ahc_outb(ahc, SEQ_FLAGS, 0);
4582 ahc_outb(ahc, SEQ_FLAGS2, 0);
4584 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4585 if (ahc->features & AHC_TWIN) {
4588 * Setup Channel B first.
4590 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4591 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4592 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4593 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4594 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4595 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4596 if ((ahc->features & AHC_ULTRA2) != 0)
4597 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4598 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4599 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4601 /* Select Channel A */
4602 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4604 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4605 if ((ahc->features & AHC_ULTRA2) != 0)
4606 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4608 ahc_outb(ahc, SCSIID, ahc->our_id);
4609 scsi_conf = ahc_inb(ahc, SCSICONF);
4610 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4612 |ENSTIMER|ACTNEGEN);
4613 if ((ahc->features & AHC_ULTRA2) != 0)
4614 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4615 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4616 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4618 /* There are no untagged SCBs active yet. */
4619 for (i = 0; i < 16; i++) {
4620 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4621 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4625 * The SCB based BTT allows an entry per
4626 * target and lun pair.
4628 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4629 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4633 /* All of our queues are empty */
4634 for (i = 0; i < 256; i++)
4635 ahc->qoutfifo[i] = SCB_LIST_NULL;
4636 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4638 for (i = 0; i < 256; i++)
4639 ahc->qinfifo[i] = SCB_LIST_NULL;
4641 if ((ahc->features & AHC_MULTI_TID) != 0) {
4642 ahc_outb(ahc, TARGID, 0);
4643 ahc_outb(ahc, TARGID + 1, 0);
4647 * Tell the sequencer where it can find our arrays in memory.
4649 physaddr = ahc->scb_data->hscb_busaddr;
4650 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4651 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4652 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4653 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4655 physaddr = ahc->shared_data_busaddr;
4656 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4657 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4658 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4659 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4662 * Initialize the group code to command length table.
4663 * This overrides the values in TARG_SCSIRATE, so only
4664 * setup the table after we have processed that information.
4666 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4667 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4668 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4669 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4670 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4671 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4672 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4673 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4675 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4676 ahc_outb(ahc, HS_MAILBOX, 0);
4678 /* Tell the sequencer of our initial queue positions */
4679 if ((ahc->features & AHC_TARGETMODE) != 0) {
4680 ahc->tqinfifonext = 1;
4681 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4682 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4684 ahc->qinfifonext = 0;
4685 ahc->qoutfifonext = 0;
4686 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4687 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4688 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4689 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4690 ahc_outb(ahc, SDSCB_QOFF, 0);
4692 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4693 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4694 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4697 /* We don't have any waiting selections */
4698 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4700 /* Our disconnection list is empty too */
4701 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4703 /* Message out buffer starts empty */
4704 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4707 * Setup the allowed SCSI Sequences based on operational mode.
4708 * If we are a target, we'll enalbe select in operations once
4709 * we've had a lun enabled.
4711 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4712 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4713 scsiseq_template |= ENRSELI;
4714 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4716 /* Initialize our list of free SCBs. */
4717 ahc_build_free_scb_list(ahc);
4720 * Tell the sequencer which SCB will be the next one it receives.
4722 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4725 * Load the Sequencer program and Enable the adapter
4729 printf("%s: Downloading Sequencer Program...",
4732 error = ahc_loadseq(ahc);
4736 if ((ahc->features & AHC_ULTRA2) != 0) {
4740 * Wait for up to 500ms for our transceivers
4741 * to settle. If the adapter does not have
4742 * a cable attached, the transceivers may
4743 * never settle, so don't complain if we
4747 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4756 * Start the board, ready for normal operation
4759 ahc_init(struct ahc_softc *ahc)
4767 size_t driver_data_size;
4770 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4771 ahc->flags |= AHC_SEQUENCER_DEBUG;
4774 #ifdef AHC_PRINT_SRAM
4775 printf("Scratch Ram:");
4776 for (i = 0x20; i < 0x5f; i++) {
4777 if (((i % 8) == 0) && (i != 0)) {
4780 printf (" 0x%x", ahc_inb(ahc, i));
4782 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4783 for (i = 0x70; i < 0x7f; i++) {
4784 if (((i % 8) == 0) && (i != 0)) {
4787 printf (" 0x%x", ahc_inb(ahc, i));
4792 * Reading uninitialized scratch ram may
4793 * generate parity errors.
4795 ahc_outb(ahc, CLRINT, CLRPARERR);
4796 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4801 * Assume we have a board at this stage and it has been reset.
4803 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4804 ahc->our_id = ahc->our_id_b = 7;
4807 * Default to allowing initiator operations.
4809 ahc->flags |= AHC_INITIATORROLE;
4812 * Only allow target mode features if this unit has them enabled.
4814 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4815 ahc->features &= ~AHC_TARGETMODE;
4818 /* DMA tag for mapping buffers into device visible space. */
4819 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4820 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4821 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4822 ? (dma_addr_t)0x7FFFFFFFFFULL
4823 : BUS_SPACE_MAXADDR_32BIT,
4824 /*highaddr*/BUS_SPACE_MAXADDR,
4825 /*filter*/NULL, /*filterarg*/NULL,
4826 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4827 /*nsegments*/AHC_NSEG,
4828 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4829 /*flags*/BUS_DMA_ALLOCNOW,
4830 &ahc->buffer_dmat) != 0) {
4838 * DMA tag for our command fifos and other data in system memory
4839 * the card's sequencer must be able to access. For initiator
4840 * roles, we need to allocate space for the qinfifo and qoutfifo.
4841 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4842 * When providing for the target mode role, we must additionally
4843 * provide space for the incoming target command fifo and an extra
4844 * byte to deal with a dma bug in some chip versions.
4846 driver_data_size = 2 * 256 * sizeof(uint8_t);
4847 if ((ahc->features & AHC_TARGETMODE) != 0)
4848 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4849 + /*DMA WideOdd Bug Buffer*/1;
4850 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4851 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4852 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4853 /*highaddr*/BUS_SPACE_MAXADDR,
4854 /*filter*/NULL, /*filterarg*/NULL,
4857 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4858 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4864 /* Allocation of driver data */
4865 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4866 (void **)&ahc->qoutfifo,
4867 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4873 /* And permanently map it in */
4874 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4875 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4876 &ahc->shared_data_busaddr, /*flags*/0);
4878 if ((ahc->features & AHC_TARGETMODE) != 0) {
4879 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4880 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4881 ahc->dma_bug_buf = ahc->shared_data_busaddr
4882 + driver_data_size - 1;
4883 /* All target command blocks start out invalid. */
4884 for (i = 0; i < AHC_TMODE_CMDS; i++)
4885 ahc->targetcmds[i].cmd_valid = 0;
4886 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4887 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4889 ahc->qinfifo = &ahc->qoutfifo[256];
4893 /* Allocate SCB data now that buffer_dmat is initialized */
4894 if (ahc->scb_data->maxhscbs == 0)
4895 if (ahc_init_scbdata(ahc) != 0)
4899 * Allocate a tstate to house information for our
4900 * initiator presence on the bus as well as the user
4901 * data for any target mode initiator.
4903 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4904 printf("%s: unable to allocate ahc_tmode_tstate. "
4905 "Failing attach\n", ahc_name(ahc));
4909 if ((ahc->features & AHC_TWIN) != 0) {
4910 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4911 printf("%s: unable to allocate ahc_tmode_tstate. "
4912 "Failing attach\n", ahc_name(ahc));
4917 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4918 ahc->flags |= AHC_PAGESCBS;
4920 ahc->flags &= ~AHC_PAGESCBS;
4924 if (ahc_debug & AHC_SHOW_MISC) {
4925 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4926 "ahc_dma %u bytes\n",
4928 (u_int)sizeof(struct hardware_scb),
4929 (u_int)sizeof(struct scb),
4930 (u_int)sizeof(struct ahc_dma_seg));
4932 #endif /* AHC_DEBUG */
4935 * Look at the information that board initialization or
4936 * the board bios has left us.
4938 if (ahc->features & AHC_TWIN) {
4939 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4940 if ((scsi_conf & RESET_SCSI) != 0
4941 && (ahc->flags & AHC_INITIATORROLE) != 0)
4942 ahc->flags |= AHC_RESET_BUS_B;
4945 scsi_conf = ahc_inb(ahc, SCSICONF);
4946 if ((scsi_conf & RESET_SCSI) != 0
4947 && (ahc->flags & AHC_INITIATORROLE) != 0)
4948 ahc->flags |= AHC_RESET_BUS_A;
4951 tagenable = ALL_TARGETS_MASK;
4953 /* Grab the disconnection disable table and invert it for our needs */
4954 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4955 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4956 "device parameters\n", ahc_name(ahc));
4957 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4958 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4959 discenable = ALL_TARGETS_MASK;
4960 if ((ahc->features & AHC_ULTRA) != 0)
4961 ultraenb = ALL_TARGETS_MASK;
4963 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4964 | ahc_inb(ahc, DISC_DSB));
4965 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4966 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4967 | ahc_inb(ahc, ULTRA_ENB);
4970 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4973 for (i = 0; i <= max_targ; i++) {
4974 struct ahc_initiator_tinfo *tinfo;
4975 struct ahc_tmode_tstate *tstate;
4981 our_id = ahc->our_id;
4983 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4985 our_id = ahc->our_id_b;
4988 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4989 target_id, &tstate);
4990 /* Default to async narrow across the board */
4991 memset(tinfo, 0, sizeof(*tinfo));
4992 if (ahc->flags & AHC_USEDEFAULTS) {
4993 if ((ahc->features & AHC_WIDE) != 0)
4994 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4997 * These will be truncated when we determine the
4998 * connection type we have with the target.
5000 tinfo->user.period = ahc_syncrates->period;
5001 tinfo->user.offset = MAX_OFFSET;
5006 /* Take the settings leftover in scratch RAM. */
5007 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5009 if ((ahc->features & AHC_ULTRA2) != 0) {
5013 if ((scsirate & SOFS) == 0x0F) {
5015 * Haven't negotiated yet,
5016 * so the format is different.
5018 scsirate = (scsirate & SXFR) >> 4
5021 | (scsirate & WIDEXFER);
5022 offset = MAX_OFFSET_ULTRA2;
5024 offset = ahc_inb(ahc, TARG_OFFSET + i);
5025 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5026 /* Set to the lowest sync rate, 5MHz */
5028 maxsync = AHC_SYNCRATE_ULTRA2;
5029 if ((ahc->features & AHC_DT) != 0)
5030 maxsync = AHC_SYNCRATE_DT;
5031 tinfo->user.period =
5032 ahc_find_period(ahc, scsirate, maxsync);
5034 tinfo->user.period = 0;
5036 tinfo->user.offset = MAX_OFFSET;
5037 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5038 && (ahc->features & AHC_DT) != 0)
5039 tinfo->user.ppr_options =
5041 } else if ((scsirate & SOFS) != 0) {
5042 if ((scsirate & SXFR) == 0x40
5043 && (ultraenb & mask) != 0) {
5044 /* Treat 10MHz as a non-ultra speed */
5048 tinfo->user.period =
5049 ahc_find_period(ahc, scsirate,
5051 ? AHC_SYNCRATE_ULTRA
5052 : AHC_SYNCRATE_FAST);
5053 if (tinfo->user.period != 0)
5054 tinfo->user.offset = MAX_OFFSET;
5056 if (tinfo->user.period == 0)
5057 tinfo->user.offset = 0;
5058 if ((scsirate & WIDEXFER) != 0
5059 && (ahc->features & AHC_WIDE) != 0)
5060 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5061 tinfo->user.protocol_version = 4;
5062 if ((ahc->features & AHC_DT) != 0)
5063 tinfo->user.transport_version = 3;
5065 tinfo->user.transport_version = 2;
5066 tinfo->goal.protocol_version = 2;
5067 tinfo->goal.transport_version = 2;
5068 tinfo->curr.protocol_version = 2;
5069 tinfo->curr.transport_version = 2;
5071 tstate->ultraenb = 0;
5073 ahc->user_discenable = discenable;
5074 ahc->user_tagenable = tagenable;
5076 return (ahc->bus_chip_init(ahc));
5080 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5084 hcntrl = ahc_inb(ahc, HCNTRL);
5086 ahc->pause &= ~INTEN;
5087 ahc->unpause &= ~INTEN;
5090 ahc->pause |= INTEN;
5091 ahc->unpause |= INTEN;
5093 ahc_outb(ahc, HCNTRL, hcntrl);
5097 * Ensure that the card is paused in a location
5098 * outside of all critical sections and that all
5099 * pending work is completed prior to returning.
5100 * This routine should only be called from outside
5101 * an interrupt context.
5104 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5111 ahc->flags |= AHC_ALL_INTERRUPTS;
5119 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5120 ahc_clear_critical_section(ahc);
5121 intstat = ahc_inb(ahc, INTSTAT);
5123 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5124 && ((intstat & INT_PEND) != 0
5125 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5126 if (maxloops == 0) {
5127 printf("Infinite interrupt loop, INTSTAT = %x",
5128 ahc_inb(ahc, INTSTAT));
5130 ahc_platform_flushwork(ahc);
5131 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5135 ahc_suspend(struct ahc_softc *ahc)
5138 ahc_pause_and_flushwork(ahc);
5140 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5145 #ifdef AHC_TARGET_MODE
5147 * XXX What about ATIOs that have not yet been serviced?
5148 * Perhaps we should just refuse to be suspended if we
5149 * are acting in a target role.
5151 if (ahc->pending_device != NULL) {
5161 ahc_resume(struct ahc_softc *ahc)
5164 ahc_reset(ahc, /*reinit*/TRUE);
5165 ahc_intr_enable(ahc, TRUE);
5170 /************************** Busy Target Table *********************************/
5172 * Return the untagged transaction id for a given target/channel lun.
5173 * Optionally, clear the entry.
5176 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5179 u_int target_offset;
5181 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5184 saved_scbptr = ahc_inb(ahc, SCBPTR);
5185 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5186 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5187 ahc_outb(ahc, SCBPTR, saved_scbptr);
5189 target_offset = TCL_TARGET_OFFSET(tcl);
5190 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5197 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5199 u_int target_offset;
5201 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5204 saved_scbptr = ahc_inb(ahc, SCBPTR);
5205 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5206 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5207 ahc_outb(ahc, SCBPTR, saved_scbptr);
5209 target_offset = TCL_TARGET_OFFSET(tcl);
5210 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5215 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5217 u_int target_offset;
5219 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5222 saved_scbptr = ahc_inb(ahc, SCBPTR);
5223 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5224 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5225 ahc_outb(ahc, SCBPTR, saved_scbptr);
5227 target_offset = TCL_TARGET_OFFSET(tcl);
5228 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5232 /************************** SCB and SCB queue management **********************/
5234 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5235 char channel, int lun, u_int tag, role_t role)
5237 int targ = SCB_GET_TARGET(ahc, scb);
5238 char chan = SCB_GET_CHANNEL(ahc, scb);
5239 int slun = SCB_GET_LUN(scb);
5242 match = ((chan == channel) || (channel == ALL_CHANNELS));
5244 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5246 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5248 #ifdef AHC_TARGET_MODE
5251 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5252 if (role == ROLE_INITIATOR) {
5253 match = (group != XPT_FC_GROUP_TMODE)
5254 && ((tag == scb->hscb->tag)
5255 || (tag == SCB_LIST_NULL));
5256 } else if (role == ROLE_TARGET) {
5257 match = (group == XPT_FC_GROUP_TMODE)
5258 && ((tag == scb->io_ctx->csio.tag_id)
5259 || (tag == SCB_LIST_NULL));
5261 #else /* !AHC_TARGET_MODE */
5262 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5263 #endif /* AHC_TARGET_MODE */
5270 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5276 target = SCB_GET_TARGET(ahc, scb);
5277 lun = SCB_GET_LUN(scb);
5278 channel = SCB_GET_CHANNEL(ahc, scb);
5280 ahc_search_qinfifo(ahc, target, channel, lun,
5281 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5282 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5284 ahc_platform_freeze_devq(ahc, scb);
5288 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5290 struct scb *prev_scb;
5293 if (ahc_qinfifo_count(ahc) != 0) {
5297 prev_pos = ahc->qinfifonext - 1;
5298 prev_tag = ahc->qinfifo[prev_pos];
5299 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5301 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5302 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5303 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5305 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5310 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5313 if (prev_scb == NULL) {
5314 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5316 prev_scb->hscb->next = scb->hscb->tag;
5317 ahc_sync_scb(ahc, prev_scb,
5318 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5320 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5321 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5322 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5326 ahc_qinfifo_count(struct ahc_softc *ahc)
5331 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5332 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5333 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5335 qinpos = ahc_inb(ahc, QINPOS);
5336 diff = ahc->qinfifonext - qinpos;
5341 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5342 int lun, u_int tag, role_t role, uint32_t status,
5343 ahc_search_action action)
5346 struct scb *prev_scb;
5356 qintail = ahc->qinfifonext;
5357 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5359 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5360 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5362 qinstart = ahc_inb(ahc, QINPOS);
5367 if (action == SEARCH_COMPLETE) {
5369 * Don't attempt to run any queued untagged transactions
5370 * until we are done with the abort process.
5372 ahc_freeze_untagged_queues(ahc);
5376 * Start with an empty queue. Entries that are not chosen
5377 * for removal will be re-added to the queue as we go.
5379 ahc->qinfifonext = qinpos;
5380 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5382 while (qinpos != qintail) {
5383 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5385 printf("qinpos = %d, SCB index = %d\n",
5386 qinpos, ahc->qinfifo[qinpos]);
5390 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5392 * We found an scb that needs to be acted on.
5396 case SEARCH_COMPLETE:
5401 ostat = ahc_get_transaction_status(scb);
5402 if (ostat == CAM_REQ_INPROG)
5403 ahc_set_transaction_status(scb, status);
5404 cstat = ahc_get_transaction_status(scb);
5405 if (cstat != CAM_REQ_CMP)
5406 ahc_freeze_scb(scb);
5407 if ((scb->flags & SCB_ACTIVE) == 0)
5408 printf("Inactive SCB in qinfifo\n");
5416 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5421 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5427 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5428 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5430 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5433 if (action != SEARCH_COUNT
5435 && (qinstart != ahc->qinfifonext)) {
5437 * The sequencer may be in the process of dmaing
5438 * down the SCB at the beginning of the queue.
5439 * This could be problematic if either the first,
5440 * or the second SCB is removed from the queue
5441 * (the first SCB includes a pointer to the "next"
5442 * SCB to dma). If we have removed any entries, swap
5443 * the first element in the queue with the next HSCB
5444 * so the sequencer will notice that NEXT_QUEUED_SCB
5445 * has changed during its dma attempt and will retry
5448 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5451 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5452 found, qinstart, ahc->qinfifonext);
5453 panic("First/Second Qinfifo fixup\n");
5456 * ahc_swap_with_next_hscb forces our next pointer to
5457 * point to the reserved SCB for future commands. Save
5458 * and restore our original next pointer to maintain
5461 next = scb->hscb->next;
5462 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5463 ahc_swap_with_next_hscb(ahc, scb);
5464 scb->hscb->next = next;
5465 ahc->qinfifo[qinstart] = scb->hscb->tag;
5467 /* Tell the card about the new head of the qinfifo. */
5468 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5470 /* Fixup the tail "next" pointer. */
5471 qintail = ahc->qinfifonext - 1;
5472 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5473 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5477 * Search waiting for selection list.
5479 curscbptr = ahc_inb(ahc, SCBPTR);
5480 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5481 prev = SCB_LIST_NULL;
5483 while (next != SCB_LIST_NULL) {
5486 ahc_outb(ahc, SCBPTR, next);
5487 scb_index = ahc_inb(ahc, SCB_TAG);
5488 if (scb_index >= ahc->scb_data->numscbs) {
5489 printf("Waiting List inconsistency. "
5490 "SCB index == %d, yet numscbs == %d.",
5491 scb_index, ahc->scb_data->numscbs);
5492 ahc_dump_card_state(ahc);
5493 panic("for safety");
5495 scb = ahc_lookup_scb(ahc, scb_index);
5497 printf("scb_index = %d, next = %d\n",
5499 panic("Waiting List traversal\n");
5501 if (ahc_match_scb(ahc, scb, target, channel,
5502 lun, SCB_LIST_NULL, role)) {
5504 * We found an scb that needs to be acted on.
5508 case SEARCH_COMPLETE:
5513 ostat = ahc_get_transaction_status(scb);
5514 if (ostat == CAM_REQ_INPROG)
5515 ahc_set_transaction_status(scb,
5517 cstat = ahc_get_transaction_status(scb);
5518 if (cstat != CAM_REQ_CMP)
5519 ahc_freeze_scb(scb);
5520 if ((scb->flags & SCB_ACTIVE) == 0)
5521 printf("Inactive SCB in Waiting List\n");
5526 next = ahc_rem_wscb(ahc, next, prev);
5530 next = ahc_inb(ahc, SCB_NEXT);
5536 next = ahc_inb(ahc, SCB_NEXT);
5539 ahc_outb(ahc, SCBPTR, curscbptr);
5541 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5542 channel, lun, status, action);
5544 if (action == SEARCH_COMPLETE)
5545 ahc_release_untagged_queues(ahc);
5550 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
5551 int target, char channel, int lun, uint32_t status,
5552 ahc_search_action action)
5559 if (action == SEARCH_COMPLETE) {
5561 * Don't attempt to run any queued untagged transactions
5562 * until we are done with the abort process.
5564 ahc_freeze_untagged_queues(ahc);
5569 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5572 if (target != CAM_TARGET_WILDCARD) {
5583 for (; i < maxtarget; i++) {
5584 struct scb_tailq *untagged_q;
5585 struct scb *next_scb;
5587 untagged_q = &(ahc->untagged_queues[i]);
5588 next_scb = TAILQ_FIRST(untagged_q);
5589 while (next_scb != NULL) {
5592 next_scb = TAILQ_NEXT(scb, links.tqe);
5595 * The head of the list may be the currently
5596 * active untagged command for a device.
5597 * We're only searching for commands that
5598 * have not been started. A transaction
5599 * marked active but still in the qinfifo
5600 * is removed by the qinfifo scanning code
5603 if ((scb->flags & SCB_ACTIVE) != 0)
5606 if (ahc_match_scb(ahc, scb, target, channel, lun,
5607 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5608 || (ctx != NULL && ctx != scb->io_ctx))
5612 * We found an scb that needs to be acted on.
5616 case SEARCH_COMPLETE:
5621 ostat = ahc_get_transaction_status(scb);
5622 if (ostat == CAM_REQ_INPROG)
5623 ahc_set_transaction_status(scb, status);
5624 cstat = ahc_get_transaction_status(scb);
5625 if (cstat != CAM_REQ_CMP)
5626 ahc_freeze_scb(scb);
5627 if ((scb->flags & SCB_ACTIVE) == 0)
5628 printf("Inactive SCB in untaggedQ\n");
5633 scb->flags &= ~SCB_UNTAGGEDQ;
5634 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5642 if (action == SEARCH_COMPLETE)
5643 ahc_release_untagged_queues(ahc);
5648 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5649 int lun, u_int tag, int stop_on_first, int remove,
5659 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5660 prev = SCB_LIST_NULL;
5663 /* restore this when we're done */
5664 active_scb = ahc_inb(ahc, SCBPTR);
5666 /* Silence compiler */
5667 active_scb = SCB_LIST_NULL;
5669 while (next != SCB_LIST_NULL) {
5672 ahc_outb(ahc, SCBPTR, next);
5673 scb_index = ahc_inb(ahc, SCB_TAG);
5674 if (scb_index >= ahc->scb_data->numscbs) {
5675 printf("Disconnected List inconsistency. "
5676 "SCB index == %d, yet numscbs == %d.",
5677 scb_index, ahc->scb_data->numscbs);
5678 ahc_dump_card_state(ahc);
5679 panic("for safety");
5683 panic("Disconnected List Loop. "
5684 "cur SCBPTR == %x, prev SCBPTR == %x.",
5687 scbp = ahc_lookup_scb(ahc, scb_index);
5688 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5689 tag, ROLE_INITIATOR)) {
5693 ahc_rem_scb_from_disc_list(ahc, prev, next);
5696 next = ahc_inb(ahc, SCB_NEXT);
5702 next = ahc_inb(ahc, SCB_NEXT);
5706 ahc_outb(ahc, SCBPTR, active_scb);
5711 * Remove an SCB from the on chip list of disconnected transactions.
5712 * This is empty/unused if we are not performing SCB paging.
5715 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5719 ahc_outb(ahc, SCBPTR, scbptr);
5720 next = ahc_inb(ahc, SCB_NEXT);
5722 ahc_outb(ahc, SCB_CONTROL, 0);
5724 ahc_add_curscb_to_free_list(ahc);
5726 if (prev != SCB_LIST_NULL) {
5727 ahc_outb(ahc, SCBPTR, prev);
5728 ahc_outb(ahc, SCB_NEXT, next);
5730 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5736 * Add the SCB as selected by SCBPTR onto the on chip list of
5737 * free hardware SCBs. This list is empty/unused if we are not
5738 * performing SCB paging.
5741 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5744 * Invalidate the tag so that our abort
5745 * routines don't think it's active.
5747 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5749 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5750 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5751 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5756 * Manipulate the waiting for selection list and return the
5757 * scb that follows the one that we remove.
5760 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5765 * Select the SCB we want to abort and
5766 * pull the next pointer out of it.
5768 curscb = ahc_inb(ahc, SCBPTR);
5769 ahc_outb(ahc, SCBPTR, scbpos);
5770 next = ahc_inb(ahc, SCB_NEXT);
5772 /* Clear the necessary fields */
5773 ahc_outb(ahc, SCB_CONTROL, 0);
5775 ahc_add_curscb_to_free_list(ahc);
5777 /* update the waiting list */
5778 if (prev == SCB_LIST_NULL) {
5779 /* First in the list */
5780 ahc_outb(ahc, WAITING_SCBH, next);
5783 * Ensure we aren't attempting to perform
5784 * selection for this entry.
5786 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5789 * Select the scb that pointed to us
5790 * and update its next pointer.
5792 ahc_outb(ahc, SCBPTR, prev);
5793 ahc_outb(ahc, SCB_NEXT, next);
5797 * Point us back at the original scb position.
5799 ahc_outb(ahc, SCBPTR, curscb);
5803 /******************************** Error Handling ******************************/
5805 * Abort all SCBs that match the given description (target/channel/lun/tag),
5806 * setting their status to the passed in status if the status has not already
5807 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5808 * is paused before it is called.
5811 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5812 int lun, u_int tag, role_t role, uint32_t status)
5815 struct scb *scbp_next;
5825 * Don't attempt to run any queued untagged transactions
5826 * until we are done with the abort process.
5828 ahc_freeze_untagged_queues(ahc);
5830 /* restore this when we're done */
5831 active_scb = ahc_inb(ahc, SCBPTR);
5833 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5834 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5837 * Clean out the busy target table for any untagged commands.
5841 if (target != CAM_TARGET_WILDCARD) {
5848 if (lun == CAM_LUN_WILDCARD) {
5851 * Unless we are using an SCB based
5852 * busy targets table, there is only
5853 * one table entry for all luns of
5858 if ((ahc->flags & AHC_SCB_BTT) != 0)
5859 maxlun = AHC_NUM_LUNS;
5865 if (role != ROLE_TARGET) {
5866 for (;i < maxtarget; i++) {
5867 for (j = minlun;j < maxlun; j++) {
5871 tcl = BUILD_TCL(i << 4, j);
5872 scbid = ahc_index_busy_tcl(ahc, tcl);
5873 scbp = ahc_lookup_scb(ahc, scbid);
5875 || ahc_match_scb(ahc, scbp, target, channel,
5876 lun, tag, role) == 0)
5878 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5883 * Go through the disconnected list and remove any entries we
5884 * have queued for completion, 0'ing their control byte too.
5885 * We save the active SCB and restore it ourselves, so there
5886 * is no reason for this search to restore it too.
5888 ahc_search_disc_list(ahc, target, channel, lun, tag,
5889 /*stop_on_first*/FALSE, /*remove*/TRUE,
5890 /*save_state*/FALSE);
5894 * Go through the hardware SCB array looking for commands that
5895 * were active but not on any list. In some cases, these remnants
5896 * might not still have mappings in the scbindex array (e.g. unexpected
5897 * bus free with the same scb queued for an abort). Don't hold this
5900 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5903 ahc_outb(ahc, SCBPTR, i);
5904 scbid = ahc_inb(ahc, SCB_TAG);
5905 scbp = ahc_lookup_scb(ahc, scbid);
5906 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5908 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5909 ahc_add_curscb_to_free_list(ahc);
5913 * Go through the pending CCB list and look for
5914 * commands for this target that are still active.
5915 * These are other tagged commands that were
5916 * disconnected when the reset occurred.
5918 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5919 while (scbp_next != NULL) {
5921 scbp_next = LIST_NEXT(scbp, pending_links);
5922 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5925 ostat = ahc_get_transaction_status(scbp);
5926 if (ostat == CAM_REQ_INPROG)
5927 ahc_set_transaction_status(scbp, status);
5928 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5929 ahc_freeze_scb(scbp);
5930 if ((scbp->flags & SCB_ACTIVE) == 0)
5931 printf("Inactive SCB on pending list\n");
5932 ahc_done(ahc, scbp);
5936 ahc_outb(ahc, SCBPTR, active_scb);
5937 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5938 ahc_release_untagged_queues(ahc);
5943 ahc_reset_current_bus(struct ahc_softc *ahc)
5947 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5948 scsiseq = ahc_inb(ahc, SCSISEQ);
5949 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5950 ahc_flush_device_writes(ahc);
5951 ahc_delay(AHC_BUSRESET_DELAY);
5952 /* Turn off the bus reset */
5953 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5955 ahc_clear_intstat(ahc);
5957 /* Re-enable reset interrupts */
5958 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5962 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5964 struct ahc_devinfo devinfo;
5965 u_int initiator, target, max_scsiid;
5973 ahc->pending_device = NULL;
5975 ahc_compile_devinfo(&devinfo,
5976 CAM_TARGET_WILDCARD,
5977 CAM_TARGET_WILDCARD,
5979 channel, ROLE_UNKNOWN);
5982 /* Make sure the sequencer is in a safe location. */
5983 ahc_clear_critical_section(ahc);
5986 * Run our command complete fifos to ensure that we perform
5987 * completion processing on any commands that 'completed'
5988 * before the reset occurred.
5990 ahc_run_qoutfifo(ahc);
5991 #ifdef AHC_TARGET_MODE
5993 * XXX - In Twin mode, the tqinfifo may have commands
5994 * for an unaffected channel in it. However, if
5995 * we have run out of ATIO resources to drain that
5996 * queue, we may not get them all out here. Further,
5997 * the blocked transactions for the reset channel
5998 * should just be killed off, irrespecitve of whether
5999 * we are blocked on ATIO resources. Write a routine
6000 * to compact the tqinfifo appropriately.
6002 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6003 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6008 * Reset the bus if we are initiating this reset
6010 sblkctl = ahc_inb(ahc, SBLKCTL);
6012 if ((ahc->features & AHC_TWIN) != 0
6013 && ((sblkctl & SELBUSB) != 0))
6015 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6016 if (cur_channel != channel) {
6017 /* Case 1: Command for another bus is active
6018 * Stealthily reset the other bus without
6019 * upsetting the current bus.
6021 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6022 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6023 #ifdef AHC_TARGET_MODE
6025 * Bus resets clear ENSELI, so we cannot
6026 * defer re-enabling bus reset interrupts
6027 * if we are in target mode.
6029 if ((ahc->flags & AHC_TARGETROLE) != 0)
6030 simode1 |= ENSCSIRST;
6032 ahc_outb(ahc, SIMODE1, simode1);
6034 ahc_reset_current_bus(ahc);
6035 ahc_clear_intstat(ahc);
6036 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6037 ahc_outb(ahc, SBLKCTL, sblkctl);
6038 restart_needed = FALSE;
6040 /* Case 2: A command from this bus is active or we're idle */
6041 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6042 #ifdef AHC_TARGET_MODE
6044 * Bus resets clear ENSELI, so we cannot
6045 * defer re-enabling bus reset interrupts
6046 * if we are in target mode.
6048 if ((ahc->flags & AHC_TARGETROLE) != 0)
6049 simode1 |= ENSCSIRST;
6051 ahc_outb(ahc, SIMODE1, simode1);
6053 ahc_reset_current_bus(ahc);
6054 ahc_clear_intstat(ahc);
6055 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6056 restart_needed = TRUE;
6060 * Clean up all the state information for the
6061 * pending transactions on this bus.
6063 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6064 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6065 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6067 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6069 #ifdef AHC_TARGET_MODE
6071 * Send an immediate notify ccb to all target more peripheral
6072 * drivers affected by this action.
6074 for (target = 0; target <= max_scsiid; target++) {
6075 struct ahc_tmode_tstate* tstate;
6078 tstate = ahc->enabled_targets[target];
6081 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6082 struct ahc_tmode_lstate* lstate;
6084 lstate = tstate->enabled_luns[lun];
6088 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6089 EVENT_TYPE_BUS_RESET, /*arg*/0);
6090 ahc_send_lstate_events(ahc, lstate);
6094 /* Notify the XPT that a bus reset occurred */
6095 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6096 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6099 * Revert to async/narrow transfers until we renegotiate.
6101 for (target = 0; target <= max_scsiid; target++) {
6103 if (ahc->enabled_targets[target] == NULL)
6105 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6106 struct ahc_devinfo devinfo;
6108 ahc_compile_devinfo(&devinfo, target, initiator,
6110 channel, ROLE_UNKNOWN);
6111 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6112 AHC_TRANS_CUR, /*paused*/TRUE);
6113 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6114 /*period*/0, /*offset*/0,
6115 /*ppr_options*/0, AHC_TRANS_CUR,
6128 /***************************** Residual Processing ****************************/
6130 * Calculate the residual for a just completed SCB.
6133 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6135 struct hardware_scb *hscb;
6136 struct status_pkt *spkt;
6138 uint32_t resid_sgptr;
6144 * SG_RESID_VALID clear in sgptr.
6145 * 2) Transferless command
6146 * 3) Never performed any transfers.
6147 * sgptr has SG_FULL_RESID set.
6148 * 4) No residual but target did not
6149 * save data pointers after the
6150 * last transfer, so sgptr was
6152 * 5) We have a partial residual.
6153 * Use residual_sgptr to determine
6158 sgptr = ahc_le32toh(hscb->sgptr);
6159 if ((sgptr & SG_RESID_VALID) == 0)
6162 sgptr &= ~SG_RESID_VALID;
6164 if ((sgptr & SG_LIST_NULL) != 0)
6168 spkt = &hscb->shared_data.status;
6169 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6170 if ((sgptr & SG_FULL_RESID) != 0) {
6172 resid = ahc_get_transfer_length(scb);
6173 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6176 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6177 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6179 struct ahc_dma_seg *sg;
6182 * Remainder of the SG where the transfer
6185 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6186 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6188 /* The residual sg_ptr always points to the next sg */
6192 * Add up the contents of all residual
6193 * SG segments that are after the SG where
6194 * the transfer stopped.
6196 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6198 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6201 if ((scb->flags & SCB_SENSE) == 0)
6202 ahc_set_residual(scb, resid);
6204 ahc_set_sense_residual(scb, resid);
6207 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6208 ahc_print_path(ahc, scb);
6209 printf("Handled %sResidual of %d bytes\n",
6210 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6215 /******************************* Target Mode **********************************/
6216 #ifdef AHC_TARGET_MODE
6218 * Add a target mode event to this lun's queue
6221 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6222 u_int initiator_id, u_int event_type, u_int event_arg)
6224 struct ahc_tmode_event *event;
6227 xpt_freeze_devq(lstate->path, /*count*/1);
6228 if (lstate->event_w_idx >= lstate->event_r_idx)
6229 pending = lstate->event_w_idx - lstate->event_r_idx;
6231 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6232 - (lstate->event_r_idx - lstate->event_w_idx);
6234 if (event_type == EVENT_TYPE_BUS_RESET
6235 || event_type == MSG_BUS_DEV_RESET) {
6237 * Any earlier events are irrelevant, so reset our buffer.
6238 * This has the effect of allowing us to deal with reset
6239 * floods (an external device holding down the reset line)
6240 * without losing the event that is really interesting.
6242 lstate->event_r_idx = 0;
6243 lstate->event_w_idx = 0;
6244 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6247 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6248 xpt_print_path(lstate->path);
6249 printf("immediate event %x:%x lost\n",
6250 lstate->event_buffer[lstate->event_r_idx].event_type,
6251 lstate->event_buffer[lstate->event_r_idx].event_arg);
6252 lstate->event_r_idx++;
6253 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6254 lstate->event_r_idx = 0;
6255 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6258 event = &lstate->event_buffer[lstate->event_w_idx];
6259 event->initiator_id = initiator_id;
6260 event->event_type = event_type;
6261 event->event_arg = event_arg;
6262 lstate->event_w_idx++;
6263 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6264 lstate->event_w_idx = 0;
6268 * Send any target mode events queued up waiting
6269 * for immediate notify resources.
6272 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6274 struct ccb_hdr *ccbh;
6275 struct ccb_immed_notify *inot;
6277 while (lstate->event_r_idx != lstate->event_w_idx
6278 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6279 struct ahc_tmode_event *event;
6281 event = &lstate->event_buffer[lstate->event_r_idx];
6282 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6283 inot = (struct ccb_immed_notify *)ccbh;
6284 switch (event->event_type) {
6285 case EVENT_TYPE_BUS_RESET:
6286 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6289 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6290 inot->message_args[0] = event->event_type;
6291 inot->message_args[1] = event->event_arg;
6294 inot->initiator_id = event->initiator_id;
6295 inot->sense_len = 0;
6296 xpt_done((union ccb *)inot);
6297 lstate->event_r_idx++;
6298 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6299 lstate->event_r_idx = 0;
6304 /******************** Sequencer Program Patching/Download *********************/
6308 ahc_dumpseq(struct ahc_softc* ahc)
6312 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6313 ahc_outb(ahc, SEQADDR0, 0);
6314 ahc_outb(ahc, SEQADDR1, 0);
6315 for (i = 0; i < ahc->instruction_ram_size; i++) {
6316 uint8_t ins_bytes[4];
6318 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6319 printf("0x%08x\n", ins_bytes[0] << 24
6320 | ins_bytes[1] << 16
6328 ahc_loadseq(struct ahc_softc *ahc)
6330 struct cs cs_table[num_critical_sections];
6331 u_int begin_set[num_critical_sections];
6332 u_int end_set[num_critical_sections];
6333 struct patch *cur_patch;
6338 u_int sg_prefetch_cnt;
6340 uint8_t download_consts[7];
6343 * Start out with 0 critical sections
6344 * that apply to this firmware load.
6348 memset(begin_set, 0, sizeof(begin_set));
6349 memset(end_set, 0, sizeof(end_set));
6351 /* Setup downloadable constant table */
6352 download_consts[QOUTFIFO_OFFSET] = 0;
6353 if (ahc->targetcmds != NULL)
6354 download_consts[QOUTFIFO_OFFSET] += 32;
6355 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6356 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6357 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6358 sg_prefetch_cnt = ahc->pci_cachesize;
6359 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6360 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6361 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6362 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6363 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6365 cur_patch = patches;
6368 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6369 ahc_outb(ahc, SEQADDR0, 0);
6370 ahc_outb(ahc, SEQADDR1, 0);
6372 for (i = 0; i < sizeof(seqprog)/4; i++) {
6373 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6375 * Don't download this instruction as it
6376 * is in a patch that was removed.
6381 if (downloaded == ahc->instruction_ram_size) {
6383 * We're about to exceed the instruction
6384 * storage capacity for this chip. Fail
6387 printf("\n%s: Program too large for instruction memory "
6388 "size of %d!\n", ahc_name(ahc),
6389 ahc->instruction_ram_size);
6394 * Move through the CS table until we find a CS
6395 * that might apply to this instruction.
6397 for (; cur_cs < num_critical_sections; cur_cs++) {
6398 if (critical_sections[cur_cs].end <= i) {
6399 if (begin_set[cs_count] == TRUE
6400 && end_set[cs_count] == FALSE) {
6401 cs_table[cs_count].end = downloaded;
6402 end_set[cs_count] = TRUE;
6407 if (critical_sections[cur_cs].begin <= i
6408 && begin_set[cs_count] == FALSE) {
6409 cs_table[cs_count].begin = downloaded;
6410 begin_set[cs_count] = TRUE;
6414 ahc_download_instr(ahc, i, download_consts);
6418 ahc->num_critical_sections = cs_count;
6419 if (cs_count != 0) {
6421 cs_count *= sizeof(struct cs);
6422 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6423 if (ahc->critical_sections == NULL)
6424 panic("ahc_loadseq: Could not malloc");
6425 memcpy(ahc->critical_sections, cs_table, cs_count);
6427 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6430 printf(" %d instructions downloaded\n", downloaded);
6431 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6432 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6438 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6439 u_int start_instr, u_int *skip_addr)
6441 struct patch *cur_patch;
6442 struct patch *last_patch;
6445 num_patches = sizeof(patches)/sizeof(struct patch);
6446 last_patch = &patches[num_patches];
6447 cur_patch = *start_patch;
6449 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6451 if (cur_patch->patch_func(ahc) == 0) {
6453 /* Start rejecting code */
6454 *skip_addr = start_instr + cur_patch->skip_instr;
6455 cur_patch += cur_patch->skip_patch;
6457 /* Accepted this patch. Advance to the next
6458 * one and wait for our intruction pointer to
6465 *start_patch = cur_patch;
6466 if (start_instr < *skip_addr)
6467 /* Still skipping */
6474 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6476 union ins_formats instr;
6477 struct ins_format1 *fmt1_ins;
6478 struct ins_format3 *fmt3_ins;
6482 * The firmware is always compiled into a little endian format.
6484 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6486 fmt1_ins = &instr.format1;
6489 /* Pull the opcode */
6490 opcode = instr.format1.opcode;
6501 struct patch *cur_patch;
6507 fmt3_ins = &instr.format3;
6509 address = fmt3_ins->address;
6510 cur_patch = patches;
6513 for (i = 0; i < address;) {
6515 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6517 if (skip_addr > i) {
6520 end_addr = MIN(address, skip_addr);
6521 address_offset += end_addr - i;
6527 address -= address_offset;
6528 fmt3_ins->address = address;
6537 if (fmt1_ins->parity != 0) {
6538 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6540 fmt1_ins->parity = 0;
6541 if ((ahc->features & AHC_CMD_CHAN) == 0
6542 && opcode == AIC_OP_BMOV) {
6544 * Block move was added at the same time
6545 * as the command channel. Verify that
6546 * this is only a move of a single element
6547 * and convert the BMOV to a MOV
6548 * (AND with an immediate of FF).
6550 if (fmt1_ins->immediate != 1)
6551 panic("%s: BMOV not supported\n",
6553 fmt1_ins->opcode = AIC_OP_AND;
6554 fmt1_ins->immediate = 0xff;
6558 if ((ahc->features & AHC_ULTRA2) != 0) {
6561 /* Calculate odd parity for the instruction */
6562 for (i = 0, count = 0; i < 31; i++) {
6566 if ((instr.integer & mask) != 0)
6569 if ((count & 0x01) == 0)
6570 instr.format1.parity = 1;
6572 /* Compress the instruction for older sequencers */
6573 if (fmt3_ins != NULL) {
6576 | (fmt3_ins->source << 8)
6577 | (fmt3_ins->address << 16)
6578 | (fmt3_ins->opcode << 25);
6582 | (fmt1_ins->source << 8)
6583 | (fmt1_ins->destination << 16)
6584 | (fmt1_ins->ret << 24)
6585 | (fmt1_ins->opcode << 25);
6588 /* The sequencer is a little endian cpu */
6589 instr.integer = ahc_htole32(instr.integer);
6590 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6593 panic("Unknown opcode encountered in seq program");
6599 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6600 const char *name, u_int address, u_int value,
6601 u_int *cur_column, u_int wrap_point)
6606 if (cur_column != NULL && *cur_column >= wrap_point) {
6610 printed = printf("%s[0x%x]", name, value);
6611 if (table == NULL) {
6612 printed += printf(" ");
6613 *cur_column += printed;
6617 while (printed_mask != 0xFF) {
6620 for (entry = 0; entry < num_entries; entry++) {
6621 if (((value & table[entry].mask)
6622 != table[entry].value)
6623 || ((printed_mask & table[entry].mask)
6624 == table[entry].mask))
6627 printed += printf("%s%s",
6628 printed_mask == 0 ? ":(" : "|",
6630 printed_mask |= table[entry].mask;
6634 if (entry >= num_entries)
6637 if (printed_mask != 0)
6638 printed += printf(") ");
6640 printed += printf(" ");
6641 if (cur_column != NULL)
6642 *cur_column += printed;
6647 ahc_dump_card_state(struct ahc_softc *ahc)
6650 struct scb_tailq *untagged_q;
6661 uint8_t saved_scbptr;
6663 if (ahc_is_paused(ahc)) {
6670 saved_scbptr = ahc_inb(ahc, SCBPTR);
6671 last_phase = ahc_inb(ahc, LASTPHASE);
6672 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6673 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6674 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6675 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6677 printf("Card was paused\n");
6678 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6679 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6680 ahc_inb(ahc, ARG_2));
6681 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6682 ahc_inb(ahc, SCBPTR));
6684 if ((ahc->features & AHC_DT) != 0)
6685 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6686 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6687 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6688 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6689 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6690 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6691 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6692 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6693 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6694 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6695 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6696 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6697 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6698 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6699 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6700 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6701 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6702 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6703 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6707 for (i = 0; i < STACK_SIZE; i++)
6708 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6709 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6710 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6711 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6713 printf("QINFIFO entries: ");
6714 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6715 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6716 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6718 qinpos = ahc_inb(ahc, QINPOS);
6719 qintail = ahc->qinfifonext;
6720 while (qinpos != qintail) {
6721 printf("%d ", ahc->qinfifo[qinpos]);
6726 printf("Waiting Queue entries: ");
6727 scb_index = ahc_inb(ahc, WAITING_SCBH);
6729 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6730 ahc_outb(ahc, SCBPTR, scb_index);
6731 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6732 scb_index = ahc_inb(ahc, SCB_NEXT);
6736 printf("Disconnected Queue entries: ");
6737 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6739 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6740 ahc_outb(ahc, SCBPTR, scb_index);
6741 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6742 scb_index = ahc_inb(ahc, SCB_NEXT);
6746 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6747 printf("QOUTFIFO entries: ");
6748 qoutpos = ahc->qoutfifonext;
6750 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6751 printf("%d ", ahc->qoutfifo[qoutpos]);
6756 printf("Sequencer Free SCB List: ");
6757 scb_index = ahc_inb(ahc, FREE_SCBH);
6759 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6760 ahc_outb(ahc, SCBPTR, scb_index);
6761 printf("%d ", scb_index);
6762 scb_index = ahc_inb(ahc, SCB_NEXT);
6766 printf("Sequencer SCB Info: ");
6767 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6768 ahc_outb(ahc, SCBPTR, i);
6769 cur_col = printf("\n%3d ", i);
6771 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6772 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6773 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6774 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6778 printf("Pending list: ");
6780 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6783 cur_col = printf("\n%3d ", scb->hscb->tag);
6784 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6785 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6786 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6787 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6788 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6790 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6792 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6798 printf("Kernel Free SCB list: ");
6800 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6803 printf("%d ", scb->hscb->tag);
6807 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6808 for (target = 0; target <= maxtarget; target++) {
6809 untagged_q = &ahc->untagged_queues[target];
6810 if (TAILQ_FIRST(untagged_q) == NULL)
6812 printf("Untagged Q(%d): ", target);
6814 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6817 printf("%d ", scb->hscb->tag);
6822 ahc_platform_dump_card_state(ahc);
6823 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6824 ahc_outb(ahc, SCBPTR, saved_scbptr);
6829 /************************* Target Mode ****************************************/
6830 #ifdef AHC_TARGET_MODE
6832 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6833 struct ahc_tmode_tstate **tstate,
6834 struct ahc_tmode_lstate **lstate,
6835 int notfound_failure)
6838 if ((ahc->features & AHC_TARGETMODE) == 0)
6839 return (CAM_REQ_INVALID);
6842 * Handle the 'black hole' device that sucks up
6843 * requests to unattached luns on enabled targets.
6845 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6846 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6848 *lstate = ahc->black_hole;
6852 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
6853 if (ccb->ccb_h.target_id > max_id)
6854 return (CAM_TID_INVALID);
6856 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6857 return (CAM_LUN_INVALID);
6859 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6861 if (*tstate != NULL)
6863 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6866 if (notfound_failure != 0 && *lstate == NULL)
6867 return (CAM_PATH_INVALID);
6869 return (CAM_REQ_CMP);
6873 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6875 struct ahc_tmode_tstate *tstate;
6876 struct ahc_tmode_lstate *lstate;
6877 struct ccb_en_lun *cel;
6887 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6888 /*notfound_failure*/FALSE);
6890 if (status != CAM_REQ_CMP) {
6891 ccb->ccb_h.status = status;
6895 if (cam_sim_bus(sim) == 0)
6896 our_id = ahc->our_id;
6898 our_id = ahc->our_id_b;
6900 if (ccb->ccb_h.target_id != our_id) {
6902 * our_id represents our initiator ID, or
6903 * the ID of the first target to have an
6904 * enabled lun in target mode. There are
6905 * two cases that may preclude enabling a
6906 * target id other than our_id.
6908 * o our_id is for an active initiator role.
6909 * Since the hardware does not support
6910 * reselections to the initiator role at
6911 * anything other than our_id, and our_id
6912 * is used by the hardware to indicate the
6913 * ID to use for both select-out and
6914 * reselect-out operations, the only target
6915 * ID we can support in this mode is our_id.
6917 * o The MULTARGID feature is not available and
6918 * a previous target mode ID has been enabled.
6920 if ((ahc->features & AHC_MULTIROLE) != 0) {
6922 if ((ahc->features & AHC_MULTI_TID) != 0
6923 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6925 * Only allow additional targets if
6926 * the initiator role is disabled.
6927 * The hardware cannot handle a re-select-in
6928 * on the initiator id during a re-select-out
6929 * on a different target id.
6931 status = CAM_TID_INVALID;
6932 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6933 || ahc->enabled_luns > 0) {
6935 * Only allow our target id to change
6936 * if the initiator role is not configured
6937 * and there are no enabled luns which
6938 * are attached to the currently registered
6941 status = CAM_TID_INVALID;
6943 } else if ((ahc->features & AHC_MULTI_TID) == 0
6944 && ahc->enabled_luns > 0) {
6946 status = CAM_TID_INVALID;
6950 if (status != CAM_REQ_CMP) {
6951 ccb->ccb_h.status = status;
6956 * We now have an id that is valid.
6957 * If we aren't in target mode, switch modes.
6959 if ((ahc->flags & AHC_TARGETROLE) == 0
6960 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6962 ahc_flag saved_flags;
6964 printf("Configuring Target Mode\n");
6966 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6967 ccb->ccb_h.status = CAM_BUSY;
6968 ahc_unlock(ahc, &s);
6971 saved_flags = ahc->flags;
6972 ahc->flags |= AHC_TARGETROLE;
6973 if ((ahc->features & AHC_MULTIROLE) == 0)
6974 ahc->flags &= ~AHC_INITIATORROLE;
6976 error = ahc_loadseq(ahc);
6979 * Restore original configuration and notify
6980 * the caller that we cannot support target mode.
6981 * Since the adapter started out in this
6982 * configuration, the firmware load will succeed,
6983 * so there is no point in checking ahc_loadseq's
6986 ahc->flags = saved_flags;
6987 (void)ahc_loadseq(ahc);
6989 ahc_unlock(ahc, &s);
6990 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
6994 ahc_unlock(ahc, &s);
6997 target = ccb->ccb_h.target_id;
6998 lun = ccb->ccb_h.target_lun;
6999 channel = SIM_CHANNEL(ahc, sim);
7000 target_mask = 0x01 << target;
7004 if (cel->enable != 0) {
7007 /* Are we already enabled?? */
7008 if (lstate != NULL) {
7009 xpt_print_path(ccb->ccb_h.path);
7010 printf("Lun already enabled\n");
7011 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7015 if (cel->grp6_len != 0
7016 || cel->grp7_len != 0) {
7018 * Don't (yet?) support vendor
7019 * specific commands.
7021 ccb->ccb_h.status = CAM_REQ_INVALID;
7022 printf("Non-zero Group Codes\n");
7028 * Setup our data structures.
7030 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7031 tstate = ahc_alloc_tstate(ahc, target, channel);
7032 if (tstate == NULL) {
7033 xpt_print_path(ccb->ccb_h.path);
7034 printf("Couldn't allocate tstate\n");
7035 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7039 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7040 if (lstate == NULL) {
7041 xpt_print_path(ccb->ccb_h.path);
7042 printf("Couldn't allocate lstate\n");
7043 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7046 memset(lstate, 0, sizeof(*lstate));
7047 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7048 xpt_path_path_id(ccb->ccb_h.path),
7049 xpt_path_target_id(ccb->ccb_h.path),
7050 xpt_path_lun_id(ccb->ccb_h.path));
7051 if (status != CAM_REQ_CMP) {
7052 free(lstate, M_DEVBUF);
7053 xpt_print_path(ccb->ccb_h.path);
7054 printf("Couldn't allocate path\n");
7055 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7058 SLIST_INIT(&lstate->accept_tios);
7059 SLIST_INIT(&lstate->immed_notifies);
7062 if (target != CAM_TARGET_WILDCARD) {
7063 tstate->enabled_luns[lun] = lstate;
7064 ahc->enabled_luns++;
7066 if ((ahc->features & AHC_MULTI_TID) != 0) {
7069 targid_mask = ahc_inb(ahc, TARGID)
7070 | (ahc_inb(ahc, TARGID + 1) << 8);
7072 targid_mask |= target_mask;
7073 ahc_outb(ahc, TARGID, targid_mask);
7074 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7076 ahc_update_scsiid(ahc, targid_mask);
7081 channel = SIM_CHANNEL(ahc, sim);
7082 our_id = SIM_SCSI_ID(ahc, sim);
7085 * This can only happen if selections
7088 if (target != our_id) {
7093 sblkctl = ahc_inb(ahc, SBLKCTL);
7094 cur_channel = (sblkctl & SELBUSB)
7096 if ((ahc->features & AHC_TWIN) == 0)
7098 swap = cur_channel != channel;
7100 ahc->our_id = target;
7102 ahc->our_id_b = target;
7105 ahc_outb(ahc, SBLKCTL,
7108 ahc_outb(ahc, SCSIID, target);
7111 ahc_outb(ahc, SBLKCTL, sblkctl);
7115 ahc->black_hole = lstate;
7116 /* Allow select-in operations */
7117 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7118 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7120 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7121 scsiseq = ahc_inb(ahc, SCSISEQ);
7123 ahc_outb(ahc, SCSISEQ, scsiseq);
7126 ahc_unlock(ahc, &s);
7127 ccb->ccb_h.status = CAM_REQ_CMP;
7128 xpt_print_path(ccb->ccb_h.path);
7129 printf("Lun now enabled for target mode\n");
7134 if (lstate == NULL) {
7135 ccb->ccb_h.status = CAM_LUN_INVALID;
7141 ccb->ccb_h.status = CAM_REQ_CMP;
7142 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7143 struct ccb_hdr *ccbh;
7145 ccbh = &scb->io_ctx->ccb_h;
7146 if (ccbh->func_code == XPT_CONT_TARGET_IO
7147 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7148 printf("CTIO pending\n");
7149 ccb->ccb_h.status = CAM_REQ_INVALID;
7150 ahc_unlock(ahc, &s);
7155 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7156 printf("ATIOs pending\n");
7157 ccb->ccb_h.status = CAM_REQ_INVALID;
7160 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7161 printf("INOTs pending\n");
7162 ccb->ccb_h.status = CAM_REQ_INVALID;
7165 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7166 ahc_unlock(ahc, &s);
7170 xpt_print_path(ccb->ccb_h.path);
7171 printf("Target mode disabled\n");
7172 xpt_free_path(lstate->path);
7173 free(lstate, M_DEVBUF);
7176 /* Can we clean up the target too? */
7177 if (target != CAM_TARGET_WILDCARD) {
7178 tstate->enabled_luns[lun] = NULL;
7179 ahc->enabled_luns--;
7180 for (empty = 1, i = 0; i < 8; i++)
7181 if (tstate->enabled_luns[i] != NULL) {
7187 ahc_free_tstate(ahc, target, channel,
7189 if (ahc->features & AHC_MULTI_TID) {
7192 targid_mask = ahc_inb(ahc, TARGID)
7193 | (ahc_inb(ahc, TARGID + 1)
7196 targid_mask &= ~target_mask;
7197 ahc_outb(ahc, TARGID, targid_mask);
7198 ahc_outb(ahc, TARGID+1,
7199 (targid_mask >> 8));
7200 ahc_update_scsiid(ahc, targid_mask);
7205 ahc->black_hole = NULL;
7208 * We can't allow selections without
7209 * our black hole device.
7213 if (ahc->enabled_luns == 0) {
7214 /* Disallow select-in */
7217 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7219 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7220 scsiseq = ahc_inb(ahc, SCSISEQ);
7222 ahc_outb(ahc, SCSISEQ, scsiseq);
7224 if ((ahc->features & AHC_MULTIROLE) == 0) {
7225 printf("Configuring Initiator Mode\n");
7226 ahc->flags &= ~AHC_TARGETROLE;
7227 ahc->flags |= AHC_INITIATORROLE;
7229 * Returning to a configuration that
7230 * fit previously will always succeed.
7232 (void)ahc_loadseq(ahc);
7235 * Unpaused. The extra unpause
7236 * that follows is harmless.
7241 ahc_unlock(ahc, &s);
7246 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7251 if ((ahc->features & AHC_MULTI_TID) == 0)
7252 panic("ahc_update_scsiid called on non-multitid unit\n");
7255 * Since we will rely on the TARGID mask
7256 * for selection enables, ensure that OID
7257 * in SCSIID is not set to some other ID
7258 * that we don't want to allow selections on.
7260 if ((ahc->features & AHC_ULTRA2) != 0)
7261 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7263 scsiid = ahc_inb(ahc, SCSIID);
7264 scsiid_mask = 0x1 << (scsiid & OID);
7265 if ((targid_mask & scsiid_mask) == 0) {
7268 /* ffs counts from 1 */
7269 our_id = ffs(targid_mask);
7271 our_id = ahc->our_id;
7277 if ((ahc->features & AHC_ULTRA2) != 0)
7278 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7280 ahc_outb(ahc, SCSIID, scsiid);
7284 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7286 struct target_cmd *cmd;
7289 * If the card supports auto-access pause,
7290 * we can access the card directly regardless
7291 * of whether it is paused or not.
7293 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7296 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7297 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7300 * Only advance through the queue if we
7301 * have the resources to process the command.
7303 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7307 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7308 ahc->shared_data_dmamap,
7309 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7310 sizeof(struct target_cmd),
7311 BUS_DMASYNC_PREREAD);
7312 ahc->tqinfifonext++;
7315 * Lazily update our position in the target mode incoming
7316 * command queue as seen by the sequencer.
7318 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7319 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7322 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7323 hs_mailbox &= ~HOST_TQINPOS;
7324 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7325 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7329 ahc_outb(ahc, KERNEL_TQINPOS,
7330 ahc->tqinfifonext & HOST_TQINPOS);
7339 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7341 struct ahc_tmode_tstate *tstate;
7342 struct ahc_tmode_lstate *lstate;
7343 struct ccb_accept_tio *atio;
7349 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7350 target = SCSIID_OUR_ID(cmd->scsiid);
7351 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7354 tstate = ahc->enabled_targets[target];
7357 lstate = tstate->enabled_luns[lun];
7360 * Commands for disabled luns go to the black hole driver.
7363 lstate = ahc->black_hole;
7365 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7367 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7369 * Wait for more ATIOs from the peripheral driver for this lun.
7372 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7375 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7377 printf("Incoming command from %d for %d:%d%s\n",
7378 initiator, target, lun,
7379 lstate == ahc->black_hole ? "(Black Holed)" : "");
7381 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7383 if (lstate == ahc->black_hole) {
7384 /* Fill in the wildcards */
7385 atio->ccb_h.target_id = target;
7386 atio->ccb_h.target_lun = lun;
7390 * Package it up and send it off to
7391 * whomever has this lun enabled.
7393 atio->sense_len = 0;
7394 atio->init_id = initiator;
7395 if (byte[0] != 0xFF) {
7396 /* Tag was included */
7397 atio->tag_action = *byte++;
7398 atio->tag_id = *byte++;
7399 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7401 atio->ccb_h.flags = 0;
7405 /* Okay. Now determine the cdb size based on the command code */
7406 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7422 /* Only copy the opcode. */
7424 printf("Reserved or VU command code type encountered\n");
7428 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7430 atio->ccb_h.status |= CAM_CDB_RECVD;
7432 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7434 * We weren't allowed to disconnect.
7435 * We're hanging on the bus until a
7436 * continue target I/O comes in response
7437 * to this accept tio.
7440 printf("Received Immediate Command %d:%d:%d - %p\n",
7441 initiator, target, lun, ahc->pending_device);
7443 ahc->pending_device = lstate;
7444 ahc_freeze_ccb((union ccb *)atio);
7445 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7447 xpt_done((union ccb*)atio);
projects / linux-2.6 / blob