git.oblomov.eu Git - linux-2.6/blob - drivers/video/savage/savagefb_driver.c

   1 /*
   2  * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
   3  *
   4  * Copyright (c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>
   5  *                          Sven Neumann <neo@directfb.org>
   6  *
   7  *
   8  * Card specific code is based on XFree86's savage driver.
   9  * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
  10  *
  11  * This file is subject to the terms and conditions of the GNU General
  12  * Public License.  See the file COPYING in the main directory of this
  13  * archive for more details.
  14  *
  15  * 0.4.0 (neo)
  16  *  - hardware accelerated clear and move
  17  *
  18  * 0.3.2 (dok)
  19  *  - wait for vertical retrace before writing to cr67
  20  *    at the beginning of savagefb_set_par
  21  *  - use synchronization registers cr23 and cr26
  22  *
  23  * 0.3.1 (dok)
  24  *  - reset 3D engine
  25  *  - don't return alpha bits for 32bit format
  26  *
  27  * 0.3.0 (dok)
  28  *  - added WaitIdle functions for all Savage types
  29  *  - do WaitIdle before mode switching
  30  *  - code cleanup
  31  *
  32  * 0.2.0 (dok)
  33  *  - first working version
  34  *
  35  *
  36  * TODO
  37  * - clock validations in decode_var
  38  *
  39  * BUGS
  40  * - white margin on bootup
  41  *
  42  */
  43
  44 #include <linux/module.h>
  45 #include <linux/kernel.h>
  46 #include <linux/errno.h>
  47 #include <linux/string.h>
  48 #include <linux/mm.h>
  49 #include <linux/slab.h>
  50 #include <linux/delay.h>
  51 #include <linux/fb.h>
  52 #include <linux/pci.h>
  53 #include <linux/init.h>
  54 #include <linux/console.h>
  55
  56 #include <asm/io.h>
  57 #include <asm/irq.h>
  58 #include <asm/pgtable.h>
  59 #include <asm/system.h>
  60 #include <asm/uaccess.h>
  61
  62 #ifdef CONFIG_MTRR
  63 #include <asm/mtrr.h>
  64 #endif
  65
  66 #include "savagefb.h"
  67
  68
  69 #define SAVAGEFB_VERSION "0.4.0_2.6"
  70
  71 /* --------------------------------------------------------------------- */
  72
  73
  74 static char *mode_option __devinitdata = NULL;
  75
  76 #ifdef MODULE
  77
  78 MODULE_AUTHOR("(c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>");
  79 MODULE_LICENSE("GPL");
  80 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
  81
  82 #endif
  83
  84
  85 /* --------------------------------------------------------------------- */
  86
  87 static void vgaHWSeqReset(struct savagefb_par *par, int start)
  88 {
  89         if (start)
  90                 VGAwSEQ(0x00, 0x01, par);       /* Synchronous Reset */
  91         else
  92                 VGAwSEQ(0x00, 0x03, par);       /* End Reset */
  93 }
  94
  95 static void vgaHWProtect(struct savagefb_par *par, int on)
  96 {
  97         unsigned char tmp;
  98
  99         if (on) {
 100                 /*
 101                  * Turn off screen and disable sequencer.
 102                  */
 103                 tmp = VGArSEQ(0x01, par);
 104
 105                 vgaHWSeqReset(par, 1);          /* start synchronous reset */
 106                 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
 107
 108                 VGAenablePalette(par);
 109         } else {
 110                 /*
 111                  * Reenable sequencer, then turn on screen.
 112                  */
 113
 114                 tmp = VGArSEQ(0x01, par);
 115
 116                 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
 117                 vgaHWSeqReset(par, 0);          /* clear synchronous reset */
 118
 119                 VGAdisablePalette(par);
 120         }
 121 }
 122
 123 static void vgaHWRestore(struct savagefb_par  *par, struct savage_reg *reg)
 124 {
 125         int i;
 126
 127         VGAwMISC(reg->MiscOutReg, par);
 128
 129         for (i = 1; i < 5; i++)
 130                 VGAwSEQ(i, reg->Sequencer[i], par);
 131
 132         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
 133            CRTC[17] */
 134         VGAwCR(17, reg->CRTC[17] & ~0x80, par);
 135
 136         for (i = 0; i < 25; i++)
 137                 VGAwCR(i, reg->CRTC[i], par);
 138
 139         for (i = 0; i < 9; i++)
 140                 VGAwGR(i, reg->Graphics[i], par);
 141
 142         VGAenablePalette(par);
 143
 144         for (i = 0; i < 21; i++)
 145                 VGAwATTR(i, reg->Attribute[i], par);
 146
 147         VGAdisablePalette(par);
 148 }
 149
 150 static void vgaHWInit(struct fb_var_screeninfo *var,
 151                       struct savagefb_par            *par,
 152                       struct xtimings                *timings,
 153                       struct savage_reg              *reg)
 154 {
 155         reg->MiscOutReg = 0x23;
 156
 157         if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
 158                 reg->MiscOutReg |= 0x40;
 159
 160         if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
 161                 reg->MiscOutReg |= 0x80;
 162
 163         /*
 164          * Time Sequencer
 165          */
 166         reg->Sequencer[0x00] = 0x00;
 167         reg->Sequencer[0x01] = 0x01;
 168         reg->Sequencer[0x02] = 0x0F;
 169         reg->Sequencer[0x03] = 0x00;          /* Font select */
 170         reg->Sequencer[0x04] = 0x0E;          /* Misc */
 171
 172         /*
 173          * CRTC Controller
 174          */
 175         reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
 176         reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
 177         reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
 178         reg->CRTC[0x03] = (((timings->HSyncEnd >> 3)  - 1) & 0x1f) | 0x80;
 179         reg->CRTC[0x04] = (timings->HSyncStart >> 3);
 180         reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
 181                 (((timings->HSyncEnd >> 3)) & 0x1f);
 182         reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
 183         reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
 184                 (((timings->VDisplay - 1) & 0x100) >> 7) |
 185                 ((timings->VSyncStart & 0x100) >> 6) |
 186                 (((timings->VSyncStart - 1) & 0x100) >> 5) |
 187                 0x10 |
 188                 (((timings->VTotal - 2) & 0x200) >> 4) |
 189                 (((timings->VDisplay - 1) & 0x200) >> 3) |
 190                 ((timings->VSyncStart & 0x200) >> 2);
 191         reg->CRTC[0x08] = 0x00;
 192         reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
 193
 194         if (timings->dblscan)
 195                 reg->CRTC[0x09] |= 0x80;
 196
 197         reg->CRTC[0x0a] = 0x00;
 198         reg->CRTC[0x0b] = 0x00;
 199         reg->CRTC[0x0c] = 0x00;
 200         reg->CRTC[0x0d] = 0x00;
 201         reg->CRTC[0x0e] = 0x00;
 202         reg->CRTC[0x0f] = 0x00;
 203         reg->CRTC[0x10] = timings->VSyncStart & 0xff;
 204         reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
 205         reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
 206         reg->CRTC[0x13] = var->xres_virtual >> 4;
 207         reg->CRTC[0x14] = 0x00;
 208         reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
 209         reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
 210         reg->CRTC[0x17] = 0xc3;
 211         reg->CRTC[0x18] = 0xff;
 212
 213         /*
 214          * are these unnecessary?
 215          * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 216          * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 217          */
 218
 219         /*
 220          * Graphics Display Controller
 221          */
 222         reg->Graphics[0x00] = 0x00;
 223         reg->Graphics[0x01] = 0x00;
 224         reg->Graphics[0x02] = 0x00;
 225         reg->Graphics[0x03] = 0x00;
 226         reg->Graphics[0x04] = 0x00;
 227         reg->Graphics[0x05] = 0x40;
 228         reg->Graphics[0x06] = 0x05;   /* only map 64k VGA memory !!!! */
 229         reg->Graphics[0x07] = 0x0F;
 230         reg->Graphics[0x08] = 0xFF;
 231
 232
 233         reg->Attribute[0x00]  = 0x00; /* standard colormap translation */
 234         reg->Attribute[0x01]  = 0x01;
 235         reg->Attribute[0x02]  = 0x02;
 236         reg->Attribute[0x03]  = 0x03;
 237         reg->Attribute[0x04]  = 0x04;
 238         reg->Attribute[0x05]  = 0x05;
 239         reg->Attribute[0x06]  = 0x06;
 240         reg->Attribute[0x07]  = 0x07;
 241         reg->Attribute[0x08]  = 0x08;
 242         reg->Attribute[0x09]  = 0x09;
 243         reg->Attribute[0x0a] = 0x0A;
 244         reg->Attribute[0x0b] = 0x0B;
 245         reg->Attribute[0x0c] = 0x0C;
 246         reg->Attribute[0x0d] = 0x0D;
 247         reg->Attribute[0x0e] = 0x0E;
 248         reg->Attribute[0x0f] = 0x0F;
 249         reg->Attribute[0x10] = 0x41;
 250         reg->Attribute[0x11] = 0xFF;
 251         reg->Attribute[0x12] = 0x0F;
 252         reg->Attribute[0x13] = 0x00;
 253         reg->Attribute[0x14] = 0x00;
 254 }
 255
 256 /* -------------------- Hardware specific routines ------------------------- */
 257
 258 /*
 259  * Hardware Acceleration for SavageFB
 260  */
 261
 262 /* Wait for fifo space */
 263 static void
 264 savage3D_waitfifo(struct savagefb_par *par, int space)
 265 {
 266         int slots = MAXFIFO - space;
 267
 268         while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
 269 }
 270
 271 static void
 272 savage4_waitfifo(struct savagefb_par *par, int space)
 273 {
 274         int slots = MAXFIFO - space;
 275
 276         while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
 277 }
 278
 279 static void
 280 savage2000_waitfifo(struct savagefb_par *par, int space)
 281 {
 282         int slots = MAXFIFO - space;
 283
 284         while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
 285 }
 286
 287 /* Wait for idle accelerator */
 288 static void
 289 savage3D_waitidle(struct savagefb_par *par)
 290 {
 291         while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
 292 }
 293
 294 static void
 295 savage4_waitidle(struct savagefb_par *par)
 296 {
 297         while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
 298 }
 299
 300 static void
 301 savage2000_waitidle(struct savagefb_par *par)
 302 {
 303         while ((savage_in32(0x48C60, par) & 0x009fffff));
 304 }
 305
 306 #ifdef CONFIG_FB_SAVAGE_ACCEL
 307 static void
 308 SavageSetup2DEngine(struct savagefb_par  *par)
 309 {
 310         unsigned long GlobalBitmapDescriptor;
 311
 312         GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
 313         BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
 314         BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
 315
 316         switch(par->chip) {
 317         case S3_SAVAGE3D:
 318         case S3_SAVAGE_MX:
 319                 /* Disable BCI */
 320                 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
 321                 /* Setup BCI command overflow buffer */
 322                 savage_out32(0x48C14,
 323                              (par->cob_offset >> 11) | (par->cob_index << 29),
 324                              par);
 325                 /* Program shadow status update. */
 326                 savage_out32(0x48C10, 0x78207220, par);
 327                 savage_out32(0x48C0C, 0, par);
 328                 /* Enable BCI and command overflow buffer */
 329                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
 330                 break;
 331         case S3_SAVAGE4:
 332         case S3_PROSAVAGE:
 333         case S3_SUPERSAVAGE:
 334                 /* Disable BCI */
 335                 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
 336                 /* Program shadow status update */
 337                 savage_out32(0x48C10, 0x00700040, par);
 338                 savage_out32(0x48C0C, 0, par);
 339                 /* Enable BCI without the COB */
 340                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
 341                 break;
 342         case S3_SAVAGE2000:
 343                 /* Disable BCI */
 344                 savage_out32(0x48C18, 0, par);
 345                 /* Setup BCI command overflow buffer */
 346                 savage_out32(0x48C18,
 347                              (par->cob_offset >> 7) | (par->cob_index),
 348                              par);
 349                 /* Disable shadow status update */
 350                 savage_out32(0x48A30, 0, par);
 351                 /* Enable BCI and command overflow buffer */
 352                 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
 353                              par);
 354                 break;
 355             default:
 356                 break;
 357         }
 358         /* Turn on 16-bit register access. */
 359         vga_out8(0x3d4, 0x31, par);
 360         vga_out8(0x3d5, 0x0c, par);
 361
 362         /* Set stride to use GBD. */
 363         vga_out8(0x3d4, 0x50, par);
 364         vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
 365
 366         /* Enable 2D engine. */
 367         vga_out8(0x3d4, 0x40, par);
 368         vga_out8(0x3d5, 0x01, par);
 369
 370         savage_out32(MONO_PAT_0, ~0, par);
 371         savage_out32(MONO_PAT_1, ~0, par);
 372
 373         /* Setup plane masks */
 374         savage_out32(0x8128, ~0, par); /* enable all write planes */
 375         savage_out32(0x812C, ~0, par); /* enable all read planes */
 376         savage_out16(0x8134, 0x27, par);
 377         savage_out16(0x8136, 0x07, par);
 378
 379         /* Now set the GBD */
 380         par->bci_ptr = 0;
 381         par->SavageWaitFifo(par, 4);
 382
 383         BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
 384         BCI_SEND(0);
 385         BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
 386         BCI_SEND(GlobalBitmapDescriptor);
 387 }
 388
 389 static void savagefb_set_clip(struct fb_info *info)
 390 {
 391         struct savagefb_par *par = info->par;
 392         int cmd;
 393
 394         cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
 395         par->bci_ptr = 0;
 396         par->SavageWaitFifo(par,3);
 397         BCI_SEND(cmd);
 398         BCI_SEND(BCI_CLIP_TL(0, 0));
 399         BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
 400 }
 401 #else
 402 static void SavageSetup2DEngine(struct savagefb_par  *par) {}
 403
 404 #endif
 405
 406 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
 407                             int min_n2, int max_n2, long freq_min,
 408                             long freq_max, unsigned int *mdiv,
 409                             unsigned int *ndiv, unsigned int *r)
 410 {
 411         long diff, best_diff;
 412         unsigned int m;
 413         unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
 414
 415         if (freq < freq_min / (1 << max_n2)) {
 416                 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
 417                 freq = freq_min / (1 << max_n2);
 418         }
 419         if (freq > freq_max / (1 << min_n2)) {
 420                 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
 421                 freq = freq_max / (1 << min_n2);
 422         }
 423
 424         /* work out suitable timings */
 425         best_diff = freq;
 426
 427         for (n2=min_n2; n2<=max_n2; n2++) {
 428                 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
 429                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 430                                 BASE_FREQ;
 431                         if (m < min_m+2 || m > 127+2)
 432                                 continue;
 433                         if ((m * BASE_FREQ >= freq_min * n1) &&
 434                             (m * BASE_FREQ <= freq_max * n1)) {
 435                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 436                                 if (diff < 0)
 437                                         diff = -diff;
 438                                 if (diff < best_diff) {
 439                                         best_diff = diff;
 440                                         best_m = m;
 441                                         best_n1 = n1;
 442                                         best_n2 = n2;
 443                                 }
 444                         }
 445                 }
 446         }
 447
 448         *ndiv = best_n1 - 2;
 449         *r = best_n2;
 450         *mdiv = best_m - 2;
 451 }
 452
 453 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
 454                              int min_n2, int max_n2, long freq_min,
 455                              long freq_max, unsigned char *mdiv,
 456                              unsigned char *ndiv)
 457 {
 458         long diff, best_diff;
 459         unsigned int m;
 460         unsigned char n1, n2;
 461         unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
 462
 463         best_diff = freq;
 464
 465         for (n2 = min_n2; n2 <= max_n2; n2++) {
 466                 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
 467                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 468                                 BASE_FREQ;
 469                         if (m < min_m + 2 || m > 127+2)
 470                                 continue;
 471                         if ((m * BASE_FREQ >= freq_min * n1) &&
 472                             (m * BASE_FREQ <= freq_max * n1)) {
 473                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 474                                 if (diff < 0)
 475                                         diff = -diff;
 476                                 if (diff < best_diff) {
 477                                         best_diff = diff;
 478                                         best_m = m;
 479                                         best_n1 = n1;
 480                                         best_n2 = n2;
 481                                 }
 482                         }
 483                 }
 484         }
 485
 486         if (max_n1 == 63)
 487                 *ndiv = (best_n1 - 2) | (best_n2 << 6);
 488         else
 489                 *ndiv = (best_n1 - 2) | (best_n2 << 5);
 490
 491         *mdiv = best_m - 2;
 492
 493         return 0;
 494 }
 495
 496 #ifdef SAVAGEFB_DEBUG
 497 /* This function is used to debug, it prints out the contents of s3 regs */
 498
 499 static void SavagePrintRegs(void)
 500 {
 501         unsigned char i;
 502         int vgaCRIndex = 0x3d4;
 503         int vgaCRReg = 0x3d5;
 504
 505         printk(KERN_DEBUG "SR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
 506                "xF");
 507
 508         for (i = 0; i < 0x70; i++) {
 509                 if (!(i % 16))
 510                         printk(KERN_DEBUG "\nSR%xx ", i >> 4);
 511                 vga_out8(0x3c4, i, par);
 512                 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
 513         }
 514
 515         printk(KERN_DEBUG "\n\nCR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
 516                "xD xE xF");
 517
 518         for (i = 0; i < 0xB7; i++) {
 519                 if (!(i % 16))
 520                         printk(KERN_DEBUG "\nCR%xx ", i >> 4);
 521                 vga_out8(vgaCRIndex, i, par);
 522                 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
 523         }
 524
 525         printk(KERN_DEBUG "\n\n");
 526 }
 527 #endif
 528
 529 /* --------------------------------------------------------------------- */
 530
 531 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
 532 {
 533         unsigned char cr3a, cr53, cr66;
 534
 535         vga_out16(0x3d4, 0x4838, par);
 536         vga_out16(0x3d4, 0xa039, par);
 537         vga_out16(0x3c4, 0x0608, par);
 538
 539         vga_out8(0x3d4, 0x66, par);
 540         cr66 = vga_in8(0x3d5, par);
 541         vga_out8(0x3d5, cr66 | 0x80, par);
 542         vga_out8(0x3d4, 0x3a, par);
 543         cr3a = vga_in8(0x3d5, par);
 544         vga_out8(0x3d5, cr3a | 0x80, par);
 545         vga_out8(0x3d4, 0x53, par);
 546         cr53 = vga_in8(0x3d5, par);
 547         vga_out8(0x3d5, cr53 & 0x7f, par);
 548
 549         vga_out8(0x3d4, 0x66, par);
 550         vga_out8(0x3d5, cr66, par);
 551         vga_out8(0x3d4, 0x3a, par);
 552         vga_out8(0x3d5, cr3a, par);
 553
 554         vga_out8(0x3d4, 0x66, par);
 555         vga_out8(0x3d5, cr66, par);
 556         vga_out8(0x3d4, 0x3a, par);
 557         vga_out8(0x3d5, cr3a, par);
 558
 559         /* unlock extended seq regs */
 560         vga_out8(0x3c4, 0x08, par);
 561         reg->SR08 = vga_in8(0x3c5, par);
 562         vga_out8(0x3c5, 0x06, par);
 563
 564         /* now save all the extended regs we need */
 565         vga_out8(0x3d4, 0x31, par);
 566         reg->CR31 = vga_in8(0x3d5, par);
 567         vga_out8(0x3d4, 0x32, par);
 568         reg->CR32 = vga_in8(0x3d5, par);
 569         vga_out8(0x3d4, 0x34, par);
 570         reg->CR34 = vga_in8(0x3d5, par);
 571         vga_out8(0x3d4, 0x36, par);
 572         reg->CR36 = vga_in8(0x3d5, par);
 573         vga_out8(0x3d4, 0x3a, par);
 574         reg->CR3A = vga_in8(0x3d5, par);
 575         vga_out8(0x3d4, 0x40, par);
 576         reg->CR40 = vga_in8(0x3d5, par);
 577         vga_out8(0x3d4, 0x42, par);
 578         reg->CR42 = vga_in8(0x3d5, par);
 579         vga_out8(0x3d4, 0x45, par);
 580         reg->CR45 = vga_in8(0x3d5, par);
 581         vga_out8(0x3d4, 0x50, par);
 582         reg->CR50 = vga_in8(0x3d5, par);
 583         vga_out8(0x3d4, 0x51, par);
 584         reg->CR51 = vga_in8(0x3d5, par);
 585         vga_out8(0x3d4, 0x53, par);
 586         reg->CR53 = vga_in8(0x3d5, par);
 587         vga_out8(0x3d4, 0x58, par);
 588         reg->CR58 = vga_in8(0x3d5, par);
 589         vga_out8(0x3d4, 0x60, par);
 590         reg->CR60 = vga_in8(0x3d5, par);
 591         vga_out8(0x3d4, 0x66, par);
 592         reg->CR66 = vga_in8(0x3d5, par);
 593         vga_out8(0x3d4, 0x67, par);
 594         reg->CR67 = vga_in8(0x3d5, par);
 595         vga_out8(0x3d4, 0x68, par);
 596         reg->CR68 = vga_in8(0x3d5, par);
 597         vga_out8(0x3d4, 0x69, par);
 598         reg->CR69 = vga_in8(0x3d5, par);
 599         vga_out8(0x3d4, 0x6f, par);
 600         reg->CR6F = vga_in8(0x3d5, par);
 601
 602         vga_out8(0x3d4, 0x33, par);
 603         reg->CR33 = vga_in8(0x3d5, par);
 604         vga_out8(0x3d4, 0x86, par);
 605         reg->CR86 = vga_in8(0x3d5, par);
 606         vga_out8(0x3d4, 0x88, par);
 607         reg->CR88 = vga_in8(0x3d5, par);
 608         vga_out8(0x3d4, 0x90, par);
 609         reg->CR90 = vga_in8(0x3d5, par);
 610         vga_out8(0x3d4, 0x91, par);
 611         reg->CR91 = vga_in8(0x3d5, par);
 612         vga_out8(0x3d4, 0xb0, par);
 613         reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
 614
 615         /* extended mode timing regs */
 616         vga_out8(0x3d4, 0x3b, par);
 617         reg->CR3B = vga_in8(0x3d5, par);
 618         vga_out8(0x3d4, 0x3c, par);
 619         reg->CR3C = vga_in8(0x3d5, par);
 620         vga_out8(0x3d4, 0x43, par);
 621         reg->CR43 = vga_in8(0x3d5, par);
 622         vga_out8(0x3d4, 0x5d, par);
 623         reg->CR5D = vga_in8(0x3d5, par);
 624         vga_out8(0x3d4, 0x5e, par);
 625         reg->CR5E = vga_in8(0x3d5, par);
 626         vga_out8(0x3d4, 0x65, par);
 627         reg->CR65 = vga_in8(0x3d5, par);
 628
 629         /* save seq extended regs for DCLK PLL programming */
 630         vga_out8(0x3c4, 0x0e, par);
 631         reg->SR0E = vga_in8(0x3c5, par);
 632         vga_out8(0x3c4, 0x0f, par);
 633         reg->SR0F = vga_in8(0x3c5, par);
 634         vga_out8(0x3c4, 0x10, par);
 635         reg->SR10 = vga_in8(0x3c5, par);
 636         vga_out8(0x3c4, 0x11, par);
 637         reg->SR11 = vga_in8(0x3c5, par);
 638         vga_out8(0x3c4, 0x12, par);
 639         reg->SR12 = vga_in8(0x3c5, par);
 640         vga_out8(0x3c4, 0x13, par);
 641         reg->SR13 = vga_in8(0x3c5, par);
 642         vga_out8(0x3c4, 0x29, par);
 643         reg->SR29 = vga_in8(0x3c5, par);
 644
 645         vga_out8(0x3c4, 0x15, par);
 646         reg->SR15 = vga_in8(0x3c5, par);
 647         vga_out8(0x3c4, 0x30, par);
 648         reg->SR30 = vga_in8(0x3c5, par);
 649         vga_out8(0x3c4, 0x18, par);
 650         reg->SR18 = vga_in8(0x3c5, par);
 651
 652         /* Save flat panel expansion regsters. */
 653         if (par->chip == S3_SAVAGE_MX) {
 654                 int i;
 655
 656                 for (i = 0; i < 8; i++) {
 657                         vga_out8(0x3c4, 0x54+i, par);
 658                         reg->SR54[i] = vga_in8(0x3c5, par);
 659                 }
 660         }
 661
 662         vga_out8(0x3d4, 0x66, par);
 663         cr66 = vga_in8(0x3d5, par);
 664         vga_out8(0x3d5, cr66 | 0x80, par);
 665         vga_out8(0x3d4, 0x3a, par);
 666         cr3a = vga_in8(0x3d5, par);
 667         vga_out8(0x3d5, cr3a | 0x80, par);
 668
 669         /* now save MIU regs */
 670         if (par->chip != S3_SAVAGE_MX) {
 671                 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
 672                 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
 673                 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
 674                 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
 675         }
 676
 677         vga_out8(0x3d4, 0x3a, par);
 678         vga_out8(0x3d5, cr3a, par);
 679         vga_out8(0x3d4, 0x66, par);
 680         vga_out8(0x3d5, cr66, par);
 681 }
 682
 683 static void savage_set_default_par(struct savagefb_par *par,
 684                                 struct savage_reg *reg)
 685 {
 686         unsigned char cr3a, cr53, cr66;
 687
 688         vga_out16(0x3d4, 0x4838, par);
 689         vga_out16(0x3d4, 0xa039, par);
 690         vga_out16(0x3c4, 0x0608, par);
 691
 692         vga_out8(0x3d4, 0x66, par);
 693         cr66 = vga_in8(0x3d5, par);
 694         vga_out8(0x3d5, cr66 | 0x80, par);
 695         vga_out8(0x3d4, 0x3a, par);
 696         cr3a = vga_in8(0x3d5, par);
 697         vga_out8(0x3d5, cr3a | 0x80, par);
 698         vga_out8(0x3d4, 0x53, par);
 699         cr53 = vga_in8(0x3d5, par);
 700         vga_out8(0x3d5, cr53 & 0x7f, par);
 701
 702         vga_out8(0x3d4, 0x66, par);
 703         vga_out8(0x3d5, cr66, par);
 704         vga_out8(0x3d4, 0x3a, par);
 705         vga_out8(0x3d5, cr3a, par);
 706
 707         vga_out8(0x3d4, 0x66, par);
 708         vga_out8(0x3d5, cr66, par);
 709         vga_out8(0x3d4, 0x3a, par);
 710         vga_out8(0x3d5, cr3a, par);
 711
 712         /* unlock extended seq regs */
 713         vga_out8(0x3c4, 0x08, par);
 714         vga_out8(0x3c5, reg->SR08, par);
 715         vga_out8(0x3c5, 0x06, par);
 716
 717         /* now restore all the extended regs we need */
 718         vga_out8(0x3d4, 0x31, par);
 719         vga_out8(0x3d5, reg->CR31, par);
 720         vga_out8(0x3d4, 0x32, par);
 721         vga_out8(0x3d5, reg->CR32, par);
 722         vga_out8(0x3d4, 0x34, par);
 723         vga_out8(0x3d5, reg->CR34, par);
 724         vga_out8(0x3d4, 0x36, par);
 725         vga_out8(0x3d5,reg->CR36, par);
 726         vga_out8(0x3d4, 0x3a, par);
 727         vga_out8(0x3d5, reg->CR3A, par);
 728         vga_out8(0x3d4, 0x40, par);
 729         vga_out8(0x3d5, reg->CR40, par);
 730         vga_out8(0x3d4, 0x42, par);
 731         vga_out8(0x3d5, reg->CR42, par);
 732         vga_out8(0x3d4, 0x45, par);
 733         vga_out8(0x3d5, reg->CR45, par);
 734         vga_out8(0x3d4, 0x50, par);
 735         vga_out8(0x3d5, reg->CR50, par);
 736         vga_out8(0x3d4, 0x51, par);
 737         vga_out8(0x3d5, reg->CR51, par);
 738         vga_out8(0x3d4, 0x53, par);
 739         vga_out8(0x3d5, reg->CR53, par);
 740         vga_out8(0x3d4, 0x58, par);
 741         vga_out8(0x3d5, reg->CR58, par);
 742         vga_out8(0x3d4, 0x60, par);
 743         vga_out8(0x3d5, reg->CR60, par);
 744         vga_out8(0x3d4, 0x66, par);
 745         vga_out8(0x3d5, reg->CR66, par);
 746         vga_out8(0x3d4, 0x67, par);
 747         vga_out8(0x3d5, reg->CR67, par);
 748         vga_out8(0x3d4, 0x68, par);
 749         vga_out8(0x3d5, reg->CR68, par);
 750         vga_out8(0x3d4, 0x69, par);
 751         vga_out8(0x3d5, reg->CR69, par);
 752         vga_out8(0x3d4, 0x6f, par);
 753         vga_out8(0x3d5, reg->CR6F, par);
 754
 755         vga_out8(0x3d4, 0x33, par);
 756         vga_out8(0x3d5, reg->CR33, par);
 757         vga_out8(0x3d4, 0x86, par);
 758         vga_out8(0x3d5, reg->CR86, par);
 759         vga_out8(0x3d4, 0x88, par);
 760         vga_out8(0x3d5, reg->CR88, par);
 761         vga_out8(0x3d4, 0x90, par);
 762         vga_out8(0x3d5, reg->CR90, par);
 763         vga_out8(0x3d4, 0x91, par);
 764         vga_out8(0x3d5, reg->CR91, par);
 765         vga_out8(0x3d4, 0xb0, par);
 766         vga_out8(0x3d5, reg->CRB0, par);
 767
 768         /* extended mode timing regs */
 769         vga_out8(0x3d4, 0x3b, par);
 770         vga_out8(0x3d5, reg->CR3B, par);
 771         vga_out8(0x3d4, 0x3c, par);
 772         vga_out8(0x3d5, reg->CR3C, par);
 773         vga_out8(0x3d4, 0x43, par);
 774         vga_out8(0x3d5, reg->CR43, par);
 775         vga_out8(0x3d4, 0x5d, par);
 776         vga_out8(0x3d5, reg->CR5D, par);
 777         vga_out8(0x3d4, 0x5e, par);
 778         vga_out8(0x3d5, reg->CR5E, par);
 779         vga_out8(0x3d4, 0x65, par);
 780         vga_out8(0x3d5, reg->CR65, par);
 781
 782         /* save seq extended regs for DCLK PLL programming */
 783         vga_out8(0x3c4, 0x0e, par);
 784         vga_out8(0x3c5, reg->SR0E, par);
 785         vga_out8(0x3c4, 0x0f, par);
 786         vga_out8(0x3c5, reg->SR0F, par);
 787         vga_out8(0x3c4, 0x10, par);
 788         vga_out8(0x3c5, reg->SR10, par);
 789         vga_out8(0x3c4, 0x11, par);
 790         vga_out8(0x3c5, reg->SR11, par);
 791         vga_out8(0x3c4, 0x12, par);
 792         vga_out8(0x3c5, reg->SR12, par);
 793         vga_out8(0x3c4, 0x13, par);
 794         vga_out8(0x3c5, reg->SR13, par);
 795         vga_out8(0x3c4, 0x29, par);
 796         vga_out8(0x3c5, reg->SR29, par);
 797
 798         vga_out8(0x3c4, 0x15, par);
 799         vga_out8(0x3c5, reg->SR15, par);
 800         vga_out8(0x3c4, 0x30, par);
 801         vga_out8(0x3c5, reg->SR30, par);
 802         vga_out8(0x3c4, 0x18, par);
 803         vga_out8(0x3c5, reg->SR18, par);
 804
 805         /* Save flat panel expansion regsters. */
 806         if (par->chip == S3_SAVAGE_MX) {
 807                 int i;
 808
 809                 for (i = 0; i < 8; i++) {
 810                         vga_out8(0x3c4, 0x54+i, par);
 811                         vga_out8(0x3c5, reg->SR54[i], par);
 812                 }
 813         }
 814
 815         vga_out8(0x3d4, 0x66, par);
 816         cr66 = vga_in8(0x3d5, par);
 817         vga_out8(0x3d5, cr66 | 0x80, par);
 818         vga_out8(0x3d4, 0x3a, par);
 819         cr3a = vga_in8(0x3d5, par);
 820         vga_out8(0x3d5, cr3a | 0x80, par);
 821
 822         /* now save MIU regs */
 823         if (par->chip != S3_SAVAGE_MX) {
 824                 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
 825                 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
 826                 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
 827                 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
 828         }
 829
 830         vga_out8(0x3d4, 0x3a, par);
 831         vga_out8(0x3d5, cr3a, par);
 832         vga_out8(0x3d4, 0x66, par);
 833         vga_out8(0x3d5, cr66, par);
 834 }
 835
 836 static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
 837 {
 838         var->xres = var->xres_virtual = modedb->xres;
 839         var->yres = modedb->yres;
 840         if (var->yres_virtual < var->yres)
 841             var->yres_virtual = var->yres;
 842         var->xoffset = var->yoffset = 0;
 843         var->pixclock = modedb->pixclock;
 844         var->left_margin = modedb->left_margin;
 845         var->right_margin = modedb->right_margin;
 846         var->upper_margin = modedb->upper_margin;
 847         var->lower_margin = modedb->lower_margin;
 848         var->hsync_len = modedb->hsync_len;
 849         var->vsync_len = modedb->vsync_len;
 850         var->sync = modedb->sync;
 851         var->vmode = modedb->vmode;
 852 }
 853
 854 static int savagefb_check_var(struct fb_var_screeninfo   *var,
 855                               struct fb_info *info)
 856 {
 857         struct savagefb_par *par = info->par;
 858         int memlen, vramlen, mode_valid = 0;
 859
 860         DBG("savagefb_check_var");
 861
 862         var->transp.offset = 0;
 863         var->transp.length = 0;
 864         switch (var->bits_per_pixel) {
 865         case 8:
 866                 var->red.offset = var->green.offset =
 867                         var->blue.offset = 0;
 868                 var->red.length = var->green.length =
 869                         var->blue.length = var->bits_per_pixel;
 870                 break;
 871         case 16:
 872                 var->red.offset = 11;
 873                 var->red.length = 5;
 874                 var->green.offset = 5;
 875                 var->green.length = 6;
 876                 var->blue.offset = 0;
 877                 var->blue.length = 5;
 878                 break;
 879         case 32:
 880                 var->transp.offset = 24;
 881                 var->transp.length = 8;
 882                 var->red.offset = 16;
 883                 var->red.length = 8;
 884                 var->green.offset = 8;
 885                 var->green.length = 8;
 886                 var->blue.offset = 0;
 887                 var->blue.length = 8;
 888                 break;
 889
 890         default:
 891                 return -EINVAL;
 892         }
 893
 894         if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 895             !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 896                 mode_valid = 1;
 897
 898         /* calculate modeline if supported by monitor */
 899         if (!mode_valid && info->monspecs.gtf) {
 900                 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 901                         mode_valid = 1;
 902         }
 903
 904         if (!mode_valid) {
 905                 struct fb_videomode *mode;
 906
 907                 mode = fb_find_best_mode(var, &info->modelist);
 908                 if (mode) {
 909                         savage_update_var(var, mode);
 910                         mode_valid = 1;
 911                 }
 912         }
 913
 914         if (!mode_valid && info->monspecs.modedb_len)
 915                 return -EINVAL;
 916
 917         /* Is the mode larger than the LCD panel? */
 918         if (par->SavagePanelWidth &&
 919             (var->xres > par->SavagePanelWidth ||
 920              var->yres > par->SavagePanelHeight)) {
 921                 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
 922                        "(%dx%d)\n", var->xres,  var->yres,
 923                        par->SavagePanelWidth,
 924                        par->SavagePanelHeight);
 925                 return -1;
 926         }
 927
 928         if (var->yres_virtual < var->yres)
 929                 var->yres_virtual = var->yres;
 930         if (var->xres_virtual < var->xres)
 931                 var->xres_virtual = var->xres;
 932
 933         vramlen = info->fix.smem_len;
 934
 935         memlen = var->xres_virtual * var->bits_per_pixel *
 936                 var->yres_virtual / 8;
 937         if (memlen > vramlen) {
 938                 var->yres_virtual = vramlen * 8 /
 939                         (var->xres_virtual * var->bits_per_pixel);
 940                 memlen = var->xres_virtual * var->bits_per_pixel *
 941                         var->yres_virtual / 8;
 942         }
 943
 944         /* we must round yres/xres down, we already rounded y/xres_virtual up
 945            if it was possible. We should return -EINVAL, but I disagree */
 946         if (var->yres_virtual < var->yres)
 947                 var->yres = var->yres_virtual;
 948         if (var->xres_virtual < var->xres)
 949                 var->xres = var->xres_virtual;
 950         if (var->xoffset + var->xres > var->xres_virtual)
 951                 var->xoffset = var->xres_virtual - var->xres;
 952         if (var->yoffset + var->yres > var->yres_virtual)
 953                 var->yoffset = var->yres_virtual - var->yres;
 954
 955         return 0;
 956 }
 957
 958
 959 static int savagefb_decode_var(struct fb_var_screeninfo   *var,
 960                                struct savagefb_par        *par,
 961                                struct savage_reg          *reg)
 962 {
 963         struct xtimings timings;
 964         int width, dclk, i, j; /*, refresh; */
 965         unsigned int m, n, r;
 966         unsigned char tmp = 0;
 967         unsigned int pixclock = var->pixclock;
 968
 969         DBG("savagefb_decode_var");
 970
 971         memset(&timings, 0, sizeof(timings));
 972
 973         if (!pixclock) pixclock = 10000;        /* 10ns = 100MHz */
 974         timings.Clock = 1000000000 / pixclock;
 975         if (timings.Clock < 1) timings.Clock = 1;
 976         timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
 977         timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
 978         timings.HDisplay = var->xres;
 979         timings.HSyncStart = timings.HDisplay + var->right_margin;
 980         timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
 981         timings.HTotal = timings.HSyncEnd + var->left_margin;
 982         timings.VDisplay = var->yres;
 983         timings.VSyncStart = timings.VDisplay + var->lower_margin;
 984         timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
 985         timings.VTotal = timings.VSyncEnd + var->upper_margin;
 986         timings.sync = var->sync;
 987
 988
 989         par->depth  = var->bits_per_pixel;
 990         par->vwidth = var->xres_virtual;
 991
 992         if (var->bits_per_pixel == 16  &&  par->chip == S3_SAVAGE3D) {
 993                 timings.HDisplay *= 2;
 994                 timings.HSyncStart *= 2;
 995                 timings.HSyncEnd *= 2;
 996                 timings.HTotal *= 2;
 997         }
 998
 999         /*
1000          * This will allocate the datastructure and initialize all of the
1001          * generic VGA registers.
1002          */
1003         vgaHWInit(var, par, &timings, reg);
1004
1005         /* We need to set CR67 whether or not we use the BIOS. */
1006
1007         dclk = timings.Clock;
1008         reg->CR67 = 0x00;
1009
1010         switch(var->bits_per_pixel) {
1011         case 8:
1012                 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1013                         reg->CR67 = 0x10;       /* 8bpp, 2 pixels/clock */
1014                 else
1015                         reg->CR67 = 0x00;       /* 8bpp, 1 pixel/clock */
1016                 break;
1017         case 15:
1018                 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1019                     ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1020                         reg->CR67 = 0x30;       /* 15bpp, 2 pixel/clock */
1021                 else
1022                         reg->CR67 = 0x20;       /* 15bpp, 1 pixels/clock */
1023                 break;
1024         case 16:
1025                 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1026                    ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1027                         reg->CR67 = 0x50;       /* 16bpp, 2 pixel/clock */
1028                 else
1029                         reg->CR67 = 0x40;       /* 16bpp, 1 pixels/clock */
1030                 break;
1031         case 24:
1032                 reg->CR67 = 0x70;
1033                 break;
1034         case 32:
1035                 reg->CR67 = 0xd0;
1036                 break;
1037         }
1038
1039         /*
1040          * Either BIOS use is disabled, or we failed to find a suitable
1041          * match.  Fall back to traditional register-crunching.
1042          */
1043
1044         vga_out8(0x3d4, 0x3a, par);
1045         tmp = vga_in8(0x3d5, par);
1046         if (1 /*FIXME:psav->pci_burst*/)
1047                 reg->CR3A = (tmp & 0x7f) | 0x15;
1048         else
1049                 reg->CR3A = tmp | 0x95;
1050
1051         reg->CR53 = 0x00;
1052         reg->CR31 = 0x8c;
1053         reg->CR66 = 0x89;
1054
1055         vga_out8(0x3d4, 0x58, par);
1056         reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1057         reg->CR58 |= 0x13;
1058
1059         reg->SR15 = 0x03 | 0x80;
1060         reg->SR18 = 0x00;
1061         reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1062
1063         vga_out8(0x3d4, 0x40, par);
1064         reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1065
1066         reg->MMPR0 = 0x010400;
1067         reg->MMPR1 = 0x00;
1068         reg->MMPR2 = 0x0808;
1069         reg->MMPR3 = 0x08080810;
1070
1071         SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1072         /* m = 107; n = 4; r = 2; */
1073
1074         if (par->MCLK <= 0) {
1075                 reg->SR10 = 255;
1076                 reg->SR11 = 255;
1077         } else {
1078                 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1079                                    &reg->SR11, &reg->SR10);
1080                 /*      reg->SR10 = 80; // MCLK == 286000 */
1081                 /*      reg->SR11 = 125; */
1082         }
1083
1084         reg->SR12 = (r << 6) | (n & 0x3f);
1085         reg->SR13 = m & 0xff;
1086         reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1087
1088         if (var->bits_per_pixel < 24)
1089                 reg->MMPR0 -= 0x8000;
1090         else
1091                 reg->MMPR0 -= 0x4000;
1092
1093         if (timings.interlaced)
1094                 reg->CR42 = 0x20;
1095         else
1096                 reg->CR42 = 0x00;
1097
1098         reg->CR34 = 0x10; /* display fifo */
1099
1100         i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1101                 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1102                 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1103                 ((timings.HSyncStart & 0x800) >> 7);
1104
1105         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1106                 i |= 0x08;
1107         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1108                 i |= 0x20;
1109
1110         j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1111              reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1112
1113         if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1114                 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1115                     reg->CRTC[0] + ((i & 0x01) << 8))
1116                         j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1117                 else
1118                         j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1119         }
1120
1121         reg->CR3B = j & 0xff;
1122         i |= (j & 0x100) >> 2;
1123         reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1124         reg->CR5D = i;
1125         reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1126                 (((timings.VDisplay - 1) & 0x400) >> 9) |
1127                 (((timings.VSyncStart) & 0x400) >> 8) |
1128                 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1129         width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1130         reg->CR91 = reg->CRTC[19] = 0xff & width;
1131         reg->CR51 = (0x300 & width) >> 4;
1132         reg->CR90 = 0x80 | (width >> 8);
1133         reg->MiscOutReg |= 0x0c;
1134
1135         /* Set frame buffer description. */
1136
1137         if (var->bits_per_pixel <= 8)
1138                 reg->CR50 = 0;
1139         else if (var->bits_per_pixel <= 16)
1140                 reg->CR50 = 0x10;
1141         else
1142                 reg->CR50 = 0x30;
1143
1144         if (var->xres_virtual <= 640)
1145                 reg->CR50 |= 0x40;
1146         else if (var->xres_virtual == 800)
1147                 reg->CR50 |= 0x80;
1148         else if (var->xres_virtual == 1024)
1149                 reg->CR50 |= 0x00;
1150         else if (var->xres_virtual == 1152)
1151                 reg->CR50 |= 0x01;
1152         else if (var->xres_virtual == 1280)
1153                 reg->CR50 |= 0xc0;
1154         else if (var->xres_virtual == 1600)
1155                 reg->CR50 |= 0x81;
1156         else
1157                 reg->CR50 |= 0xc1;      /* Use GBD */
1158
1159         if (par->chip == S3_SAVAGE2000)
1160                 reg->CR33 = 0x08;
1161         else
1162                 reg->CR33 = 0x20;
1163
1164         reg->CRTC[0x17] = 0xeb;
1165
1166         reg->CR67 |= 1;
1167
1168         vga_out8(0x3d4, 0x36, par);
1169         reg->CR36 = vga_in8(0x3d5, par);
1170         vga_out8(0x3d4, 0x68, par);
1171         reg->CR68 = vga_in8(0x3d5, par);
1172         reg->CR69 = 0;
1173         vga_out8(0x3d4, 0x6f, par);
1174         reg->CR6F = vga_in8(0x3d5, par);
1175         vga_out8(0x3d4, 0x86, par);
1176         reg->CR86 = vga_in8(0x3d5, par);
1177         vga_out8(0x3d4, 0x88, par);
1178         reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1179         vga_out8(0x3d4, 0xb0, par);
1180         reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1181
1182         return 0;
1183 }
1184
1185 /* --------------------------------------------------------------------- */
1186
1187 /*
1188  *    Set a single color register. Return != 0 for invalid regno.
1189  */
1190 static int savagefb_setcolreg(unsigned        regno,
1191                               unsigned        red,
1192                               unsigned        green,
1193                               unsigned        blue,
1194                               unsigned        transp,
1195                               struct fb_info *info)
1196 {
1197         struct savagefb_par *par = info->par;
1198
1199         if (regno >= NR_PALETTE)
1200                 return -EINVAL;
1201
1202         par->palette[regno].red    = red;
1203         par->palette[regno].green  = green;
1204         par->palette[regno].blue   = blue;
1205         par->palette[regno].transp = transp;
1206
1207         switch (info->var.bits_per_pixel) {
1208         case 8:
1209                 vga_out8(0x3c8, regno, par);
1210
1211                 vga_out8(0x3c9, red   >> 10, par);
1212                 vga_out8(0x3c9, green >> 10, par);
1213                 vga_out8(0x3c9, blue  >> 10, par);
1214                 break;
1215
1216         case 16:
1217                 if (regno < 16)
1218                         ((u32 *)info->pseudo_palette)[regno] =
1219                                 ((red   & 0xf800)      ) |
1220                                 ((green & 0xfc00) >>  5) |
1221                                 ((blue  & 0xf800) >> 11);
1222                 break;
1223
1224         case 24:
1225                 if (regno < 16)
1226                         ((u32 *)info->pseudo_palette)[regno] =
1227                                 ((red    & 0xff00) <<  8) |
1228                                 ((green  & 0xff00)      ) |
1229                                 ((blue   & 0xff00) >>  8);
1230                 break;
1231         case 32:
1232                 if (regno < 16)
1233                         ((u32 *)info->pseudo_palette)[regno] =
1234                                 ((transp & 0xff00) << 16) |
1235                                 ((red    & 0xff00) <<  8) |
1236                                 ((green  & 0xff00)      ) |
1237                                 ((blue   & 0xff00) >>  8);
1238                 break;
1239
1240         default:
1241                 return 1;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static void savagefb_set_par_int(struct savagefb_par  *par, struct savage_reg *reg)
1248 {
1249         unsigned char tmp, cr3a, cr66, cr67;
1250
1251         DBG("savagefb_set_par_int");
1252
1253         par->SavageWaitIdle(par);
1254
1255         vga_out8(0x3c2, 0x23, par);
1256
1257         vga_out16(0x3d4, 0x4838, par);
1258         vga_out16(0x3d4, 0xa539, par);
1259         vga_out16(0x3c4, 0x0608, par);
1260
1261         vgaHWProtect(par, 1);
1262
1263         /*
1264          * Some Savage/MX and /IX systems go nuts when trying to exit the
1265          * server after WindowMaker has displayed a gradient background.  I
1266          * haven't been able to find what causes it, but a non-destructive
1267          * switch to mode 3 here seems to eliminate the issue.
1268          */
1269
1270         VerticalRetraceWait(par);
1271         vga_out8(0x3d4, 0x67, par);
1272         cr67 = vga_in8(0x3d5, par);
1273         vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1274
1275         vga_out8(0x3d4, 0x23, par);
1276         vga_out8(0x3d5, 0x00, par);
1277         vga_out8(0x3d4, 0x26, par);
1278         vga_out8(0x3d5, 0x00, par);
1279
1280         /* restore extended regs */
1281         vga_out8(0x3d4, 0x66, par);
1282         vga_out8(0x3d5, reg->CR66, par);
1283         vga_out8(0x3d4, 0x3a, par);
1284         vga_out8(0x3d5, reg->CR3A, par);
1285         vga_out8(0x3d4, 0x31, par);
1286         vga_out8(0x3d5, reg->CR31, par);
1287         vga_out8(0x3d4, 0x32, par);
1288         vga_out8(0x3d5, reg->CR32, par);
1289         vga_out8(0x3d4, 0x58, par);
1290         vga_out8(0x3d5, reg->CR58, par);
1291         vga_out8(0x3d4, 0x53, par);
1292         vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1293
1294         vga_out16(0x3c4, 0x0608, par);
1295
1296         /* Restore DCLK registers. */
1297
1298         vga_out8(0x3c4, 0x0e, par);
1299         vga_out8(0x3c5, reg->SR0E, par);
1300         vga_out8(0x3c4, 0x0f, par);
1301         vga_out8(0x3c5, reg->SR0F, par);
1302         vga_out8(0x3c4, 0x29, par);
1303         vga_out8(0x3c5, reg->SR29, par);
1304         vga_out8(0x3c4, 0x15, par);
1305         vga_out8(0x3c5, reg->SR15, par);
1306
1307         /* Restore flat panel expansion regsters. */
1308         if (par->chip == S3_SAVAGE_MX) {
1309                 int i;
1310
1311                 for (i = 0; i < 8; i++) {
1312                         vga_out8(0x3c4, 0x54+i, par);
1313                         vga_out8(0x3c5, reg->SR54[i], par);
1314                 }
1315         }
1316
1317         vgaHWRestore (par, reg);
1318
1319         /* extended mode timing registers */
1320         vga_out8(0x3d4, 0x53, par);
1321         vga_out8(0x3d5, reg->CR53, par);
1322         vga_out8(0x3d4, 0x5d, par);
1323         vga_out8(0x3d5, reg->CR5D, par);
1324         vga_out8(0x3d4, 0x5e, par);
1325         vga_out8(0x3d5, reg->CR5E, par);
1326         vga_out8(0x3d4, 0x3b, par);
1327         vga_out8(0x3d5, reg->CR3B, par);
1328         vga_out8(0x3d4, 0x3c, par);
1329         vga_out8(0x3d5, reg->CR3C, par);
1330         vga_out8(0x3d4, 0x43, par);
1331         vga_out8(0x3d5, reg->CR43, par);
1332         vga_out8(0x3d4, 0x65, par);
1333         vga_out8(0x3d5, reg->CR65, par);
1334
1335         /* restore the desired video mode with cr67 */
1336         vga_out8(0x3d4, 0x67, par);
1337         /* following part not present in X11 driver */
1338         cr67 = vga_in8(0x3d5, par) & 0xf;
1339         vga_out8(0x3d5, 0x50 | cr67, par);
1340         udelay(10000);
1341         vga_out8(0x3d4, 0x67, par);
1342         /* end of part */
1343         vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1344
1345         /* other mode timing and extended regs */
1346         vga_out8(0x3d4, 0x34, par);
1347         vga_out8(0x3d5, reg->CR34, par);
1348         vga_out8(0x3d4, 0x40, par);
1349         vga_out8(0x3d5, reg->CR40, par);
1350         vga_out8(0x3d4, 0x42, par);
1351         vga_out8(0x3d5, reg->CR42, par);
1352         vga_out8(0x3d4, 0x45, par);
1353         vga_out8(0x3d5, reg->CR45, par);
1354         vga_out8(0x3d4, 0x50, par);
1355         vga_out8(0x3d5, reg->CR50, par);
1356         vga_out8(0x3d4, 0x51, par);
1357         vga_out8(0x3d5, reg->CR51, par);
1358
1359         /* memory timings */
1360         vga_out8(0x3d4, 0x36, par);
1361         vga_out8(0x3d5, reg->CR36, par);
1362         vga_out8(0x3d4, 0x60, par);
1363         vga_out8(0x3d5, reg->CR60, par);
1364         vga_out8(0x3d4, 0x68, par);
1365         vga_out8(0x3d5, reg->CR68, par);
1366         vga_out8(0x3d4, 0x69, par);
1367         vga_out8(0x3d5, reg->CR69, par);
1368         vga_out8(0x3d4, 0x6f, par);
1369         vga_out8(0x3d5, reg->CR6F, par);
1370
1371         vga_out8(0x3d4, 0x33, par);
1372         vga_out8(0x3d5, reg->CR33, par);
1373         vga_out8(0x3d4, 0x86, par);
1374         vga_out8(0x3d5, reg->CR86, par);
1375         vga_out8(0x3d4, 0x88, par);
1376         vga_out8(0x3d5, reg->CR88, par);
1377         vga_out8(0x3d4, 0x90, par);
1378         vga_out8(0x3d5, reg->CR90, par);
1379         vga_out8(0x3d4, 0x91, par);
1380         vga_out8(0x3d5, reg->CR91, par);
1381
1382         if (par->chip == S3_SAVAGE4) {
1383                 vga_out8(0x3d4, 0xb0, par);
1384                 vga_out8(0x3d5, reg->CRB0, par);
1385         }
1386
1387         vga_out8(0x3d4, 0x32, par);
1388         vga_out8(0x3d5, reg->CR32, par);
1389
1390         /* unlock extended seq regs */
1391         vga_out8(0x3c4, 0x08, par);
1392         vga_out8(0x3c5, 0x06, par);
1393
1394         /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1395          * that we should leave the default SR10 and SR11 values there.
1396          */
1397         if (reg->SR10 != 255) {
1398                 vga_out8(0x3c4, 0x10, par);
1399                 vga_out8(0x3c5, reg->SR10, par);
1400                 vga_out8(0x3c4, 0x11, par);
1401                 vga_out8(0x3c5, reg->SR11, par);
1402         }
1403
1404         /* restore extended seq regs for dclk */
1405         vga_out8(0x3c4, 0x0e, par);
1406         vga_out8(0x3c5, reg->SR0E, par);
1407         vga_out8(0x3c4, 0x0f, par);
1408         vga_out8(0x3c5, reg->SR0F, par);
1409         vga_out8(0x3c4, 0x12, par);
1410         vga_out8(0x3c5, reg->SR12, par);
1411         vga_out8(0x3c4, 0x13, par);
1412         vga_out8(0x3c5, reg->SR13, par);
1413         vga_out8(0x3c4, 0x29, par);
1414         vga_out8(0x3c5, reg->SR29, par);
1415         vga_out8(0x3c4, 0x18, par);
1416         vga_out8(0x3c5, reg->SR18, par);
1417
1418         /* load new m, n pll values for dclk & mclk */
1419         vga_out8(0x3c4, 0x15, par);
1420         tmp = vga_in8(0x3c5, par) & ~0x21;
1421
1422         vga_out8(0x3c5, tmp | 0x03, par);
1423         vga_out8(0x3c5, tmp | 0x23, par);
1424         vga_out8(0x3c5, tmp | 0x03, par);
1425         vga_out8(0x3c5, reg->SR15, par);
1426         udelay(100);
1427
1428         vga_out8(0x3c4, 0x30, par);
1429         vga_out8(0x3c5, reg->SR30, par);
1430         vga_out8(0x3c4, 0x08, par);
1431         vga_out8(0x3c5, reg->SR08, par);
1432
1433         /* now write out cr67 in full, possibly starting STREAMS */
1434         VerticalRetraceWait(par);
1435         vga_out8(0x3d4, 0x67, par);
1436         vga_out8(0x3d5, reg->CR67, par);
1437
1438         vga_out8(0x3d4, 0x66, par);
1439         cr66 = vga_in8(0x3d5, par);
1440         vga_out8(0x3d5, cr66 | 0x80, par);
1441         vga_out8(0x3d4, 0x3a, par);
1442         cr3a = vga_in8(0x3d5, par);
1443         vga_out8(0x3d5, cr3a | 0x80, par);
1444
1445         if (par->chip != S3_SAVAGE_MX) {
1446                 VerticalRetraceWait(par);
1447                 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1448                 par->SavageWaitIdle(par);
1449                 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1450                 par->SavageWaitIdle(par);
1451                 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1452                 par->SavageWaitIdle(par);
1453                 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1454         }
1455
1456         vga_out8(0x3d4, 0x66, par);
1457         vga_out8(0x3d5, cr66, par);
1458         vga_out8(0x3d4, 0x3a, par);
1459         vga_out8(0x3d5, cr3a, par);
1460
1461         SavageSetup2DEngine(par);
1462         vgaHWProtect(par, 0);
1463 }
1464
1465 static void savagefb_update_start(struct savagefb_par      *par,
1466                                   struct fb_var_screeninfo *var)
1467 {
1468         int base;
1469
1470         base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
1471                 * ((var->bits_per_pixel+7) / 8)) >> 2;
1472
1473         /* now program the start address registers */
1474         vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1475         vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1476         vga_out8(0x3d4, 0x69, par);
1477         vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1478 }
1479
1480
1481 static void savagefb_set_fix(struct fb_info *info)
1482 {
1483         info->fix.line_length = info->var.xres_virtual *
1484                 info->var.bits_per_pixel / 8;
1485
1486         if (info->var.bits_per_pixel == 8) {
1487                 info->fix.visual      = FB_VISUAL_PSEUDOCOLOR;
1488                 info->fix.xpanstep    = 4;
1489         } else {
1490                 info->fix.visual      = FB_VISUAL_TRUECOLOR;
1491                 info->fix.xpanstep    = 2;
1492         }
1493
1494 }
1495
1496 static int savagefb_set_par(struct fb_info *info)
1497 {
1498         struct savagefb_par *par = info->par;
1499         struct fb_var_screeninfo *var = &info->var;
1500         int err;
1501
1502         DBG("savagefb_set_par");
1503         err = savagefb_decode_var(var, par, &par->state);
1504         if (err)
1505                 return err;
1506
1507         if (par->dacSpeedBpp <= 0) {
1508                 if (var->bits_per_pixel > 24)
1509                         par->dacSpeedBpp = par->clock[3];
1510                 else if (var->bits_per_pixel >= 24)
1511                         par->dacSpeedBpp = par->clock[2];
1512                 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1513                         par->dacSpeedBpp = par->clock[1];
1514                 else if (var->bits_per_pixel <= 8)
1515                         par->dacSpeedBpp = par->clock[0];
1516         }
1517
1518         /* Set ramdac limits */
1519         par->maxClock = par->dacSpeedBpp;
1520         par->minClock = 10000;
1521
1522         savagefb_set_par_int(par, &par->state);
1523         fb_set_cmap(&info->cmap, info);
1524         savagefb_set_fix(info);
1525         savagefb_set_clip(info);
1526
1527         SavagePrintRegs();
1528         return 0;
1529 }
1530
1531 /*
1532  *    Pan or Wrap the Display
1533  */
1534 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1535                                 struct fb_info           *info)
1536 {
1537         struct savagefb_par *par = info->par;
1538
1539         savagefb_update_start(par, var);
1540         return 0;
1541 }
1542
1543 static int savagefb_blank(int blank, struct fb_info *info)
1544 {
1545         struct savagefb_par *par = info->par;
1546         u8 sr8 = 0, srd = 0;
1547
1548         if (par->display_type == DISP_CRT) {
1549                 vga_out8(0x3c4, 0x08, par);
1550                 sr8 = vga_in8(0x3c5, par);
1551                 sr8 |= 0x06;
1552                 vga_out8(0x3c5, sr8, par);
1553                 vga_out8(0x3c4, 0x0d, par);
1554                 srd = vga_in8(0x3c5, par);
1555                 srd &= 0x03;
1556
1557                 switch (blank) {
1558                 case FB_BLANK_UNBLANK:
1559                 case FB_BLANK_NORMAL:
1560                         break;
1561                 case FB_BLANK_VSYNC_SUSPEND:
1562                         srd |= 0x10;
1563                         break;
1564                 case FB_BLANK_HSYNC_SUSPEND:
1565                         srd |= 0x40;
1566                         break;
1567                 case FB_BLANK_POWERDOWN:
1568                         srd |= 0x50;
1569                         break;
1570                 }
1571
1572                 vga_out8(0x3c4, 0x0d, par);
1573                 vga_out8(0x3c5, srd, par);
1574         }
1575
1576         if (par->display_type == DISP_LCD ||
1577             par->display_type == DISP_DFP) {
1578                 switch(blank) {
1579                 case FB_BLANK_UNBLANK:
1580                 case FB_BLANK_NORMAL:
1581                         vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1582                         vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1583                         break;
1584                 case FB_BLANK_VSYNC_SUSPEND:
1585                 case FB_BLANK_HSYNC_SUSPEND:
1586                 case FB_BLANK_POWERDOWN:
1587                         vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1588                         vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1589                         break;
1590                 }
1591         }
1592
1593         return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1594 }
1595
1596 static void savagefb_save_state(struct fb_info *info)
1597 {
1598         struct savagefb_par *par = info->par;
1599
1600         savage_get_default_par(par, &par->save);
1601 }
1602
1603 static void savagefb_restore_state(struct fb_info *info)
1604 {
1605         struct savagefb_par *par = info->par;
1606
1607         savagefb_blank(FB_BLANK_POWERDOWN, info);
1608         savage_set_default_par(par, &par->save);
1609         savagefb_blank(FB_BLANK_UNBLANK, info);
1610 }
1611
1612 static struct fb_ops savagefb_ops = {
1613         .owner          = THIS_MODULE,
1614         .fb_check_var   = savagefb_check_var,
1615         .fb_set_par     = savagefb_set_par,
1616         .fb_setcolreg   = savagefb_setcolreg,
1617         .fb_pan_display = savagefb_pan_display,
1618         .fb_blank       = savagefb_blank,
1619         .fb_save_state  = savagefb_save_state,
1620         .fb_restore_state = savagefb_restore_state,
1621 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1622         .fb_fillrect    = savagefb_fillrect,
1623         .fb_copyarea    = savagefb_copyarea,
1624         .fb_imageblit   = savagefb_imageblit,
1625         .fb_sync        = savagefb_sync,
1626 #else
1627         .fb_fillrect    = cfb_fillrect,
1628         .fb_copyarea    = cfb_copyarea,
1629         .fb_imageblit   = cfb_imageblit,
1630 #endif
1631 };
1632
1633 /* --------------------------------------------------------------------- */
1634
1635 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1636         .accel_flags =  FB_ACCELF_TEXT,
1637         .xres =         800,
1638         .yres =         600,
1639         .xres_virtual =  800,
1640         .yres_virtual =  600,
1641         .bits_per_pixel = 8,
1642         .pixclock =     25000,
1643         .left_margin =  88,
1644         .right_margin = 40,
1645         .upper_margin = 23,
1646         .lower_margin = 1,
1647         .hsync_len =    128,
1648         .vsync_len =    4,
1649         .sync =         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1650         .vmode =        FB_VMODE_NONINTERLACED
1651 };
1652
1653 static void savage_enable_mmio(struct savagefb_par *par)
1654 {
1655         unsigned char val;
1656
1657         DBG("savage_enable_mmio\n");
1658
1659         val = vga_in8(0x3c3, par);
1660         vga_out8(0x3c3, val | 0x01, par);
1661         val = vga_in8(0x3cc, par);
1662         vga_out8(0x3c2, val | 0x01, par);
1663
1664         if (par->chip >= S3_SAVAGE4) {
1665                 vga_out8(0x3d4, 0x40, par);
1666                 val = vga_in8(0x3d5, par);
1667                 vga_out8(0x3d5, val | 1, par);
1668         }
1669 }
1670
1671
1672 static void savage_disable_mmio(struct savagefb_par *par)
1673 {
1674         unsigned char val;
1675
1676         DBG("savage_disable_mmio\n");
1677
1678         if (par->chip >= S3_SAVAGE4) {
1679                 vga_out8(0x3d4, 0x40, par);
1680                 val = vga_in8(0x3d5, par);
1681                 vga_out8(0x3d5, val | 1, par);
1682         }
1683 }
1684
1685
1686 static int __devinit savage_map_mmio(struct fb_info *info)
1687 {
1688         struct savagefb_par *par = info->par;
1689         DBG("savage_map_mmio");
1690
1691         if (S3_SAVAGE3D_SERIES(par->chip))
1692                 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1693                         SAVAGE_NEWMMIO_REGBASE_S3;
1694         else
1695                 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1696                         SAVAGE_NEWMMIO_REGBASE_S4;
1697
1698         par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1699
1700         par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1701         if (!par->mmio.vbase) {
1702                 printk("savagefb: unable to map memory mapped IO\n");
1703                 return -ENOMEM;
1704         } else
1705                 printk(KERN_INFO "savagefb: mapped io at %p\n",
1706                         par->mmio.vbase);
1707
1708         info->fix.mmio_start = par->mmio.pbase;
1709         info->fix.mmio_len   = par->mmio.len;
1710
1711         par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1712         par->bci_ptr  = 0;
1713
1714         savage_enable_mmio(par);
1715
1716         return 0;
1717 }
1718
1719 static void savage_unmap_mmio(struct fb_info *info)
1720 {
1721         struct savagefb_par *par = info->par;
1722         DBG("savage_unmap_mmio");
1723
1724         savage_disable_mmio(par);
1725
1726         if (par->mmio.vbase) {
1727                 iounmap(par->mmio.vbase);
1728                 par->mmio.vbase = NULL;
1729         }
1730 }
1731
1732 static int __devinit savage_map_video(struct fb_info *info,
1733                                       int video_len)
1734 {
1735         struct savagefb_par *par = info->par;
1736         int resource;
1737
1738         DBG("savage_map_video");
1739
1740         if (S3_SAVAGE3D_SERIES(par->chip))
1741                 resource = 0;
1742         else
1743                 resource = 1;
1744
1745         par->video.pbase = pci_resource_start(par->pcidev, resource);
1746         par->video.len   = video_len;
1747         par->video.vbase = ioremap(par->video.pbase, par->video.len);
1748
1749         if (!par->video.vbase) {
1750                 printk("savagefb: unable to map screen memory\n");
1751                 return -ENOMEM;
1752         } else
1753                 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1754                        "pbase == %x\n", par->video.vbase, par->video.pbase);
1755
1756         info->fix.smem_start = par->video.pbase;
1757         info->fix.smem_len   = par->video.len - par->cob_size;
1758         info->screen_base    = par->video.vbase;
1759
1760 #ifdef CONFIG_MTRR
1761         par->video.mtrr = mtrr_add(par->video.pbase, video_len,
1762                                    MTRR_TYPE_WRCOMB, 1);
1763 #endif
1764
1765         /* Clear framebuffer, it's all white in memory after boot */
1766         memset_io(par->video.vbase, 0, par->video.len);
1767
1768         return 0;
1769 }
1770
1771 static void savage_unmap_video(struct fb_info *info)
1772 {
1773         struct savagefb_par *par = info->par;
1774
1775         DBG("savage_unmap_video");
1776
1777         if (par->video.vbase) {
1778 #ifdef CONFIG_MTRR
1779                 mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
1780 #endif
1781
1782                 iounmap(par->video.vbase);
1783                 par->video.vbase = NULL;
1784                 info->screen_base = NULL;
1785         }
1786 }
1787
1788 static int savage_init_hw(struct savagefb_par *par)
1789 {
1790         unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1791
1792         static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1793         static unsigned char RamSavage4[] =  { 2, 4, 8, 12, 16, 32, 64, 32 };
1794         static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1795         static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1796         int videoRam, videoRambytes, dvi;
1797
1798         DBG("savage_init_hw");
1799
1800         /* unprotect CRTC[0-7] */
1801         vga_out8(0x3d4, 0x11, par);
1802         tmp = vga_in8(0x3d5, par);
1803         vga_out8(0x3d5, tmp & 0x7f, par);
1804
1805         /* unlock extended regs */
1806         vga_out16(0x3d4, 0x4838, par);
1807         vga_out16(0x3d4, 0xa039, par);
1808         vga_out16(0x3c4, 0x0608, par);
1809
1810         vga_out8(0x3d4, 0x40, par);
1811         tmp = vga_in8(0x3d5, par);
1812         vga_out8(0x3d5, tmp & ~0x01, par);
1813
1814         /* unlock sys regs */
1815         vga_out8(0x3d4, 0x38, par);
1816         vga_out8(0x3d5, 0x48, par);
1817
1818         /* Unlock system registers. */
1819         vga_out16(0x3d4, 0x4838, par);
1820
1821         /* Next go on to detect amount of installed ram */
1822
1823         vga_out8(0x3d4, 0x36, par);            /* for register CR36 (CONFG_REG1), */
1824         config1 = vga_in8(0x3d5, par);    /* get amount of vram installed */
1825
1826         /* Compute the amount of video memory and offscreen memory. */
1827
1828         switch  (par->chip) {
1829         case S3_SAVAGE3D:
1830                 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1831                 break;
1832
1833         case S3_SAVAGE4:
1834                 /*
1835                  * The Savage4 has one ugly special case to consider.  On
1836                  * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1837                  * when it really means 8MB.  Why do it the same when you
1838                  * can do it different...
1839                  */
1840                 vga_out8(0x3d4, 0x68, par);     /* memory control 1 */
1841                 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1842                         RamSavage4[1] = 8;
1843
1844                 /*FALLTHROUGH*/
1845
1846         case S3_SAVAGE2000:
1847                 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1848                 break;
1849
1850         case S3_SAVAGE_MX:
1851         case S3_SUPERSAVAGE:
1852                 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1853                 break;
1854
1855         case S3_PROSAVAGE:
1856                 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1857                 break;
1858
1859         default:
1860                 /* How did we get here? */
1861                 videoRam = 0;
1862                 break;
1863         }
1864
1865         videoRambytes = videoRam * 1024;
1866
1867         printk(KERN_INFO "savagefb: probed videoram:  %dk\n", videoRam);
1868
1869         /* reset graphics engine to avoid memory corruption */
1870         vga_out8(0x3d4, 0x66, par);
1871         cr66 = vga_in8(0x3d5, par);
1872         vga_out8(0x3d5, cr66 | 0x02, par);
1873         udelay(10000);
1874
1875         vga_out8(0x3d4, 0x66, par);
1876         vga_out8(0x3d5, cr66 & ~0x02, par);     /* clear reset flag */
1877         udelay(10000);
1878
1879
1880         /*
1881          * reset memory interface, 3D engine, AGP master, PCI master,
1882          * master engine unit, motion compensation/LPB
1883          */
1884         vga_out8(0x3d4, 0x3f, par);
1885         cr3f = vga_in8(0x3d5, par);
1886         vga_out8(0x3d5, cr3f | 0x08, par);
1887         udelay(10000);
1888
1889         vga_out8(0x3d4, 0x3f, par);
1890         vga_out8(0x3d5, cr3f & ~0x08, par);     /* clear reset flags */
1891         udelay(10000);
1892
1893         /* Savage ramdac speeds */
1894         par->numClocks = 4;
1895         par->clock[0] = 250000;
1896         par->clock[1] = 250000;
1897         par->clock[2] = 220000;
1898         par->clock[3] = 220000;
1899
1900         /* detect current mclk */
1901         vga_out8(0x3c4, 0x08, par);
1902         sr8 = vga_in8(0x3c5, par);
1903         vga_out8(0x3c5, 0x06, par);
1904         vga_out8(0x3c4, 0x10, par);
1905         n = vga_in8(0x3c5, par);
1906         vga_out8(0x3c4, 0x11, par);
1907         m = vga_in8(0x3c5, par);
1908         vga_out8(0x3c4, 0x08, par);
1909         vga_out8(0x3c5, sr8, par);
1910         m &= 0x7f;
1911         n1 = n & 0x1f;
1912         n2 = (n >> 5) & 0x03;
1913         par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1914         printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1915                 par->MCLK);
1916
1917         /* check for DVI/flat panel */
1918         dvi = 0;
1919
1920         if (par->chip == S3_SAVAGE4) {
1921                 unsigned char sr30 = 0x00;
1922
1923                 vga_out8(0x3c4, 0x30, par);
1924                 /* clear bit 1 */
1925                 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1926                 sr30 = vga_in8(0x3c5, par);
1927                 if (sr30 & 0x02 /*0x04 */) {
1928                         dvi = 1;
1929                         printk("savagefb: Digital Flat Panel Detected\n");
1930                 }
1931         }
1932
1933         if (S3_SAVAGE_MOBILE_SERIES(par->chip) && !par->crtonly)
1934                 par->display_type = DISP_LCD;
1935         else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1936                 par->display_type = DISP_DFP;
1937         else
1938                 par->display_type = DISP_CRT;
1939
1940         /* Check LCD panel parrmation */
1941
1942         if (par->display_type == DISP_LCD) {
1943                 unsigned char cr6b = VGArCR(0x6b, par);
1944
1945                 int panelX = (VGArSEQ(0x61, par) +
1946                               ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1947                 int panelY = (VGArSEQ(0x69, par) +
1948                               ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1949
1950                 char * sTechnology = "Unknown";
1951
1952                 /* OK, I admit it.  I don't know how to limit the max dot clock
1953                  * for LCD panels of various sizes.  I thought I copied the
1954                  * formula from the BIOS, but many users have parrmed me of
1955                  * my folly.
1956                  *
1957                  * Instead, I'll abandon any attempt to automatically limit the
1958                  * clock, and add an LCDClock option to XF86Config.  Some day,
1959                  * I should come back to this.
1960                  */
1961
1962                 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1963                         ActiveCRT = 0x01,
1964                         ActiveLCD = 0x02,
1965                         ActiveTV = 0x04,
1966                         ActiveCRT2 = 0x20,
1967                         ActiveDUO = 0x80
1968                 };
1969
1970                 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1971                         sTechnology = "TFT";
1972                 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
1973                         sTechnology = "DSTN";
1974                 } else  {
1975                         sTechnology = "STN";
1976                 }
1977
1978                 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
1979                        panelX, panelY, sTechnology,
1980                        cr6b & ActiveLCD ? "and active" : "but not active");
1981
1982                 if (cr6b & ActiveLCD)   {
1983                         /*
1984                          * If the LCD is active and panel expansion is enabled,
1985                          * we probably want to kill the HW cursor.
1986                          */
1987
1988                         printk(KERN_INFO "savagefb: Limiting video mode to "
1989                                 "%dx%d\n", panelX, panelY);
1990
1991                         par->SavagePanelWidth = panelX;
1992                         par->SavagePanelHeight = panelY;
1993
1994                 } else
1995                         par->display_type = DISP_CRT;
1996         }
1997
1998         savage_get_default_par(par, &par->state);
1999         par->save = par->state;
2000
2001         if (S3_SAVAGE4_SERIES(par->chip)) {
2002                 /*
2003                  * The Savage4 and ProSavage have COB coherency bugs which
2004                  * render the buffer useless.  We disable it.
2005                  */
2006                 par->cob_index = 2;
2007                 par->cob_size = 0x8000 << par->cob_index;
2008                 par->cob_offset = videoRambytes;
2009         } else {
2010                 /* We use 128kB for the COB on all chips. */
2011
2012                 par->cob_index  = 7;
2013                 par->cob_size   = 0x400 << par->cob_index;
2014                 par->cob_offset = videoRambytes - par->cob_size;
2015         }
2016
2017         return videoRambytes;
2018 }
2019
2020 static int __devinit savage_init_fb_info(struct fb_info *info,
2021                                          struct pci_dev *dev,
2022                                          const struct pci_device_id *id)
2023 {
2024         struct savagefb_par *par = info->par;
2025         int err = 0;
2026
2027         par->pcidev  = dev;
2028
2029         info->fix.type     = FB_TYPE_PACKED_PIXELS;
2030         info->fix.type_aux         = 0;
2031         info->fix.ypanstep         = 1;
2032         info->fix.ywrapstep   = 0;
2033         info->fix.accel       = id->driver_data;
2034
2035         switch (info->fix.accel) {
2036         case FB_ACCEL_SUPERSAVAGE:
2037                 par->chip = S3_SUPERSAVAGE;
2038                 snprintf(info->fix.id, 16, "SuperSavage");
2039                 break;
2040         case FB_ACCEL_SAVAGE4:
2041                 par->chip = S3_SAVAGE4;
2042                 snprintf(info->fix.id, 16, "Savage4");
2043                 break;
2044         case FB_ACCEL_SAVAGE3D:
2045                 par->chip = S3_SAVAGE3D;
2046                 snprintf(info->fix.id, 16, "Savage3D");
2047                 break;
2048         case FB_ACCEL_SAVAGE3D_MV:
2049                 par->chip = S3_SAVAGE3D;
2050                 snprintf(info->fix.id, 16, "Savage3D-MV");
2051                 break;
2052         case FB_ACCEL_SAVAGE2000:
2053                 par->chip = S3_SAVAGE2000;
2054                 snprintf(info->fix.id, 16, "Savage2000");
2055                 break;
2056         case FB_ACCEL_SAVAGE_MX_MV:
2057                 par->chip = S3_SAVAGE_MX;
2058                 snprintf(info->fix.id, 16, "Savage/MX-MV");
2059                 break;
2060         case FB_ACCEL_SAVAGE_MX:
2061                 par->chip = S3_SAVAGE_MX;
2062                 snprintf(info->fix.id, 16, "Savage/MX");
2063                 break;
2064         case FB_ACCEL_SAVAGE_IX_MV:
2065                 par->chip = S3_SAVAGE_MX;
2066                 snprintf(info->fix.id, 16, "Savage/IX-MV");
2067                 break;
2068         case FB_ACCEL_SAVAGE_IX:
2069                 par->chip = S3_SAVAGE_MX;
2070                 snprintf(info->fix.id, 16, "Savage/IX");
2071                 break;
2072         case FB_ACCEL_PROSAVAGE_PM:
2073                 par->chip = S3_PROSAVAGE;
2074                 snprintf(info->fix.id, 16, "ProSavagePM");
2075                 break;
2076         case FB_ACCEL_PROSAVAGE_KM:
2077                 par->chip = S3_PROSAVAGE;
2078                 snprintf(info->fix.id, 16, "ProSavageKM");
2079                 break;
2080         case FB_ACCEL_S3TWISTER_P:
2081                 par->chip = S3_PROSAVAGE;
2082                 snprintf(info->fix.id, 16, "TwisterP");
2083                 break;
2084         case FB_ACCEL_S3TWISTER_K:
2085                 par->chip = S3_PROSAVAGE;
2086                 snprintf(info->fix.id, 16, "TwisterK");
2087                 break;
2088         case FB_ACCEL_PROSAVAGE_DDR:
2089                 par->chip = S3_PROSAVAGE;
2090                 snprintf(info->fix.id, 16, "ProSavageDDR");
2091                 break;
2092         case FB_ACCEL_PROSAVAGE_DDRK:
2093                 par->chip = S3_PROSAVAGE;
2094                 snprintf(info->fix.id, 16, "ProSavage8");
2095                 break;
2096         }
2097
2098         if (S3_SAVAGE3D_SERIES(par->chip)) {
2099                 par->SavageWaitIdle = savage3D_waitidle;
2100                 par->SavageWaitFifo = savage3D_waitfifo;
2101         } else if (S3_SAVAGE4_SERIES(par->chip) ||
2102                    S3_SUPERSAVAGE == par->chip) {
2103                 par->SavageWaitIdle = savage4_waitidle;
2104                 par->SavageWaitFifo = savage4_waitfifo;
2105         } else {
2106                 par->SavageWaitIdle = savage2000_waitidle;
2107                 par->SavageWaitFifo = savage2000_waitfifo;
2108         }
2109
2110         info->var.nonstd      = 0;
2111         info->var.activate    = FB_ACTIVATE_NOW;
2112         info->var.width       = -1;
2113         info->var.height      = -1;
2114         info->var.accel_flags = 0;
2115
2116         info->fbops          = &savagefb_ops;
2117         info->flags          = FBINFO_DEFAULT |
2118                                FBINFO_HWACCEL_YPAN |
2119                                FBINFO_HWACCEL_XPAN;
2120
2121         info->pseudo_palette = par->pseudo_palette;
2122
2123 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2124         /* FIFO size + padding for commands */
2125         info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL);
2126
2127         err = -ENOMEM;
2128         if (info->pixmap.addr) {
2129                 memset(info->pixmap.addr, 0, 8*1024);
2130                 info->pixmap.size = 8*1024;
2131                 info->pixmap.scan_align = 4;
2132                 info->pixmap.buf_align = 4;
2133                 info->pixmap.access_align = 32;
2134
2135                 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2136                 if (!err)
2137                 info->flags |= FBINFO_HWACCEL_COPYAREA |
2138                                FBINFO_HWACCEL_FILLRECT |
2139                                FBINFO_HWACCEL_IMAGEBLIT;
2140         }
2141 #endif
2142         return err;
2143 }
2144
2145 /* --------------------------------------------------------------------- */
2146
2147 static int __devinit savagefb_probe(struct pci_dev* dev,
2148                                     const struct pci_device_id* id)
2149 {
2150         struct fb_info *info;
2151         struct savagefb_par *par;
2152         u_int h_sync, v_sync;
2153         int err, lpitch;
2154         int video_len;
2155
2156         DBG("savagefb_probe");
2157         SavagePrintRegs();
2158
2159         info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2160         if (!info)
2161                 return -ENOMEM;
2162         par = info->par;
2163         err = pci_enable_device(dev);
2164         if (err)
2165                 goto failed_enable;
2166
2167         if ((err = pci_request_regions(dev, "savagefb"))) {
2168                 printk(KERN_ERR "cannot request PCI regions\n");
2169                 goto failed_enable;
2170         }
2171
2172         err = -ENOMEM;
2173
2174         if ((err = savage_init_fb_info(info, dev, id)))
2175                 goto failed_init;
2176
2177         err = savage_map_mmio(info);
2178         if (err)
2179                 goto failed_mmio;
2180
2181         video_len = savage_init_hw(par);
2182         /* FIXME: cant be negative */
2183         if (video_len < 0) {
2184                 err = video_len;
2185                 goto failed_mmio;
2186         }
2187
2188         err = savage_map_video(info, video_len);
2189         if (err)
2190                 goto failed_video;
2191
2192         INIT_LIST_HEAD(&info->modelist);
2193 #if defined(CONFIG_FB_SAVAGE_I2C)
2194         savagefb_create_i2c_busses(info);
2195         savagefb_probe_i2c_connector(info, &par->edid);
2196         fb_edid_to_monspecs(par->edid, &info->monspecs);
2197         kfree(par->edid);
2198         fb_videomode_to_modelist(info->monspecs.modedb,
2199                                  info->monspecs.modedb_len,
2200                                  &info->modelist);
2201 #endif
2202         info->var = savagefb_var800x600x8;
2203
2204         if (mode_option) {
2205                 fb_find_mode(&info->var, info, mode_option,
2206                              info->monspecs.modedb, info->monspecs.modedb_len,
2207                              NULL, 8);
2208         } else if (info->monspecs.modedb != NULL) {
2209                 struct fb_videomode *modedb;
2210
2211                 modedb = fb_find_best_display(&info->monspecs,
2212                                               &info->modelist);
2213                 savage_update_var(&info->var, modedb);
2214         }
2215
2216         /* maximize virtual vertical length */
2217         lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2218         info->var.yres_virtual = info->fix.smem_len/lpitch;
2219
2220         if (info->var.yres_virtual < info->var.yres)
2221                 goto failed;
2222
2223 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2224         /*
2225          * The clipping coordinates are masked with 0xFFF, so limit our
2226          * virtual resolutions to these sizes.
2227          */
2228         if (info->var.yres_virtual > 0x1000)
2229                 info->var.yres_virtual = 0x1000;
2230
2231         if (info->var.xres_virtual > 0x1000)
2232                 info->var.xres_virtual = 0x1000;
2233 #endif
2234         savagefb_check_var(&info->var, info);
2235         savagefb_set_fix(info);
2236
2237         /*
2238          * Calculate the hsync and vsync frequencies.  Note that
2239          * we split the 1e12 constant up so that we can preserve
2240          * the precision and fit the results into 32-bit registers.
2241          *  (1953125000 * 512 = 1e12)
2242          */
2243         h_sync = 1953125000 / info->var.pixclock;
2244         h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2245                                  info->var.right_margin +
2246                                  info->var.hsync_len);
2247         v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2248                            info->var.lower_margin + info->var.vsync_len);
2249
2250         printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2251                "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2252                info->fix.smem_len >> 10,
2253                info->var.xres, info->var.yres,
2254                h_sync / 1000, h_sync % 1000, v_sync);
2255
2256
2257         fb_destroy_modedb(info->monspecs.modedb);
2258         info->monspecs.modedb = NULL;
2259
2260         err = register_framebuffer(info);
2261         if (err < 0)
2262                 goto failed;
2263
2264         printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2265                info->fix.id);
2266
2267         /*
2268          * Our driver data
2269          */
2270         pci_set_drvdata(dev, info);
2271
2272         return 0;
2273
2274  failed:
2275 #ifdef CONFIG_FB_SAVAGE_I2C
2276         savagefb_delete_i2c_busses(info);
2277 #endif
2278         fb_alloc_cmap(&info->cmap, 0, 0);
2279         savage_unmap_video(info);
2280  failed_video:
2281         savage_unmap_mmio(info);
2282  failed_mmio:
2283         kfree(info->pixmap.addr);
2284  failed_init:
2285         pci_release_regions(dev);
2286  failed_enable:
2287         framebuffer_release(info);
2288
2289         return err;
2290 }
2291
2292 static void __devexit savagefb_remove(struct pci_dev *dev)
2293 {
2294         struct fb_info *info = pci_get_drvdata(dev);
2295
2296         DBG("savagefb_remove");
2297
2298         if (info) {
2299                 /*
2300                  * If unregister_framebuffer fails, then
2301                  * we will be leaving hooks that could cause
2302                  * oopsen laying around.
2303                  */
2304                 if (unregister_framebuffer(info))
2305                         printk(KERN_WARNING "savagefb: danger danger! "
2306                                "Oopsen imminent!\n");
2307
2308 #ifdef CONFIG_FB_SAVAGE_I2C
2309                 savagefb_delete_i2c_busses(info);
2310 #endif
2311                 fb_alloc_cmap(&info->cmap, 0, 0);
2312                 savage_unmap_video(info);
2313                 savage_unmap_mmio(info);
2314                 kfree(info->pixmap.addr);
2315                 pci_release_regions(dev);
2316                 framebuffer_release(info);
2317
2318                 /*
2319                  * Ensure that the driver data is no longer
2320                  * valid.
2321                  */
2322                 pci_set_drvdata(dev, NULL);
2323         }
2324 }
2325
2326 static int savagefb_suspend(struct pci_dev* dev, pm_message_t state)
2327 {
2328         struct fb_info *info = pci_get_drvdata(dev);
2329         struct savagefb_par *par = info->par;
2330
2331         DBG("savagefb_suspend");
2332
2333
2334         par->pm_state = state.event;
2335
2336         /*
2337          * For PM_EVENT_FREEZE, do not power down so the console
2338          * can remain active.
2339          */
2340         if (state.event == PM_EVENT_FREEZE) {
2341                 dev->dev.power.power_state = state;
2342                 return 0;
2343         }
2344
2345         acquire_console_sem();
2346         fb_set_suspend(info, 1);
2347
2348         if (info->fbops->fb_sync)
2349                 info->fbops->fb_sync(info);
2350
2351         savagefb_blank(FB_BLANK_POWERDOWN, info);
2352         savage_set_default_par(par, &par->save);
2353         savage_disable_mmio(par);
2354         pci_save_state(dev);
2355         pci_disable_device(dev);
2356         pci_set_power_state(dev, pci_choose_state(dev, state));
2357         release_console_sem();
2358
2359         return 0;
2360 }
2361
2362 static int savagefb_resume(struct pci_dev* dev)
2363 {
2364         struct fb_info *info = pci_get_drvdata(dev);
2365         struct savagefb_par *par = info->par;
2366         int cur_state = par->pm_state;
2367
2368         DBG("savage_resume");
2369
2370         par->pm_state = PM_EVENT_ON;
2371
2372         /*
2373          * The adapter was not powered down coming back from a
2374          * PM_EVENT_FREEZE.
2375          */
2376         if (cur_state == PM_EVENT_FREEZE) {
2377                 pci_set_power_state(dev, PCI_D0);
2378                 return 0;
2379         }
2380
2381         acquire_console_sem();
2382
2383         pci_set_power_state(dev, PCI_D0);
2384         pci_restore_state(dev);
2385
2386         if (pci_enable_device(dev))
2387                 DBG("err");
2388
2389         pci_set_master(dev);
2390         savage_enable_mmio(par);
2391         savage_init_hw(par);
2392         savagefb_set_par(info);
2393         fb_set_suspend(info, 0);
2394         savagefb_blank(FB_BLANK_UNBLANK, info);
2395         release_console_sem();
2396
2397         return 0;
2398 }
2399
2400
2401 static struct pci_device_id savagefb_devices[] __devinitdata = {
2402         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2403          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2404
2405         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2406          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2407
2408         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2409          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2410
2411         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2412          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2413
2414         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2415          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2416
2417         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2418          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2419
2420         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2421          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2422
2423         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2424          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2425
2426         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2427          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2428
2429         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2430          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2431
2432         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2433          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2434
2435         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2436          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2437
2438         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2439          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2440
2441         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2442          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2443
2444         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2445          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2446
2447         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2448          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2449
2450         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2451          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2452
2453         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2454          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2455
2456         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2457          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2458
2459         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2460          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2461
2462         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2463          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2464
2465         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2466          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2467
2468         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2469          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2470
2471         {0, 0, 0, 0, 0, 0, 0}
2472 };
2473
2474 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2475
2476 static struct pci_driver savagefb_driver = {
2477         .name =     "savagefb",
2478         .id_table = savagefb_devices,
2479         .probe =    savagefb_probe,
2480         .suspend =  savagefb_suspend,
2481         .resume =   savagefb_resume,
2482         .remove =   __devexit_p(savagefb_remove)
2483 };
2484
2485 /* **************************** exit-time only **************************** */
2486
2487 static void __exit savage_done(void)
2488 {
2489         DBG("savage_done");
2490         pci_unregister_driver(&savagefb_driver);
2491 }
2492
2493
2494 /* ************************* init in-kernel code ************************** */
2495
2496 static int __init savagefb_setup(char *options)
2497 {
2498 #ifndef MODULE
2499         char *this_opt;
2500
2501         if (!options || !*options)
2502                 return 0;
2503
2504         while ((this_opt = strsep(&options, ",")) != NULL) {
2505                 mode_option = this_opt;
2506         }
2507 #endif /* !MODULE */
2508         return 0;
2509 }
2510
2511 static int __init savagefb_init(void)
2512 {
2513         char *option;
2514
2515         DBG("savagefb_init");
2516
2517         if (fb_get_options("savagefb", &option))
2518                 return -ENODEV;
2519
2520         savagefb_setup(option);
2521         return pci_register_driver(&savagefb_driver);
2522
2523 }
2524
2525 module_init(savagefb_init);
2526 module_exit(savage_done);
2527
2528 module_param(mode_option, charp, 0);
2529 MODULE_PARM_DESC(mode_option, "Specify initial video mode");