Merge with http://kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6] / arch / ppc / syslib / ibm44x_common.c
1 /*
2  * arch/ppc/syslib/ibm44x_common.c
3  *
4  * PPC44x system library
5  *
6  * Matt Porter <mporter@kernel.crashing.org>
7  * Copyright 2002-2005 MontaVista Software Inc.
8  *
9  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10  * Copyright (c) 2003, 2004 Zultys Technologies
11  *
12  * This program is free software; you can redistribute  it and/or modify it
13  * under  the terms of  the GNU General  Public License as published by the
14  * Free Software Foundation;  either version 2 of the  License, or (at your
15  * option) any later version.
16  *
17  */
18 #include <linux/config.h>
19 #include <linux/time.h>
20 #include <linux/types.h>
21 #include <linux/serial.h>
22 #include <linux/module.h>
23 #include <linux/initrd.h>
24
25 #include <asm/ibm44x.h>
26 #include <asm/mmu.h>
27 #include <asm/machdep.h>
28 #include <asm/time.h>
29 #include <asm/ppc4xx_pic.h>
30 #include <asm/param.h>
31 #include <asm/bootinfo.h>
32 #include <asm/ppcboot.h>
33
34 #include <syslib/gen550.h>
35
36 /* Global Variables */
37 bd_t __res;
38
39 phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
40 {
41         phys_addr_t page_4gb = 0;
42
43         /*
44          * Trap the least significant 32-bit portions of an
45          * address in the 440's 36-bit address space.  Fix
46          * them up with the appropriate ERPN
47          */
48         if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
49                 page_4gb = PPC44x_IO_PAGE;
50         else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
51                 page_4gb = PPC44x_PCICFG_PAGE;
52 #ifdef CONFIG_440SP
53         else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
54                 page_4gb = PPC44x_PCICFG_PAGE;
55         else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
56                 page_4gb = PPC44x_PCICFG_PAGE;
57 #endif
58         else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
59                 page_4gb = PPC44x_PCIMEM_PAGE;
60
61         return (page_4gb | addr);
62 };
63 EXPORT_SYMBOL(fixup_bigphys_addr);
64
65 void __init ibm44x_calibrate_decr(unsigned int freq)
66 {
67         tb_ticks_per_jiffy = freq / HZ;
68         tb_to_us = mulhwu_scale_factor(freq, 1000000);
69
70         /* Set the time base to zero */
71         mtspr(SPRN_TBWL, 0);
72         mtspr(SPRN_TBWU, 0);
73
74         /* Clear any pending timer interrupts */
75         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
76
77         /* Enable decrementer interrupt */
78         mtspr(SPRN_TCR, TCR_DIE);
79 }
80
81 extern void abort(void);
82
83 static void ibm44x_restart(char *cmd)
84 {
85         local_irq_disable();
86         abort();
87 }
88
89 static void ibm44x_power_off(void)
90 {
91         local_irq_disable();
92         for(;;);
93 }
94
95 static void ibm44x_halt(void)
96 {
97         local_irq_disable();
98         for(;;);
99 }
100
101 /*
102  * Read the 44x memory controller to get size of system memory.
103  */
104 static unsigned long __init ibm44x_find_end_of_memory(void)
105 {
106         u32 i, bank_config;
107         u32 mem_size = 0;
108
109         for (i=0; i<4; i++)
110         {
111                 switch (i)
112                 {
113                         case 0:
114                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
115                                 break;
116                         case 1:
117                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
118                                 break;
119                         case 2:
120                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
121                                 break;
122                         case 3:
123                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
124                                 break;
125                 }
126
127                 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
128
129                 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
130                         continue;
131                 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
132                 {
133                         case SDRAM_CONFIG_SIZE_8M:
134                                 mem_size += PPC44x_MEM_SIZE_8M;
135                                 break;
136                         case SDRAM_CONFIG_SIZE_16M:
137                                 mem_size += PPC44x_MEM_SIZE_16M;
138                                 break;
139                         case SDRAM_CONFIG_SIZE_32M:
140                                 mem_size += PPC44x_MEM_SIZE_32M;
141                                 break;
142                         case SDRAM_CONFIG_SIZE_64M:
143                                 mem_size += PPC44x_MEM_SIZE_64M;
144                                 break;
145                         case SDRAM_CONFIG_SIZE_128M:
146                                 mem_size += PPC44x_MEM_SIZE_128M;
147                                 break;
148                         case SDRAM_CONFIG_SIZE_256M:
149                                 mem_size += PPC44x_MEM_SIZE_256M;
150                                 break;
151                         case SDRAM_CONFIG_SIZE_512M:
152                                 mem_size += PPC44x_MEM_SIZE_512M;
153                                 break;
154                 }
155         }
156         return mem_size;
157 }
158
159 void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
160                                  unsigned long r6, unsigned long r7)
161 {
162         parse_bootinfo(find_bootinfo());
163
164         /*
165          * If we were passed in a board information, copy it into the
166          * residual data area.
167          */
168         if (r3)
169                 __res = *(bd_t *)(r3 + KERNELBASE);
170
171 #if defined(CONFIG_BLK_DEV_INITRD)
172         /*
173          * If the init RAM disk has been configured in, and there's a valid
174          * starting address for it, set it up.
175          */
176         if (r4) {
177                 initrd_start = r4 + KERNELBASE;
178                 initrd_end = r5 + KERNELBASE;
179         }
180 #endif  /* CONFIG_BLK_DEV_INITRD */
181
182         /* Copy the kernel command line arguments to a safe place. */
183
184         if (r6) {
185                 *(char *) (r7 + KERNELBASE) = 0;
186                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
187         }
188
189         ppc_md.init_IRQ = ppc4xx_pic_init;
190         ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
191         ppc_md.restart = ibm44x_restart;
192         ppc_md.power_off = ibm44x_power_off;
193         ppc_md.halt = ibm44x_halt;
194
195 #ifdef CONFIG_SERIAL_TEXT_DEBUG
196         ppc_md.progress = gen550_progress;
197 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
198 #ifdef CONFIG_KGDB
199         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
200 #endif
201
202         /*
203          * The Abatron BDI JTAG debugger does not tolerate others
204          * mucking with the debug registers.
205          */
206 #if !defined(CONFIG_BDI_SWITCH)
207         /* Enable internal debug mode */
208         mtspr(SPRN_DBCR0, (DBCR0_IDM));
209
210         /* Clear any residual debug events */
211         mtspr(SPRN_DBSR, 0xffffffff);
212 #endif
213 }
214
215 /* Called from machine_check_exception */
216 void platform_machine_check(struct pt_regs *regs)
217 {
218 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
219         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
220                mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
221                mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
222                mfdcr(DCRN_PLB0_BESRL));
223         printk("PLB1: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
224                mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
225                mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
226                mfdcr(DCRN_PLB1_BESRL));
227 #else
228         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x\n",
229                 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
230                 mfdcr(DCRN_PLB0_ACR),  mfdcr(DCRN_PLB0_BESR));
231 #endif
232         printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
233                 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
234                 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
235         printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n",
236                 mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL),
237                 mfdcr(DCRN_OPB0_BSTAT));
238 }