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   1 /*******************************************************************************
   2 *
   3 *      "swarm_cs4297a.c" --  Cirrus Logic-Crystal CS4297a linux audio driver.
   4 *
   5 *      Copyright (C) 2001  Broadcom Corporation.
   6 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   7 *            -- adapted from drivers by Thomas Sailer,
   8 *            -- but don't bug him; Problems should go to:
   9 *            -- tom woller (twoller@crystal.cirrus.com) or
  10 *               (audio@crystal.cirrus.com).
  11 *            -- adapted from cs4281 PCI driver for cs4297a on
  12 *               BCM1250 Synchronous Serial interface
  13 *               (Kip Walker, Broadcom Corp.)
  14 *      Copyright (C) 2004  Maciej W. Rozycki
  15 *      Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  16 *
  17 *      This program is free software; you can redistribute it and/or modify
  18 *      it under the terms of the GNU General Public License as published by
  19 *      the Free Software Foundation; either version 2 of the License, or
  20 *      (at your option) any later version.
  21 *
  22 *      This program is distributed in the hope that it will be useful,
  23 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 *      GNU General Public License for more details.
  26 *
  27 *      You should have received a copy of the GNU General Public License
  28 *      along with this program; if not, write to the Free Software
  29 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 * Module command line parameters:
  32 *   none
  33 *
  34 *  Supported devices:
  35 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  36 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  37 *  /dev/midi   simple MIDI UART interface, no ioctl
  38 *
  39 * Modification History
  40 * 08/20/00 trw - silence and no stopping DAC until release
  41 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  42 * 09/18/00 trw - added 16bit only record with conversion
  43 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  44 *                capture/playback rates)
  45 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  46 *                libOSSm.so)
  47 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  48 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  49 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  50 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  51 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  52 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  53 * 12/08/00 trw - added PM support.
  54 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  55 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  56 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  57 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  58 *                defaultorder-100 as power of 2 for the buffer size. example:
  59 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  60 *
  61 *******************************************************************************/
  62
  63 #include <linux/list.h>
  64 #include <linux/module.h>
  65 #include <linux/string.h>
  66 #include <linux/ioport.h>
  67 #include <linux/sched.h>
  68 #include <linux/delay.h>
  69 #include <linux/sound.h>
  70 #include <linux/slab.h>
  71 #include <linux/soundcard.h>
  72 #include <linux/ac97_codec.h>
  73 #include <linux/pci.h>
  74 #include <linux/bitops.h>
  75 #include <linux/interrupt.h>
  76 #include <linux/init.h>
  77 #include <linux/poll.h>
  78 #include <linux/mutex.h>
  79 #include <linux/kernel.h>
  80
  81 #include <asm/byteorder.h>
  82 #include <asm/dma.h>
  83 #include <asm/io.h>
  84 #include <asm/uaccess.h>
  85
  86 #include <asm/sibyte/sb1250_regs.h>
  87 #include <asm/sibyte/sb1250_int.h>
  88 #include <asm/sibyte/sb1250_dma.h>
  89 #include <asm/sibyte/sb1250_scd.h>
  90 #include <asm/sibyte/sb1250_syncser.h>
  91 #include <asm/sibyte/sb1250_mac.h>
  92 #include <asm/sibyte/sb1250.h>
  93
  94 struct cs4297a_state;
  95
  96 static void stop_dac(struct cs4297a_state *s);
  97 static void stop_adc(struct cs4297a_state *s);
  98 static void start_dac(struct cs4297a_state *s);
  99 static void start_adc(struct cs4297a_state *s);
 100 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 101
 102 // ---------------------------------------------------------------------
 103
 104 #define CS4297a_MAGIC           0xf00beef1
 105
 106 // buffer order determines the size of the dma buffer for the driver.
 107 // under Linux, a smaller buffer allows more responsiveness from many of the
 108 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 109 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 110 // rather than 64k as some of the games work more responsively.
 111 // log base 2( buff sz = 32k).
 112
 113 //static unsigned long defaultorder = 3;
 114 //MODULE_PARM(defaultorder, "i");
 115
 116 //
 117 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 118 //
 119 #define CSDEBUG 0
 120 #if CSDEBUG
 121 #define CSDEBUG_INTERFACE 1
 122 #else
 123 #undef CSDEBUG_INTERFACE
 124 #endif
 125 //
 126 // cs_debugmask areas
 127 //
 128 #define CS_INIT         0x00000001      // initialization and probe functions
 129 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 130 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 131 #define CS_FUNCTION     0x00000008      // enter/leave functions
 132 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 133 #define CS_WAVE_READ    0x00000020      // read information for wave
 134 #define CS_AC97         0x00000040      // AC97 register access
 135 #define CS_DESCR        0x00000080      // descriptor management
 136 #define CS_OPEN         0x00000400      // all open functions in the driver
 137 #define CS_RELEASE      0x00000800      // all release functions in the driver
 138 #define CS_PARMS        0x00001000      // functional and operational parameters
 139 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 140 #define CS_TMP          0x10000000      // tmp debug mask bit
 141
 142 //
 143 // CSDEBUG is usual mode is set to 1, then use the
 144 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 145 // Debug level of 1 has been defined to be kernel errors and info
 146 // that should be printed on any released driver.
 147 //
 148 #if CSDEBUG
 149 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 150 #else
 151 #define CS_DBGOUT(mask,level,x)
 152 #endif
 153
 154 #if CSDEBUG
 155 static unsigned long cs_debuglevel = 4; // levels range from 1-9
 156 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
 157 module_param(cs_debuglevel, int, 0);
 158 module_param(cs_debugmask, int, 0);
 159 #endif
 160 #define CS_TRUE         1
 161 #define CS_FALSE        0
 162
 163 #define CS_TYPE_ADC 0
 164 #define CS_TYPE_DAC 1
 165
 166 #define SER_BASE    (A_SER_BASE_1 + KSEG1)
 167 #define SS_CSR(t)   (SER_BASE+t)
 168 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
 169 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
 170
 171 #define FRAME_BYTES            32
 172 #define FRAME_SAMPLE_BYTES      4
 173
 174 /* Should this be variable? */
 175 #define SAMPLE_BUF_SIZE        (16*1024)
 176 #define SAMPLE_FRAME_COUNT     (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
 177 /* The driver can explode/shrink the frames to/from a smaller sample
 178    buffer */
 179 #define DMA_BLOAT_FACTOR       1
 180 #define DMA_DESCR              (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
 181 #define DMA_BUF_SIZE           (DMA_DESCR * FRAME_BYTES)
 182
 183 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
 184 #define DMA_INT_CNT            ((1 << S_DMA_INT_PKTCNT) - 1)
 185
 186 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
 187 #define REG_LATENCY            150
 188
 189 #define FRAME_TX_US             20
 190
 191 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
 192
 193 static const char invalid_magic[] =
 194     KERN_CRIT "cs4297a: invalid magic value\n";
 195
 196 #define VALIDATE_STATE(s)                          \
 197 ({                                                 \
 198         if (!(s) || (s)->magic != CS4297a_MAGIC) { \
 199                 printk(invalid_magic);             \
 200                 return -ENXIO;                     \
 201         }                                          \
 202 })
 203
 204 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
 205
 206 typedef struct serdma_descr_s {
 207         u64 descr_a;
 208         u64 descr_b;
 209 } serdma_descr_t;
 210
 211 typedef unsigned long paddr_t;
 212
 213 typedef struct serdma_s {
 214         unsigned         ringsz;
 215         serdma_descr_t  *descrtab;
 216         serdma_descr_t  *descrtab_end;
 217         paddr_t          descrtab_phys;
 218
 219         serdma_descr_t  *descr_add;
 220         serdma_descr_t  *descr_rem;
 221
 222         u64  *dma_buf;           // buffer for DMA contents (frames)
 223         paddr_t          dma_buf_phys;
 224         u16  *sample_buf;               // tmp buffer for sample conversions
 225         u16  *sb_swptr;
 226         u16  *sb_hwptr;
 227         u16  *sb_end;
 228
 229         dma_addr_t dmaaddr;
 230 //        unsigned buforder;    // Log base 2 of 'dma_buf' size in bytes..
 231         unsigned numfrag;       // # of 'fragments' in the buffer.
 232         unsigned fragshift;     // Log base 2 of fragment size.
 233         unsigned hwptr, swptr;
 234         unsigned total_bytes;   // # bytes process since open.
 235         unsigned blocks;        // last returned blocks value GETOPTR
 236         unsigned wakeup;        // interrupt occurred on block
 237         int count;
 238         unsigned underrun;      // underrun flag
 239         unsigned error; // over/underrun
 240         wait_queue_head_t wait;
 241         wait_queue_head_t reg_wait;
 242         // redundant, but makes calculations easier
 243         unsigned fragsize;      // 2**fragshift..
 244         unsigned sbufsz;        // 2**buforder.
 245         unsigned fragsamples;
 246         // OSS stuff
 247         unsigned mapped:1;      // Buffer mapped in cs4297a_mmap()?
 248         unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 249         unsigned endcleared:1;
 250         unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 251         unsigned ossfragshift;
 252         int ossmaxfrags;
 253         unsigned subdivision;
 254 } serdma_t;
 255
 256 struct cs4297a_state {
 257         // magic
 258         unsigned int magic;
 259
 260         struct list_head list;
 261
 262         // soundcore stuff
 263         int dev_audio;
 264         int dev_mixer;
 265
 266         // hardware resources
 267         unsigned int irq;
 268
 269         struct {
 270                 unsigned int rx_ovrrn; /* FIFO */
 271                 unsigned int rx_overflow; /* staging buffer */
 272                 unsigned int tx_underrun;
 273                 unsigned int rx_bad;
 274                 unsigned int rx_good;
 275         } stats;
 276
 277         // mixer registers
 278         struct {
 279                 unsigned short vol[10];
 280                 unsigned int recsrc;
 281                 unsigned int modcnt;
 282                 unsigned short micpreamp;
 283         } mix;
 284
 285         // wave stuff
 286         struct properties {
 287                 unsigned fmt;
 288                 unsigned fmt_original;  // original requested format
 289                 unsigned channels;
 290                 unsigned rate;
 291         } prop_dac, prop_adc;
 292         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 293         unsigned ena;
 294         spinlock_t lock;
 295         struct mutex open_mutex;
 296         struct mutex open_sem_adc;
 297         struct mutex open_sem_dac;
 298         fmode_t open_mode;
 299         wait_queue_head_t open_wait;
 300         wait_queue_head_t open_wait_adc;
 301         wait_queue_head_t open_wait_dac;
 302
 303         dma_addr_t dmaaddr_sample_buf;
 304         unsigned buforder_sample_buf;   // Log base 2 of 'dma_buf' size in bytes..
 305
 306         serdma_t dma_dac, dma_adc;
 307
 308         volatile u16 read_value;
 309         volatile u16 read_reg;
 310         volatile u64 reg_request;
 311 };
 312
 313 #if 1
 314 #define prog_codec(a,b)
 315 #define dealloc_dmabuf(a,b);
 316 #endif
 317
 318 static int prog_dmabuf_adc(struct cs4297a_state *s)
 319 {
 320         s->dma_adc.ready = 1;
 321         return 0;
 322 }
 323
 324
 325 static int prog_dmabuf_dac(struct cs4297a_state *s)
 326 {
 327         s->dma_dac.ready = 1;
 328         return 0;
 329 }
 330
 331 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
 332                           unsigned len, unsigned char c)
 333 {
 334         if (bptr + len > bsize) {
 335                 unsigned x = bsize - bptr;
 336                 memset(((char *) buf) + bptr, c, x);
 337                 bptr = 0;
 338                 len -= x;
 339         }
 340         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
 341                 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
 342                         (unsigned)c, (unsigned)((char *) buf) + bptr, len));
 343         memset(((char *) buf) + bptr, c, len);
 344 }
 345
 346 #if CSDEBUG
 347
 348 // DEBUG ROUTINES
 349
 350 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 351 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 352 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 353 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 354
 355 static void cs_printioctl(unsigned int x)
 356 {
 357         unsigned int i;
 358         unsigned char vidx;
 359         // Index of mixtable1[] member is Device ID
 360         // and must be <= SOUND_MIXER_NRDEVICES.
 361         // Value of array member is index into s->mix.vol[]
 362         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 363                 [SOUND_MIXER_PCM] = 1,  // voice
 364                 [SOUND_MIXER_LINE1] = 2,        // AUX
 365                 [SOUND_MIXER_CD] = 3,   // CD
 366                 [SOUND_MIXER_LINE] = 4, // Line
 367                 [SOUND_MIXER_SYNTH] = 5,        // FM
 368                 [SOUND_MIXER_MIC] = 6,  // Mic
 369                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 370                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 371                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 372         };
 373
 374         switch (x) {
 375         case SOUND_MIXER_CS_GETDBGMASK:
 376                 CS_DBGOUT(CS_IOCTL, 4,
 377                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 378                 break;
 379         case SOUND_MIXER_CS_GETDBGLEVEL:
 380                 CS_DBGOUT(CS_IOCTL, 4,
 381                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 382                 break;
 383         case SOUND_MIXER_CS_SETDBGMASK:
 384                 CS_DBGOUT(CS_IOCTL, 4,
 385                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 386                 break;
 387         case SOUND_MIXER_CS_SETDBGLEVEL:
 388                 CS_DBGOUT(CS_IOCTL, 4,
 389                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 390                 break;
 391         case OSS_GETVERSION:
 392                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 393                 break;
 394         case SNDCTL_DSP_SYNC:
 395                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 396                 break;
 397         case SNDCTL_DSP_SETDUPLEX:
 398                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 399                 break;
 400         case SNDCTL_DSP_GETCAPS:
 401                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 402                 break;
 403         case SNDCTL_DSP_RESET:
 404                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 405                 break;
 406         case SNDCTL_DSP_SPEED:
 407                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 408                 break;
 409         case SNDCTL_DSP_STEREO:
 410                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 411                 break;
 412         case SNDCTL_DSP_CHANNELS:
 413                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 414                 break;
 415         case SNDCTL_DSP_GETFMTS:
 416                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 417                 break;
 418         case SNDCTL_DSP_SETFMT:
 419                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 420                 break;
 421         case SNDCTL_DSP_POST:
 422                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 423                 break;
 424         case SNDCTL_DSP_GETTRIGGER:
 425                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 426                 break;
 427         case SNDCTL_DSP_SETTRIGGER:
 428                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 429                 break;
 430         case SNDCTL_DSP_GETOSPACE:
 431                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 432                 break;
 433         case SNDCTL_DSP_GETISPACE:
 434                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 435                 break;
 436         case SNDCTL_DSP_NONBLOCK:
 437                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 438                 break;
 439         case SNDCTL_DSP_GETODELAY:
 440                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 441                 break;
 442         case SNDCTL_DSP_GETIPTR:
 443                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 444                 break;
 445         case SNDCTL_DSP_GETOPTR:
 446                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 447                 break;
 448         case SNDCTL_DSP_GETBLKSIZE:
 449                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 450                 break;
 451         case SNDCTL_DSP_SETFRAGMENT:
 452                 CS_DBGOUT(CS_IOCTL, 4,
 453                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 454                 break;
 455         case SNDCTL_DSP_SUBDIVIDE:
 456                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 457                 break;
 458         case SOUND_PCM_READ_RATE:
 459                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 460                 break;
 461         case SOUND_PCM_READ_CHANNELS:
 462                 CS_DBGOUT(CS_IOCTL, 4,
 463                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 464                 break;
 465         case SOUND_PCM_READ_BITS:
 466                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 467                 break;
 468         case SOUND_PCM_WRITE_FILTER:
 469                 CS_DBGOUT(CS_IOCTL, 4,
 470                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 471                 break;
 472         case SNDCTL_DSP_SETSYNCRO:
 473                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 474                 break;
 475         case SOUND_PCM_READ_FILTER:
 476                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 477                 break;
 478         case SOUND_MIXER_PRIVATE1:
 479                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 480                 break;
 481         case SOUND_MIXER_PRIVATE2:
 482                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 483                 break;
 484         case SOUND_MIXER_PRIVATE3:
 485                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 486                 break;
 487         case SOUND_MIXER_PRIVATE4:
 488                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 489                 break;
 490         case SOUND_MIXER_PRIVATE5:
 491                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 492                 break;
 493         case SOUND_MIXER_INFO:
 494                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 495                 break;
 496         case SOUND_OLD_MIXER_INFO:
 497                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 498                 break;
 499
 500         default:
 501                 switch (_IOC_NR(x)) {
 502                 case SOUND_MIXER_VOLUME:
 503                         CS_DBGOUT(CS_IOCTL, 4,
 504                                   printk("SOUND_MIXER_VOLUME:\n"));
 505                         break;
 506                 case SOUND_MIXER_SPEAKER:
 507                         CS_DBGOUT(CS_IOCTL, 4,
 508                                   printk("SOUND_MIXER_SPEAKER:\n"));
 509                         break;
 510                 case SOUND_MIXER_RECLEV:
 511                         CS_DBGOUT(CS_IOCTL, 4,
 512                                   printk("SOUND_MIXER_RECLEV:\n"));
 513                         break;
 514                 case SOUND_MIXER_MIC:
 515                         CS_DBGOUT(CS_IOCTL, 4,
 516                                   printk("SOUND_MIXER_MIC:\n"));
 517                         break;
 518                 case SOUND_MIXER_SYNTH:
 519                         CS_DBGOUT(CS_IOCTL, 4,
 520                                   printk("SOUND_MIXER_SYNTH:\n"));
 521                         break;
 522                 case SOUND_MIXER_RECSRC:
 523                         CS_DBGOUT(CS_IOCTL, 4,
 524                                   printk("SOUND_MIXER_RECSRC:\n"));
 525                         break;
 526                 case SOUND_MIXER_DEVMASK:
 527                         CS_DBGOUT(CS_IOCTL, 4,
 528                                   printk("SOUND_MIXER_DEVMASK:\n"));
 529                         break;
 530                 case SOUND_MIXER_RECMASK:
 531                         CS_DBGOUT(CS_IOCTL, 4,
 532                                   printk("SOUND_MIXER_RECMASK:\n"));
 533                         break;
 534                 case SOUND_MIXER_STEREODEVS:
 535                         CS_DBGOUT(CS_IOCTL, 4,
 536                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 537                         break;
 538                 case SOUND_MIXER_CAPS:
 539                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 540                         break;
 541                 default:
 542                         i = _IOC_NR(x);
 543                         if (i >= SOUND_MIXER_NRDEVICES
 544                             || !(vidx = mixtable1[i])) {
 545                                 CS_DBGOUT(CS_IOCTL, 4, printk
 546                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 547                                                 x, i));
 548                         } else {
 549                                 CS_DBGOUT(CS_IOCTL, 4, printk
 550                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 551                                                 x, i));
 552                         }
 553                         break;
 554                 }
 555         }
 556 }
 557 #endif
 558
 559
 560 static int ser_init(struct cs4297a_state *s)
 561 {
 562         int i;
 563
 564         CS_DBGOUT(CS_INIT, 2,
 565                   printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
 566
 567         __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
 568
 569         __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
 570         __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
 571         __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
 572
 573         __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
 574         __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
 575         __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
 576
 577         /* This looks good from experimentation */
 578         __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
 579                M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
 580               SS_CSR(R_SER_LINE_MODE));
 581
 582         /* This looks good from experimentation */
 583         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 584               SS_TXTBL(0));
 585         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 586               SS_TXTBL(1));
 587         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 588               SS_TXTBL(2));
 589         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
 590               M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
 591
 592         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 593               SS_RXTBL(0));
 594         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 595               SS_RXTBL(1));
 596         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 597               SS_RXTBL(2));
 598         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
 599               M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
 600
 601         for (i=4; i<16; i++) {
 602                 /* Just in case... */
 603                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
 604                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int init_serdma(serdma_t *dma)
 611 {
 612         CS_DBGOUT(CS_INIT, 2,
 613                   printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
 614                          DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
 615
 616         /* Descriptors */
 617         dma->ringsz = DMA_DESCR;
 618         dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
 619         if (!dma->descrtab) {
 620                 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
 621                 return -1;
 622         }
 623         dma->descrtab_end = dma->descrtab + dma->ringsz;
 624         /* XXX bloddy mess, use proper DMA API here ...  */
 625         dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
 626         dma->descr_add = dma->descr_rem = dma->descrtab;
 627
 628         /* Frame buffer area */
 629         dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
 630         if (!dma->dma_buf) {
 631                 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
 632                 kfree(dma->descrtab);
 633                 return -1;
 634         }
 635         dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
 636
 637         /* Samples buffer area */
 638         dma->sbufsz = SAMPLE_BUF_SIZE;
 639         dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
 640         if (!dma->sample_buf) {
 641                 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
 642                 kfree(dma->descrtab);
 643                 kfree(dma->dma_buf);
 644                 return -1;
 645         }
 646         dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
 647         dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
 648         dma->fragsize = dma->sbufsz >> 1;
 649
 650         CS_DBGOUT(CS_INIT, 4,
 651                   printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
 652                          (int)dma->descrtab, (int)dma->dma_buf,
 653                          (int)dma->sample_buf));
 654
 655         return 0;
 656 }
 657
 658 static int dma_init(struct cs4297a_state *s)
 659 {
 660         int i;
 661
 662         CS_DBGOUT(CS_INIT, 2,
 663                   printk(KERN_INFO "cs4297a: Setting up DMA\n"));
 664
 665         if (init_serdma(&s->dma_adc) ||
 666             init_serdma(&s->dma_dac))
 667                 return -1;
 668
 669         if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
 670             __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
 671                 panic("DMA state corrupted?!");
 672         }
 673
 674         /* Initialize now - the descr/buffer pairings will never
 675            change... */
 676         for (i=0; i<DMA_DESCR; i++) {
 677                 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
 678                         (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
 679                 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
 680                 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
 681                         (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
 682                 s->dma_adc.descrtab[i].descr_b = 0;
 683         }
 684
 685         __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
 686                V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
 687               SS_CSR(R_SER_DMA_CONFIG0_RX));
 688         __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
 689         __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
 690
 691         __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
 692         __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
 693         __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
 694
 695         /* Prep the receive DMA descriptor ring */
 696         __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 697
 698         __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
 699
 700         __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
 701               SS_CSR(R_SER_INT_MASK));
 702
 703         /* Enable the rx/tx; let the codec warm up to the sync and
 704            start sending good frames before the receive FIFO is
 705            enabled */
 706         __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 707         udelay(1000);
 708         __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 709
 710         /* XXXKW is this magic? (the "1" part) */
 711         while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
 712                 ;
 713
 714         CS_DBGOUT(CS_INIT, 4,
 715                   printk(KERN_INFO "cs4297a: status: %08x\n",
 716                          (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
 717
 718         return 0;
 719 }
 720
 721 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
 722 {
 723         serdma_t *d = &s->dma_dac;
 724         u64 *data_p;
 725         unsigned swptr;
 726         unsigned long flags;
 727         serdma_descr_t *descr;
 728
 729         if (s->reg_request) {
 730                 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
 731                 return -1;
 732         }
 733
 734         if (s->ena & FMODE_WRITE) {
 735                 /* Since a writer has the DSP open, we have to mux the
 736                    request in */
 737                 s->reg_request = data;
 738                 interruptible_sleep_on(&s->dma_dac.reg_wait);
 739                 /* XXXKW how can I deal with the starvation case where
 740                    the opener isn't writing? */
 741         } else {
 742                 /* Be safe when changing ring pointers */
 743                 spin_lock_irqsave(&s->lock, flags);
 744                 if (d->hwptr != d->swptr) {
 745                         printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
 746                                d->hwptr, d->swptr);
 747                         spin_unlock_irqrestore(&s->lock, flags);
 748                         return -1;
 749                 }
 750                 swptr = d->swptr;
 751                 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
 752                 spin_unlock_irqrestore(&s->lock, flags);
 753
 754                 descr = &d->descrtab[swptr];
 755                 data_p = &d->dma_buf[swptr * 4];
 756                 *data_p = cpu_to_be64(data);
 757                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
 758                 CS_DBGOUT(CS_DESCR, 4,
 759                           printk(KERN_INFO "cs4297a: add_tx  %p (%x -> %x)\n",
 760                                  data_p, swptr, d->hwptr));
 761         }
 762
 763         CS_DBGOUT(CS_FUNCTION, 6,
 764                   printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
 765
 766         return 0;
 767 }
 768
 769 //****************************************************************************
 770 // "cs4297a_read_ac97" -- Reads an AC97 register
 771 //****************************************************************************
 772 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
 773                             u32 * value)
 774 {
 775         CS_DBGOUT(CS_AC97, 1,
 776                   printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
 777         if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
 778                 return -1;
 779
 780         interruptible_sleep_on(&s->dma_adc.reg_wait);
 781         *value = s->read_value;
 782         CS_DBGOUT(CS_AC97, 2,
 783                   printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
 784
 785         return 0;
 786 }
 787
 788
 789 //****************************************************************************
 790 // "cs4297a_write_ac97()"-- writes an AC97 register
 791 //****************************************************************************
 792 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
 793                              u32 value)
 794 {
 795         CS_DBGOUT(CS_AC97, 1,
 796                   printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
 797         return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
 798 }
 799
 800 static void stop_dac(struct cs4297a_state *s)
 801 {
 802         unsigned long flags;
 803
 804         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
 805         spin_lock_irqsave(&s->lock, flags);
 806         s->ena &= ~FMODE_WRITE;
 807 #if 0
 808         /* XXXKW what do I really want here?  My theory for now is
 809            that I just flip the "ena" bit, and the interrupt handler
 810            will stop processing the xmit channel */
 811         __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
 812               SS_CSR(R_SER_DMA_ENABLE));
 813 #endif
 814
 815         spin_unlock_irqrestore(&s->lock, flags);
 816 }
 817
 818
 819 static void start_dac(struct cs4297a_state *s)
 820 {
 821         unsigned long flags;
 822
 823         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
 824         spin_lock_irqsave(&s->lock, flags);
 825         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
 826                                         (s->dma_dac.count > 0
 827                                         && s->dma_dac.ready))) {
 828                 s->ena |= FMODE_WRITE;
 829                 /* XXXKW what do I really want here?  My theory for
 830                    now is that I just flip the "ena" bit, and the
 831                    interrupt handler will start processing the xmit
 832                    channel */
 833
 834                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
 835                         "cs4297a: start_dac(): start dma\n"));
 836
 837         }
 838         spin_unlock_irqrestore(&s->lock, flags);
 839         CS_DBGOUT(CS_FUNCTION, 3,
 840                   printk(KERN_INFO "cs4297a: start_dac()-\n"));
 841 }
 842
 843
 844 static void stop_adc(struct cs4297a_state *s)
 845 {
 846         unsigned long flags;
 847
 848         CS_DBGOUT(CS_FUNCTION, 3,
 849                   printk(KERN_INFO "cs4297a: stop_adc()+\n"));
 850
 851         spin_lock_irqsave(&s->lock, flags);
 852         s->ena &= ~FMODE_READ;
 853
 854         if (s->conversion == 1) {
 855                 s->conversion = 0;
 856                 s->prop_adc.fmt = s->prop_adc.fmt_original;
 857         }
 858         /* Nothing to do really, I need to keep the DMA going
 859            XXXKW when do I get here, and is there more I should do? */
 860         spin_unlock_irqrestore(&s->lock, flags);
 861         CS_DBGOUT(CS_FUNCTION, 3,
 862                   printk(KERN_INFO "cs4297a: stop_adc()-\n"));
 863 }
 864
 865
 866 static void start_adc(struct cs4297a_state *s)
 867 {
 868         unsigned long flags;
 869
 870         CS_DBGOUT(CS_FUNCTION, 2,
 871                   printk(KERN_INFO "cs4297a: start_adc()+\n"));
 872
 873         if (!(s->ena & FMODE_READ) &&
 874             (s->dma_adc.mapped || s->dma_adc.count <=
 875              (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
 876             && s->dma_adc.ready) {
 877                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
 878                         //
 879                         // now only use 16 bit capture, due to truncation issue
 880                         // in the chip, noticable distortion occurs.
 881                         // allocate buffer and then convert from 16 bit to
 882                         // 8 bit for the user buffer.
 883                         //
 884                         s->prop_adc.fmt_original = s->prop_adc.fmt;
 885                         if (s->prop_adc.fmt & AFMT_S8) {
 886                                 s->prop_adc.fmt &= ~AFMT_S8;
 887                                 s->prop_adc.fmt |= AFMT_S16_LE;
 888                         }
 889                         if (s->prop_adc.fmt & AFMT_U8) {
 890                                 s->prop_adc.fmt &= ~AFMT_U8;
 891                                 s->prop_adc.fmt |= AFMT_U16_LE;
 892                         }
 893                         //
 894                         // prog_dmabuf_adc performs a stop_adc() but that is
 895                         // ok since we really haven't started the DMA yet.
 896                         //
 897                         prog_codec(s, CS_TYPE_ADC);
 898
 899                         prog_dmabuf_adc(s);
 900                         s->conversion = 1;
 901                 }
 902                 spin_lock_irqsave(&s->lock, flags);
 903                 s->ena |= FMODE_READ;
 904                 /* Nothing to do really, I am probably already
 905                    DMAing...  XXXKW when do I get here, and is there
 906                    more I should do? */
 907                 spin_unlock_irqrestore(&s->lock, flags);
 908
 909                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
 910                          "cs4297a: start_adc(): start adc\n"));
 911         }
 912         CS_DBGOUT(CS_FUNCTION, 2,
 913                   printk(KERN_INFO "cs4297a: start_adc()-\n"));
 914
 915 }
 916
 917
 918 // call with spinlock held!
 919 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
 920 {
 921         int good_diff, diff, diff2;
 922         u64 *data_p, data;
 923         u32 *s_ptr;
 924         unsigned hwptr;
 925         u32 status;
 926         serdma_t *d;
 927         serdma_descr_t *descr;
 928
 929         // update ADC pointer
 930         status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
 931
 932         if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
 933                 d = &s->dma_adc;
 934                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
 935                                      d->descrtab_phys) / sizeof(serdma_descr_t));
 936
 937                 if (s->ena & FMODE_READ) {
 938                         CS_DBGOUT(CS_FUNCTION, 2,
 939                                   printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
 940                                          d->swptr, d->hwptr, hwptr, intflag));
 941                         /* Number of DMA buffers available for software: */
 942                         diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
 943                         d->hwptr = hwptr;
 944                         good_diff = 0;
 945                         s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
 946                         descr = &d->descrtab[d->swptr];
 947                         while (diff2--) {
 948                                 u64 data = be64_to_cpu(*(u64 *)s_ptr);
 949                                 u64 descr_a;
 950                                 u16 left, right;
 951                                 descr_a = descr->descr_a;
 952                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
 953                                 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
 954                                         printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
 955                                 }
 956                                 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
 957                                     (!(descr_a & M_DMA_SERRX_SOP)) ||
 958                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
 959                                         s->stats.rx_bad++;
 960                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
 961                                         continue;
 962                                 }
 963                                 s->stats.rx_good++;
 964                                 if ((data >> 61) == 7) {
 965                                         s->read_value = (data >> 12) & 0xffff;
 966                                         s->read_reg = (data >> 40) & 0x7f;
 967                                         wake_up(&d->reg_wait);
 968                                 }
 969                                 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
 970                                         s->stats.rx_overflow++;
 971                                         printk(KERN_DEBUG "cs4297a: RX overflow\n");
 972                                         continue;
 973                                 }
 974                                 good_diff++;
 975                                 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
 976                                        ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
 977                                 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
 978                                 *d->sb_hwptr++ = cpu_to_be16(left);
 979                                 *d->sb_hwptr++ = cpu_to_be16(right);
 980                                 if (d->sb_hwptr == d->sb_end)
 981                                         d->sb_hwptr = d->sample_buf;
 982                                 descr++;
 983                                 if (descr == d->descrtab_end) {
 984                                         descr = d->descrtab;
 985                                         s_ptr = (u32 *)s->dma_adc.dma_buf;
 986                                 } else {
 987                                         s_ptr += 8;
 988                                 }
 989                         }
 990                         d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
 991                         d->count += good_diff * FRAME_SAMPLE_BYTES;
 992                         if (d->count > d->sbufsz) {
 993                                 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
 994                         }
 995                         d->swptr = (d->swptr + diff) % d->ringsz;
 996                         __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 997                         if (d->mapped) {
 998                                 if (d->count >= (signed) d->fragsize)
 999                                         wake_up(&d->wait);
1000                         } else {
1001                                 if (d->count > 0) {
1002                                         CS_DBGOUT(CS_WAVE_READ, 4,
1003                                                   printk(KERN_INFO
1004                                                          "cs4297a: update count -> %d\n", d->count));
1005                                         wake_up(&d->wait);
1006                                 }
1007                         }
1008                 } else {
1009                         /* Receive is going even if no one is
1010                            listening (for register accesses and to
1011                            avoid FIFO overrun) */
1012                         diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1013                         if (!diff) {
1014                                 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1015                         }
1016
1017                         descr = &d->descrtab[d->swptr];
1018                         data_p = &d->dma_buf[d->swptr*4];
1019
1020                         /* Force this to happen at least once; I got
1021                            here because of an interrupt, so there must
1022                            be a buffer to process. */
1023                         do {
1024                                 data = be64_to_cpu(*data_p);
1025                                 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1026                                         printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1027                                                (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1028                                                (long)CPHYSADDR((long)data_p));
1029                                 }
1030                                 if (!(data & (1LL << 63)) ||
1031                                     !(descr->descr_a & M_DMA_SERRX_SOP) ||
1032                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1033                                         s->stats.rx_bad++;
1034                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1035                                 } else {
1036                                         s->stats.rx_good++;
1037                                         if ((data >> 61) == 7) {
1038                                                 s->read_value = (data >> 12) & 0xffff;
1039                                                 s->read_reg = (data >> 40) & 0x7f;
1040                                                 wake_up(&d->reg_wait);
1041                                         }
1042                                 }
1043                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
1044                                 descr++;
1045                                 d->swptr++;
1046                                 data_p += 4;
1047                                 if (descr == d->descrtab_end) {
1048                                         descr = d->descrtab;
1049                                         d->swptr = 0;
1050                                         data_p = d->dma_buf;
1051                                 }
1052                                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1053                         } while (--diff);
1054                         d->hwptr = hwptr;
1055
1056                         CS_DBGOUT(CS_DESCR, 6,
1057                                   printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1058                 }
1059
1060                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1061                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1062                                 (unsigned)s, d->hwptr,
1063                                 d->total_bytes, d->count));
1064         }
1065
1066         /* XXXKW worry about s->reg_request -- there is a starvation
1067            case if s->ena has FMODE_WRITE on, but the client isn't
1068            doing writes */
1069
1070         // update DAC pointer
1071         //
1072         // check for end of buffer, means that we are going to wait for another interrupt
1073         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1074         //
1075         if (s->ena & FMODE_WRITE) {
1076                 serdma_t *d = &s->dma_dac;
1077                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1078                                      d->descrtab_phys) / sizeof(serdma_descr_t));
1079                 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1080                 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1081                                                    "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1082                                                    d->hwptr, hwptr, d->swptr, diff, d->count));
1083                 d->hwptr = hwptr;
1084                 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1085                 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1086                 if (d->mapped) {
1087                         d->count += diff * FRAME_SAMPLE_BYTES;
1088                         if (d->count >= d->fragsize) {
1089                                 d->wakeup = 1;
1090                                 wake_up(&d->wait);
1091                                 if (d->count > d->sbufsz)
1092                                         d->count &= d->sbufsz - 1;
1093                         }
1094                 } else {
1095                         d->count -= diff * FRAME_SAMPLE_BYTES;
1096                         if (d->count <= 0) {
1097                                 //
1098                                 // fill with silence, and do not shut down the DAC.
1099                                 // Continue to play silence until the _release.
1100                                 //
1101                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1102                                         "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1103                                                 (unsigned)(s->prop_dac.fmt &
1104                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1105                                                 (unsigned)d->dma_buf,
1106                                                 d->ringsz));
1107                                 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1108                                 if (d->count < 0) {
1109                                         d->underrun = 1;
1110                                         s->stats.tx_underrun++;
1111                                         d->count = 0;
1112                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1113                                          "cs4297a: cs4297a_update_ptr(): underrun\n"));
1114                                 }
1115                         } else if (d->count <=
1116                                    (signed) d->fragsize
1117                                    && !d->endcleared) {
1118                           /* XXXKW what is this for? */
1119                                 clear_advance(d->dma_buf,
1120                                               d->sbufsz,
1121                                               d->swptr,
1122                                               d->fragsize,
1123                                               0);
1124                                 d->endcleared = 1;
1125                         }
1126                         if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1127                         {
1128                                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1129                                           printk(KERN_INFO
1130                                                  "cs4297a: update count -> %d\n", d->count));
1131                                 wake_up(&d->wait);
1132                         }
1133                 }
1134                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1135                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1136                                 (unsigned) s, d->hwptr,
1137                                 d->total_bytes, d->count));
1138         }
1139 }
1140
1141 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1142                        unsigned long arg)
1143 {
1144         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1145         // Value of array member is recording source Device ID Mask.
1146         static const unsigned int mixer_src[8] = {
1147                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1148                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1149         };
1150
1151         // Index of mixtable1[] member is Device ID
1152         // and must be <= SOUND_MIXER_NRDEVICES.
1153         // Value of array member is index into s->mix.vol[]
1154         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1155                 [SOUND_MIXER_PCM] = 1,  // voice
1156                 [SOUND_MIXER_LINE1] = 2,        // AUX
1157                 [SOUND_MIXER_CD] = 3,   // CD
1158                 [SOUND_MIXER_LINE] = 4, // Line
1159                 [SOUND_MIXER_SYNTH] = 5,        // FM
1160                 [SOUND_MIXER_MIC] = 6,  // Mic
1161                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
1162                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
1163                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
1164         };
1165
1166         static const unsigned mixreg[] = {
1167                 AC97_PCMOUT_VOL,
1168                 AC97_AUX_VOL,
1169                 AC97_CD_VOL,
1170                 AC97_LINEIN_VOL
1171         };
1172         unsigned char l, r, rl, rr, vidx;
1173         unsigned char attentbl[11] =
1174             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1175         unsigned temp1;
1176         int i, val;
1177
1178         VALIDATE_STATE(s);
1179         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1180                  "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1181                          (unsigned) s, cmd));
1182 #if CSDEBUG
1183         cs_printioctl(cmd);
1184 #endif
1185 #if CSDEBUG_INTERFACE
1186
1187         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1188             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1189             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1190             (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1191         {
1192                 switch (cmd) {
1193
1194                 case SOUND_MIXER_CS_GETDBGMASK:
1195                         return put_user(cs_debugmask,
1196                                         (unsigned long *) arg);
1197
1198                 case SOUND_MIXER_CS_GETDBGLEVEL:
1199                         return put_user(cs_debuglevel,
1200                                         (unsigned long *) arg);
1201
1202                 case SOUND_MIXER_CS_SETDBGMASK:
1203                         if (get_user(val, (unsigned long *) arg))
1204                                 return -EFAULT;
1205                         cs_debugmask = val;
1206                         return 0;
1207
1208                 case SOUND_MIXER_CS_SETDBGLEVEL:
1209                         if (get_user(val, (unsigned long *) arg))
1210                                 return -EFAULT;
1211                         cs_debuglevel = val;
1212                         return 0;
1213                 default:
1214                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1215                                 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1216                         return 0;
1217                 }
1218         }
1219 #endif
1220
1221         if (cmd == SOUND_MIXER_PRIVATE1) {
1222                 return -EINVAL;
1223         }
1224         if (cmd == SOUND_MIXER_PRIVATE2) {
1225                 // enable/disable/query spatializer
1226                 if (get_user(val, (int *) arg))
1227                         return -EFAULT;
1228                 if (val != -1) {
1229                         temp1 = (val & 0x3f) >> 2;
1230                         cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1231                         cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1232                                          &temp1);
1233                         cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1234                                           temp1 | 0x2000);
1235                 }
1236                 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1237                 return put_user((temp1 << 2) | 3, (int *) arg);
1238         }
1239         if (cmd == SOUND_MIXER_INFO) {
1240                 mixer_info info;
1241                 memset(&info, 0, sizeof(info));
1242                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1243                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1244                 info.modify_counter = s->mix.modcnt;
1245                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1246                         return -EFAULT;
1247                 return 0;
1248         }
1249         if (cmd == SOUND_OLD_MIXER_INFO) {
1250                 _old_mixer_info info;
1251                 memset(&info, 0, sizeof(info));
1252                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1253                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1254                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1255                         return -EFAULT;
1256                 return 0;
1257         }
1258         if (cmd == OSS_GETVERSION)
1259                 return put_user(SOUND_VERSION, (int *) arg);
1260
1261         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1262                 return -EINVAL;
1263
1264         // If ioctl has only the SIOC_READ bit(bit 31)
1265         // on, process the only-read commands.
1266         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1267                 switch (_IOC_NR(cmd)) {
1268                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1269                         cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1270                                          &temp1);
1271                         return put_user(mixer_src[temp1 & 7], (int *) arg);
1272
1273                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
1274                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1275                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1276                                         (int *) arg);
1277
1278                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
1279                         return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1280                                         (int *) arg);
1281
1282                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
1283                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1284                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1285                                         (int *) arg);
1286
1287                 case SOUND_MIXER_CAPS:
1288                         return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1289
1290                 default:
1291                         i = _IOC_NR(cmd);
1292                         if (i >= SOUND_MIXER_NRDEVICES
1293                             || !(vidx = mixtable1[i]))
1294                                 return -EINVAL;
1295                         return put_user(s->mix.vol[vidx - 1], (int *) arg);
1296                 }
1297         }
1298         // If ioctl doesn't have both the SIOC_READ and
1299         // the SIOC_WRITE bit set, return invalid.
1300         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1301                 return -EINVAL;
1302
1303         // Increment the count of volume writes.
1304         s->mix.modcnt++;
1305
1306         // Isolate the command; it must be a write.
1307         switch (_IOC_NR(cmd)) {
1308
1309         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1310                 if (get_user(val, (int *) arg))
1311                         return -EFAULT;
1312                 i = hweight32(val);     // i = # bits on in val.
1313                 if (i != 1)     // One & only 1 bit must be on.
1314                         return 0;
1315                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1316                         if (val == mixer_src[i]) {
1317                                 temp1 = (i << 8) | i;
1318                                 cs4297a_write_ac97(s,
1319                                                   AC97_RECORD_SELECT,
1320                                                   temp1);
1321                                 return 0;
1322                         }
1323                 }
1324                 return 0;
1325
1326         case SOUND_MIXER_VOLUME:
1327                 if (get_user(val, (int *) arg))
1328                         return -EFAULT;
1329                 l = val & 0xff;
1330                 if (l > 100)
1331                         l = 100;        // Max soundcard.h vol is 100.
1332                 if (l < 6) {
1333                         rl = 63;
1334                         l = 0;
1335                 } else
1336                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
1337
1338                 r = (val >> 8) & 0xff;
1339                 if (r > 100)
1340                         r = 100;        // Max right volume is 100, too
1341                 if (r < 6) {
1342                         rr = 63;
1343                         r = 0;
1344                 } else
1345                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
1346
1347                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
1348                         temp1 = 0x8000; //  turn on the mute bit.
1349                 else
1350                         temp1 = 0;
1351
1352                 temp1 |= (rl << 8) | rr;
1353
1354                 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1355                 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1356
1357 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1358                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1359 #else
1360                 s->mix.vol[8] = val;
1361 #endif
1362                 return put_user(s->mix.vol[8], (int *) arg);
1363
1364         case SOUND_MIXER_SPEAKER:
1365                 if (get_user(val, (int *) arg))
1366                         return -EFAULT;
1367                 l = val & 0xff;
1368                 if (l > 100)
1369                         l = 100;
1370                 if (l < 3) {
1371                         rl = 0;
1372                         l = 0;
1373                 } else {
1374                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
1375                         l = (rl * 13 + 5) / 2;
1376                 }
1377
1378                 if (rl < 3) {
1379                         temp1 = 0x8000;
1380                         rl = 0;
1381                 } else
1382                         temp1 = 0;
1383                 rl = 15 - rl;   // Convert volume to attenuation.
1384                 temp1 |= rl << 1;
1385                 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1386
1387 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1388                 s->mix.vol[6] = l << 8;
1389 #else
1390                 s->mix.vol[6] = val;
1391 #endif
1392                 return put_user(s->mix.vol[6], (int *) arg);
1393
1394         case SOUND_MIXER_RECLEV:
1395                 if (get_user(val, (int *) arg))
1396                         return -EFAULT;
1397                 l = val & 0xff;
1398                 if (l > 100)
1399                         l = 100;
1400                 r = (val >> 8) & 0xff;
1401                 if (r > 100)
1402                         r = 100;
1403                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
1404                 rr = (r * 2 - 5) / 13;
1405                 if (rl < 3 && rr < 3)
1406                         temp1 = 0x8000;
1407                 else
1408                         temp1 = 0;
1409
1410                 temp1 = temp1 | (rl << 8) | rr;
1411                 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1412
1413 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1414                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1415 #else
1416                 s->mix.vol[7] = val;
1417 #endif
1418                 return put_user(s->mix.vol[7], (int *) arg);
1419
1420         case SOUND_MIXER_MIC:
1421                 if (get_user(val, (int *) arg))
1422                         return -EFAULT;
1423                 l = val & 0xff;
1424                 if (l > 100)
1425                         l = 100;
1426                 if (l < 1) {
1427                         l = 0;
1428                         rl = 0;
1429                 } else {
1430                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
1431                         l = (rl * 16 + 4) / 5;
1432                 }
1433                 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1434                 temp1 &= 0x40;  // Isolate 20db gain bit.
1435                 if (rl < 3) {
1436                         temp1 |= 0x8000;
1437                         rl = 0;
1438                 }
1439                 rl = 31 - rl;   // Convert volume to attenuation.
1440                 temp1 |= rl;
1441                 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1442
1443 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1444                 s->mix.vol[5] = val << 8;
1445 #else
1446                 s->mix.vol[5] = val;
1447 #endif
1448                 return put_user(s->mix.vol[5], (int *) arg);
1449
1450
1451         case SOUND_MIXER_SYNTH:
1452                 if (get_user(val, (int *) arg))
1453                         return -EFAULT;
1454                 l = val & 0xff;
1455                 if (l > 100)
1456                         l = 100;
1457                 if (get_user(val, (int *) arg))
1458                         return -EFAULT;
1459                 r = (val >> 8) & 0xff;
1460                 if (r > 100)
1461                         r = 100;
1462                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
1463                 rr = (r * 2 - 11) / 3;
1464                 if (rl < 3)     // If l is low, turn on
1465                         temp1 = 0x0080; //  the mute bit.
1466                 else
1467                         temp1 = 0;
1468
1469                 rl = 63 - rl;   // Convert vol to attenuation.
1470 //              writel(temp1 | rl, s->pBA0 + FMLVC);
1471                 if (rr < 3)     //  If rr is low, turn on
1472                         temp1 = 0x0080; //   the mute bit.
1473                 else
1474                         temp1 = 0;
1475                 rr = 63 - rr;   // Convert vol to attenuation.
1476 //              writel(temp1 | rr, s->pBA0 + FMRVC);
1477
1478 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1479                 s->mix.vol[4] = (r << 8) | l;
1480 #else
1481                 s->mix.vol[4] = val;
1482 #endif
1483                 return put_user(s->mix.vol[4], (int *) arg);
1484
1485
1486         default:
1487                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1488                         "cs4297a: mixer_ioctl(): default\n"));
1489
1490                 i = _IOC_NR(cmd);
1491                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1492                         return -EINVAL;
1493                 if (get_user(val, (int *) arg))
1494                         return -EFAULT;
1495                 l = val & 0xff;
1496                 if (l > 100)
1497                         l = 100;
1498                 if (l < 1) {
1499                         l = 0;
1500                         rl = 31;
1501                 } else
1502                         rl = (attentbl[(l * 10) / 100]) >> 1;
1503
1504                 r = (val >> 8) & 0xff;
1505                 if (r > 100)
1506                         r = 100;
1507                 if (r < 1) {
1508                         r = 0;
1509                         rr = 31;
1510                 } else
1511                         rr = (attentbl[(r * 10) / 100]) >> 1;
1512                 if ((rl > 30) && (rr > 30))
1513                         temp1 = 0x8000;
1514                 else
1515                         temp1 = 0;
1516                 temp1 = temp1 | (rl << 8) | rr;
1517                 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1518
1519 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1520                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1521 #else
1522                 s->mix.vol[vidx - 1] = val;
1523 #endif
1524                 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1525         }
1526 }
1527
1528
1529 // ---------------------------------------------------------------------
1530
1531 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1532 {
1533         int minor = iminor(inode);
1534         struct cs4297a_state *s=NULL;
1535         struct list_head *entry;
1536
1537         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1538                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1539
1540         list_for_each(entry, &cs4297a_devs)
1541         {
1542                 s = list_entry(entry, struct cs4297a_state, list);
1543                 if(s->dev_mixer == minor)
1544                         break;
1545         }
1546         if (!s)
1547         {
1548                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1549                         printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1550                 return -ENODEV;
1551         }
1552         VALIDATE_STATE(s);
1553         file->private_data = s;
1554
1555         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1556                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1557
1558         return nonseekable_open(inode, file);
1559 }
1560
1561
1562 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1563 {
1564         struct cs4297a_state *s =
1565             (struct cs4297a_state *) file->private_data;
1566
1567         VALIDATE_STATE(s);
1568         return 0;
1569 }
1570
1571
1572 static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1573                                unsigned int cmd, unsigned long arg)
1574 {
1575         return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1576                            arg);
1577 }
1578
1579
1580 // ******************************************************************************************
1581 //   Mixer file operations struct.
1582 // ******************************************************************************************
1583 static const struct file_operations cs4297a_mixer_fops = {
1584         .owner          = THIS_MODULE,
1585         .llseek         = no_llseek,
1586         .ioctl          = cs4297a_ioctl_mixdev,
1587         .open           = cs4297a_open_mixdev,
1588         .release        = cs4297a_release_mixdev,
1589 };
1590
1591 // ---------------------------------------------------------------------
1592
1593
1594 static int drain_adc(struct cs4297a_state *s, int nonblock)
1595 {
1596         /* This routine serves no purpose currently - any samples
1597            sitting in the receive queue will just be processed by the
1598            background consumer.  This would be different if DMA
1599            actually stopped when there were no clients. */
1600         return 0;
1601 }
1602
1603 static int drain_dac(struct cs4297a_state *s, int nonblock)
1604 {
1605         DECLARE_WAITQUEUE(wait, current);
1606         unsigned long flags;
1607         unsigned hwptr;
1608         unsigned tmo;
1609         int count;
1610
1611         if (s->dma_dac.mapped)
1612                 return 0;
1613         if (nonblock)
1614                 return -EBUSY;
1615         add_wait_queue(&s->dma_dac.wait, &wait);
1616         while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1617                (s->dma_dac.count > 0)) {
1618                 if (!signal_pending(current)) {
1619                         set_current_state(TASK_INTERRUPTIBLE);
1620                         /* XXXKW is this calculation working? */
1621                         tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1622                         schedule_timeout(tmo + 1);
1623                 } else {
1624                         /* XXXKW do I care if there is a signal pending? */
1625                 }
1626         }
1627         spin_lock_irqsave(&s->lock, flags);
1628         /* Reset the bookkeeping */
1629         hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1630                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1631         s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1632         spin_unlock_irqrestore(&s->lock, flags);
1633         remove_wait_queue(&s->dma_dac.wait, &wait);
1634         current->state = TASK_RUNNING;
1635         return 0;
1636 }
1637
1638
1639 // ---------------------------------------------------------------------
1640
1641 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1642                            loff_t * ppos)
1643 {
1644         struct cs4297a_state *s =
1645             (struct cs4297a_state *) file->private_data;
1646         ssize_t ret;
1647         unsigned long flags;
1648         int cnt, count_fr, cnt_by;
1649         unsigned copied = 0;
1650
1651         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1652                   printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1653
1654         VALIDATE_STATE(s);
1655         if (s->dma_adc.mapped)
1656                 return -ENXIO;
1657         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1658                 return ret;
1659         if (!access_ok(VERIFY_WRITE, buffer, count))
1660                 return -EFAULT;
1661         ret = 0;
1662 //
1663 // "count" is the amount of bytes to read (from app), is decremented each loop
1664 //      by the amount of bytes that have been returned to the user buffer.
1665 // "cnt" is the running total of each read from the buffer (changes each loop)
1666 // "buffer" points to the app's buffer
1667 // "ret" keeps a running total of the amount of bytes that have been copied
1668 //      to the user buffer.
1669 // "copied" is the total bytes copied into the user buffer for each loop.
1670 //
1671         while (count > 0) {
1672                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1673                         "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1674                                 count, s->dma_adc.count,
1675                                 s->dma_adc.swptr, s->dma_adc.hwptr));
1676                 spin_lock_irqsave(&s->lock, flags);
1677
1678                 /* cnt will be the number of available samples (16-bit
1679                    stereo); it starts out as the maxmimum consequetive
1680                    samples */
1681                 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1682                 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1683
1684                 // dma_adc.count is the current total bytes that have not been read.
1685                 // if the amount of unread bytes from the current sw pointer to the
1686                 // end of the buffer is greater than the current total bytes that
1687                 // have not been read, then set the "cnt" (unread bytes) to the
1688                 // amount of unread bytes.
1689
1690                 if (count_fr < cnt)
1691                         cnt = count_fr;
1692                 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1693                 spin_unlock_irqrestore(&s->lock, flags);
1694                 //
1695                 // if we are converting from 8/16 then we need to copy
1696                 // twice the number of 16 bit bytes then 8 bit bytes.
1697                 //
1698                 if (s->conversion) {
1699                         if (cnt_by > (count * 2)) {
1700                                 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1701                                 cnt_by = count * 2;
1702                         }
1703                 } else {
1704                         if (cnt_by > count) {
1705                                 cnt = count / FRAME_SAMPLE_BYTES;
1706                                 cnt_by = count;
1707                         }
1708                 }
1709                 //
1710                 // "cnt" NOW is the smaller of the amount that will be read,
1711                 // and the amount that is requested in this read (or partial).
1712                 // if there are no bytes in the buffer to read, then start the
1713                 // ADC and wait for the interrupt handler to wake us up.
1714                 //
1715                 if (cnt <= 0) {
1716
1717                         // start up the dma engine and then continue back to the top of
1718                         // the loop when wake up occurs.
1719                         start_adc(s);
1720                         if (file->f_flags & O_NONBLOCK)
1721                                 return ret ? ret : -EAGAIN;
1722                         interruptible_sleep_on(&s->dma_adc.wait);
1723                         if (signal_pending(current))
1724                                 return ret ? ret : -ERESTARTSYS;
1725                         continue;
1726                 }
1727                 // there are bytes in the buffer to read.
1728                 // copy from the hw buffer over to the user buffer.
1729                 // user buffer is designated by "buffer"
1730                 // virtual address to copy from is dma_buf+swptr
1731                 // the "cnt" is the number of bytes to read.
1732
1733                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1734                         "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1735                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1736                          " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1737                                  s->dma_adc.sbufsz, s->dma_adc.count,
1738                                  (unsigned) buffer, ret));
1739
1740                 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1741                         return ret ? ret : -EFAULT;
1742                 copied = cnt_by;
1743
1744                 /* Return the descriptors */
1745                 spin_lock_irqsave(&s->lock, flags);
1746                 CS_DBGOUT(CS_FUNCTION, 2,
1747                           printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1748                 s->dma_adc.count -= cnt_by;
1749                 s->dma_adc.sb_swptr += cnt * 2;
1750                 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1751                         s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1752                 spin_unlock_irqrestore(&s->lock, flags);
1753                 count -= copied;
1754                 buffer += copied;
1755                 ret += copied;
1756                 start_adc(s);
1757         }
1758         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1759                   printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1760         return ret;
1761 }
1762
1763
1764 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1765                             size_t count, loff_t * ppos)
1766 {
1767         struct cs4297a_state *s =
1768             (struct cs4297a_state *) file->private_data;
1769         ssize_t ret;
1770         unsigned long flags;
1771         unsigned swptr, hwptr;
1772         int cnt;
1773
1774         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1775                   printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1776                          count));
1777         VALIDATE_STATE(s);
1778
1779         if (s->dma_dac.mapped)
1780                 return -ENXIO;
1781         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1782                 return ret;
1783         if (!access_ok(VERIFY_READ, buffer, count))
1784                 return -EFAULT;
1785         ret = 0;
1786         while (count > 0) {
1787                 serdma_t *d = &s->dma_dac;
1788                 int copy_cnt;
1789                 u32 *s_tmpl;
1790                 u32 *t_tmpl;
1791                 u32 left, right;
1792                 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1793
1794                 /* XXXXXX this is broken for BLOAT_FACTOR */
1795                 spin_lock_irqsave(&s->lock, flags);
1796                 if (d->count < 0) {
1797                         d->count = 0;
1798                         d->swptr = d->hwptr;
1799                 }
1800                 if (d->underrun) {
1801                         d->underrun = 0;
1802                         hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1803                                              d->descrtab_phys) / sizeof(serdma_descr_t));
1804                         d->swptr = d->hwptr = hwptr;
1805                 }
1806                 swptr = d->swptr;
1807                 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1808                 /* Will this write fill up the buffer? */
1809                 if (d->count + cnt > d->sbufsz)
1810                         cnt = d->sbufsz - d->count;
1811                 spin_unlock_irqrestore(&s->lock, flags);
1812                 if (cnt > count)
1813                         cnt = count;
1814                 if (cnt <= 0) {
1815                         start_dac(s);
1816                         if (file->f_flags & O_NONBLOCK)
1817                                 return ret ? ret : -EAGAIN;
1818                         interruptible_sleep_on(&d->wait);
1819                         if (signal_pending(current))
1820                                 return ret ? ret : -ERESTARTSYS;
1821                         continue;
1822                 }
1823                 if (copy_from_user(d->sample_buf, buffer, cnt))
1824                         return ret ? ret : -EFAULT;
1825
1826                 copy_cnt = cnt;
1827                 s_tmpl = (u32 *)d->sample_buf;
1828                 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1829
1830                 /* XXXKW assuming 16-bit stereo! */
1831                 do {
1832                         u32 tmp;
1833
1834                         t_tmpl[0] = cpu_to_be32(0x98000000);
1835
1836                         tmp = be32_to_cpu(s_tmpl[0]);
1837                         left = tmp & 0xffff;
1838                         right = tmp >> 16;
1839                         if (swap) {
1840                                 left = swab16(left);
1841                                 right = swab16(right);
1842                         }
1843                         t_tmpl[1] = cpu_to_be32(left >> 8);
1844                         t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1845                                                 (right << 4));
1846
1847                         s_tmpl++;
1848                         t_tmpl += 8;
1849                         copy_cnt -= 4;
1850                 } while (copy_cnt);
1851
1852                 /* Mux in any pending read/write accesses */
1853                 if (s->reg_request) {
1854                         *(u64 *)(d->dma_buf + (swptr * 4)) |=
1855                                 cpu_to_be64(s->reg_request);
1856                         s->reg_request = 0;
1857                         wake_up(&s->dma_dac.reg_wait);
1858                 }
1859
1860                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1861                           printk(KERN_INFO
1862                                  "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1863
1864                 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1865                 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1866                 spin_lock_irqsave(&s->lock, flags);
1867                 d->swptr = swptr;
1868                 d->count += cnt;
1869                 d->endcleared = 0;
1870                 spin_unlock_irqrestore(&s->lock, flags);
1871                 count -= cnt;
1872                 buffer += cnt;
1873                 ret += cnt;
1874                 start_dac(s);
1875         }
1876         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1877                   printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1878         return ret;
1879 }
1880
1881
1882 static unsigned int cs4297a_poll(struct file *file,
1883                                 struct poll_table_struct *wait)
1884 {
1885         struct cs4297a_state *s =
1886             (struct cs4297a_state *) file->private_data;
1887         unsigned long flags;
1888         unsigned int mask = 0;
1889
1890         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1891                   printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1892         VALIDATE_STATE(s);
1893         if (file->f_mode & FMODE_WRITE) {
1894                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1895                           printk(KERN_INFO
1896                                  "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1897                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1898                         return 0;
1899                 poll_wait(file, &s->dma_dac.wait, wait);
1900         }
1901         if (file->f_mode & FMODE_READ) {
1902                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1903                           printk(KERN_INFO
1904                                  "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1905                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1906                         return 0;
1907                 poll_wait(file, &s->dma_adc.wait, wait);
1908         }
1909         spin_lock_irqsave(&s->lock, flags);
1910         cs4297a_update_ptr(s,CS_FALSE);
1911         if (file->f_mode & FMODE_WRITE) {
1912                 if (s->dma_dac.mapped) {
1913                         if (s->dma_dac.count >=
1914                             (signed) s->dma_dac.fragsize) {
1915                                 if (s->dma_dac.wakeup)
1916                                         mask |= POLLOUT | POLLWRNORM;
1917                                 else
1918                                         mask = 0;
1919                                 s->dma_dac.wakeup = 0;
1920                         }
1921                 } else {
1922                         if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1923                                 mask |= POLLOUT | POLLWRNORM;
1924                 }
1925         } else if (file->f_mode & FMODE_READ) {
1926                 if (s->dma_adc.mapped) {
1927                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1928                                 mask |= POLLIN | POLLRDNORM;
1929                 } else {
1930                         if (s->dma_adc.count > 0)
1931                                 mask |= POLLIN | POLLRDNORM;
1932                 }
1933         }
1934         spin_unlock_irqrestore(&s->lock, flags);
1935         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1936                   printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1937                          mask));
1938         return mask;
1939 }
1940
1941
1942 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1943 {
1944         /* XXXKW currently no mmap support */
1945         return -EINVAL;
1946         return 0;
1947 }
1948
1949
1950 static int cs4297a_ioctl(struct inode *inode, struct file *file,
1951                         unsigned int cmd, unsigned long arg)
1952 {
1953         struct cs4297a_state *s =
1954             (struct cs4297a_state *) file->private_data;
1955         unsigned long flags;
1956         audio_buf_info abinfo;
1957         count_info cinfo;
1958         int val, mapped, ret;
1959
1960         CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1961                  "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1962                          (unsigned) file, cmd));
1963 #if CSDEBUG
1964         cs_printioctl(cmd);
1965 #endif
1966         VALIDATE_STATE(s);
1967         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1968             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1969         switch (cmd) {
1970         case OSS_GETVERSION:
1971                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1972                         "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1973                                  SOUND_VERSION));
1974                 return put_user(SOUND_VERSION, (int *) arg);
1975
1976         case SNDCTL_DSP_SYNC:
1977                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1978                          "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1979                 if (file->f_mode & FMODE_WRITE)
1980                         return drain_dac(s,
1981                                          0 /*file->f_flags & O_NONBLOCK */
1982                                          );
1983                 return 0;
1984
1985         case SNDCTL_DSP_SETDUPLEX:
1986                 return 0;
1987
1988         case SNDCTL_DSP_GETCAPS:
1989                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1990                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
1991                                 (int *) arg);
1992
1993         case SNDCTL_DSP_RESET:
1994                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1995                          "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
1996                 if (file->f_mode & FMODE_WRITE) {
1997                         stop_dac(s);
1998                         synchronize_irq(s->irq);
1999                         s->dma_dac.count = s->dma_dac.total_bytes =
2000                                 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2001                         s->dma_dac.swptr = s->dma_dac.hwptr =
2002                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2003                                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2004                 }
2005                 if (file->f_mode & FMODE_READ) {
2006                         stop_adc(s);
2007                         synchronize_irq(s->irq);
2008                         s->dma_adc.count = s->dma_adc.total_bytes =
2009                                 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2010                         s->dma_adc.swptr = s->dma_adc.hwptr =
2011                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2012                                        s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2013                 }
2014                 return 0;
2015
2016         case SNDCTL_DSP_SPEED:
2017                 if (get_user(val, (int *) arg))
2018                         return -EFAULT;
2019                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2020                          "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2021                 val = 48000;
2022                 return put_user(val, (int *) arg);
2023
2024         case SNDCTL_DSP_STEREO:
2025                 if (get_user(val, (int *) arg))
2026                         return -EFAULT;
2027                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2028                          "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2029                 if (file->f_mode & FMODE_READ) {
2030                         stop_adc(s);
2031                         s->dma_adc.ready = 0;
2032                         s->prop_adc.channels = val ? 2 : 1;
2033                 }
2034                 if (file->f_mode & FMODE_WRITE) {
2035                         stop_dac(s);
2036                         s->dma_dac.ready = 0;
2037                         s->prop_dac.channels = val ? 2 : 1;
2038                 }
2039                 return 0;
2040
2041         case SNDCTL_DSP_CHANNELS:
2042                 if (get_user(val, (int *) arg))
2043                         return -EFAULT;
2044                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2045                          "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2046                                  val));
2047                 if (val != 0) {
2048                         if (file->f_mode & FMODE_READ) {
2049                                 stop_adc(s);
2050                                 s->dma_adc.ready = 0;
2051                                 if (val >= 2)
2052                                         s->prop_adc.channels = 2;
2053                                 else
2054                                         s->prop_adc.channels = 1;
2055                         }
2056                         if (file->f_mode & FMODE_WRITE) {
2057                                 stop_dac(s);
2058                                 s->dma_dac.ready = 0;
2059                                 if (val >= 2)
2060                                         s->prop_dac.channels = 2;
2061                                 else
2062                                         s->prop_dac.channels = 1;
2063                         }
2064                 }
2065
2066                 if (file->f_mode & FMODE_WRITE)
2067                         val = s->prop_dac.channels;
2068                 else if (file->f_mode & FMODE_READ)
2069                         val = s->prop_adc.channels;
2070
2071                 return put_user(val, (int *) arg);
2072
2073         case SNDCTL_DSP_GETFMTS:        // Returns a mask
2074                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2075                         "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2076                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2077                                  AFMT_U8));
2078                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2079                                 AFMT_U8, (int *) arg);
2080
2081         case SNDCTL_DSP_SETFMT:
2082                 if (get_user(val, (int *) arg))
2083                         return -EFAULT;
2084                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2085                          "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2086                                  val));
2087                 if (val != AFMT_QUERY) {
2088                         if (file->f_mode & FMODE_READ) {
2089                                 stop_adc(s);
2090                                 s->dma_adc.ready = 0;
2091                                 if (val != AFMT_S16_LE
2092                                     && val != AFMT_U16_LE && val != AFMT_S8
2093                                     && val != AFMT_U8)
2094                                         val = AFMT_U8;
2095                                 s->prop_adc.fmt = val;
2096                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2097                         }
2098                         if (file->f_mode & FMODE_WRITE) {
2099                                 stop_dac(s);
2100                                 s->dma_dac.ready = 0;
2101                                 if (val != AFMT_S16_LE
2102                                     && val != AFMT_U16_LE && val != AFMT_S8
2103                                     && val != AFMT_U8)
2104                                         val = AFMT_U8;
2105                                 s->prop_dac.fmt = val;
2106                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2107                         }
2108                 } else {
2109                         if (file->f_mode & FMODE_WRITE)
2110                                 val = s->prop_dac.fmt_original;
2111                         else if (file->f_mode & FMODE_READ)
2112                                 val = s->prop_adc.fmt_original;
2113                 }
2114                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2115                   "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2116                         val));
2117                 return put_user(val, (int *) arg);
2118
2119         case SNDCTL_DSP_POST:
2120                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2121                          "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2122                 return 0;
2123
2124         case SNDCTL_DSP_GETTRIGGER:
2125                 val = 0;
2126                 if (file->f_mode & s->ena & FMODE_READ)
2127                         val |= PCM_ENABLE_INPUT;
2128                 if (file->f_mode & s->ena & FMODE_WRITE)
2129                         val |= PCM_ENABLE_OUTPUT;
2130                 return put_user(val, (int *) arg);
2131
2132         case SNDCTL_DSP_SETTRIGGER:
2133                 if (get_user(val, (int *) arg))
2134                         return -EFAULT;
2135                 if (file->f_mode & FMODE_READ) {
2136                         if (val & PCM_ENABLE_INPUT) {
2137                                 if (!s->dma_adc.ready
2138                                     && (ret = prog_dmabuf_adc(s)))
2139                                         return ret;
2140                                 start_adc(s);
2141                         } else
2142                                 stop_adc(s);
2143                 }
2144                 if (file->f_mode & FMODE_WRITE) {
2145                         if (val & PCM_ENABLE_OUTPUT) {
2146                                 if (!s->dma_dac.ready
2147                                     && (ret = prog_dmabuf_dac(s)))
2148                                         return ret;
2149                                 start_dac(s);
2150                         } else
2151                                 stop_dac(s);
2152                 }
2153                 return 0;
2154
2155         case SNDCTL_DSP_GETOSPACE:
2156                 if (!(file->f_mode & FMODE_WRITE))
2157                         return -EINVAL;
2158                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2159                         return val;
2160                 spin_lock_irqsave(&s->lock, flags);
2161                 cs4297a_update_ptr(s,CS_FALSE);
2162                 abinfo.fragsize = s->dma_dac.fragsize;
2163                 if (s->dma_dac.mapped)
2164                         abinfo.bytes = s->dma_dac.sbufsz;
2165                 else
2166                         abinfo.bytes =
2167                             s->dma_dac.sbufsz - s->dma_dac.count;
2168                 abinfo.fragstotal = s->dma_dac.numfrag;
2169                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2170                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2171                         "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2172                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2173                                 abinfo.fragments));
2174                 spin_unlock_irqrestore(&s->lock, flags);
2175                 return copy_to_user((void *) arg, &abinfo,
2176                                     sizeof(abinfo)) ? -EFAULT : 0;
2177
2178         case SNDCTL_DSP_GETISPACE:
2179                 if (!(file->f_mode & FMODE_READ))
2180                         return -EINVAL;
2181                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2182                         return val;
2183                 spin_lock_irqsave(&s->lock, flags);
2184                 cs4297a_update_ptr(s,CS_FALSE);
2185                 if (s->conversion) {
2186                         abinfo.fragsize = s->dma_adc.fragsize / 2;
2187                         abinfo.bytes = s->dma_adc.count / 2;
2188                         abinfo.fragstotal = s->dma_adc.numfrag;
2189                         abinfo.fragments =
2190                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
2191                 } else {
2192                         abinfo.fragsize = s->dma_adc.fragsize;
2193                         abinfo.bytes = s->dma_adc.count;
2194                         abinfo.fragstotal = s->dma_adc.numfrag;
2195                         abinfo.fragments =
2196                             abinfo.bytes >> s->dma_adc.fragshift;
2197                 }
2198                 spin_unlock_irqrestore(&s->lock, flags);
2199                 return copy_to_user((void *) arg, &abinfo,
2200                                     sizeof(abinfo)) ? -EFAULT : 0;
2201
2202         case SNDCTL_DSP_NONBLOCK:
2203                 spin_lock(&file->f_lock);
2204                 file->f_flags |= O_NONBLOCK;
2205                 spin_unlock(&file->f_lock);
2206                 return 0;
2207
2208         case SNDCTL_DSP_GETODELAY:
2209                 if (!(file->f_mode & FMODE_WRITE))
2210                         return -EINVAL;
2211                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2212                         return 0;
2213                 spin_lock_irqsave(&s->lock, flags);
2214                 cs4297a_update_ptr(s,CS_FALSE);
2215                 val = s->dma_dac.count;
2216                 spin_unlock_irqrestore(&s->lock, flags);
2217                 return put_user(val, (int *) arg);
2218
2219         case SNDCTL_DSP_GETIPTR:
2220                 if (!(file->f_mode & FMODE_READ))
2221                         return -EINVAL;
2222                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2223                         return 0;
2224                 spin_lock_irqsave(&s->lock, flags);
2225                 cs4297a_update_ptr(s,CS_FALSE);
2226                 cinfo.bytes = s->dma_adc.total_bytes;
2227                 if (s->dma_adc.mapped) {
2228                         cinfo.blocks =
2229                             (cinfo.bytes >> s->dma_adc.fragshift) -
2230                             s->dma_adc.blocks;
2231                         s->dma_adc.blocks =
2232                             cinfo.bytes >> s->dma_adc.fragshift;
2233                 } else {
2234                         if (s->conversion) {
2235                                 cinfo.blocks =
2236                                     s->dma_adc.count /
2237                                     2 >> (s->dma_adc.fragshift - 1);
2238                         } else
2239                                 cinfo.blocks =
2240                                     s->dma_adc.count >> s->dma_adc.
2241                                     fragshift;
2242                 }
2243                 if (s->conversion)
2244                         cinfo.ptr = s->dma_adc.hwptr / 2;
2245                 else
2246                         cinfo.ptr = s->dma_adc.hwptr;
2247                 if (s->dma_adc.mapped)
2248                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
2249                 spin_unlock_irqrestore(&s->lock, flags);
2250                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2251
2252         case SNDCTL_DSP_GETOPTR:
2253                 if (!(file->f_mode & FMODE_WRITE))
2254                         return -EINVAL;
2255                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2256                         return 0;
2257                 spin_lock_irqsave(&s->lock, flags);
2258                 cs4297a_update_ptr(s,CS_FALSE);
2259                 cinfo.bytes = s->dma_dac.total_bytes;
2260                 if (s->dma_dac.mapped) {
2261                         cinfo.blocks =
2262                             (cinfo.bytes >> s->dma_dac.fragshift) -
2263                             s->dma_dac.blocks;
2264                         s->dma_dac.blocks =
2265                             cinfo.bytes >> s->dma_dac.fragshift;
2266                 } else {
2267                         cinfo.blocks =
2268                             s->dma_dac.count >> s->dma_dac.fragshift;
2269                 }
2270                 cinfo.ptr = s->dma_dac.hwptr;
2271                 if (s->dma_dac.mapped)
2272                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
2273                 spin_unlock_irqrestore(&s->lock, flags);
2274                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2275
2276         case SNDCTL_DSP_GETBLKSIZE:
2277                 if (file->f_mode & FMODE_WRITE) {
2278                         if ((val = prog_dmabuf_dac(s)))
2279                                 return val;
2280                         return put_user(s->dma_dac.fragsize, (int *) arg);
2281                 }
2282                 if ((val = prog_dmabuf_adc(s)))
2283                         return val;
2284                 if (s->conversion)
2285                         return put_user(s->dma_adc.fragsize / 2,
2286                                         (int *) arg);
2287                 else
2288                         return put_user(s->dma_adc.fragsize, (int *) arg);
2289
2290         case SNDCTL_DSP_SETFRAGMENT:
2291                 if (get_user(val, (int *) arg))
2292                         return -EFAULT;
2293                 return 0;       // Say OK, but do nothing.
2294
2295         case SNDCTL_DSP_SUBDIVIDE:
2296                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2297                     || (file->f_mode & FMODE_WRITE
2298                         && s->dma_dac.subdivision)) return -EINVAL;
2299                 if (get_user(val, (int *) arg))
2300                         return -EFAULT;
2301                 if (val != 1 && val != 2 && val != 4)
2302                         return -EINVAL;
2303                 if (file->f_mode & FMODE_READ)
2304                         s->dma_adc.subdivision = val;
2305                 else if (file->f_mode & FMODE_WRITE)
2306                         s->dma_dac.subdivision = val;
2307                 return 0;
2308
2309         case SOUND_PCM_READ_RATE:
2310                 if (file->f_mode & FMODE_READ)
2311                         return put_user(s->prop_adc.rate, (int *) arg);
2312                 else if (file->f_mode & FMODE_WRITE)
2313                         return put_user(s->prop_dac.rate, (int *) arg);
2314
2315         case SOUND_PCM_READ_CHANNELS:
2316                 if (file->f_mode & FMODE_READ)
2317                         return put_user(s->prop_adc.channels, (int *) arg);
2318                 else if (file->f_mode & FMODE_WRITE)
2319                         return put_user(s->prop_dac.channels, (int *) arg);
2320
2321         case SOUND_PCM_READ_BITS:
2322                 if (file->f_mode & FMODE_READ)
2323                         return
2324                             put_user(
2325                                      (s->prop_adc.
2326                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2327                                      (int *) arg);
2328                 else if (file->f_mode & FMODE_WRITE)
2329                         return
2330                             put_user(
2331                                      (s->prop_dac.
2332                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2333                                      (int *) arg);
2334
2335         case SOUND_PCM_WRITE_FILTER:
2336         case SNDCTL_DSP_SETSYNCRO:
2337         case SOUND_PCM_READ_FILTER:
2338                 return -EINVAL;
2339         }
2340         return mixer_ioctl(s, cmd, arg);
2341 }
2342
2343
2344 static int cs4297a_release(struct inode *inode, struct file *file)
2345 {
2346         struct cs4297a_state *s =
2347             (struct cs4297a_state *) file->private_data;
2348
2349         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2350                  "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2351                          (unsigned) inode, (unsigned) file, file->f_mode));
2352         VALIDATE_STATE(s);
2353
2354         if (file->f_mode & FMODE_WRITE) {
2355                 drain_dac(s, file->f_flags & O_NONBLOCK);
2356                 mutex_lock(&s->open_sem_dac);
2357                 stop_dac(s);
2358                 dealloc_dmabuf(s, &s->dma_dac);
2359                 s->open_mode &= ~FMODE_WRITE;
2360                 mutex_unlock(&s->open_sem_dac);
2361                 wake_up(&s->open_wait_dac);
2362         }
2363         if (file->f_mode & FMODE_READ) {
2364                 drain_adc(s, file->f_flags & O_NONBLOCK);
2365                 mutex_lock(&s->open_sem_adc);
2366                 stop_adc(s);
2367                 dealloc_dmabuf(s, &s->dma_adc);
2368                 s->open_mode &= ~FMODE_READ;
2369                 mutex_unlock(&s->open_sem_adc);
2370                 wake_up(&s->open_wait_adc);
2371         }
2372         return 0;
2373 }
2374
2375 static int cs4297a_open(struct inode *inode, struct file *file)
2376 {
2377         int minor = iminor(inode);
2378         struct cs4297a_state *s=NULL;
2379         struct list_head *entry;
2380
2381         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2382                 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2383                         (unsigned) inode, (unsigned) file, file->f_mode));
2384         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2385                 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2386
2387         list_for_each(entry, &cs4297a_devs)
2388         {
2389                 s = list_entry(entry, struct cs4297a_state, list);
2390
2391                 if (!((s->dev_audio ^ minor) & ~0xf))
2392                         break;
2393         }
2394         if (entry == &cs4297a_devs)
2395                 return -ENODEV;
2396         if (!s) {
2397                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2398                         "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2399                 return -ENODEV;
2400         }
2401         VALIDATE_STATE(s);
2402         file->private_data = s;
2403
2404         // wait for device to become free
2405         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2406                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2407                          "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2408                 return -ENODEV;
2409         }
2410         if (file->f_mode & FMODE_WRITE) {
2411                 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2412                         printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2413                         while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2414                                 ;
2415                 }
2416
2417                 mutex_lock(&s->open_sem_dac);
2418                 while (s->open_mode & FMODE_WRITE) {
2419                         if (file->f_flags & O_NONBLOCK) {
2420                                 mutex_unlock(&s->open_sem_dac);
2421                                 return -EBUSY;
2422                         }
2423                         mutex_unlock(&s->open_sem_dac);
2424                         interruptible_sleep_on(&s->open_wait_dac);
2425
2426                         if (signal_pending(current)) {
2427                                 printk("open - sig pending\n");
2428                                 return -ERESTARTSYS;
2429                         }
2430                         mutex_lock(&s->open_sem_dac);
2431                 }
2432         }
2433         if (file->f_mode & FMODE_READ) {
2434                 mutex_lock(&s->open_sem_adc);
2435                 while (s->open_mode & FMODE_READ) {
2436                         if (file->f_flags & O_NONBLOCK) {
2437                                 mutex_unlock(&s->open_sem_adc);
2438                                 return -EBUSY;
2439                         }
2440                         mutex_unlock(&s->open_sem_adc);
2441                         interruptible_sleep_on(&s->open_wait_adc);
2442
2443                         if (signal_pending(current)) {
2444                                 printk("open - sig pending\n");
2445                                 return -ERESTARTSYS;
2446                         }
2447                         mutex_lock(&s->open_sem_adc);
2448                 }
2449         }
2450         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2451         if (file->f_mode & FMODE_READ) {
2452                 s->prop_adc.fmt = AFMT_S16_BE;
2453                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2454                 s->prop_adc.channels = 2;
2455                 s->prop_adc.rate = 48000;
2456                 s->conversion = 0;
2457                 s->ena &= ~FMODE_READ;
2458                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2459                     s->dma_adc.subdivision = 0;
2460                 mutex_unlock(&s->open_sem_adc);
2461
2462                 if (prog_dmabuf_adc(s)) {
2463                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2464                                 "cs4297a: adc Program dmabufs failed.\n"));
2465                         cs4297a_release(inode, file);
2466                         return -ENOMEM;
2467                 }
2468         }
2469         if (file->f_mode & FMODE_WRITE) {
2470                 s->prop_dac.fmt = AFMT_S16_BE;
2471                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2472                 s->prop_dac.channels = 2;
2473                 s->prop_dac.rate = 48000;
2474                 s->conversion = 0;
2475                 s->ena &= ~FMODE_WRITE;
2476                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2477                     s->dma_dac.subdivision = 0;
2478                 mutex_unlock(&s->open_sem_dac);
2479
2480                 if (prog_dmabuf_dac(s)) {
2481                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2482                                 "cs4297a: dac Program dmabufs failed.\n"));
2483                         cs4297a_release(inode, file);
2484                         return -ENOMEM;
2485                 }
2486         }
2487         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2488                   printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2489         return nonseekable_open(inode, file);
2490 }
2491
2492
2493 // ******************************************************************************************
2494 //   Wave (audio) file operations struct.
2495 // ******************************************************************************************
2496 static const struct file_operations cs4297a_audio_fops = {
2497         .owner          = THIS_MODULE,
2498         .llseek         = no_llseek,
2499         .read           = cs4297a_read,
2500         .write          = cs4297a_write,
2501         .poll           = cs4297a_poll,
2502         .ioctl          = cs4297a_ioctl,
2503         .mmap           = cs4297a_mmap,
2504         .open           = cs4297a_open,
2505         .release        = cs4297a_release,
2506 };
2507
2508 static void cs4297a_interrupt(int irq, void *dev_id)
2509 {
2510         struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2511         u32 status;
2512
2513         status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2514
2515         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2516                  "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2517
2518 #if 0
2519         /* XXXKW what check *should* be done here? */
2520         if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2521                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2522                 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2523                 return;
2524         }
2525 #endif
2526
2527         if (status & M_SYNCSER_RX_SYNC_ERR) {
2528                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2529                 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2530                 return;
2531         }
2532
2533         if (status & M_SYNCSER_RX_OVERRUN) {
2534                 int newptr, i;
2535                 s->stats.rx_ovrrn++;
2536                 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2537
2538                 /* Fix things up: get the receive descriptor pool
2539                    clean and give them back to the hardware */
2540                 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2541                         ;
2542                 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2543                                      s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2544                 for (i=0; i<DMA_DESCR; i++) {
2545                         s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2546                 }
2547                 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2548                 s->dma_adc.count = 0;
2549                 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2550                 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2551         }
2552
2553         spin_lock(&s->lock);
2554         cs4297a_update_ptr(s,CS_TRUE);
2555         spin_unlock(&s->lock);
2556
2557         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2558                   "cs4297a: cs4297a_interrupt()-\n"));
2559 }
2560
2561 #if 0
2562 static struct initvol {
2563         int mixch;
2564         int vol;
2565 } initvol[] __initdata = {
2566
2567         {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2568         {SOUND_MIXER_WRITE_PCM, 0x4040},
2569         {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2570         {SOUND_MIXER_WRITE_CD, 0x4040},
2571         {SOUND_MIXER_WRITE_LINE, 0x4040},
2572         {SOUND_MIXER_WRITE_LINE1, 0x4040},
2573         {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2574         {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2575         {SOUND_MIXER_WRITE_MIC, 0x0000}
2576 };
2577 #endif
2578
2579 static int __init cs4297a_init(void)
2580 {
2581         struct cs4297a_state *s;
2582         u32 pwr, id;
2583         mm_segment_t fs;
2584         int rval;
2585 #ifndef CONFIG_BCM_CS4297A_CSWARM
2586         u64 cfg;
2587         int mdio_val;
2588 #endif
2589
2590         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2591                 "cs4297a: cs4297a_init_module()+ \n"));
2592
2593 #ifndef CONFIG_BCM_CS4297A_CSWARM
2594         mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2595                 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2596
2597         /* Check syscfg for synchronous serial on port 1 */
2598         cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2599         if (!(cfg & M_SYS_SER1_ENABLE)) {
2600                 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2601                 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2602                 if (!(cfg & M_SYS_SER1_ENABLE)) {
2603                   printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2604                   return -1;
2605                 }
2606
2607                 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2608
2609                 /* Force the codec (on SWARM) to reset by clearing
2610                    GENO, preserving MDIO (no effect on CSWARM) */
2611                 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2612                 udelay(10);
2613         }
2614
2615         /* Now set GENO */
2616         __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2617         /* Give the codec some time to finish resetting (start the bit clock) */
2618         udelay(100);
2619 #endif
2620
2621         if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2622                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2623                       "cs4297a: probe() no memory for state struct.\n"));
2624                 return -1;
2625         }
2626         s->magic = CS4297a_MAGIC;
2627         init_waitqueue_head(&s->dma_adc.wait);
2628         init_waitqueue_head(&s->dma_dac.wait);
2629         init_waitqueue_head(&s->dma_adc.reg_wait);
2630         init_waitqueue_head(&s->dma_dac.reg_wait);
2631         init_waitqueue_head(&s->open_wait);
2632         init_waitqueue_head(&s->open_wait_adc);
2633         init_waitqueue_head(&s->open_wait_dac);
2634         mutex_init(&s->open_sem_adc);
2635         mutex_init(&s->open_sem_dac);
2636         spin_lock_init(&s->lock);
2637
2638         s->irq = K_INT_SER_1;
2639
2640         if (request_irq
2641             (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2642                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2643                           printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2644                 goto err_irq;
2645         }
2646         if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2647             0) {
2648                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2649                          "cs4297a: probe() register_sound_dsp() failed.\n"));
2650                 goto err_dev1;
2651         }
2652         if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2653             0) {
2654                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2655                          "cs4297a: probe() register_sound_mixer() failed.\n"));
2656                 goto err_dev2;
2657         }
2658
2659         if (ser_init(s) || dma_init(s)) {
2660                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2661                          "cs4297a: ser_init failed.\n"));
2662                 goto err_dev3;
2663         }
2664
2665         do {
2666                 udelay(4000);
2667                 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2668         } while (!rval && (pwr != 0xf));
2669
2670         if (!rval) {
2671                 char *sb1250_duart_present;
2672
2673                 fs = get_fs();
2674                 set_fs(KERNEL_DS);
2675 #if 0
2676                 val = SOUND_MASK_LINE;
2677                 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2678                 for (i = 0; i < ARRAY_SIZE(initvol); i++) {
2679                         val = initvol[i].vol;
2680                         mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2681                 }
2682 //                cs4297a_write_ac97(s, 0x18, 0x0808);
2683 #else
2684                 //                cs4297a_write_ac97(s, 0x5e, 0x180);
2685                 cs4297a_write_ac97(s, 0x02, 0x0808);
2686                 cs4297a_write_ac97(s, 0x18, 0x0808);
2687 #endif
2688                 set_fs(fs);
2689
2690                 list_add(&s->list, &cs4297a_devs);
2691
2692                 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2693
2694                 sb1250_duart_present = symbol_get(sb1250_duart_present);
2695                 if (sb1250_duart_present)
2696                         sb1250_duart_present[1] = 0;
2697
2698                 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2699
2700                 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2701                           printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2702
2703                 return 0;
2704         }
2705
2706  err_dev3:
2707         unregister_sound_mixer(s->dev_mixer);
2708  err_dev2:
2709         unregister_sound_dsp(s->dev_audio);
2710  err_dev1:
2711         free_irq(s->irq, s);
2712  err_irq:
2713         kfree(s);
2714
2715         printk(KERN_INFO "cs4297a: initialization failed\n");
2716
2717         return -1;
2718 }
2719
2720 static void __exit cs4297a_cleanup(void)
2721 {
2722         /*
2723           XXXKW
2724            disable_irq, free_irq
2725            drain DMA queue
2726            disable DMA
2727            disable TX/RX
2728            free memory
2729         */
2730         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2731                   printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2732 }
2733
2734 // ---------------------------------------------------------------------
2735
2736 MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2737 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2738
2739 // ---------------------------------------------------------------------
2740
2741 module_init(cs4297a_init);
2742 module_exit(cs4297a_cleanup);