Merge master.kernel.org:/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
[linux-2.6] / drivers / isdn / hisax / bkm_a8.c
1 /* $Id: bkm_a8.c,v 1.22.2.4 2004/01/15 14:02:34 keil Exp $
2  *
3  * low level stuff for Scitel Quadro (4*S0, passive)
4  *
5  * Author       Roland Klabunde
6  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de>
7  * 
8  * This software may be used and distributed according to the terms
9  * of the GNU General Public License, incorporated herein by reference.
10  *
11  */
12
13
14 #include <linux/init.h>
15 #include "hisax.h"
16 #include "isac.h"
17 #include "ipac.h"
18 #include "hscx.h"
19 #include "isdnl1.h"
20 #include <linux/pci.h>
21 #include "bkm_ax.h"
22
23 #ifdef CONFIG_PCI
24
25 #define ATTEMPT_PCI_REMAPPING   /* Required for PLX rev 1 */
26
27 extern const char *CardType[];
28
29 static const char sct_quadro_revision[] = "$Revision: 1.22.2.4 $";
30
31 static const char *sct_quadro_subtypes[] =
32 {
33         "",
34         "#1",
35         "#2",
36         "#3",
37         "#4"
38 };
39
40
41 #define wordout(addr,val) outw(val,addr)
42 #define wordin(addr) inw(addr)
43
44 static inline u_char
45 readreg(unsigned int ale, unsigned int adr, u_char off)
46 {
47         register u_char ret;
48         wordout(ale, off);
49         ret = wordin(adr) & 0xFF;
50         return (ret);
51 }
52
53 static inline void
54 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
55 {
56         int i;
57         wordout(ale, off);
58         for (i = 0; i < size; i++)
59                 data[i] = wordin(adr) & 0xFF;
60 }
61
62
63 static inline void
64 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
65 {
66         wordout(ale, off);
67         wordout(adr, data);
68 }
69
70 static inline void
71 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
72 {
73         int i;
74         wordout(ale, off);
75         for (i = 0; i < size; i++)
76                 wordout(adr, data[i]);
77 }
78
79 /* Interface functions */
80
81 static u_char
82 ReadISAC(struct IsdnCardState *cs, u_char offset)
83 {
84         return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
85 }
86
87 static void
88 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
89 {
90         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
91 }
92
93 static void
94 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
95 {
96         readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
97 }
98
99 static void
100 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
101 {
102         writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
103 }
104
105
106 static u_char
107 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
108 {
109         return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
110 }
111
112 static void
113 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
114 {
115         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
116 }
117
118 /* Set the specific ipac to active */
119 static void
120 set_ipac_active(struct IsdnCardState *cs, u_int active)
121 {
122         /* set irq mask */
123         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
124                 active ? 0xc0 : 0xff);
125 }
126
127 /*
128  * fast interrupt HSCX stuff goes here
129  */
130
131 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
132         cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
133 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
134         cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
135 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
136         cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
137 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
138         cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
139
140 #include "hscx_irq.c"
141
142 static irqreturn_t
143 bkm_interrupt_ipac(int intno, void *dev_id)
144 {
145         struct IsdnCardState *cs = dev_id;
146         u_char ista, val, icnt = 5;
147         u_long flags;
148
149         spin_lock_irqsave(&cs->lock, flags);
150         ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
151         if (!(ista & 0x3f)) { /* not this IPAC */
152                 spin_unlock_irqrestore(&cs->lock, flags);
153                 return IRQ_NONE;
154         }
155       Start_IPAC:
156         if (cs->debug & L1_DEB_IPAC)
157                 debugl1(cs, "IPAC ISTA %02X", ista);
158         if (ista & 0x0f) {
159                 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
160                 if (ista & 0x01)
161                         val |= 0x01;
162                 if (ista & 0x04)
163                         val |= 0x02;
164                 if (ista & 0x08)
165                         val |= 0x04;
166                 if (val) {
167                         hscx_int_main(cs, val);
168                 }
169         }
170         if (ista & 0x20) {
171                 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
172                 if (val) {
173                         isac_interrupt(cs, val);
174                 }
175         }
176         if (ista & 0x10) {
177                 val = 0x01;
178                 isac_interrupt(cs, val);
179         }
180         ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
181         if ((ista & 0x3f) && icnt) {
182                 icnt--;
183                 goto Start_IPAC;
184         }
185         if (!icnt)
186                 printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
187                        CardType[cs->typ],
188                        sct_quadro_subtypes[cs->subtyp]);
189         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
190         writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
191         spin_unlock_irqrestore(&cs->lock, flags);
192         return IRQ_HANDLED;
193 }
194
195 static void
196 release_io_sct_quadro(struct IsdnCardState *cs)
197 {
198         release_region(cs->hw.ax.base & 0xffffffc0, 128);
199         if (cs->subtyp == SCT_1)
200                 release_region(cs->hw.ax.plx_adr, 64);
201 }
202
203 static void
204 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable)
205 {
206         if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
207                 if (bEnable)
208                         wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
209                 else
210                         wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
211         }
212 }
213
214 static void
215 reset_bkm(struct IsdnCardState *cs)
216 {
217         if (cs->subtyp == SCT_1) {
218                 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
219                 mdelay(10);
220                 /* Remove the soft reset */
221                 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
222                 mdelay(10);
223         }
224 }
225
226 static int
227 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
228 {
229         u_long flags;
230
231         switch (mt) {
232                 case CARD_RESET:
233                         spin_lock_irqsave(&cs->lock, flags);
234                         /* Disable ints */
235                         set_ipac_active(cs, 0);
236                         enable_bkm_int(cs, 0);
237                         reset_bkm(cs);
238                         spin_unlock_irqrestore(&cs->lock, flags);
239                         return (0);
240                 case CARD_RELEASE:
241                         /* Sanity */
242                         spin_lock_irqsave(&cs->lock, flags);
243                         set_ipac_active(cs, 0);
244                         enable_bkm_int(cs, 0);
245                         spin_unlock_irqrestore(&cs->lock, flags);
246                         release_io_sct_quadro(cs);
247                         return (0);
248                 case CARD_INIT:
249                         spin_lock_irqsave(&cs->lock, flags);
250                         cs->debug |= L1_DEB_IPAC;
251                         set_ipac_active(cs, 1);
252                         inithscxisac(cs, 3);
253                         /* Enable ints */
254                         enable_bkm_int(cs, 1);
255                         spin_unlock_irqrestore(&cs->lock, flags);
256                         return (0);
257                 case CARD_TEST:
258                         return (0);
259         }
260         return (0);
261 }
262
263 static int __devinit
264 sct_alloc_io(u_int adr, u_int len)
265 {
266         if (!request_region(adr, len, "scitel")) {
267                 printk(KERN_WARNING
268                         "HiSax: Scitel port %#x-%#x already in use\n",
269                         adr, adr + len);
270                 return (1);
271         }
272         return(0);
273 }
274
275 static struct pci_dev *dev_a8 __devinitdata = NULL;
276 static u16  sub_vendor_id __devinitdata = 0;
277 static u16  sub_sys_id __devinitdata = 0;
278 static u_char pci_bus __devinitdata = 0;
279 static u_char pci_device_fn __devinitdata = 0;
280 static u_char pci_irq __devinitdata = 0;
281
282 #endif /* CONFIG_PCI */
283
284 int __devinit
285 setup_sct_quadro(struct IsdnCard *card)
286 {
287 #ifdef CONFIG_PCI
288         struct IsdnCardState *cs = card->cs;
289         char tmp[64];
290         u_char pci_rev_id;
291         u_int found = 0;
292         u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
293
294         strcpy(tmp, sct_quadro_revision);
295         printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
296         if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
297                 cs->subtyp = SCT_1;     /* Preset */
298         } else
299                 return (0);
300
301         /* Identify subtype by para[0] */
302         if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
303                 cs->subtyp = card->para[0];
304         else {
305                 printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
306                         CardType[card->typ]);
307                 return (0);
308         }
309         if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
310                 (sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
311                 return (0);
312         if (cs->subtyp == SCT_1) {
313                 while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
314                         PCI_DEVICE_ID_PLX_9050, dev_a8))) {
315                         
316                         sub_vendor_id = dev_a8->subsystem_vendor;
317                         sub_sys_id = dev_a8->subsystem_device;
318                         if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
319                                 (sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
320                                 if (pci_enable_device(dev_a8))
321                                         return(0);
322                                 pci_ioaddr1 = pci_resource_start(dev_a8, 1);
323                                 pci_irq = dev_a8->irq;
324                                 pci_bus = dev_a8->bus->number;
325                                 pci_device_fn = dev_a8->devfn;
326                                 found = 1;
327                                 break;
328                         }
329                 }
330                 if (!found) {
331                         printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
332                                 CardType[card->typ],
333                                 sct_quadro_subtypes[cs->subtyp]);
334                         return (0);
335                 }
336 #ifdef ATTEMPT_PCI_REMAPPING
337 /* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
338                 pci_read_config_byte(dev_a8, PCI_REVISION_ID, &pci_rev_id);
339                 if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
340                         printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
341                                 CardType[card->typ],
342                                 sct_quadro_subtypes[cs->subtyp]);
343                         /* Restart PCI negotiation */
344                         pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, (u_int) - 1);
345                         /* Move up by 0x80 byte */
346                         pci_ioaddr1 += 0x80;
347                         pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
348                         pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, pci_ioaddr1);
349                         dev_a8->resource[ 1].start = pci_ioaddr1;
350                 }
351 #endif /* End HACK */
352         }
353         if (!pci_irq) {         /* IRQ range check ?? */
354                 printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
355                        CardType[card->typ],
356                        sct_quadro_subtypes[cs->subtyp]);
357                 return (0);
358         }
359         pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
360         pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
361         pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
362         pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
363         pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
364         if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
365                 printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
366                        CardType[card->typ],
367                        sct_quadro_subtypes[cs->subtyp]);
368                 return (0);
369         }
370         pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
371         pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
372         pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
373         pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
374         pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
375         /* Take over */
376         cs->irq = pci_irq;
377         cs->irq_flags |= IRQF_SHARED;
378         /* pci_ioaddr1 is unique to all subdevices */
379         /* pci_ioaddr2 is for the fourth subdevice only */
380         /* pci_ioaddr3 is for the third subdevice only */
381         /* pci_ioaddr4 is for the second subdevice only */
382         /* pci_ioaddr5 is for the first subdevice only */
383         cs->hw.ax.plx_adr = pci_ioaddr1;
384         /* Enter all ipac_base addresses */
385         switch(cs->subtyp) {
386                 case 1:
387                         cs->hw.ax.base = pci_ioaddr5 + 0x00;
388                         if (sct_alloc_io(pci_ioaddr1, 128))
389                                 return(0);
390                         if (sct_alloc_io(pci_ioaddr5, 64))
391                                 return(0);
392                         /* disable all IPAC */
393                         writereg(pci_ioaddr5, pci_ioaddr5 + 4,
394                                 IPAC_MASK, 0xFF);
395                         writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
396                                 IPAC_MASK, 0xFF);
397                         writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
398                                 IPAC_MASK, 0xFF);
399                         writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
400                                 IPAC_MASK, 0xFF);
401                         break;
402                 case 2:
403                         cs->hw.ax.base = pci_ioaddr4 + 0x08;
404                         if (sct_alloc_io(pci_ioaddr4, 64))
405                                 return(0);
406                         break;
407                 case 3:
408                         cs->hw.ax.base = pci_ioaddr3 + 0x10;
409                         if (sct_alloc_io(pci_ioaddr3, 64))
410                                 return(0);
411                         break;
412                 case 4:
413                         cs->hw.ax.base = pci_ioaddr2 + 0x20;
414                         if (sct_alloc_io(pci_ioaddr2, 64))
415                                 return(0);
416                         break;
417         }       
418         /* For isac and hscx data path */
419         cs->hw.ax.data_adr = cs->hw.ax.base + 4;
420
421         printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
422                CardType[card->typ],
423                sct_quadro_subtypes[cs->subtyp],
424                cs->hw.ax.plx_adr,
425                cs->hw.ax.base,
426                cs->hw.ax.data_adr,
427                cs->irq);
428
429         test_and_set_bit(HW_IPAC, &cs->HW_Flags);
430
431         cs->readisac = &ReadISAC;
432         cs->writeisac = &WriteISAC;
433         cs->readisacfifo = &ReadISACfifo;
434         cs->writeisacfifo = &WriteISACfifo;
435
436         cs->BC_Read_Reg = &ReadHSCX;
437         cs->BC_Write_Reg = &WriteHSCX;
438         cs->BC_Send_Data = &hscx_fill_fifo;
439         cs->cardmsg = &BKM_card_msg;
440         cs->irq_func = &bkm_interrupt_ipac;
441
442         printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
443                 CardType[card->typ],
444                 sct_quadro_subtypes[cs->subtyp],
445                 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
446         return (1);
447 #else
448         printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
449 #endif /* CONFIG_PCI */
450 }