Merge master.kernel.org:/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
[linux-2.6] / drivers / video / nvidia / nv_setup.c
1  /***************************************************************************\
2 |*                                                                           *|
3 |*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
4 |*                                                                           *|
5 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
6 |*     international laws.  Users and possessors of this source code are     *|
7 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
8 |*     use this code in individual and commercial software.                  *|
9 |*                                                                           *|
10 |*     Any use of this source code must include,  in the user documenta-     *|
11 |*     tion and  internal comments to the code,  notices to the end user     *|
12 |*     as follows:                                                           *|
13 |*                                                                           *|
14 |*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
15 |*                                                                           *|
16 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
17 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
18 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
19 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
20 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
21 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
22 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
23 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
24 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
25 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
26 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
27 |*                                                                           *|
28 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
29 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
30 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
31 |*     computer  software  documentation,"  as such  terms  are  used in     *|
32 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
33 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
34 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
35 |*     all U.S. Government End Users  acquire the source code  with only     *|
36 |*     those rights set forth herein.                                        *|
37 |*                                                                           *|
38  \***************************************************************************/
39
40 /*
41  * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42  * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43  * where the source code is provided "as is" without warranty of any kind.
44  * The only usage restriction is for the copyright notices to be retained
45  * whenever code is used.
46  *
47  * Antonino Daplas <adaplas@pol.net> 2005-03-11
48  */
49
50 #include <video/vga.h>
51 #include <linux/delay.h>
52 #include <linux/pci.h>
53 #include "nv_type.h"
54 #include "nv_local.h"
55 #include "nv_proto.h"
56 /*
57  * Override VGA I/O routines.
58  */
59 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
60 {
61         VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
62         VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
63 }
64 u8 NVReadCrtc(struct nvidia_par *par, u8 index)
65 {
66         VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
67         return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
68 }
69 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
70 {
71         VGA_WR08(par->PVIO, VGA_GFX_I, index);
72         VGA_WR08(par->PVIO, VGA_GFX_D, value);
73 }
74 u8 NVReadGr(struct nvidia_par *par, u8 index)
75 {
76         VGA_WR08(par->PVIO, VGA_GFX_I, index);
77         return (VGA_RD08(par->PVIO, VGA_GFX_D));
78 }
79 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
80 {
81         VGA_WR08(par->PVIO, VGA_SEQ_I, index);
82         VGA_WR08(par->PVIO, VGA_SEQ_D, value);
83 }
84 u8 NVReadSeq(struct nvidia_par *par, u8 index)
85 {
86         VGA_WR08(par->PVIO, VGA_SEQ_I, index);
87         return (VGA_RD08(par->PVIO, VGA_SEQ_D));
88 }
89 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
90 {
91         volatile u8 tmp;
92
93         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
94         if (par->paletteEnabled)
95                 index &= ~0x20;
96         else
97                 index |= 0x20;
98         VGA_WR08(par->PCIO, VGA_ATT_IW, index);
99         VGA_WR08(par->PCIO, VGA_ATT_W, value);
100 }
101 u8 NVReadAttr(struct nvidia_par *par, u8 index)
102 {
103         volatile u8 tmp;
104
105         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
106         if (par->paletteEnabled)
107                 index &= ~0x20;
108         else
109                 index |= 0x20;
110         VGA_WR08(par->PCIO, VGA_ATT_IW, index);
111         return (VGA_RD08(par->PCIO, VGA_ATT_R));
112 }
113 void NVWriteMiscOut(struct nvidia_par *par, u8 value)
114 {
115         VGA_WR08(par->PVIO, VGA_MIS_W, value);
116 }
117 u8 NVReadMiscOut(struct nvidia_par *par)
118 {
119         return (VGA_RD08(par->PVIO, VGA_MIS_R));
120 }
121 #if 0
122 void NVEnablePalette(struct nvidia_par *par)
123 {
124         volatile u8 tmp;
125
126         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
127         VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
128         par->paletteEnabled = 1;
129 }
130 void NVDisablePalette(struct nvidia_par *par)
131 {
132         volatile u8 tmp;
133
134         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
135         VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
136         par->paletteEnabled = 0;
137 }
138 #endif  /*  0  */
139 void NVWriteDacMask(struct nvidia_par *par, u8 value)
140 {
141         VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
142 }
143 #if 0
144 u8 NVReadDacMask(struct nvidia_par *par)
145 {
146         return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
147 }
148 #endif  /*  0  */
149 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
150 {
151         VGA_WR08(par->PDIO, VGA_PEL_IR, value);
152 }
153 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
154 {
155         VGA_WR08(par->PDIO, VGA_PEL_IW, value);
156 }
157 void NVWriteDacData(struct nvidia_par *par, u8 value)
158 {
159         VGA_WR08(par->PDIO, VGA_PEL_D, value);
160 }
161 u8 NVReadDacData(struct nvidia_par *par)
162 {
163         return (VGA_RD08(par->PDIO, VGA_PEL_D));
164 }
165
166 static int NVIsConnected(struct nvidia_par *par, int output)
167 {
168         volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
169         u32 reg52C, reg608;
170         int present;
171
172         if (output)
173                 PRAMDAC += 0x800;
174
175         reg52C = NV_RD32(PRAMDAC, 0x052C);
176         reg608 = NV_RD32(PRAMDAC, 0x0608);
177
178         NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
179
180         NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
181         msleep(1);
182         NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
183
184         NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
185         NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
186                 0x00001000);
187
188         msleep(1);
189
190         present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
191
192         if (present)
193                 printk("nvidiafb: CRTC%i analog found\n", output);
194         else
195                 printk("nvidiafb: CRTC%i analog not found\n", output);
196
197         NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
198                 0x0000EFFF);
199
200         NV_WR32(PRAMDAC, 0x052C, reg52C);
201         NV_WR32(PRAMDAC, 0x0608, reg608);
202
203         return present;
204 }
205
206 static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
207 {
208         if (head) {
209                 par->PCIO = par->PCIO0 + 0x2000;
210                 par->PCRTC = par->PCRTC0 + 0x800;
211                 par->PRAMDAC = par->PRAMDAC0 + 0x800;
212                 par->PDIO = par->PDIO0 + 0x2000;
213         } else {
214                 par->PCIO = par->PCIO0;
215                 par->PCRTC = par->PCRTC0;
216                 par->PRAMDAC = par->PRAMDAC0;
217                 par->PDIO = par->PDIO0;
218         }
219 }
220
221 static void nv4GetConfig(struct nvidia_par *par)
222 {
223         if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
224                 par->RamAmountKBytes =
225                     ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
226                     1024 * 2;
227         } else {
228                 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
229                 case 0:
230                         par->RamAmountKBytes = 1024 * 32;
231                         break;
232                 case 1:
233                         par->RamAmountKBytes = 1024 * 4;
234                         break;
235                 case 2:
236                         par->RamAmountKBytes = 1024 * 8;
237                         break;
238                 case 3:
239                 default:
240                         par->RamAmountKBytes = 1024 * 16;
241                         break;
242                 }
243         }
244         par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
245             14318 : 13500;
246         par->CURSOR = &par->PRAMIN[0x1E00];
247         par->MinVClockFreqKHz = 12000;
248         par->MaxVClockFreqKHz = 350000;
249 }
250
251 static void nv10GetConfig(struct nvidia_par *par)
252 {
253         struct pci_dev *dev;
254         u32 implementation = par->Chipset & 0x0ff0;
255
256 #ifdef __BIG_ENDIAN
257         /* turn on big endian register access */
258         if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
259                 NV_WR32(par->PMC, 0x0004, 0x01000001);
260                 mb();
261         }
262 #endif
263
264         dev = pci_get_bus_and_slot(0, 1);
265         if ((par->Chipset & 0xffff) == 0x01a0) {
266                 int amt = 0;
267
268                 pci_read_config_dword(dev, 0x7c, &amt);
269                 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
270         } else if ((par->Chipset & 0xffff) == 0x01f0) {
271                 int amt = 0;
272
273                 pci_read_config_dword(dev, 0x84, &amt);
274                 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
275         } else {
276                 par->RamAmountKBytes =
277                     (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
278         }
279         pci_dev_put(dev);
280
281         par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
282             14318 : 13500;
283
284         if (par->twoHeads && (implementation != 0x0110)) {
285                 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
286                         par->CrystalFreqKHz = 27000;
287         }
288
289         par->CURSOR = NULL;     /* can't set this here */
290         par->MinVClockFreqKHz = 12000;
291         par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
292 }
293
294 int NVCommonSetup(struct fb_info *info)
295 {
296         struct nvidia_par *par = info->par;
297         struct fb_var_screeninfo *var;
298         u16 implementation = par->Chipset & 0x0ff0;
299         u8 *edidA = NULL, *edidB = NULL;
300         struct fb_monspecs *monitorA, *monitorB;
301         struct fb_monspecs *monA = NULL, *monB = NULL;
302         int mobile = 0;
303         int tvA = 0;
304         int tvB = 0;
305         int FlatPanel = -1;     /* really means the CRTC is slaved */
306         int Television = 0;
307         int err = 0;
308
309         var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
310         monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
311         monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
312
313         if (!var || !monitorA || !monitorB) {
314                 err = -ENOMEM;
315                 goto done;
316         }
317
318         par->PRAMIN = par->REGS + (0x00710000 / 4);
319         par->PCRTC0 = par->REGS + (0x00600000 / 4);
320         par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
321         par->PFB = par->REGS + (0x00100000 / 4);
322         par->PFIFO = par->REGS + (0x00002000 / 4);
323         par->PGRAPH = par->REGS + (0x00400000 / 4);
324         par->PEXTDEV = par->REGS + (0x00101000 / 4);
325         par->PTIMER = par->REGS + (0x00009000 / 4);
326         par->PMC = par->REGS + (0x00000000 / 4);
327         par->FIFO = par->REGS + (0x00800000 / 4);
328
329         /* 8 bit registers */
330         par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
331         par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
332         par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
333
334         par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
335             (implementation != 0x0100) &&
336             (implementation != 0x0150) &&
337             (implementation != 0x01A0) && (implementation != 0x0200);
338
339         par->fpScaler = (par->FpScale && par->twoHeads &&
340                          (implementation != 0x0110));
341
342         par->twoStagePLL = (implementation == 0x0310) ||
343             (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
344
345         par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
346             (implementation != 0x0100);
347
348         par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
349
350         /* look for known laptop chips */
351         switch (par->Chipset & 0xffff) {
352         case 0x0112:
353         case 0x0174:
354         case 0x0175:
355         case 0x0176:
356         case 0x0177:
357         case 0x0179:
358         case 0x017C:
359         case 0x017D:
360         case 0x0186:
361         case 0x0187:
362         case 0x018D:
363         case 0x0228:
364         case 0x0286:
365         case 0x028C:
366         case 0x0316:
367         case 0x0317:
368         case 0x031A:
369         case 0x031B:
370         case 0x031C:
371         case 0x031D:
372         case 0x031E:
373         case 0x031F:
374         case 0x0324:
375         case 0x0325:
376         case 0x0328:
377         case 0x0329:
378         case 0x032C:
379         case 0x032D:
380         case 0x0347:
381         case 0x0348:
382         case 0x0349:
383         case 0x034B:
384         case 0x034C:
385         case 0x0160:
386         case 0x0166:
387         case 0x0169:
388         case 0x016B:
389         case 0x016C:
390         case 0x016D:
391         case 0x00C8:
392         case 0x00CC:
393         case 0x0144:
394         case 0x0146:
395         case 0x0147:
396         case 0x0148:
397         case 0x0098:
398         case 0x0099:
399                 mobile = 1;
400                 break;
401         default:
402                 break;
403         }
404
405         if (par->Architecture == NV_ARCH_04)
406                 nv4GetConfig(par);
407         else
408                 nv10GetConfig(par);
409
410         NVSelectHeadRegisters(par, 0);
411
412         NVLockUnlock(par, 0);
413
414         par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
415
416         par->Television = 0;
417
418         nvidia_create_i2c_busses(par);
419         if (!par->twoHeads) {
420                 par->CRTCnumber = 0;
421                 if (nvidia_probe_i2c_connector(info, 1, &edidA))
422                         nvidia_probe_of_connector(info, 1, &edidA);
423                 if (edidA && !fb_parse_edid(edidA, var)) {
424                         printk("nvidiafb: EDID found from BUS1\n");
425                         monA = monitorA;
426                         fb_edid_to_monspecs(edidA, monA);
427                         FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
428
429                         /* NV4 doesn't support FlatPanels */
430                         if ((par->Chipset & 0x0fff) <= 0x0020)
431                                 FlatPanel = 0;
432                 } else {
433                         VGA_WR08(par->PCIO, 0x03D4, 0x28);
434                         if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
435                                 VGA_WR08(par->PCIO, 0x03D4, 0x33);
436                                 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
437                                         Television = 1;
438                                 FlatPanel = 1;
439                         } else {
440                                 FlatPanel = 0;
441                         }
442                         printk("nvidiafb: HW is currently programmed for %s\n",
443                                FlatPanel ? (Television ? "TV" : "DFP") :
444                                "CRT");
445                 }
446
447                 if (par->FlatPanel == -1) {
448                         par->FlatPanel = FlatPanel;
449                         par->Television = Television;
450                 } else {
451                         printk("nvidiafb: Forcing display type to %s as "
452                                "specified\n", par->FlatPanel ? "DFP" : "CRT");
453                 }
454         } else {
455                 u8 outputAfromCRTC, outputBfromCRTC;
456                 int CRTCnumber = -1;
457                 u8 slaved_on_A, slaved_on_B;
458                 int analog_on_A, analog_on_B;
459                 u32 oldhead;
460                 u8 cr44;
461
462                 if (implementation != 0x0110) {
463                         if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
464                                 outputAfromCRTC = 1;
465                         else
466                                 outputAfromCRTC = 0;
467                         if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
468                                 outputBfromCRTC = 1;
469                         else
470                                 outputBfromCRTC = 0;
471                         analog_on_A = NVIsConnected(par, 0);
472                         analog_on_B = NVIsConnected(par, 1);
473                 } else {
474                         outputAfromCRTC = 0;
475                         outputBfromCRTC = 1;
476                         analog_on_A = 0;
477                         analog_on_B = 0;
478                 }
479
480                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
481                 cr44 = VGA_RD08(par->PCIO, 0x03D5);
482
483                 VGA_WR08(par->PCIO, 0x03D5, 3);
484                 NVSelectHeadRegisters(par, 1);
485                 NVLockUnlock(par, 0);
486
487                 VGA_WR08(par->PCIO, 0x03D4, 0x28);
488                 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
489                 if (slaved_on_B) {
490                         VGA_WR08(par->PCIO, 0x03D4, 0x33);
491                         tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
492                 }
493
494                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
495                 VGA_WR08(par->PCIO, 0x03D5, 0);
496                 NVSelectHeadRegisters(par, 0);
497                 NVLockUnlock(par, 0);
498
499                 VGA_WR08(par->PCIO, 0x03D4, 0x28);
500                 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
501                 if (slaved_on_A) {
502                         VGA_WR08(par->PCIO, 0x03D4, 0x33);
503                         tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
504                 }
505
506                 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
507                 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
508
509                 if (nvidia_probe_i2c_connector(info, 1, &edidA))
510                         nvidia_probe_of_connector(info, 1, &edidA);
511                 if (edidA && !fb_parse_edid(edidA, var)) {
512                         printk("nvidiafb: EDID found from BUS1\n");
513                         monA = monitorA;
514                         fb_edid_to_monspecs(edidA, monA);
515                 }
516
517                 if (nvidia_probe_i2c_connector(info, 2, &edidB))
518                         nvidia_probe_of_connector(info, 2, &edidB);
519                 if (edidB && !fb_parse_edid(edidB, var)) {
520                         printk("nvidiafb: EDID found from BUS2\n");
521                         monB = monitorB;
522                         fb_edid_to_monspecs(edidB, monB);
523                 }
524
525                 if (slaved_on_A && !tvA) {
526                         CRTCnumber = 0;
527                         FlatPanel = 1;
528                         printk("nvidiafb: CRTC 0 is currently programmed for "
529                                "DFP\n");
530                 } else if (slaved_on_B && !tvB) {
531                         CRTCnumber = 1;
532                         FlatPanel = 1;
533                         printk("nvidiafb: CRTC 1 is currently programmed "
534                                "for DFP\n");
535                 } else if (analog_on_A) {
536                         CRTCnumber = outputAfromCRTC;
537                         FlatPanel = 0;
538                         printk("nvidiafb: CRTC %i appears to have a "
539                                "CRT attached\n", CRTCnumber);
540                 } else if (analog_on_B) {
541                         CRTCnumber = outputBfromCRTC;
542                         FlatPanel = 0;
543                         printk("nvidiafb: CRTC %i"
544                                "appears to have a "
545                                "CRT attached\n", CRTCnumber);
546                 } else if (slaved_on_A) {
547                         CRTCnumber = 0;
548                         FlatPanel = 1;
549                         Television = 1;
550                         printk("nvidiafb: CRTC 0 is currently programmed "
551                                "for TV\n");
552                 } else if (slaved_on_B) {
553                         CRTCnumber = 1;
554                         FlatPanel = 1;
555                         Television = 1;
556                         printk("nvidiafb: CRTC 1 is currently programmed for "
557                                "TV\n");
558                 } else if (monA) {
559                         FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
560                 } else if (monB) {
561                         FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
562                 }
563
564                 if (par->FlatPanel == -1) {
565                         if (FlatPanel != -1) {
566                                 par->FlatPanel = FlatPanel;
567                                 par->Television = Television;
568                         } else {
569                                 printk("nvidiafb: Unable to detect display "
570                                        "type...\n");
571                                 if (mobile) {
572                                         printk("...On a laptop, assuming "
573                                                "DFP\n");
574                                         par->FlatPanel = 1;
575                                 } else {
576                                         printk("...Using default of CRT\n");
577                                         par->FlatPanel = 0;
578                                 }
579                         }
580                 } else {
581                         printk("nvidiafb: Forcing display type to %s as "
582                                "specified\n", par->FlatPanel ? "DFP" : "CRT");
583                 }
584
585                 if (par->CRTCnumber == -1) {
586                         if (CRTCnumber != -1)
587                                 par->CRTCnumber = CRTCnumber;
588                         else {
589                                 printk("nvidiafb: Unable to detect which "
590                                        "CRTCNumber...\n");
591                                 if (par->FlatPanel)
592                                         par->CRTCnumber = 1;
593                                 else
594                                         par->CRTCnumber = 0;
595                                 printk("...Defaulting to CRTCNumber %i\n",
596                                        par->CRTCnumber);
597                         }
598                 } else {
599                         printk("nvidiafb: Forcing CRTCNumber %i as "
600                                "specified\n", par->CRTCnumber);
601                 }
602
603                 if (monA) {
604                         if (((monA->input & FB_DISP_DDI) &&
605                              par->FlatPanel) ||
606                             ((!(monA->input & FB_DISP_DDI)) &&
607                              !par->FlatPanel)) {
608                                 if (monB) {
609                                         fb_destroy_modedb(monB->modedb);
610                                         monB = NULL;
611                                 }
612                         } else {
613                                 fb_destroy_modedb(monA->modedb);
614                                 monA = NULL;
615                         }
616                 }
617
618                 if (monB) {
619                         if (((monB->input & FB_DISP_DDI) &&
620                              !par->FlatPanel) ||
621                             ((!(monB->input & FB_DISP_DDI)) &&
622                              par->FlatPanel)) {
623                                 fb_destroy_modedb(monB->modedb);
624                                 monB = NULL;
625                         } else
626                                 monA = monB;
627                 }
628
629                 if (implementation == 0x0110)
630                         cr44 = par->CRTCnumber * 0x3;
631
632                 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
633
634                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
635                 VGA_WR08(par->PCIO, 0x03D5, cr44);
636                 NVSelectHeadRegisters(par, par->CRTCnumber);
637         }
638
639         printk("nvidiafb: Using %s on CRTC %i\n",
640                par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
641                par->CRTCnumber);
642
643         if (par->FlatPanel && !par->Television) {
644                 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
645                 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
646                 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
647
648                 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
649         }
650
651         if (monA)
652                 info->monspecs = *monA;
653
654         if (!par->FlatPanel || !par->twoHeads)
655                 par->FPDither = 0;
656
657         par->LVDS = 0;
658         if (par->FlatPanel && par->twoHeads) {
659                 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
660                 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
661                         par->LVDS = 1;
662                 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
663         }
664
665         kfree(edidA);
666         kfree(edidB);
667 done:
668         kfree(var);
669         kfree(monitorA);
670         kfree(monitorB);
671         return err;
672 }