git.oblomov.eu Git - linux-2.6/blob - arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/stddef.h>
  18
  19 #include <asm/bugs.h>
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         local_irq_disable();
  43         if (!need_resched())
  44                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  45         local_irq_enable();
  46 }
  47
  48 /*
  49  * There is a race when WAIT instruction executed with interrupt
  50  * enabled.
  51  * But it is implementation-dependent wheter the pipelie restarts when
  52  * a non-enabled interrupt is requested.
  53  */
  54 static void r4k_wait(void)
  55 {
  56         __asm__("       .set    mips3                   \n"
  57                 "       wait                            \n"
  58                 "       .set    mips0                   \n");
  59 }
  60
  61 /*
  62  * This variant is preferable as it allows testing need_resched and going to
  63  * sleep depending on the outcome atomically.  Unfortunately the "It is
  64  * implementation-dependent whether the pipeline restarts when a non-enabled
  65  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  66  * using this version a gamble.
  67  */
  68 static void r4k_wait_irqoff(void)
  69 {
  70         local_irq_disable();
  71         if (!need_resched())
  72                 __asm__("       .set    mips3           \n"
  73                         "       wait                    \n"
  74                         "       .set    mips0           \n");
  75         local_irq_enable();
  76 }
  77
  78 /*
  79  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  80  * have any pending stores when the WAIT instruction is executed.
  81  */
  82 static void rm7k_wait_irqoff(void)
  83 {
  84         local_irq_disable();
  85         if (!need_resched())
  86                 __asm__(
  87                 "       .set    push                                    \n"
  88                 "       .set    mips3                                   \n"
  89                 "       .set    noat                                    \n"
  90                 "       mfc0    $1, $12                                 \n"
  91                 "       sync                                            \n"
  92                 "       mtc0    $1, $12         # stalls until W stage  \n"
  93                 "       wait                                            \n"
  94                 "       mtc0    $1, $12         # stalls until W stage  \n"
  95                 "       .set    pop                                     \n");
  96         local_irq_enable();
  97 }
  98
  99 /* The Au1xxx wait is available only if using 32khz counter or
 100  * external timer source, but specifically not CP0 Counter. */
 101 int allow_au1k_wait;
 102
 103 static void au1k_wait(void)
 104 {
 105         /* using the wait instruction makes CP0 counter unusable */
 106         __asm__("       .set    mips3                   \n"
 107                 "       cache   0x14, 0(%0)             \n"
 108                 "       cache   0x14, 32(%0)            \n"
 109                 "       sync                            \n"
 110                 "       nop                             \n"
 111                 "       wait                            \n"
 112                 "       nop                             \n"
 113                 "       nop                             \n"
 114                 "       nop                             \n"
 115                 "       nop                             \n"
 116                 "       .set    mips0                   \n"
 117                 : : "r" (au1k_wait));
 118 }
 119
 120 static int __initdata nowait = 0;
 121
 122 static int __init wait_disable(char *s)
 123 {
 124         nowait = 1;
 125
 126         return 1;
 127 }
 128
 129 __setup("nowait", wait_disable);
 130
 131 static inline void check_wait(void)
 132 {
 133         struct cpuinfo_mips *c = &current_cpu_data;
 134
 135         if (nowait) {
 136                 printk("Wait instruction disabled.\n");
 137                 return;
 138         }
 139
 140         switch (c->cputype) {
 141         case CPU_R3081:
 142         case CPU_R3081E:
 143                 cpu_wait = r3081_wait;
 144                 break;
 145         case CPU_TX3927:
 146                 cpu_wait = r39xx_wait;
 147                 break;
 148         case CPU_R4200:
 149 /*      case CPU_R4300: */
 150         case CPU_R4600:
 151         case CPU_R4640:
 152         case CPU_R4650:
 153         case CPU_R4700:
 154         case CPU_R5000:
 155         case CPU_NEVADA:
 156         case CPU_4KC:
 157         case CPU_4KEC:
 158         case CPU_4KSC:
 159         case CPU_5KC:
 160         case CPU_25KF:
 161         case CPU_PR4450:
 162         case CPU_BCM3302:
 163                 cpu_wait = r4k_wait;
 164                 break;
 165
 166         case CPU_RM7000:
 167                 cpu_wait = rm7k_wait_irqoff;
 168                 break;
 169
 170         case CPU_24K:
 171         case CPU_34K:
 172                 cpu_wait = r4k_wait;
 173                 if (read_c0_config7() & MIPS_CONF7_WII)
 174                         cpu_wait = r4k_wait_irqoff;
 175                 break;
 176
 177         case CPU_74K:
 178                 cpu_wait = r4k_wait;
 179                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 180                         cpu_wait = r4k_wait_irqoff;
 181                 break;
 182
 183         case CPU_TX49XX:
 184                 cpu_wait = r4k_wait_irqoff;
 185                 break;
 186         case CPU_AU1000:
 187         case CPU_AU1100:
 188         case CPU_AU1500:
 189         case CPU_AU1550:
 190         case CPU_AU1200:
 191                 if (allow_au1k_wait)
 192                         cpu_wait = au1k_wait;
 193                 break;
 194         case CPU_20KC:
 195                 /*
 196                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 197                  * WAIT on Rev2.0 and Rev3.0 has E16.
 198                  * Rev3.1 WAIT is nop, why bother
 199                  */
 200                 if ((c->processor_id & 0xff) <= 0x64)
 201                         break;
 202
 203                 /*
 204                  * Another rev is incremeting c0_count at a reduced clock
 205                  * rate while in WAIT mode.  So we basically have the choice
 206                  * between using the cp0 timer as clocksource or avoiding
 207                  * the WAIT instruction.  Until more details are known,
 208                  * disable the use of WAIT for 20Kc entirely.
 209                    cpu_wait = r4k_wait;
 210                  */
 211                 break;
 212         case CPU_RM9000:
 213                 if ((c->processor_id & 0x00ff) >= 0x40)
 214                         cpu_wait = r4k_wait;
 215                 break;
 216         default:
 217                 break;
 218         }
 219 }
 220
 221 static inline void check_errata(void)
 222 {
 223         struct cpuinfo_mips *c = &current_cpu_data;
 224
 225         switch (c->cputype) {
 226         case CPU_34K:
 227                 /*
 228                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 229                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 230                  * making use of VPE1 will be responsable for that VPE.
 231                  */
 232                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 233                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 234                 break;
 235         default:
 236                 break;
 237         }
 238 }
 239
 240 void __init check_bugs32(void)
 241 {
 242         check_wait();
 243         check_errata();
 244 }
 245
 246 /*
 247  * Probe whether cpu has config register by trying to play with
 248  * alternate cache bit and see whether it matters.
 249  * It's used by cpu_probe to distinguish between R3000A and R3081.
 250  */
 251 static inline int cpu_has_confreg(void)
 252 {
 253 #ifdef CONFIG_CPU_R3000
 254         extern unsigned long r3k_cache_size(unsigned long);
 255         unsigned long size1, size2;
 256         unsigned long cfg = read_c0_conf();
 257
 258         size1 = r3k_cache_size(ST0_ISC);
 259         write_c0_conf(cfg ^ R30XX_CONF_AC);
 260         size2 = r3k_cache_size(ST0_ISC);
 261         write_c0_conf(cfg);
 262         return size1 != size2;
 263 #else
 264         return 0;
 265 #endif
 266 }
 267
 268 /*
 269  * Get the FPU Implementation/Revision.
 270  */
 271 static inline unsigned long cpu_get_fpu_id(void)
 272 {
 273         unsigned long tmp, fpu_id;
 274
 275         tmp = read_c0_status();
 276         __enable_fpu();
 277         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 278         write_c0_status(tmp);
 279         return fpu_id;
 280 }
 281
 282 /*
 283  * Check the CPU has an FPU the official way.
 284  */
 285 static inline int __cpu_has_fpu(void)
 286 {
 287         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 288 }
 289
 290 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 291                 | MIPS_CPU_COUNTER)
 292
 293 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 294 {
 295         switch (c->processor_id & 0xff00) {
 296         case PRID_IMP_R2000:
 297                 c->cputype = CPU_R2000;
 298                 c->isa_level = MIPS_CPU_ISA_I;
 299                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 300                              MIPS_CPU_NOFPUEX;
 301                 if (__cpu_has_fpu())
 302                         c->options |= MIPS_CPU_FPU;
 303                 c->tlbsize = 64;
 304                 break;
 305         case PRID_IMP_R3000:
 306                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 307                         if (cpu_has_confreg())
 308                                 c->cputype = CPU_R3081E;
 309                         else
 310                                 c->cputype = CPU_R3000A;
 311                 else
 312                         c->cputype = CPU_R3000;
 313                 c->isa_level = MIPS_CPU_ISA_I;
 314                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 315                              MIPS_CPU_NOFPUEX;
 316                 if (__cpu_has_fpu())
 317                         c->options |= MIPS_CPU_FPU;
 318                 c->tlbsize = 64;
 319                 break;
 320         case PRID_IMP_R4000:
 321                 if (read_c0_config() & CONF_SC) {
 322                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 323                                 c->cputype = CPU_R4400PC;
 324                         else
 325                                 c->cputype = CPU_R4000PC;
 326                 } else {
 327                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 328                                 c->cputype = CPU_R4400SC;
 329                         else
 330                                 c->cputype = CPU_R4000SC;
 331                 }
 332
 333                 c->isa_level = MIPS_CPU_ISA_III;
 334                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 335                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 336                              MIPS_CPU_LLSC;
 337                 c->tlbsize = 48;
 338                 break;
 339         case PRID_IMP_VR41XX:
 340                 switch (c->processor_id & 0xf0) {
 341                 case PRID_REV_VR4111:
 342                         c->cputype = CPU_VR4111;
 343                         break;
 344                 case PRID_REV_VR4121:
 345                         c->cputype = CPU_VR4121;
 346                         break;
 347                 case PRID_REV_VR4122:
 348                         if ((c->processor_id & 0xf) < 0x3)
 349                                 c->cputype = CPU_VR4122;
 350                         else
 351                                 c->cputype = CPU_VR4181A;
 352                         break;
 353                 case PRID_REV_VR4130:
 354                         if ((c->processor_id & 0xf) < 0x4)
 355                                 c->cputype = CPU_VR4131;
 356                         else
 357                                 c->cputype = CPU_VR4133;
 358                         break;
 359                 default:
 360                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 361                         c->cputype = CPU_VR41XX;
 362                         break;
 363                 }
 364                 c->isa_level = MIPS_CPU_ISA_III;
 365                 c->options = R4K_OPTS;
 366                 c->tlbsize = 32;
 367                 break;
 368         case PRID_IMP_R4300:
 369                 c->cputype = CPU_R4300;
 370                 c->isa_level = MIPS_CPU_ISA_III;
 371                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 372                              MIPS_CPU_LLSC;
 373                 c->tlbsize = 32;
 374                 break;
 375         case PRID_IMP_R4600:
 376                 c->cputype = CPU_R4600;
 377                 c->isa_level = MIPS_CPU_ISA_III;
 378                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 379                              MIPS_CPU_LLSC;
 380                 c->tlbsize = 48;
 381                 break;
 382         #if 0
 383         case PRID_IMP_R4650:
 384                 /*
 385                  * This processor doesn't have an MMU, so it's not
 386                  * "real easy" to run Linux on it. It is left purely
 387                  * for documentation.  Commented out because it shares
 388                  * it's c0_prid id number with the TX3900.
 389                  */
 390                 c->cputype = CPU_R4650;
 391                 c->isa_level = MIPS_CPU_ISA_III;
 392                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 393                 c->tlbsize = 48;
 394                 break;
 395         #endif
 396         case PRID_IMP_TX39:
 397                 c->isa_level = MIPS_CPU_ISA_I;
 398                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 399
 400                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 401                         c->cputype = CPU_TX3927;
 402                         c->tlbsize = 64;
 403                 } else {
 404                         switch (c->processor_id & 0xff) {
 405                         case PRID_REV_TX3912:
 406                                 c->cputype = CPU_TX3912;
 407                                 c->tlbsize = 32;
 408                                 break;
 409                         case PRID_REV_TX3922:
 410                                 c->cputype = CPU_TX3922;
 411                                 c->tlbsize = 64;
 412                                 break;
 413                         default:
 414                                 c->cputype = CPU_UNKNOWN;
 415                                 break;
 416                         }
 417                 }
 418                 break;
 419         case PRID_IMP_R4700:
 420                 c->cputype = CPU_R4700;
 421                 c->isa_level = MIPS_CPU_ISA_III;
 422                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 423                              MIPS_CPU_LLSC;
 424                 c->tlbsize = 48;
 425                 break;
 426         case PRID_IMP_TX49:
 427                 c->cputype = CPU_TX49XX;
 428                 c->isa_level = MIPS_CPU_ISA_III;
 429                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 430                 if (!(c->processor_id & 0x08))
 431                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 432                 c->tlbsize = 48;
 433                 break;
 434         case PRID_IMP_R5000:
 435                 c->cputype = CPU_R5000;
 436                 c->isa_level = MIPS_CPU_ISA_IV;
 437                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 438                              MIPS_CPU_LLSC;
 439                 c->tlbsize = 48;
 440                 break;
 441         case PRID_IMP_R5432:
 442                 c->cputype = CPU_R5432;
 443                 c->isa_level = MIPS_CPU_ISA_IV;
 444                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 445                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 446                 c->tlbsize = 48;
 447                 break;
 448         case PRID_IMP_R5500:
 449                 c->cputype = CPU_R5500;
 450                 c->isa_level = MIPS_CPU_ISA_IV;
 451                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 452                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 453                 c->tlbsize = 48;
 454                 break;
 455         case PRID_IMP_NEVADA:
 456                 c->cputype = CPU_NEVADA;
 457                 c->isa_level = MIPS_CPU_ISA_IV;
 458                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 459                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 460                 c->tlbsize = 48;
 461                 break;
 462         case PRID_IMP_R6000:
 463                 c->cputype = CPU_R6000;
 464                 c->isa_level = MIPS_CPU_ISA_II;
 465                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 466                              MIPS_CPU_LLSC;
 467                 c->tlbsize = 32;
 468                 break;
 469         case PRID_IMP_R6000A:
 470                 c->cputype = CPU_R6000A;
 471                 c->isa_level = MIPS_CPU_ISA_II;
 472                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 473                              MIPS_CPU_LLSC;
 474                 c->tlbsize = 32;
 475                 break;
 476         case PRID_IMP_RM7000:
 477                 c->cputype = CPU_RM7000;
 478                 c->isa_level = MIPS_CPU_ISA_IV;
 479                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 480                              MIPS_CPU_LLSC;
 481                 /*
 482                  * Undocumented RM7000:  Bit 29 in the info register of
 483                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 484                  * entries.
 485                  *
 486                  * 29      1 =>    64 entry JTLB
 487                  *         0 =>    48 entry JTLB
 488                  */
 489                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 490                 break;
 491         case PRID_IMP_RM9000:
 492                 c->cputype = CPU_RM9000;
 493                 c->isa_level = MIPS_CPU_ISA_IV;
 494                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 495                              MIPS_CPU_LLSC;
 496                 /*
 497                  * Bit 29 in the info register of the RM9000
 498                  * indicates if the TLB has 48 or 64 entries.
 499                  *
 500                  * 29      1 =>    64 entry JTLB
 501                  *         0 =>    48 entry JTLB
 502                  */
 503                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 504                 break;
 505         case PRID_IMP_R8000:
 506                 c->cputype = CPU_R8000;
 507                 c->isa_level = MIPS_CPU_ISA_IV;
 508                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 509                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 510                              MIPS_CPU_LLSC;
 511                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 512                 break;
 513         case PRID_IMP_R10000:
 514                 c->cputype = CPU_R10000;
 515                 c->isa_level = MIPS_CPU_ISA_IV;
 516                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 517                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 518                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 519                              MIPS_CPU_LLSC;
 520                 c->tlbsize = 64;
 521                 break;
 522         case PRID_IMP_R12000:
 523                 c->cputype = CPU_R12000;
 524                 c->isa_level = MIPS_CPU_ISA_IV;
 525                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 526                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 527                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 528                              MIPS_CPU_LLSC;
 529                 c->tlbsize = 64;
 530                 break;
 531         case PRID_IMP_R14000:
 532                 c->cputype = CPU_R14000;
 533                 c->isa_level = MIPS_CPU_ISA_IV;
 534                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 535                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 536                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 537                              MIPS_CPU_LLSC;
 538                 c->tlbsize = 64;
 539                 break;
 540         case PRID_IMP_LOONGSON2:
 541                 c->cputype = CPU_LOONGSON2;
 542                 c->isa_level = MIPS_CPU_ISA_III;
 543                 c->options = R4K_OPTS |
 544                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 545                              MIPS_CPU_32FPR;
 546                 c->tlbsize = 64;
 547                 break;
 548         }
 549 }
 550
 551 static char unknown_isa[] __initdata = KERN_ERR \
 552         "Unsupported ISA type, c0.config0: %d.";
 553
 554 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 555 {
 556         unsigned int config0;
 557         int isa;
 558
 559         config0 = read_c0_config();
 560
 561         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 562                 c->options |= MIPS_CPU_TLB;
 563         isa = (config0 & MIPS_CONF_AT) >> 13;
 564         switch (isa) {
 565         case 0:
 566                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 567                 case 0:
 568                         c->isa_level = MIPS_CPU_ISA_M32R1;
 569                         break;
 570                 case 1:
 571                         c->isa_level = MIPS_CPU_ISA_M32R2;
 572                         break;
 573                 default:
 574                         goto unknown;
 575                 }
 576                 break;
 577         case 2:
 578                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 579                 case 0:
 580                         c->isa_level = MIPS_CPU_ISA_M64R1;
 581                         break;
 582                 case 1:
 583                         c->isa_level = MIPS_CPU_ISA_M64R2;
 584                         break;
 585                 default:
 586                         goto unknown;
 587                 }
 588                 break;
 589         default:
 590                 goto unknown;
 591         }
 592
 593         return config0 & MIPS_CONF_M;
 594
 595 unknown:
 596         panic(unknown_isa, config0);
 597 }
 598
 599 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 600 {
 601         unsigned int config1;
 602
 603         config1 = read_c0_config1();
 604
 605         if (config1 & MIPS_CONF1_MD)
 606                 c->ases |= MIPS_ASE_MDMX;
 607         if (config1 & MIPS_CONF1_WR)
 608                 c->options |= MIPS_CPU_WATCH;
 609         if (config1 & MIPS_CONF1_CA)
 610                 c->ases |= MIPS_ASE_MIPS16;
 611         if (config1 & MIPS_CONF1_EP)
 612                 c->options |= MIPS_CPU_EJTAG;
 613         if (config1 & MIPS_CONF1_FP) {
 614                 c->options |= MIPS_CPU_FPU;
 615                 c->options |= MIPS_CPU_32FPR;
 616         }
 617         if (cpu_has_tlb)
 618                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 619
 620         return config1 & MIPS_CONF_M;
 621 }
 622
 623 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 624 {
 625         unsigned int config2;
 626
 627         config2 = read_c0_config2();
 628
 629         if (config2 & MIPS_CONF2_SL)
 630                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 631
 632         return config2 & MIPS_CONF_M;
 633 }
 634
 635 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 636 {
 637         unsigned int config3;
 638
 639         config3 = read_c0_config3();
 640
 641         if (config3 & MIPS_CONF3_SM)
 642                 c->ases |= MIPS_ASE_SMARTMIPS;
 643         if (config3 & MIPS_CONF3_DSP)
 644                 c->ases |= MIPS_ASE_DSP;
 645         if (config3 & MIPS_CONF3_VINT)
 646                 c->options |= MIPS_CPU_VINT;
 647         if (config3 & MIPS_CONF3_VEIC)
 648                 c->options |= MIPS_CPU_VEIC;
 649         if (config3 & MIPS_CONF3_MT)
 650                 c->ases |= MIPS_ASE_MIPSMT;
 651         if (config3 & MIPS_CONF3_ULRI)
 652                 c->options |= MIPS_CPU_ULRI;
 653
 654         return config3 & MIPS_CONF_M;
 655 }
 656
 657 static void __init decode_configs(struct cpuinfo_mips *c)
 658 {
 659         /* MIPS32 or MIPS64 compliant CPU.  */
 660         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 661                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 662
 663         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 664
 665         /* Read Config registers.  */
 666         if (!decode_config0(c))
 667                 return;                 /* actually worth a panic() */
 668         if (!decode_config1(c))
 669                 return;
 670         if (!decode_config2(c))
 671                 return;
 672         if (!decode_config3(c))
 673                 return;
 674 }
 675
 676 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 677 {
 678         decode_configs(c);
 679         switch (c->processor_id & 0xff00) {
 680         case PRID_IMP_4KC:
 681                 c->cputype = CPU_4KC;
 682                 break;
 683         case PRID_IMP_4KEC:
 684                 c->cputype = CPU_4KEC;
 685                 break;
 686         case PRID_IMP_4KECR2:
 687                 c->cputype = CPU_4KEC;
 688                 break;
 689         case PRID_IMP_4KSC:
 690         case PRID_IMP_4KSD:
 691                 c->cputype = CPU_4KSC;
 692                 break;
 693         case PRID_IMP_5KC:
 694                 c->cputype = CPU_5KC;
 695                 break;
 696         case PRID_IMP_20KC:
 697                 c->cputype = CPU_20KC;
 698                 break;
 699         case PRID_IMP_24K:
 700         case PRID_IMP_24KE:
 701                 c->cputype = CPU_24K;
 702                 break;
 703         case PRID_IMP_25KF:
 704                 c->cputype = CPU_25KF;
 705                 break;
 706         case PRID_IMP_34K:
 707                 c->cputype = CPU_34K;
 708                 break;
 709         case PRID_IMP_74K:
 710                 c->cputype = CPU_74K;
 711                 break;
 712         }
 713 }
 714
 715 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 716 {
 717         decode_configs(c);
 718         switch (c->processor_id & 0xff00) {
 719         case PRID_IMP_AU1_REV1:
 720         case PRID_IMP_AU1_REV2:
 721                 switch ((c->processor_id >> 24) & 0xff) {
 722                 case 0:
 723                         c->cputype = CPU_AU1000;
 724                         break;
 725                 case 1:
 726                         c->cputype = CPU_AU1500;
 727                         break;
 728                 case 2:
 729                         c->cputype = CPU_AU1100;
 730                         break;
 731                 case 3:
 732                         c->cputype = CPU_AU1550;
 733                         break;
 734                 case 4:
 735                         c->cputype = CPU_AU1200;
 736                         break;
 737                 default:
 738                         panic("Unknown Au Core!");
 739                         break;
 740                 }
 741                 break;
 742         }
 743 }
 744
 745 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 746 {
 747         decode_configs(c);
 748
 749         switch (c->processor_id & 0xff00) {
 750         case PRID_IMP_SB1:
 751                 c->cputype = CPU_SB1;
 752                 /* FPU in pass1 is known to have issues. */
 753                 if ((c->processor_id & 0xff) < 0x02)
 754                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 755                 break;
 756         case PRID_IMP_SB1A:
 757                 c->cputype = CPU_SB1A;
 758                 break;
 759         }
 760 }
 761
 762 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 763 {
 764         decode_configs(c);
 765         switch (c->processor_id & 0xff00) {
 766         case PRID_IMP_SR71000:
 767                 c->cputype = CPU_SR71000;
 768                 c->scache.ways = 8;
 769                 c->tlbsize = 64;
 770                 break;
 771         }
 772 }
 773
 774 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
 775 {
 776         decode_configs(c);
 777         switch (c->processor_id & 0xff00) {
 778         case PRID_IMP_PR4450:
 779                 c->cputype = CPU_PR4450;
 780                 c->isa_level = MIPS_CPU_ISA_M32R1;
 781                 break;
 782         default:
 783                 panic("Unknown Philips Core!"); /* REVISIT: die? */
 784                 break;
 785         }
 786 }
 787
 788
 789 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
 790 {
 791         decode_configs(c);
 792         switch (c->processor_id & 0xff00) {
 793         case PRID_IMP_BCM3302:
 794                 c->cputype = CPU_BCM3302;
 795                 break;
 796         case PRID_IMP_BCM4710:
 797                 c->cputype = CPU_BCM4710;
 798                 break;
 799         default:
 800                 c->cputype = CPU_UNKNOWN;
 801                 break;
 802         }
 803 }
 804
 805 const char *__cpu_name[NR_CPUS];
 806
 807 /*
 808  * Name a CPU
 809  */
 810 static __init const char *cpu_to_name(struct cpuinfo_mips *c)
 811 {
 812         const char *name = NULL;
 813
 814         switch (c->cputype) {
 815         case CPU_UNKNOWN:       name = "unknown"; break;
 816         case CPU_R2000:         name = "R2000"; break;
 817         case CPU_R3000:         name = "R3000"; break;
 818         case CPU_R3000A:        name = "R3000A"; break;
 819         case CPU_R3041:         name = "R3041"; break;
 820         case CPU_R3051:         name = "R3051"; break;
 821         case CPU_R3052:         name = "R3052"; break;
 822         case CPU_R3081:         name = "R3081"; break;
 823         case CPU_R3081E:        name = "R3081E"; break;
 824         case CPU_R4000PC:       name = "R4000PC"; break;
 825         case CPU_R4000SC:       name = "R4000SC"; break;
 826         case CPU_R4000MC:       name = "R4000MC"; break;
 827         case CPU_R4200:         name = "R4200"; break;
 828         case CPU_R4400PC:       name = "R4400PC"; break;
 829         case CPU_R4400SC:       name = "R4400SC"; break;
 830         case CPU_R4400MC:       name = "R4400MC"; break;
 831         case CPU_R4600:         name = "R4600"; break;
 832         case CPU_R6000:         name = "R6000"; break;
 833         case CPU_R6000A:        name = "R6000A"; break;
 834         case CPU_R8000:         name = "R8000"; break;
 835         case CPU_R10000:        name = "R10000"; break;
 836         case CPU_R12000:        name = "R12000"; break;
 837         case CPU_R14000:        name = "R14000"; break;
 838         case CPU_R4300:         name = "R4300"; break;
 839         case CPU_R4650:         name = "R4650"; break;
 840         case CPU_R4700:         name = "R4700"; break;
 841         case CPU_R5000:         name = "R5000"; break;
 842         case CPU_R5000A:        name = "R5000A"; break;
 843         case CPU_R4640:         name = "R4640"; break;
 844         case CPU_NEVADA:        name = "Nevada"; break;
 845         case CPU_RM7000:        name = "RM7000"; break;
 846         case CPU_RM9000:        name = "RM9000"; break;
 847         case CPU_R5432:         name = "R5432"; break;
 848         case CPU_4KC:           name = "MIPS 4Kc"; break;
 849         case CPU_5KC:           name = "MIPS 5Kc"; break;
 850         case CPU_R4310:         name = "R4310"; break;
 851         case CPU_SB1:           name = "SiByte SB1"; break;
 852         case CPU_SB1A:          name = "SiByte SB1A"; break;
 853         case CPU_TX3912:        name = "TX3912"; break;
 854         case CPU_TX3922:        name = "TX3922"; break;
 855         case CPU_TX3927:        name = "TX3927"; break;
 856         case CPU_AU1000:        name = "Au1000"; break;
 857         case CPU_AU1500:        name = "Au1500"; break;
 858         case CPU_AU1100:        name = "Au1100"; break;
 859         case CPU_AU1550:        name = "Au1550"; break;
 860         case CPU_AU1200:        name = "Au1200"; break;
 861         case CPU_4KEC:          name = "MIPS 4KEc"; break;
 862         case CPU_4KSC:          name = "MIPS 4KSc"; break;
 863         case CPU_VR41XX:        name = "NEC Vr41xx"; break;
 864         case CPU_R5500:         name = "R5500"; break;
 865         case CPU_TX49XX:        name = "TX49xx"; break;
 866         case CPU_20KC:          name = "MIPS 20Kc"; break;
 867         case CPU_24K:           name = "MIPS 24K"; break;
 868         case CPU_25KF:          name = "MIPS 25Kf"; break;
 869         case CPU_34K:           name = "MIPS 34K"; break;
 870         case CPU_74K:           name = "MIPS 74K"; break;
 871         case CPU_VR4111:        name = "NEC VR4111"; break;
 872         case CPU_VR4121:        name = "NEC VR4121"; break;
 873         case CPU_VR4122:        name = "NEC VR4122"; break;
 874         case CPU_VR4131:        name = "NEC VR4131"; break;
 875         case CPU_VR4133:        name = "NEC VR4133"; break;
 876         case CPU_VR4181:        name = "NEC VR4181"; break;
 877         case CPU_VR4181A:       name = "NEC VR4181A"; break;
 878         case CPU_SR71000:       name = "Sandcraft SR71000"; break;
 879         case CPU_BCM3302:       name = "Broadcom BCM3302"; break;
 880         case CPU_BCM4710:       name = "Broadcom BCM4710"; break;
 881         case CPU_PR4450:        name = "Philips PR4450"; break;
 882         case CPU_LOONGSON2:     name = "ICT Loongson-2"; break;
 883         default:
 884                 BUG();
 885         }
 886
 887         return name;
 888 }
 889
 890 __init void cpu_probe(void)
 891 {
 892         struct cpuinfo_mips *c = &current_cpu_data;
 893         unsigned int cpu = smp_processor_id();
 894
 895         c->processor_id = PRID_IMP_UNKNOWN;
 896         c->fpu_id       = FPIR_IMP_NONE;
 897         c->cputype      = CPU_UNKNOWN;
 898
 899         c->processor_id = read_c0_prid();
 900         switch (c->processor_id & 0xff0000) {
 901         case PRID_COMP_LEGACY:
 902                 cpu_probe_legacy(c);
 903                 break;
 904         case PRID_COMP_MIPS:
 905                 cpu_probe_mips(c);
 906                 break;
 907         case PRID_COMP_ALCHEMY:
 908                 cpu_probe_alchemy(c);
 909                 break;
 910         case PRID_COMP_SIBYTE:
 911                 cpu_probe_sibyte(c);
 912                 break;
 913         case PRID_COMP_BROADCOM:
 914                 cpu_probe_broadcom(c);
 915                 break;
 916         case PRID_COMP_SANDCRAFT:
 917                 cpu_probe_sandcraft(c);
 918                 break;
 919         case PRID_COMP_PHILIPS:
 920                 cpu_probe_philips(c);
 921                 break;
 922         default:
 923                 c->cputype = CPU_UNKNOWN;
 924         }
 925
 926         /*
 927          * Platform code can force the cpu type to optimize code
 928          * generation. In that case be sure the cpu type is correctly
 929          * manually setup otherwise it could trigger some nasty bugs.
 930          */
 931         BUG_ON(current_cpu_type() != c->cputype);
 932
 933         if (c->options & MIPS_CPU_FPU) {
 934                 c->fpu_id = cpu_get_fpu_id();
 935
 936                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 937                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 938                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 939                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 940                         if (c->fpu_id & MIPS_FPIR_3D)
 941                                 c->ases |= MIPS_ASE_MIPS3D;
 942                 }
 943         }
 944
 945         __cpu_name[cpu] = cpu_to_name(c);
 946 }
 947
 948 __init void cpu_report(void)
 949 {
 950         struct cpuinfo_mips *c = &current_cpu_data;
 951
 952         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
 953                c->processor_id, cpu_name_string());
 954         if (c->options & MIPS_CPU_FPU)
 955                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
 956 }