git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { 0 }
  38 };
  39
  40 static void ath_detach(struct ath_softc *sc);
  41
  42 /* return bus cachesize in 4B word units */
  43
  44 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  45 {
  46         u8 u8tmp;
  47
  48         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  49         *csz = (int)u8tmp;
  50
  51         /*
  52          * This check was put in to avoid "unplesant" consequences if
  53          * the bootrom has not fully initialized all PCI devices.
  54          * Sometimes the cache line size register is not set
  55          */
  56
  57         if (*csz == 0)
  58                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  59 }
  60
  61 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  62 {
  63         sc->sc_curmode = mode;
  64         /*
  65          * All protection frames are transmited at 2Mb/s for
  66          * 11g, otherwise at 1Mb/s.
  67          * XXX select protection rate index from rate table.
  68          */
  69         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  70 }
  71
  72 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  73 {
  74         if (chan->chanmode == CHANNEL_A)
  75                 return ATH9K_MODE_11A;
  76         else if (chan->chanmode == CHANNEL_G)
  77                 return ATH9K_MODE_11G;
  78         else if (chan->chanmode == CHANNEL_B)
  79                 return ATH9K_MODE_11B;
  80         else if (chan->chanmode == CHANNEL_A_HT20)
  81                 return ATH9K_MODE_11NA_HT20;
  82         else if (chan->chanmode == CHANNEL_G_HT20)
  83                 return ATH9K_MODE_11NG_HT20;
  84         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  85                 return ATH9K_MODE_11NA_HT40PLUS;
  86         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  87                 return ATH9K_MODE_11NA_HT40MINUS;
  88         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  89                 return ATH9K_MODE_11NG_HT40PLUS;
  90         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  91                 return ATH9K_MODE_11NG_HT40MINUS;
  92
  93         WARN_ON(1); /* should not get here */
  94
  95         return ATH9K_MODE_11B;
  96 }
  97
  98 static void ath_update_txpow(struct ath_softc *sc)
  99 {
 100         struct ath_hal *ah = sc->sc_ah;
 101         u32 txpow;
 102
 103         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 104                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 105                 /* read back in case value is clamped */
 106                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 107                 sc->sc_curtxpow = txpow;
 108         }
 109 }
 110
 111 static u8 parse_mpdudensity(u8 mpdudensity)
 112 {
 113         /*
 114          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 115          *   0 for no restriction
 116          *   1 for 1/4 us
 117          *   2 for 1/2 us
 118          *   3 for 1 us
 119          *   4 for 2 us
 120          *   5 for 4 us
 121          *   6 for 8 us
 122          *   7 for 16 us
 123          */
 124         switch (mpdudensity) {
 125         case 0:
 126                 return 0;
 127         case 1:
 128         case 2:
 129         case 3:
 130                 /* Our lower layer calculations limit our precision to
 131                    1 microsecond */
 132                 return 1;
 133         case 4:
 134                 return 2;
 135         case 5:
 136                 return 4;
 137         case 6:
 138                 return 8;
 139         case 7:
 140                 return 16;
 141         default:
 142                 return 0;
 143         }
 144 }
 145
 146 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 147 {
 148         struct ath_rate_table *rate_table = NULL;
 149         struct ieee80211_supported_band *sband;
 150         struct ieee80211_rate *rate;
 151         int i, maxrates;
 152
 153         switch (band) {
 154         case IEEE80211_BAND_2GHZ:
 155                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 156                 break;
 157         case IEEE80211_BAND_5GHZ:
 158                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         if (rate_table == NULL)
 165                 return;
 166
 167         sband = &sc->sbands[band];
 168         rate = sc->rates[band];
 169
 170         if (rate_table->rate_cnt > ATH_RATE_MAX)
 171                 maxrates = ATH_RATE_MAX;
 172         else
 173                 maxrates = rate_table->rate_cnt;
 174
 175         for (i = 0; i < maxrates; i++) {
 176                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 177                 rate[i].hw_value = rate_table->info[i].ratecode;
 178                 sband->n_bitrates++;
 179                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 180                         rate[i].bitrate / 10, rate[i].hw_value);
 181         }
 182 }
 183
 184 static int ath_setup_channels(struct ath_softc *sc)
 185 {
 186         struct ath_hal *ah = sc->sc_ah;
 187         int nchan, i, a = 0, b = 0;
 188         u8 regclassids[ATH_REGCLASSIDS_MAX];
 189         u32 nregclass = 0;
 190         struct ieee80211_supported_band *band_2ghz;
 191         struct ieee80211_supported_band *band_5ghz;
 192         struct ieee80211_channel *chan_2ghz;
 193         struct ieee80211_channel *chan_5ghz;
 194         struct ath9k_channel *c;
 195
 196         /* Fill in ah->ah_channels */
 197         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 198                                       regclassids, ATH_REGCLASSIDS_MAX,
 199                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 200                 u32 rd = ah->ah_currentRD;
 201                 DPRINTF(sc, ATH_DBG_FATAL,
 202                         "Unable to collect channel list; "
 203                         "regdomain likely %u country code %u\n",
 204                         rd, CTRY_DEFAULT);
 205                 return -EINVAL;
 206         }
 207
 208         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 209         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 210         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 211         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 212
 213         for (i = 0; i < nchan; i++) {
 214                 c = &ah->ah_channels[i];
 215                 if (IS_CHAN_2GHZ(c)) {
 216                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 217                         chan_2ghz[a].center_freq = c->channel;
 218                         chan_2ghz[a].max_power = c->maxTxPower;
 219
 220                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 221                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 222                         if (c->channelFlags & CHANNEL_PASSIVE)
 223                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 224
 225                         band_2ghz->n_channels = ++a;
 226
 227                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 228                                 "channelFlags: 0x%x\n",
 229                                 c->channel, c->channelFlags);
 230                 } else if (IS_CHAN_5GHZ(c)) {
 231                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 232                         chan_5ghz[b].center_freq = c->channel;
 233                         chan_5ghz[b].max_power = c->maxTxPower;
 234
 235                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 236                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 237                         if (c->channelFlags & CHANNEL_PASSIVE)
 238                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 239
 240                         band_5ghz->n_channels = ++b;
 241
 242                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 243                                 "channelFlags: 0x%x\n",
 244                                 c->channel, c->channelFlags);
 245                 }
 246         }
 247
 248         return 0;
 249 }
 250
 251 /*
 252  * Set/change channels.  If the channel is really being changed, it's done
 253  * by reseting the chip.  To accomplish this we must first cleanup any pending
 254  * DMA, then restart stuff.
 255 */
 256 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 257 {
 258         struct ath_hal *ah = sc->sc_ah;
 259         bool fastcc = true, stopped;
 260
 261         if (sc->sc_flags & SC_OP_INVALID)
 262                 return -EIO;
 263
 264         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 265             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 266             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 267             (sc->sc_flags & SC_OP_FULL_RESET)) {
 268                 int status;
 269                 /*
 270                  * This is only performed if the channel settings have
 271                  * actually changed.
 272                  *
 273                  * To switch channels clear any pending DMA operations;
 274                  * wait long enough for the RX fifo to drain, reset the
 275                  * hardware at the new frequency, and then re-enable
 276                  * the relevant bits of the h/w.
 277                  */
 278                 ath9k_hw_set_interrupts(ah, 0);
 279                 ath_draintxq(sc, false);
 280                 stopped = ath_stoprecv(sc);
 281
 282                 /* XXX: do not flush receive queue here. We don't want
 283                  * to flush data frames already in queue because of
 284                  * changing channel. */
 285
 286                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 287                         fastcc = false;
 288
 289                 DPRINTF(sc, ATH_DBG_CONFIG,
 290                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 291                         sc->sc_ah->ah_curchan->channel,
 292                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 293
 294                 spin_lock_bh(&sc->sc_resetlock);
 295                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 296                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 297                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 298                         DPRINTF(sc, ATH_DBG_FATAL,
 299                                 "Unable to reset channel %u (%uMhz) "
 300                                 "flags 0x%x hal status %u\n",
 301                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 302                                                   hchan->channelFlags),
 303                                 hchan->channel, hchan->channelFlags, status);
 304                         spin_unlock_bh(&sc->sc_resetlock);
 305                         return -EIO;
 306                 }
 307                 spin_unlock_bh(&sc->sc_resetlock);
 308
 309                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 310                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 311
 312                 if (ath_startrecv(sc) != 0) {
 313                         DPRINTF(sc, ATH_DBG_FATAL,
 314                                 "Unable to restart recv logic\n");
 315                         return -EIO;
 316                 }
 317
 318                 ath_setcurmode(sc, ath_chan2mode(hchan));
 319                 ath_update_txpow(sc);
 320                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 321         }
 322         return 0;
 323 }
 324
 325 /*
 326  *  This routine performs the periodic noise floor calibration function
 327  *  that is used to adjust and optimize the chip performance.  This
 328  *  takes environmental changes (location, temperature) into account.
 329  *  When the task is complete, it reschedules itself depending on the
 330  *  appropriate interval that was calculated.
 331  */
 332 static void ath_ani_calibrate(unsigned long data)
 333 {
 334         struct ath_softc *sc;
 335         struct ath_hal *ah;
 336         bool longcal = false;
 337         bool shortcal = false;
 338         bool aniflag = false;
 339         unsigned int timestamp = jiffies_to_msecs(jiffies);
 340         u32 cal_interval;
 341
 342         sc = (struct ath_softc *)data;
 343         ah = sc->sc_ah;
 344
 345         /*
 346         * don't calibrate when we're scanning.
 347         * we are most likely not on our home channel.
 348         */
 349         if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
 350                 return;
 351
 352         /* Long calibration runs independently of short calibration. */
 353         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 354                 longcal = true;
 355                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 356                 sc->sc_ani.sc_longcal_timer = timestamp;
 357         }
 358
 359         /* Short calibration applies only while sc_caldone is false */
 360         if (!sc->sc_ani.sc_caldone) {
 361                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 362                     ATH_SHORT_CALINTERVAL) {
 363                         shortcal = true;
 364                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 365                         sc->sc_ani.sc_shortcal_timer = timestamp;
 366                         sc->sc_ani.sc_resetcal_timer = timestamp;
 367                 }
 368         } else {
 369                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 370                     ATH_RESTART_CALINTERVAL) {
 371                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 372                                                 &sc->sc_ani.sc_caldone);
 373                         if (sc->sc_ani.sc_caldone)
 374                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 375                 }
 376         }
 377
 378         /* Verify whether we must check ANI */
 379         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 380            ATH_ANI_POLLINTERVAL) {
 381                 aniflag = true;
 382                 sc->sc_ani.sc_checkani_timer = timestamp;
 383         }
 384
 385         /* Skip all processing if there's nothing to do. */
 386         if (longcal || shortcal || aniflag) {
 387                 /* Call ANI routine if necessary */
 388                 if (aniflag)
 389                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 390                                              ah->ah_curchan);
 391
 392                 /* Perform calibration if necessary */
 393                 if (longcal || shortcal) {
 394                         bool iscaldone = false;
 395
 396                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 397                                                sc->sc_rx_chainmask, longcal,
 398                                                &iscaldone)) {
 399                                 if (longcal)
 400                                         sc->sc_ani.sc_noise_floor =
 401                                                 ath9k_hw_getchan_noise(ah,
 402                                                                ah->ah_curchan);
 403
 404                                 DPRINTF(sc, ATH_DBG_ANI,
 405                                         "calibrate chan %u/%x nf: %d\n",
 406                                         ah->ah_curchan->channel,
 407                                         ah->ah_curchan->channelFlags,
 408                                         sc->sc_ani.sc_noise_floor);
 409                         } else {
 410                                 DPRINTF(sc, ATH_DBG_ANY,
 411                                         "calibrate chan %u/%x failed\n",
 412                                         ah->ah_curchan->channel,
 413                                         ah->ah_curchan->channelFlags);
 414                         }
 415                         sc->sc_ani.sc_caldone = iscaldone;
 416                 }
 417         }
 418
 419         /*
 420         * Set timer interval based on previous results.
 421         * The interval must be the shortest necessary to satisfy ANI,
 422         * short calibration and long calibration.
 423         */
 424         cal_interval = ATH_LONG_CALINTERVAL;
 425         if (sc->sc_ah->ah_config.enable_ani)
 426                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 427         if (!sc->sc_ani.sc_caldone)
 428                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 429
 430         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 431 }
 432
 433 /*
 434  * Update tx/rx chainmask. For legacy association,
 435  * hard code chainmask to 1x1, for 11n association, use
 436  * the chainmask configuration.
 437  */
 438 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 439 {
 440         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 441         if (is_ht) {
 442                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 443                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 444         } else {
 445                 sc->sc_tx_chainmask = 1;
 446                 sc->sc_rx_chainmask = 1;
 447         }
 448
 449         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 450                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 451 }
 452
 453 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 454 {
 455         struct ath_node *an;
 456
 457         an = (struct ath_node *)sta->drv_priv;
 458
 459         if (sc->sc_flags & SC_OP_TXAGGR)
 460                 ath_tx_node_init(sc, an);
 461
 462         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 463                              sta->ht_cap.ampdu_factor);
 464         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 465 }
 466
 467 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 468 {
 469         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 470
 471         if (sc->sc_flags & SC_OP_TXAGGR)
 472                 ath_tx_node_cleanup(sc, an);
 473 }
 474
 475 static void ath9k_tasklet(unsigned long data)
 476 {
 477         struct ath_softc *sc = (struct ath_softc *)data;
 478         u32 status = sc->sc_intrstatus;
 479
 480         if (status & ATH9K_INT_FATAL) {
 481                 /* need a chip reset */
 482                 ath_reset(sc, false);
 483                 return;
 484         } else {
 485
 486                 if (status &
 487                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 488                         spin_lock_bh(&sc->sc_rxflushlock);
 489                         ath_rx_tasklet(sc, 0);
 490                         spin_unlock_bh(&sc->sc_rxflushlock);
 491                 }
 492                 /* XXX: optimize this */
 493                 if (status & ATH9K_INT_TX)
 494                         ath_tx_tasklet(sc);
 495         }
 496
 497         /* re-enable hardware interrupt */
 498         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 499 }
 500
 501 static irqreturn_t ath_isr(int irq, void *dev)
 502 {
 503         struct ath_softc *sc = dev;
 504         struct ath_hal *ah = sc->sc_ah;
 505         enum ath9k_int status;
 506         bool sched = false;
 507
 508         do {
 509                 if (sc->sc_flags & SC_OP_INVALID) {
 510                         /*
 511                          * The hardware is not ready/present, don't
 512                          * touch anything. Note this can happen early
 513                          * on if the IRQ is shared.
 514                          */
 515                         return IRQ_NONE;
 516                 }
 517                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 518                         return IRQ_NONE;
 519                 }
 520
 521                 /*
 522                  * Figure out the reason(s) for the interrupt.  Note
 523                  * that the hal returns a pseudo-ISR that may include
 524                  * bits we haven't explicitly enabled so we mask the
 525                  * value to insure we only process bits we requested.
 526                  */
 527                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 528
 529                 status &= sc->sc_imask; /* discard unasked-for bits */
 530
 531                 /*
 532                  * If there are no status bits set, then this interrupt was not
 533                  * for me (should have been caught above).
 534                  */
 535                 if (!status)
 536                         return IRQ_NONE;
 537
 538                 sc->sc_intrstatus = status;
 539
 540                 if (status & ATH9K_INT_FATAL) {
 541                         /* need a chip reset */
 542                         sched = true;
 543                 } else if (status & ATH9K_INT_RXORN) {
 544                         /* need a chip reset */
 545                         sched = true;
 546                 } else {
 547                         if (status & ATH9K_INT_SWBA) {
 548                                 /* schedule a tasklet for beacon handling */
 549                                 tasklet_schedule(&sc->bcon_tasklet);
 550                         }
 551                         if (status & ATH9K_INT_RXEOL) {
 552                                 /*
 553                                  * NB: the hardware should re-read the link when
 554                                  *     RXE bit is written, but it doesn't work
 555                                  *     at least on older hardware revs.
 556                                  */
 557                                 sched = true;
 558                         }
 559
 560                         if (status & ATH9K_INT_TXURN)
 561                                 /* bump tx trigger level */
 562                                 ath9k_hw_updatetxtriglevel(ah, true);
 563                         /* XXX: optimize this */
 564                         if (status & ATH9K_INT_RX)
 565                                 sched = true;
 566                         if (status & ATH9K_INT_TX)
 567                                 sched = true;
 568                         if (status & ATH9K_INT_BMISS)
 569                                 sched = true;
 570                         /* carrier sense timeout */
 571                         if (status & ATH9K_INT_CST)
 572                                 sched = true;
 573                         if (status & ATH9K_INT_MIB) {
 574                                 /*
 575                                  * Disable interrupts until we service the MIB
 576                                  * interrupt; otherwise it will continue to
 577                                  * fire.
 578                                  */
 579                                 ath9k_hw_set_interrupts(ah, 0);
 580                                 /*
 581                                  * Let the hal handle the event. We assume
 582                                  * it will clear whatever condition caused
 583                                  * the interrupt.
 584                                  */
 585                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 586                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 587                         }
 588                         if (status & ATH9K_INT_TIM_TIMER) {
 589                                 if (!(ah->ah_caps.hw_caps &
 590                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 591                                         /* Clear RxAbort bit so that we can
 592                                          * receive frames */
 593                                         ath9k_hw_setrxabort(ah, 0);
 594                                         sched = true;
 595                                 }
 596                         }
 597                 }
 598         } while (0);
 599
 600         if (sched) {
 601                 /* turn off every interrupt except SWBA */
 602                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 603                 tasklet_schedule(&sc->intr_tq);
 604         }
 605
 606         return IRQ_HANDLED;
 607 }
 608
 609 static int ath_get_channel(struct ath_softc *sc,
 610                            struct ieee80211_channel *chan)
 611 {
 612         int i;
 613
 614         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 615                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 616                         return i;
 617         }
 618
 619         return -1;
 620 }
 621
 622 /* ext_chan_offset: (-1, 0, 1) (below, none, above) */
 623
 624 static u32 ath_get_extchanmode(struct ath_softc *sc,
 625                                struct ieee80211_channel *chan,
 626                                int ext_chan_offset,
 627                                enum ath9k_ht_macmode tx_chan_width)
 628 {
 629         u32 chanmode = 0;
 630
 631         switch (chan->band) {
 632         case IEEE80211_BAND_2GHZ:
 633                 if ((ext_chan_offset == 0) &&
 634                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 635                         chanmode = CHANNEL_G_HT20;
 636                 if ((ext_chan_offset == 1) &&
 637                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 638                         chanmode = CHANNEL_G_HT40PLUS;
 639                 if ((ext_chan_offset == -1) &&
 640                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 641                         chanmode = CHANNEL_G_HT40MINUS;
 642                 break;
 643         case IEEE80211_BAND_5GHZ:
 644                 if ((ext_chan_offset == 0) &&
 645                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 646                         chanmode = CHANNEL_A_HT20;
 647                 if ((ext_chan_offset == 1) &&
 648                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 649                         chanmode = CHANNEL_A_HT40PLUS;
 650                 if ((ext_chan_offset == -1) &&
 651                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 652                         chanmode = CHANNEL_A_HT40MINUS;
 653                 break;
 654         default:
 655                 break;
 656         }
 657
 658         return chanmode;
 659 }
 660
 661 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 662 {
 663         ath9k_hw_keyreset(sc->sc_ah, keyix);
 664         if (freeslot)
 665                 clear_bit(keyix, sc->sc_keymap);
 666 }
 667
 668 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 669                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 670 {
 671         bool status;
 672
 673         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 674                 keyix, hk, mac, false);
 675
 676         return status != false;
 677 }
 678
 679 static int ath_setkey_tkip(struct ath_softc *sc,
 680                            struct ieee80211_key_conf *key,
 681                            struct ath9k_keyval *hk,
 682                            const u8 *addr)
 683 {
 684         u8 *key_rxmic = NULL;
 685         u8 *key_txmic = NULL;
 686
 687         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 688         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 689
 690         if (addr == NULL) {
 691                 /* Group key installation */
 692                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 693                 return ath_keyset(sc, key->keyidx, hk, addr);
 694         }
 695         if (!sc->sc_splitmic) {
 696                 /*
 697                  * data key goes at first index,
 698                  * the hal handles the MIC keys at index+64.
 699                  */
 700                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 701                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 702                 return ath_keyset(sc, key->keyidx, hk, addr);
 703         }
 704         /*
 705          * TX key goes at first index, RX key at +32.
 706          * The hal handles the MIC keys at index+64.
 707          */
 708         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 709         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 710                 /* Txmic entry failed. No need to proceed further */
 711                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 712                         "Setting TX MIC Key Failed\n");
 713                 return 0;
 714         }
 715
 716         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 717         /* XXX delete tx key on failure? */
 718         return ath_keyset(sc, key->keyidx+32, hk, addr);
 719 }
 720
 721 static int ath_key_config(struct ath_softc *sc,
 722                           const u8 *addr,
 723                           struct ieee80211_key_conf *key)
 724 {
 725         struct ieee80211_vif *vif;
 726         struct ath9k_keyval hk;
 727         const u8 *mac = NULL;
 728         int ret = 0;
 729         enum nl80211_iftype opmode;
 730
 731         memset(&hk, 0, sizeof(hk));
 732
 733         switch (key->alg) {
 734         case ALG_WEP:
 735                 hk.kv_type = ATH9K_CIPHER_WEP;
 736                 break;
 737         case ALG_TKIP:
 738                 hk.kv_type = ATH9K_CIPHER_TKIP;
 739                 break;
 740         case ALG_CCMP:
 741                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 742                 break;
 743         default:
 744                 return -EINVAL;
 745         }
 746
 747         hk.kv_len  = key->keylen;
 748         memcpy(hk.kv_val, key->key, key->keylen);
 749
 750         if (!sc->sc_vaps[0])
 751                 return -EIO;
 752
 753         vif = sc->sc_vaps[0];
 754         opmode = vif->type;
 755
 756         /*
 757          *  Strategy:
 758          *   For STA mc tx, we will not setup a key at
 759          *   all since we never tx mc.
 760          *
 761          *   For STA mc rx, we will use the keyID.
 762          *
 763          *   For ADHOC mc tx, we will use the keyID, and no macaddr.
 764          *
 765          *   For ADHOC mc rx, we will alloc a slot and plumb the mac of
 766          *   the peer node.
 767          *   BUT we will plumb a cleartext key so that we can do
 768          *   per-Sta default key table lookup in software.
 769          */
 770         if (is_broadcast_ether_addr(addr)) {
 771                 switch (opmode) {
 772                 case NL80211_IFTYPE_STATION:
 773                         /* default key:  could be group WPA key
 774                          * or could be static WEP key */
 775                         mac = NULL;
 776                         break;
 777                 case NL80211_IFTYPE_ADHOC:
 778                         break;
 779                 case NL80211_IFTYPE_AP:
 780                         break;
 781                 default:
 782                         ASSERT(0);
 783                         break;
 784                 }
 785         } else {
 786                 mac = addr;
 787         }
 788
 789         if (key->alg == ALG_TKIP)
 790                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 791         else
 792                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 793
 794         if (!ret)
 795                 return -EIO;
 796
 797         return 0;
 798 }
 799
 800 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 801 {
 802         int freeslot;
 803
 804         freeslot = (key->keyidx >= 4) ? 1 : 0;
 805         ath_key_reset(sc, key->keyidx, freeslot);
 806 }
 807
 808 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 809 {
 810 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 811 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 812
 813         ht_info->ht_supported = true;
 814         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 815                        IEEE80211_HT_CAP_SM_PS |
 816                        IEEE80211_HT_CAP_SGI_40 |
 817                        IEEE80211_HT_CAP_DSSSCCK40;
 818
 819         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 820         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 821         /* set up supported mcs set */
 822         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 823         ht_info->mcs.rx_mask[0] = 0xff;
 824         ht_info->mcs.rx_mask[1] = 0xff;
 825         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 826 }
 827
 828 static void ath9k_ht_conf(struct ath_softc *sc,
 829                           struct ieee80211_bss_conf *bss_conf)
 830 {
 831         if (sc->hw->conf.ht.enabled) {
 832                 if (bss_conf->ht.width_40_ok)
 833                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 834                 else
 835                         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 836
 837                 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
 838
 839                 DPRINTF(sc, ATH_DBG_CONFIG,
 840                         "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width);
 841         }
 842 }
 843
 844 static inline int ath_sec_offset(u8 ext_offset)
 845 {
 846         if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE)
 847                 return 0;
 848         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
 849                 return 1;
 850         else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
 851                 return -1;
 852
 853         return 0;
 854 }
 855
 856 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 857                                  struct ieee80211_vif *vif,
 858                                  struct ieee80211_bss_conf *bss_conf)
 859 {
 860         struct ieee80211_hw *hw = sc->hw;
 861         struct ieee80211_channel *curchan = hw->conf.channel;
 862         struct ath_vap *avp = (void *)vif->drv_priv;
 863         int pos;
 864
 865         if (bss_conf->assoc) {
 866                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid);
 867
 868                 /* New association, store aid */
 869                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 870                         sc->sc_curaid = bss_conf->aid;
 871                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 872                                                sc->sc_curaid);
 873                 }
 874
 875                 /* Configure the beacon */
 876                 ath_beacon_config(sc, 0);
 877                 sc->sc_flags |= SC_OP_BEACONS;
 878
 879                 /* Reset rssi stats */
 880                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 881                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 882                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 883                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 884
 885                 /* Update chainmask */
 886                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 887
 888                 DPRINTF(sc, ATH_DBG_CONFIG,
 889                         "bssid %pM aid 0x%x\n",
 890                         sc->sc_curbssid, sc->sc_curaid);
 891
 892                 pos = ath_get_channel(sc, curchan);
 893                 if (pos == -1) {
 894                         DPRINTF(sc, ATH_DBG_FATAL,
 895                                 "Invalid channel: %d\n", curchan->center_freq);
 896                         return;
 897                 }
 898
 899                 if (hw->conf.ht.enabled) {
 900                         int offset =
 901                                 ath_sec_offset(bss_conf->ht.secondary_channel_offset);
 902                         sc->tx_chan_width = (bss_conf->ht.width_40_ok) ?
 903                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
 904
 905                         sc->sc_ah->ah_channels[pos].chanmode =
 906                                 ath_get_extchanmode(sc, curchan,
 907                                                     offset, sc->tx_chan_width);
 908                 } else {
 909                         sc->sc_ah->ah_channels[pos].chanmode =
 910                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 911                                 CHANNEL_G : CHANNEL_A;
 912                 }
 913
 914                 /* set h/w channel */
 915                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 916                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n",
 917                                 curchan->center_freq);
 918
 919                 /* Start ANI */
 920                 mod_timer(&sc->sc_ani.timer,
 921                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 922
 923         } else {
 924                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 925                 sc->sc_curaid = 0;
 926         }
 927 }
 928
 929 /********************************/
 930 /*       LED functions          */
 931 /********************************/
 932
 933 static void ath_led_brightness(struct led_classdev *led_cdev,
 934                                enum led_brightness brightness)
 935 {
 936         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 937         struct ath_softc *sc = led->sc;
 938
 939         switch (brightness) {
 940         case LED_OFF:
 941                 if (led->led_type == ATH_LED_ASSOC ||
 942                     led->led_type == ATH_LED_RADIO)
 943                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 944                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 945                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 946                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 947                 break;
 948         case LED_FULL:
 949                 if (led->led_type == ATH_LED_ASSOC)
 950                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 951                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 952                 break;
 953         default:
 954                 break;
 955         }
 956 }
 957
 958 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 959                             char *trigger)
 960 {
 961         int ret;
 962
 963         led->sc = sc;
 964         led->led_cdev.name = led->name;
 965         led->led_cdev.default_trigger = trigger;
 966         led->led_cdev.brightness_set = ath_led_brightness;
 967
 968         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 969         if (ret)
 970                 DPRINTF(sc, ATH_DBG_FATAL,
 971                         "Failed to register led:%s", led->name);
 972         else
 973                 led->registered = 1;
 974         return ret;
 975 }
 976
 977 static void ath_unregister_led(struct ath_led *led)
 978 {
 979         if (led->registered) {
 980                 led_classdev_unregister(&led->led_cdev);
 981                 led->registered = 0;
 982         }
 983 }
 984
 985 static void ath_deinit_leds(struct ath_softc *sc)
 986 {
 987         ath_unregister_led(&sc->assoc_led);
 988         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 989         ath_unregister_led(&sc->tx_led);
 990         ath_unregister_led(&sc->rx_led);
 991         ath_unregister_led(&sc->radio_led);
 992         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 993 }
 994
 995 static void ath_init_leds(struct ath_softc *sc)
 996 {
 997         char *trigger;
 998         int ret;
 999
1000         /* Configure gpio 1 for output */
1001         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1002                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1003         /* LED off, active low */
1004         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1005
1006         trigger = ieee80211_get_radio_led_name(sc->hw);
1007         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1008                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1009         ret = ath_register_led(sc, &sc->radio_led, trigger);
1010         sc->radio_led.led_type = ATH_LED_RADIO;
1011         if (ret)
1012                 goto fail;
1013
1014         trigger = ieee80211_get_assoc_led_name(sc->hw);
1015         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1016                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1017         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1018         sc->assoc_led.led_type = ATH_LED_ASSOC;
1019         if (ret)
1020                 goto fail;
1021
1022         trigger = ieee80211_get_tx_led_name(sc->hw);
1023         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1024                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1025         ret = ath_register_led(sc, &sc->tx_led, trigger);
1026         sc->tx_led.led_type = ATH_LED_TX;
1027         if (ret)
1028                 goto fail;
1029
1030         trigger = ieee80211_get_rx_led_name(sc->hw);
1031         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1032                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1033         ret = ath_register_led(sc, &sc->rx_led, trigger);
1034         sc->rx_led.led_type = ATH_LED_RX;
1035         if (ret)
1036                 goto fail;
1037
1038         return;
1039
1040 fail:
1041         ath_deinit_leds(sc);
1042 }
1043
1044 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1045
1046 /*******************/
1047 /*      Rfkill     */
1048 /*******************/
1049
1050 static void ath_radio_enable(struct ath_softc *sc)
1051 {
1052         struct ath_hal *ah = sc->sc_ah;
1053         int status;
1054
1055         spin_lock_bh(&sc->sc_resetlock);
1056         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1057                             sc->tx_chan_width,
1058                             sc->sc_tx_chainmask,
1059                             sc->sc_rx_chainmask,
1060                             sc->sc_ht_extprotspacing,
1061                             false, &status)) {
1062                 DPRINTF(sc, ATH_DBG_FATAL,
1063                         "Unable to reset channel %u (%uMhz) "
1064                         "flags 0x%x hal status %u\n",
1065                         ath9k_hw_mhz2ieee(ah,
1066                                           ah->ah_curchan->channel,
1067                                           ah->ah_curchan->channelFlags),
1068                         ah->ah_curchan->channel,
1069                         ah->ah_curchan->channelFlags, status);
1070         }
1071         spin_unlock_bh(&sc->sc_resetlock);
1072
1073         ath_update_txpow(sc);
1074         if (ath_startrecv(sc) != 0) {
1075                 DPRINTF(sc, ATH_DBG_FATAL,
1076                         "Unable to restart recv logic\n");
1077                 return;
1078         }
1079
1080         if (sc->sc_flags & SC_OP_BEACONS)
1081                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1082
1083         /* Re-Enable  interrupts */
1084         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1085
1086         /* Enable LED */
1087         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1088                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1089         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1090
1091         ieee80211_wake_queues(sc->hw);
1092 }
1093
1094 static void ath_radio_disable(struct ath_softc *sc)
1095 {
1096         struct ath_hal *ah = sc->sc_ah;
1097         int status;
1098
1099
1100         ieee80211_stop_queues(sc->hw);
1101
1102         /* Disable LED */
1103         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1104         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1105
1106         /* Disable interrupts */
1107         ath9k_hw_set_interrupts(ah, 0);
1108
1109         ath_draintxq(sc, false);        /* clear pending tx frames */
1110         ath_stoprecv(sc);               /* turn off frame recv */
1111         ath_flushrecv(sc);              /* flush recv queue */
1112
1113         spin_lock_bh(&sc->sc_resetlock);
1114         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1115                             sc->tx_chan_width,
1116                             sc->sc_tx_chainmask,
1117                             sc->sc_rx_chainmask,
1118                             sc->sc_ht_extprotspacing,
1119                             false, &status)) {
1120                 DPRINTF(sc, ATH_DBG_FATAL,
1121                         "Unable to reset channel %u (%uMhz) "
1122                         "flags 0x%x hal status %u\n",
1123                         ath9k_hw_mhz2ieee(ah,
1124                                 ah->ah_curchan->channel,
1125                                 ah->ah_curchan->channelFlags),
1126                         ah->ah_curchan->channel,
1127                         ah->ah_curchan->channelFlags, status);
1128         }
1129         spin_unlock_bh(&sc->sc_resetlock);
1130
1131         ath9k_hw_phy_disable(ah);
1132         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1133 }
1134
1135 static bool ath_is_rfkill_set(struct ath_softc *sc)
1136 {
1137         struct ath_hal *ah = sc->sc_ah;
1138
1139         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1140                                   ah->ah_rfkill_polarity;
1141 }
1142
1143 /* h/w rfkill poll function */
1144 static void ath_rfkill_poll(struct work_struct *work)
1145 {
1146         struct ath_softc *sc = container_of(work, struct ath_softc,
1147                                             rf_kill.rfkill_poll.work);
1148         bool radio_on;
1149
1150         if (sc->sc_flags & SC_OP_INVALID)
1151                 return;
1152
1153         radio_on = !ath_is_rfkill_set(sc);
1154
1155         /*
1156          * enable/disable radio only when there is a
1157          * state change in RF switch
1158          */
1159         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1160                 enum rfkill_state state;
1161
1162                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1163                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1164                                 : RFKILL_STATE_HARD_BLOCKED;
1165                 } else if (radio_on) {
1166                         ath_radio_enable(sc);
1167                         state = RFKILL_STATE_UNBLOCKED;
1168                 } else {
1169                         ath_radio_disable(sc);
1170                         state = RFKILL_STATE_HARD_BLOCKED;
1171                 }
1172
1173                 if (state == RFKILL_STATE_HARD_BLOCKED)
1174                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1175                 else
1176                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1177
1178                 rfkill_force_state(sc->rf_kill.rfkill, state);
1179         }
1180
1181         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1182                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1183 }
1184
1185 /* s/w rfkill handler */
1186 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1187 {
1188         struct ath_softc *sc = data;
1189
1190         switch (state) {
1191         case RFKILL_STATE_SOFT_BLOCKED:
1192                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1193                     SC_OP_RFKILL_SW_BLOCKED)))
1194                         ath_radio_disable(sc);
1195                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1196                 return 0;
1197         case RFKILL_STATE_UNBLOCKED:
1198                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1199                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1200                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1201                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1202                                         "radio as it is disabled by h/w\n");
1203                                 return -EPERM;
1204                         }
1205                         ath_radio_enable(sc);
1206                 }
1207                 return 0;
1208         default:
1209                 return -EINVAL;
1210         }
1211 }
1212
1213 /* Init s/w rfkill */
1214 static int ath_init_sw_rfkill(struct ath_softc *sc)
1215 {
1216         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1217                                              RFKILL_TYPE_WLAN);
1218         if (!sc->rf_kill.rfkill) {
1219                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1220                 return -ENOMEM;
1221         }
1222
1223         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1224                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1225         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1226         sc->rf_kill.rfkill->data = sc;
1227         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1228         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1229         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1230
1231         return 0;
1232 }
1233
1234 /* Deinitialize rfkill */
1235 static void ath_deinit_rfkill(struct ath_softc *sc)
1236 {
1237         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1238                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1239
1240         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1241                 rfkill_unregister(sc->rf_kill.rfkill);
1242                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1243                 sc->rf_kill.rfkill = NULL;
1244         }
1245 }
1246
1247 static int ath_start_rfkill_poll(struct ath_softc *sc)
1248 {
1249         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1250                 queue_delayed_work(sc->hw->workqueue,
1251                                    &sc->rf_kill.rfkill_poll, 0);
1252
1253         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1254                 if (rfkill_register(sc->rf_kill.rfkill)) {
1255                         DPRINTF(sc, ATH_DBG_FATAL,
1256                                 "Unable to register rfkill\n");
1257                         rfkill_free(sc->rf_kill.rfkill);
1258
1259                         /* Deinitialize the device */
1260                         ath_detach(sc);
1261                         if (sc->pdev->irq)
1262                                 free_irq(sc->pdev->irq, sc);
1263                         pci_iounmap(sc->pdev, sc->mem);
1264                         pci_release_region(sc->pdev, 0);
1265                         pci_disable_device(sc->pdev);
1266                         ieee80211_free_hw(sc->hw);
1267                         return -EIO;
1268                 } else {
1269                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1270                 }
1271         }
1272
1273         return 0;
1274 }
1275 #endif /* CONFIG_RFKILL */
1276
1277 static void ath_detach(struct ath_softc *sc)
1278 {
1279         struct ieee80211_hw *hw = sc->hw;
1280         int i = 0;
1281
1282         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1283
1284 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1285         ath_deinit_rfkill(sc);
1286 #endif
1287         ath_deinit_leds(sc);
1288
1289         ieee80211_unregister_hw(hw);
1290
1291         ath_rate_control_unregister();
1292
1293         ath_rx_cleanup(sc);
1294         ath_tx_cleanup(sc);
1295
1296         tasklet_kill(&sc->intr_tq);
1297         tasklet_kill(&sc->bcon_tasklet);
1298
1299         if (!(sc->sc_flags & SC_OP_INVALID))
1300                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1301
1302         /* cleanup tx queues */
1303         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1304                 if (ATH_TXQ_SETUP(sc, i))
1305                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1306
1307         ath9k_hw_detach(sc->sc_ah);
1308         ath9k_exit_debug(sc);
1309 }
1310
1311 static int ath_init(u16 devid, struct ath_softc *sc)
1312 {
1313         struct ath_hal *ah = NULL;
1314         int status;
1315         int error = 0, i;
1316         int csz = 0;
1317
1318         /* XXX: hardware will not be ready until ath_open() being called */
1319         sc->sc_flags |= SC_OP_INVALID;
1320
1321         if (ath9k_init_debug(sc) < 0)
1322                 printk(KERN_ERR "Unable to create debugfs files\n");
1323
1324         spin_lock_init(&sc->sc_resetlock);
1325         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1326         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1327                      (unsigned long)sc);
1328
1329         /*
1330          * Cache line size is used to size and align various
1331          * structures used to communicate with the hardware.
1332          */
1333         bus_read_cachesize(sc, &csz);
1334         /* XXX assert csz is non-zero */
1335         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1336
1337         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1338         if (ah == NULL) {
1339                 DPRINTF(sc, ATH_DBG_FATAL,
1340                         "Unable to attach hardware; HAL status %u\n", status);
1341                 error = -ENXIO;
1342                 goto bad;
1343         }
1344         sc->sc_ah = ah;
1345
1346         /* Get the hardware key cache size. */
1347         sc->sc_keymax = ah->ah_caps.keycache_size;
1348         if (sc->sc_keymax > ATH_KEYMAX) {
1349                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1350                         "Warning, using only %u entries in %u key cache\n",
1351                         ATH_KEYMAX, sc->sc_keymax);
1352                 sc->sc_keymax = ATH_KEYMAX;
1353         }
1354
1355         /*
1356          * Reset the key cache since some parts do not
1357          * reset the contents on initial power up.
1358          */
1359         for (i = 0; i < sc->sc_keymax; i++)
1360                 ath9k_hw_keyreset(ah, (u16) i);
1361         /*
1362          * Mark key cache slots associated with global keys
1363          * as in use.  If we knew TKIP was not to be used we
1364          * could leave the +32, +64, and +32+64 slots free.
1365          * XXX only for splitmic.
1366          */
1367         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1368                 set_bit(i, sc->sc_keymap);
1369                 set_bit(i + 32, sc->sc_keymap);
1370                 set_bit(i + 64, sc->sc_keymap);
1371                 set_bit(i + 32 + 64, sc->sc_keymap);
1372         }
1373
1374         /* Collect the channel list using the default country code */
1375
1376         error = ath_setup_channels(sc);
1377         if (error)
1378                 goto bad;
1379
1380         /* default to MONITOR mode */
1381         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1382
1383
1384         /* Setup rate tables */
1385
1386         ath_rate_attach(sc);
1387         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1388         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1389
1390         /*
1391          * Allocate hardware transmit queues: one queue for
1392          * beacon frames and one data queue for each QoS
1393          * priority.  Note that the hal handles reseting
1394          * these queues at the needed time.
1395          */
1396         sc->sc_bhalq = ath_beaconq_setup(ah);
1397         if (sc->sc_bhalq == -1) {
1398                 DPRINTF(sc, ATH_DBG_FATAL,
1399                         "Unable to setup a beacon xmit queue\n");
1400                 error = -EIO;
1401                 goto bad2;
1402         }
1403         sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1404         if (sc->sc_cabq == NULL) {
1405                 DPRINTF(sc, ATH_DBG_FATAL,
1406                         "Unable to setup CAB xmit queue\n");
1407                 error = -EIO;
1408                 goto bad2;
1409         }
1410
1411         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1412         ath_cabq_update(sc);
1413
1414         for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1415                 sc->sc_haltype2q[i] = -1;
1416
1417         /* Setup data queues */
1418         /* NB: ensure BK queue is the lowest priority h/w queue */
1419         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1420                 DPRINTF(sc, ATH_DBG_FATAL,
1421                         "Unable to setup xmit queue for BK traffic\n");
1422                 error = -EIO;
1423                 goto bad2;
1424         }
1425
1426         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1427                 DPRINTF(sc, ATH_DBG_FATAL,
1428                         "Unable to setup xmit queue for BE traffic\n");
1429                 error = -EIO;
1430                 goto bad2;
1431         }
1432         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1433                 DPRINTF(sc, ATH_DBG_FATAL,
1434                         "Unable to setup xmit queue for VI traffic\n");
1435                 error = -EIO;
1436                 goto bad2;
1437         }
1438         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1439                 DPRINTF(sc, ATH_DBG_FATAL,
1440                         "Unable to setup xmit queue for VO traffic\n");
1441                 error = -EIO;
1442                 goto bad2;
1443         }
1444
1445         /* Initializes the noise floor to a reasonable default value.
1446          * Later on this will be updated during ANI processing. */
1447
1448         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1449         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1450
1451         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1452                                    ATH9K_CIPHER_TKIP, NULL)) {
1453                 /*
1454                  * Whether we should enable h/w TKIP MIC.
1455                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1456                  * report WMM capable, so it's always safe to turn on
1457                  * TKIP MIC in this case.
1458                  */
1459                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1460                                        0, 1, NULL);
1461         }
1462
1463         /*
1464          * Check whether the separate key cache entries
1465          * are required to handle both tx+rx MIC keys.
1466          * With split mic keys the number of stations is limited
1467          * to 27 otherwise 59.
1468          */
1469         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1470                                    ATH9K_CIPHER_TKIP, NULL)
1471             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1472                                       ATH9K_CIPHER_MIC, NULL)
1473             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1474                                       0, NULL))
1475                 sc->sc_splitmic = 1;
1476
1477         /* turn on mcast key search if possible */
1478         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1479                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1480                                              1, NULL);
1481
1482         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1483         sc->sc_config.txpowlimit_override = 0;
1484
1485         /* 11n Capabilities */
1486         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1487                 sc->sc_flags |= SC_OP_TXAGGR;
1488                 sc->sc_flags |= SC_OP_RXAGGR;
1489         }
1490
1491         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1492         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1493
1494         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1495         sc->sc_defant = ath9k_hw_getdefantenna(ah);
1496
1497         ath9k_hw_getmac(ah, sc->sc_myaddr);
1498         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1499                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1500                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1501                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1502         }
1503
1504         sc->sc_slottime = ATH9K_SLOT_TIME_9;    /* default to short slot time */
1505
1506         /* initialize beacon slots */
1507         for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1508                 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1509
1510         /* save MISC configurations */
1511         sc->sc_config.swBeaconProcess = 1;
1512
1513 #ifdef CONFIG_SLOW_ANT_DIV
1514         /* range is 40 - 255, we use something in the middle */
1515         ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1516 #endif
1517
1518         /* setup channels and rates */
1519
1520         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1521                 sc->channels[IEEE80211_BAND_2GHZ];
1522         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1523                 sc->rates[IEEE80211_BAND_2GHZ];
1524         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1525
1526         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1527                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1528                         sc->channels[IEEE80211_BAND_5GHZ];
1529                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1530                         sc->rates[IEEE80211_BAND_5GHZ];
1531                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1532         }
1533
1534         return 0;
1535 bad2:
1536         /* cleanup tx queues */
1537         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1538                 if (ATH_TXQ_SETUP(sc, i))
1539                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1540 bad:
1541         if (ah)
1542                 ath9k_hw_detach(ah);
1543
1544         return error;
1545 }
1546
1547 static int ath_attach(u16 devid, struct ath_softc *sc)
1548 {
1549         struct ieee80211_hw *hw = sc->hw;
1550         int error = 0;
1551
1552         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1553
1554         error = ath_init(devid, sc);
1555         if (error != 0)
1556                 return error;
1557
1558         /* get mac address from hardware and set in mac80211 */
1559
1560         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1561
1562         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1563                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1564                 IEEE80211_HW_SIGNAL_DBM |
1565                 IEEE80211_HW_AMPDU_AGGREGATION;
1566
1567         hw->wiphy->interface_modes =
1568                 BIT(NL80211_IFTYPE_AP) |
1569                 BIT(NL80211_IFTYPE_STATION) |
1570                 BIT(NL80211_IFTYPE_ADHOC);
1571
1572         hw->queues = 4;
1573         hw->max_rates = 4;
1574         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1575         hw->sta_data_size = sizeof(struct ath_node);
1576         hw->vif_data_size = sizeof(struct ath_vap);
1577
1578         /* Register rate control */
1579         hw->rate_control_algorithm = "ath9k_rate_control";
1580         error = ath_rate_control_register();
1581         if (error != 0) {
1582                 DPRINTF(sc, ATH_DBG_FATAL,
1583                         "Unable to register rate control algorithm: %d\n", error);
1584                 ath_rate_control_unregister();
1585                 goto bad;
1586         }
1587
1588         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1589                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1590                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1591                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1592         }
1593
1594         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1595         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1596                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1597                         &sc->sbands[IEEE80211_BAND_5GHZ];
1598
1599         /* initialize tx/rx engine */
1600         error = ath_tx_init(sc, ATH_TXBUF);
1601         if (error != 0)
1602                 goto detach;
1603
1604         error = ath_rx_init(sc, ATH_RXBUF);
1605         if (error != 0)
1606                 goto detach;
1607
1608 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1609         /* Initialze h/w Rfkill */
1610         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1611                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1612
1613         /* Initialize s/w rfkill */
1614         if (ath_init_sw_rfkill(sc))
1615                 goto detach;
1616 #endif
1617
1618         error = ieee80211_register_hw(hw);
1619         if (error != 0) {
1620                 ath_rate_control_unregister();
1621                 goto bad;
1622         }
1623
1624         /* Initialize LED control */
1625         ath_init_leds(sc);
1626
1627         return 0;
1628 detach:
1629         ath_detach(sc);
1630 bad:
1631         return error;
1632 }
1633
1634 int ath_reset(struct ath_softc *sc, bool retry_tx)
1635 {
1636         struct ath_hal *ah = sc->sc_ah;
1637         int status;
1638         int error = 0;
1639
1640         ath9k_hw_set_interrupts(ah, 0);
1641         ath_draintxq(sc, retry_tx);
1642         ath_stoprecv(sc);
1643         ath_flushrecv(sc);
1644
1645         spin_lock_bh(&sc->sc_resetlock);
1646         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1647                             sc->tx_chan_width,
1648                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1649                             sc->sc_ht_extprotspacing, false, &status)) {
1650                 DPRINTF(sc, ATH_DBG_FATAL,
1651                         "Unable to reset hardware; hal status %u\n", status);
1652                 error = -EIO;
1653         }
1654         spin_unlock_bh(&sc->sc_resetlock);
1655
1656         if (ath_startrecv(sc) != 0)
1657                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1658
1659         /*
1660          * We may be doing a reset in response to a request
1661          * that changes the channel so update any state that
1662          * might change as a result.
1663          */
1664         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1665
1666         ath_update_txpow(sc);
1667
1668         if (sc->sc_flags & SC_OP_BEACONS)
1669                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1670
1671         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1672
1673         if (retry_tx) {
1674                 int i;
1675                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1676                         if (ATH_TXQ_SETUP(sc, i)) {
1677                                 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1678                                 ath_txq_schedule(sc, &sc->sc_txq[i]);
1679                                 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1680                         }
1681                 }
1682         }
1683
1684         return error;
1685 }
1686
1687 /*
1688  *  This function will allocate both the DMA descriptor structure, and the
1689  *  buffers it contains.  These are used to contain the descriptors used
1690  *  by the system.
1691 */
1692 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1693                       struct list_head *head, const char *name,
1694                       int nbuf, int ndesc)
1695 {
1696 #define DS2PHYS(_dd, _ds)                                               \
1697         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1698 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1699 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1700
1701         struct ath_desc *ds;
1702         struct ath_buf *bf;
1703         int i, bsize, error;
1704
1705         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1706                 name, nbuf, ndesc);
1707
1708         /* ath_desc must be a multiple of DWORDs */
1709         if ((sizeof(struct ath_desc) % 4) != 0) {
1710                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1711                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1712                 error = -ENOMEM;
1713                 goto fail;
1714         }
1715
1716         dd->dd_name = name;
1717         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1718
1719         /*
1720          * Need additional DMA memory because we can't use
1721          * descriptors that cross the 4K page boundary. Assume
1722          * one skipped descriptor per 4K page.
1723          */
1724         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1725                 u32 ndesc_skipped =
1726                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1727                 u32 dma_len;
1728
1729                 while (ndesc_skipped) {
1730                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1731                         dd->dd_desc_len += dma_len;
1732
1733                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1734                 };
1735         }
1736
1737         /* allocate descriptors */
1738         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1739                               dd->dd_desc_len,
1740                               &dd->dd_desc_paddr);
1741         if (dd->dd_desc == NULL) {
1742                 error = -ENOMEM;
1743                 goto fail;
1744         }
1745         ds = dd->dd_desc;
1746         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1747                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1748                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1749
1750         /* allocate buffers */
1751         bsize = sizeof(struct ath_buf) * nbuf;
1752         bf = kmalloc(bsize, GFP_KERNEL);
1753         if (bf == NULL) {
1754                 error = -ENOMEM;
1755                 goto fail2;
1756         }
1757         memset(bf, 0, bsize);
1758         dd->dd_bufptr = bf;
1759
1760         INIT_LIST_HEAD(head);
1761         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1762                 bf->bf_desc = ds;
1763                 bf->bf_daddr = DS2PHYS(dd, ds);
1764
1765                 if (!(sc->sc_ah->ah_caps.hw_caps &
1766                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1767                         /*
1768                          * Skip descriptor addresses which can cause 4KB
1769                          * boundary crossing (addr + length) with a 32 dword
1770                          * descriptor fetch.
1771                          */
1772                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1773                                 ASSERT((caddr_t) bf->bf_desc <
1774                                        ((caddr_t) dd->dd_desc +
1775                                         dd->dd_desc_len));
1776
1777                                 ds += ndesc;
1778                                 bf->bf_desc = ds;
1779                                 bf->bf_daddr = DS2PHYS(dd, ds);
1780                         }
1781                 }
1782                 list_add_tail(&bf->list, head);
1783         }
1784         return 0;
1785 fail2:
1786         pci_free_consistent(sc->pdev,
1787                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1788 fail:
1789         memset(dd, 0, sizeof(*dd));
1790         return error;
1791 #undef ATH_DESC_4KB_BOUND_CHECK
1792 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1793 #undef DS2PHYS
1794 }
1795
1796 void ath_descdma_cleanup(struct ath_softc *sc,
1797                          struct ath_descdma *dd,
1798                          struct list_head *head)
1799 {
1800         pci_free_consistent(sc->pdev,
1801                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1802
1803         INIT_LIST_HEAD(head);
1804         kfree(dd->dd_bufptr);
1805         memset(dd, 0, sizeof(*dd));
1806 }
1807
1808 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1809 {
1810         int qnum;
1811
1812         switch (queue) {
1813         case 0:
1814                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1815                 break;
1816         case 1:
1817                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1818                 break;
1819         case 2:
1820                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1821                 break;
1822         case 3:
1823                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1824                 break;
1825         default:
1826                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1827                 break;
1828         }
1829
1830         return qnum;
1831 }
1832
1833 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1834 {
1835         int qnum;
1836
1837         switch (queue) {
1838         case ATH9K_WME_AC_VO:
1839                 qnum = 0;
1840                 break;
1841         case ATH9K_WME_AC_VI:
1842                 qnum = 1;
1843                 break;
1844         case ATH9K_WME_AC_BE:
1845                 qnum = 2;
1846                 break;
1847         case ATH9K_WME_AC_BK:
1848                 qnum = 3;
1849                 break;
1850         default:
1851                 qnum = -1;
1852                 break;
1853         }
1854
1855         return qnum;
1856 }
1857
1858 /**********************/
1859 /* mac80211 callbacks */
1860 /**********************/
1861
1862 static int ath9k_start(struct ieee80211_hw *hw)
1863 {
1864         struct ath_softc *sc = hw->priv;
1865         struct ieee80211_channel *curchan = hw->conf.channel;
1866         struct ath9k_channel *init_channel;
1867         int error = 0, pos, status;
1868
1869         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1870                 "initial channel: %d MHz\n", curchan->center_freq);
1871
1872         /* setup initial channel */
1873
1874         pos = ath_get_channel(sc, curchan);
1875         if (pos == -1) {
1876                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1877                 error = -EINVAL;
1878                 goto error;
1879         }
1880
1881         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1882         sc->sc_ah->ah_channels[pos].chanmode =
1883                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1884         init_channel = &sc->sc_ah->ah_channels[pos];
1885
1886         /* Reset SERDES registers */
1887         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1888
1889         /*
1890          * The basic interface to setting the hardware in a good
1891          * state is ``reset''.  On return the hardware is known to
1892          * be powered up and with interrupts disabled.  This must
1893          * be followed by initialization of the appropriate bits
1894          * and then setup of the interrupt mask.
1895          */
1896         spin_lock_bh(&sc->sc_resetlock);
1897         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1898                             sc->tx_chan_width,
1899                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1900                             sc->sc_ht_extprotspacing, false, &status)) {
1901                 DPRINTF(sc, ATH_DBG_FATAL,
1902                         "Unable to reset hardware; hal status %u "
1903                         "(freq %u flags 0x%x)\n", status,
1904                         init_channel->channel, init_channel->channelFlags);
1905                 error = -EIO;
1906                 spin_unlock_bh(&sc->sc_resetlock);
1907                 goto error;
1908         }
1909         spin_unlock_bh(&sc->sc_resetlock);
1910
1911         /*
1912          * This is needed only to setup initial state
1913          * but it's best done after a reset.
1914          */
1915         ath_update_txpow(sc);
1916
1917         /*
1918          * Setup the hardware after reset:
1919          * The receive engine is set going.
1920          * Frame transmit is handled entirely
1921          * in the frame output path; there's nothing to do
1922          * here except setup the interrupt mask.
1923          */
1924         if (ath_startrecv(sc) != 0) {
1925                 DPRINTF(sc, ATH_DBG_FATAL,
1926                         "Unable to start recv logic\n");
1927                 error = -EIO;
1928                 goto error;
1929         }
1930
1931         /* Setup our intr mask. */
1932         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1933                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1934                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1935
1936         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1937                 sc->sc_imask |= ATH9K_INT_GTT;
1938
1939         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1940                 sc->sc_imask |= ATH9K_INT_CST;
1941
1942         /*
1943          * Enable MIB interrupts when there are hardware phy counters.
1944          * Note we only do this (at the moment) for station mode.
1945          */
1946         if (ath9k_hw_phycounters(sc->sc_ah) &&
1947             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1948              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1949                 sc->sc_imask |= ATH9K_INT_MIB;
1950         /*
1951          * Some hardware processes the TIM IE and fires an
1952          * interrupt when the TIM bit is set.  For hardware
1953          * that does, if not overridden by configuration,
1954          * enable the TIM interrupt when operating as station.
1955          */
1956         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1957             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1958             !sc->sc_config.swBeaconProcess)
1959                 sc->sc_imask |= ATH9K_INT_TIM;
1960
1961         ath_setcurmode(sc, ath_chan2mode(init_channel));
1962
1963         sc->sc_flags &= ~SC_OP_INVALID;
1964
1965         /* Disable BMISS interrupt when we're not associated */
1966         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1967         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1968
1969         ieee80211_wake_queues(sc->hw);
1970
1971 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1972         error = ath_start_rfkill_poll(sc);
1973 #endif
1974
1975 error:
1976         return error;
1977 }
1978
1979 static int ath9k_tx(struct ieee80211_hw *hw,
1980                     struct sk_buff *skb)
1981 {
1982         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1983         struct ath_softc *sc = hw->priv;
1984         struct ath_tx_control txctl;
1985         int hdrlen, padsize;
1986
1987         memset(&txctl, 0, sizeof(struct ath_tx_control));
1988
1989         /*
1990          * As a temporary workaround, assign seq# here; this will likely need
1991          * to be cleaned up to work better with Beacon transmission and virtual
1992          * BSSes.
1993          */
1994         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1995                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1996                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1997                         sc->seq_no += 0x10;
1998                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1999                 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2000         }
2001
2002         /* Add the padding after the header if this is not already done */
2003         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2004         if (hdrlen & 3) {
2005                 padsize = hdrlen % 4;
2006                 if (skb_headroom(skb) < padsize)
2007                         return -1;
2008                 skb_push(skb, padsize);
2009                 memmove(skb->data, skb->data + padsize, hdrlen);
2010         }
2011
2012         /* Check if a tx queue is available */
2013
2014         txctl.txq = ath_test_get_txq(sc, skb);
2015         if (!txctl.txq)
2016                 goto exit;
2017
2018         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2019
2020         if (ath_tx_start(sc, skb, &txctl) != 0) {
2021                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2022                 goto exit;
2023         }
2024
2025         return 0;
2026 exit:
2027         dev_kfree_skb_any(skb);
2028         return 0;
2029 }
2030
2031 static void ath9k_stop(struct ieee80211_hw *hw)
2032 {
2033         struct ath_softc *sc = hw->priv;
2034
2035         if (sc->sc_flags & SC_OP_INVALID) {
2036                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2037                 return;
2038         }
2039
2040         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2041
2042         ieee80211_stop_queues(sc->hw);
2043
2044         /* make sure h/w will not generate any interrupt
2045          * before setting the invalid flag. */
2046         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2047
2048         if (!(sc->sc_flags & SC_OP_INVALID)) {
2049                 ath_draintxq(sc, false);
2050                 ath_stoprecv(sc);
2051                 ath9k_hw_phy_disable(sc->sc_ah);
2052         } else
2053                 sc->sc_rxlink = NULL;
2054
2055 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2056         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2057                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2058 #endif
2059         /* disable HAL and put h/w to sleep */
2060         ath9k_hw_disable(sc->sc_ah);
2061         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2062
2063         sc->sc_flags |= SC_OP_INVALID;
2064
2065         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2066 }
2067
2068 static int ath9k_add_interface(struct ieee80211_hw *hw,
2069                                struct ieee80211_if_init_conf *conf)
2070 {
2071         struct ath_softc *sc = hw->priv;
2072         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2073         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2074
2075         /* Support only vap for now */
2076
2077         if (sc->sc_nvaps)
2078                 return -ENOBUFS;
2079
2080         switch (conf->type) {
2081         case NL80211_IFTYPE_STATION:
2082                 ic_opmode = NL80211_IFTYPE_STATION;
2083                 break;
2084         case NL80211_IFTYPE_ADHOC:
2085                 ic_opmode = NL80211_IFTYPE_ADHOC;
2086                 break;
2087         case NL80211_IFTYPE_AP:
2088                 ic_opmode = NL80211_IFTYPE_AP;
2089                 break;
2090         default:
2091                 DPRINTF(sc, ATH_DBG_FATAL,
2092                         "Interface type %d not yet supported\n", conf->type);
2093                 return -EOPNOTSUPP;
2094         }
2095
2096         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2097
2098         /* Set the VAP opmode */
2099         avp->av_opmode = ic_opmode;
2100         avp->av_bslot = -1;
2101
2102         if (ic_opmode == NL80211_IFTYPE_AP)
2103                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2104
2105         sc->sc_vaps[0] = conf->vif;
2106         sc->sc_nvaps++;
2107
2108         /* Set the device opmode */
2109         sc->sc_ah->ah_opmode = ic_opmode;
2110
2111         if (conf->type == NL80211_IFTYPE_AP) {
2112                 /* TODO: is this a suitable place to start ANI for AP mode? */
2113                 /* Start ANI */
2114                 mod_timer(&sc->sc_ani.timer,
2115                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2116         }
2117
2118         return 0;
2119 }
2120
2121 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2122                                    struct ieee80211_if_init_conf *conf)
2123 {
2124         struct ath_softc *sc = hw->priv;
2125         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2126
2127         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2128
2129 #ifdef CONFIG_SLOW_ANT_DIV
2130         ath_slow_ant_div_stop(&sc->sc_antdiv);
2131 #endif
2132         /* Stop ANI */
2133         del_timer_sync(&sc->sc_ani.timer);
2134
2135         /* Reclaim beacon resources */
2136         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2137             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2138                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2139                 ath_beacon_return(sc, avp);
2140         }
2141
2142         sc->sc_flags &= ~SC_OP_BEACONS;
2143
2144         sc->sc_vaps[0] = NULL;
2145         sc->sc_nvaps--;
2146 }
2147
2148 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2149 {
2150         struct ath_softc *sc = hw->priv;
2151         struct ieee80211_conf *conf = &hw->conf;
2152
2153         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2154                 struct ieee80211_channel *curchan = hw->conf.channel;
2155                 int pos;
2156
2157                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2158                         curchan->center_freq);
2159
2160                 pos = ath_get_channel(sc, curchan);
2161                 if (pos == -1) {
2162                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2163                                 curchan->center_freq);
2164                         return -EINVAL;
2165                 }
2166
2167                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2168                 sc->sc_ah->ah_channels[pos].chanmode =
2169                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2170                         CHANNEL_G : CHANNEL_A;
2171
2172                 if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) &&
2173                     (conf->ht.enabled)) {
2174                         sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ?
2175                                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
2176
2177                         sc->sc_ah->ah_channels[pos].chanmode =
2178                                 ath_get_extchanmode(sc, curchan,
2179                                                     conf->ht.sec_chan_offset,
2180                                                     sc->tx_chan_width);
2181                 }
2182
2183                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2184                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2185                         return -EINVAL;
2186                 }
2187         }
2188
2189         if (changed & IEEE80211_CONF_CHANGE_HT)
2190                 ath_update_chainmask(sc, conf->ht.enabled);
2191
2192         if (changed & IEEE80211_CONF_CHANGE_POWER)
2193                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2194
2195         return 0;
2196 }
2197
2198 static int ath9k_config_interface(struct ieee80211_hw *hw,
2199                                   struct ieee80211_vif *vif,
2200                                   struct ieee80211_if_conf *conf)
2201 {
2202         struct ath_softc *sc = hw->priv;
2203         struct ath_hal *ah = sc->sc_ah;
2204         struct ath_vap *avp = (void *)vif->drv_priv;
2205         u32 rfilt = 0;
2206         int error, i;
2207
2208         /* TODO: Need to decide which hw opmode to use for multi-interface
2209          * cases */
2210         if (vif->type == NL80211_IFTYPE_AP &&
2211             ah->ah_opmode != NL80211_IFTYPE_AP) {
2212                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2213                 ath9k_hw_setopmode(ah);
2214                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2215                 /* Request full reset to get hw opmode changed properly */
2216                 sc->sc_flags |= SC_OP_FULL_RESET;
2217         }
2218
2219         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2220             !is_zero_ether_addr(conf->bssid)) {
2221                 switch (vif->type) {
2222                 case NL80211_IFTYPE_STATION:
2223                 case NL80211_IFTYPE_ADHOC:
2224                         /* Set BSSID */
2225                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2226                         sc->sc_curaid = 0;
2227                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2228                                                sc->sc_curaid);
2229
2230                         /* Set aggregation protection mode parameters */
2231                         sc->sc_config.ath_aggr_prot = 0;
2232
2233                         DPRINTF(sc, ATH_DBG_CONFIG,
2234                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2235                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2236
2237                         /* need to reconfigure the beacon */
2238                         sc->sc_flags &= ~SC_OP_BEACONS ;
2239
2240                         break;
2241                 default:
2242                         break;
2243                 }
2244         }
2245
2246         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2247             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2248              (vif->type == NL80211_IFTYPE_AP))) {
2249                 /*
2250                  * Allocate and setup the beacon frame.
2251                  *
2252                  * Stop any previous beacon DMA.  This may be
2253                  * necessary, for example, when an ibss merge
2254                  * causes reconfiguration; we may be called
2255                  * with beacon transmission active.
2256                  */
2257                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2258
2259                 error = ath_beacon_alloc(sc, 0);
2260                 if (error != 0)
2261                         return error;
2262
2263                 ath_beacon_sync(sc, 0);
2264         }
2265
2266         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2267         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2268                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2269                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2270                                 ath9k_hw_keysetmac(sc->sc_ah,
2271                                                    (u16)i,
2272                                                    sc->sc_curbssid);
2273         }
2274
2275         /* Only legacy IBSS for now */
2276         if (vif->type == NL80211_IFTYPE_ADHOC)
2277                 ath_update_chainmask(sc, 0);
2278
2279         return 0;
2280 }
2281
2282 #define SUPPORTED_FILTERS                       \
2283         (FIF_PROMISC_IN_BSS |                   \
2284         FIF_ALLMULTI |                          \
2285         FIF_CONTROL |                           \
2286         FIF_OTHER_BSS |                         \
2287         FIF_BCN_PRBRESP_PROMISC |               \
2288         FIF_FCSFAIL)
2289
2290 /* FIXME: sc->sc_full_reset ? */
2291 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2292                                    unsigned int changed_flags,
2293                                    unsigned int *total_flags,
2294                                    int mc_count,
2295                                    struct dev_mc_list *mclist)
2296 {
2297         struct ath_softc *sc = hw->priv;
2298         u32 rfilt;
2299
2300         changed_flags &= SUPPORTED_FILTERS;
2301         *total_flags &= SUPPORTED_FILTERS;
2302
2303         sc->rx_filter = *total_flags;
2304         rfilt = ath_calcrxfilter(sc);
2305         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2306
2307         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2308                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2309                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2310         }
2311
2312         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter);
2313 }
2314
2315 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2316                              struct ieee80211_vif *vif,
2317                              enum sta_notify_cmd cmd,
2318                              struct ieee80211_sta *sta)
2319 {
2320         struct ath_softc *sc = hw->priv;
2321
2322         switch (cmd) {
2323         case STA_NOTIFY_ADD:
2324                 ath_node_attach(sc, sta);
2325                 break;
2326         case STA_NOTIFY_REMOVE:
2327                 ath_node_detach(sc, sta);
2328                 break;
2329         default:
2330                 break;
2331         }
2332 }
2333
2334 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2335                          u16 queue,
2336                          const struct ieee80211_tx_queue_params *params)
2337 {
2338         struct ath_softc *sc = hw->priv;
2339         struct ath9k_tx_queue_info qi;
2340         int ret = 0, qnum;
2341
2342         if (queue >= WME_NUM_AC)
2343                 return 0;
2344
2345         qi.tqi_aifs = params->aifs;
2346         qi.tqi_cwmin = params->cw_min;
2347         qi.tqi_cwmax = params->cw_max;
2348         qi.tqi_burstTime = params->txop;
2349         qnum = ath_get_hal_qnum(queue, sc);
2350
2351         DPRINTF(sc, ATH_DBG_CONFIG,
2352                 "Configure tx [queue/halq] [%d/%d],  "
2353                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2354                 queue, qnum, params->aifs, params->cw_min,
2355                 params->cw_max, params->txop);
2356
2357         ret = ath_txq_update(sc, qnum, &qi);
2358         if (ret)
2359                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2360
2361         return ret;
2362 }
2363
2364 static int ath9k_set_key(struct ieee80211_hw *hw,
2365                          enum set_key_cmd cmd,
2366                          const u8 *local_addr,
2367                          const u8 *addr,
2368                          struct ieee80211_key_conf *key)
2369 {
2370         struct ath_softc *sc = hw->priv;
2371         int ret = 0;
2372
2373         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2374
2375         switch (cmd) {
2376         case SET_KEY:
2377                 ret = ath_key_config(sc, addr, key);
2378                 if (!ret) {
2379                         set_bit(key->keyidx, sc->sc_keymap);
2380                         key->hw_key_idx = key->keyidx;
2381                         /* push IV and Michael MIC generation to stack */
2382                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2383                         if (key->alg == ALG_TKIP)
2384                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2385                 }
2386                 break;
2387         case DISABLE_KEY:
2388                 ath_key_delete(sc, key);
2389                 clear_bit(key->keyidx, sc->sc_keymap);
2390                 break;
2391         default:
2392                 ret = -EINVAL;
2393         }
2394
2395         return ret;
2396 }
2397
2398 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2399                                    struct ieee80211_vif *vif,
2400                                    struct ieee80211_bss_conf *bss_conf,
2401                                    u32 changed)
2402 {
2403         struct ath_softc *sc = hw->priv;
2404
2405         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2406                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2407                         bss_conf->use_short_preamble);
2408                 if (bss_conf->use_short_preamble)
2409                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2410                 else
2411                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2412         }
2413
2414         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2415                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2416                         bss_conf->use_cts_prot);
2417                 if (bss_conf->use_cts_prot &&
2418                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2419                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2420                 else
2421                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2422         }
2423
2424         if (changed & BSS_CHANGED_HT)
2425                 ath9k_ht_conf(sc, bss_conf);
2426
2427         if (changed & BSS_CHANGED_ASSOC) {
2428                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2429                         bss_conf->assoc);
2430                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2431         }
2432 }
2433
2434 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2435 {
2436         u64 tsf;
2437         struct ath_softc *sc = hw->priv;
2438         struct ath_hal *ah = sc->sc_ah;
2439
2440         tsf = ath9k_hw_gettsf64(ah);
2441
2442         return tsf;
2443 }
2444
2445 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2446 {
2447         struct ath_softc *sc = hw->priv;
2448         struct ath_hal *ah = sc->sc_ah;
2449
2450         ath9k_hw_reset_tsf(ah);
2451 }
2452
2453 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2454                        enum ieee80211_ampdu_mlme_action action,
2455                        struct ieee80211_sta *sta,
2456                        u16 tid, u16 *ssn)
2457 {
2458         struct ath_softc *sc = hw->priv;
2459         int ret = 0;
2460
2461         switch (action) {
2462         case IEEE80211_AMPDU_RX_START:
2463                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2464                         ret = -ENOTSUPP;
2465                 break;
2466         case IEEE80211_AMPDU_RX_STOP:
2467                 break;
2468         case IEEE80211_AMPDU_TX_START:
2469                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2470                 if (ret < 0)
2471                         DPRINTF(sc, ATH_DBG_FATAL,
2472                                 "Unable to start TX aggregation\n");
2473                 else
2474                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2475                 break;
2476         case IEEE80211_AMPDU_TX_STOP:
2477                 ret = ath_tx_aggr_stop(sc, sta, tid);
2478                 if (ret < 0)
2479                         DPRINTF(sc, ATH_DBG_FATAL,
2480                                 "Unable to stop TX aggregation\n");
2481
2482                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2483                 break;
2484         case IEEE80211_AMPDU_TX_RESUME:
2485                 ath_tx_aggr_resume(sc, sta, tid);
2486                 break;
2487         default:
2488                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2489         }
2490
2491         return ret;
2492 }
2493
2494 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2495 {
2496         return -EOPNOTSUPP;
2497 }
2498
2499 static struct ieee80211_ops ath9k_ops = {
2500         .tx                 = ath9k_tx,
2501         .start              = ath9k_start,
2502         .stop               = ath9k_stop,
2503         .add_interface      = ath9k_add_interface,
2504         .remove_interface   = ath9k_remove_interface,
2505         .config             = ath9k_config,
2506         .config_interface   = ath9k_config_interface,
2507         .configure_filter   = ath9k_configure_filter,
2508         .sta_notify         = ath9k_sta_notify,
2509         .conf_tx            = ath9k_conf_tx,
2510         .bss_info_changed   = ath9k_bss_info_changed,
2511         .set_key            = ath9k_set_key,
2512         .get_tsf            = ath9k_get_tsf,
2513         .reset_tsf          = ath9k_reset_tsf,
2514         .ampdu_action       = ath9k_ampdu_action,
2515         .set_frag_threshold = ath9k_no_fragmentation,
2516 };
2517
2518 static struct {
2519         u32 version;
2520         const char * name;
2521 } ath_mac_bb_names[] = {
2522         { AR_SREV_VERSION_5416_PCI,     "5416" },
2523         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2524         { AR_SREV_VERSION_9100,         "9100" },
2525         { AR_SREV_VERSION_9160,         "9160" },
2526         { AR_SREV_VERSION_9280,         "9280" },
2527         { AR_SREV_VERSION_9285,         "9285" }
2528 };
2529
2530 static struct {
2531         u16 version;
2532         const char * name;
2533 } ath_rf_names[] = {
2534         { 0,                            "5133" },
2535         { AR_RAD5133_SREV_MAJOR,        "5133" },
2536         { AR_RAD5122_SREV_MAJOR,        "5122" },
2537         { AR_RAD2133_SREV_MAJOR,        "2133" },
2538         { AR_RAD2122_SREV_MAJOR,        "2122" }
2539 };
2540
2541 /*
2542  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2543  */
2544 static const char *
2545 ath_mac_bb_name(u32 mac_bb_version)
2546 {
2547         int i;
2548
2549         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2550                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2551                         return ath_mac_bb_names[i].name;
2552                 }
2553         }
2554
2555         return "????";
2556 }
2557
2558 /*
2559  * Return the RF name. "????" is returned if the RF is unknown.
2560  */
2561 static const char *
2562 ath_rf_name(u16 rf_version)
2563 {
2564         int i;
2565
2566         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2567                 if (ath_rf_names[i].version == rf_version) {
2568                         return ath_rf_names[i].name;
2569                 }
2570         }
2571
2572         return "????";
2573 }
2574
2575 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2576 {
2577         void __iomem *mem;
2578         struct ath_softc *sc;
2579         struct ieee80211_hw *hw;
2580         u8 csz;
2581         u32 val;
2582         int ret = 0;
2583         struct ath_hal *ah;
2584
2585         if (pci_enable_device(pdev))
2586                 return -EIO;
2587
2588         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2589
2590         if (ret) {
2591                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2592                 goto bad;
2593         }
2594
2595         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2596
2597         if (ret) {
2598                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2599                         "DMA enable failed\n");
2600                 goto bad;
2601         }
2602
2603         /*
2604          * Cache line size is used to size and align various
2605          * structures used to communicate with the hardware.
2606          */
2607         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2608         if (csz == 0) {
2609                 /*
2610                  * Linux 2.4.18 (at least) writes the cache line size
2611                  * register as a 16-bit wide register which is wrong.
2612                  * We must have this setup properly for rx buffer
2613                  * DMA to work so force a reasonable value here if it
2614                  * comes up zero.
2615                  */
2616                 csz = L1_CACHE_BYTES / sizeof(u32);
2617                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2618         }
2619         /*
2620          * The default setting of latency timer yields poor results,
2621          * set it to the value used by other systems. It may be worth
2622          * tweaking this setting more.
2623          */
2624         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2625
2626         pci_set_master(pdev);
2627
2628         /*
2629          * Disable the RETRY_TIMEOUT register (0x41) to keep
2630          * PCI Tx retries from interfering with C3 CPU state.
2631          */
2632         pci_read_config_dword(pdev, 0x40, &val);
2633         if ((val & 0x0000ff00) != 0)
2634                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2635
2636         ret = pci_request_region(pdev, 0, "ath9k");
2637         if (ret) {
2638                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2639                 ret = -ENODEV;
2640                 goto bad;
2641         }
2642
2643         mem = pci_iomap(pdev, 0, 0);
2644         if (!mem) {
2645                 printk(KERN_ERR "PCI memory map error\n") ;
2646                 ret = -EIO;
2647                 goto bad1;
2648         }
2649
2650         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2651         if (hw == NULL) {
2652                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2653                 goto bad2;
2654         }
2655
2656         SET_IEEE80211_DEV(hw, &pdev->dev);
2657         pci_set_drvdata(pdev, hw);
2658
2659         sc = hw->priv;
2660         sc->hw = hw;
2661         sc->pdev = pdev;
2662         sc->mem = mem;
2663
2664         if (ath_attach(id->device, sc) != 0) {
2665                 ret = -ENODEV;
2666                 goto bad3;
2667         }
2668
2669         /* setup interrupt service routine */
2670
2671         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2672                 printk(KERN_ERR "%s: request_irq failed\n",
2673                         wiphy_name(hw->wiphy));
2674                 ret = -EIO;
2675                 goto bad4;
2676         }
2677
2678         ah = sc->sc_ah;
2679         printk(KERN_INFO
2680                "%s: Atheros AR%s MAC/BB Rev:%x "
2681                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2682                wiphy_name(hw->wiphy),
2683                ath_mac_bb_name(ah->ah_macVersion),
2684                ah->ah_macRev,
2685                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2686                ah->ah_phyRev,
2687                (unsigned long)mem, pdev->irq);
2688
2689         return 0;
2690 bad4:
2691         ath_detach(sc);
2692 bad3:
2693         ieee80211_free_hw(hw);
2694 bad2:
2695         pci_iounmap(pdev, mem);
2696 bad1:
2697         pci_release_region(pdev, 0);
2698 bad:
2699         pci_disable_device(pdev);
2700         return ret;
2701 }
2702
2703 static void ath_pci_remove(struct pci_dev *pdev)
2704 {
2705         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2706         struct ath_softc *sc = hw->priv;
2707
2708         ath_detach(sc);
2709         if (pdev->irq)
2710                 free_irq(pdev->irq, sc);
2711         pci_iounmap(pdev, sc->mem);
2712         pci_release_region(pdev, 0);
2713         pci_disable_device(pdev);
2714         ieee80211_free_hw(hw);
2715 }
2716
2717 #ifdef CONFIG_PM
2718
2719 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2720 {
2721         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2722         struct ath_softc *sc = hw->priv;
2723
2724         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2725
2726 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2727         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2728                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2729 #endif
2730
2731         pci_save_state(pdev);
2732         pci_disable_device(pdev);
2733         pci_set_power_state(pdev, 3);
2734
2735         return 0;
2736 }
2737
2738 static int ath_pci_resume(struct pci_dev *pdev)
2739 {
2740         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2741         struct ath_softc *sc = hw->priv;
2742         u32 val;
2743         int err;
2744
2745         err = pci_enable_device(pdev);
2746         if (err)
2747                 return err;
2748         pci_restore_state(pdev);
2749         /*
2750          * Suspend/Resume resets the PCI configuration space, so we have to
2751          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2752          * PCI Tx retries from interfering with C3 CPU state
2753          */
2754         pci_read_config_dword(pdev, 0x40, &val);
2755         if ((val & 0x0000ff00) != 0)
2756                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2757
2758         /* Enable LED */
2759         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2760                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2761         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2762
2763 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2764         /*
2765          * check the h/w rfkill state on resume
2766          * and start the rfkill poll timer
2767          */
2768         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2769                 queue_delayed_work(sc->hw->workqueue,
2770                                    &sc->rf_kill.rfkill_poll, 0);
2771 #endif
2772
2773         return 0;
2774 }
2775
2776 #endif /* CONFIG_PM */
2777
2778 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2779
2780 static struct pci_driver ath_pci_driver = {
2781         .name       = "ath9k",
2782         .id_table   = ath_pci_id_table,
2783         .probe      = ath_pci_probe,
2784         .remove     = ath_pci_remove,
2785 #ifdef CONFIG_PM
2786         .suspend    = ath_pci_suspend,
2787         .resume     = ath_pci_resume,
2788 #endif /* CONFIG_PM */
2789 };
2790
2791 static int __init init_ath_pci(void)
2792 {
2793         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2794
2795         if (pci_register_driver(&ath_pci_driver) < 0) {
2796                 printk(KERN_ERR
2797                         "ath_pci: No devices found, driver not installed.\n");
2798                 pci_unregister_driver(&ath_pci_driver);
2799                 return -ENODEV;
2800         }
2801
2802         return 0;
2803 }
2804 module_init(init_ath_pci);
2805
2806 static void __exit exit_ath_pci(void)
2807 {
2808         pci_unregister_driver(&ath_pci_driver);
2809         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2810 }
2811 module_exit(exit_ath_pci);