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   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit. This method will start at the last known empty
  48  *  descriptor, and process every subsequent descriptor until there
  49  *  are none left with data (NAPI will stop after a set number of
  50  *  packets to give time to other tasks, but will eventually
  51  *  process all the packets).  The data arrives inside a
  52  *  pre-allocated skb, and so after the skb is passed up to the
  53  *  stack, a new skb must be allocated, and the address field in
  54  *  the buffer descriptor must be updated to indicate this new
  55  *  skb.
  56  *
  57  *  When the kernel requests that a packet be transmitted, the
  58  *  driver starts where it left off last time, and points the
  59  *  descriptor at the buffer which was passed in.  The driver
  60  *  then informs the DMA engine that there are packets ready to
  61  *  be transmitted.  Once the controller is finished transmitting
  62  *  the packet, an interrupt may be triggered (under the same
  63  *  conditions as for reception, but depending on the TXF bit).
  64  *  The driver then cleans up the buffer.
  65  */
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/platform_device.h>
  82 #include <linux/ip.h>
  83 #include <linux/tcp.h>
  84 #include <linux/udp.h>
  85 #include <linux/in.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95
  96 #include "gianfar.h"
  97 #include "gianfar_mii.h"
  98
  99 #define TX_TIMEOUT      (1*HZ)
 100 #undef BRIEF_GFAR_ERRORS
 101 #undef VERBOSE_GFAR_ERRORS
 102
 103 const char gfar_driver_name[] = "Gianfar Ethernet";
 104 const char gfar_driver_version[] = "1.3";
 105
 106 static int gfar_enet_open(struct net_device *dev);
 107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 108 static void gfar_reset_task(struct work_struct *work);
 109 static void gfar_timeout(struct net_device *dev);
 110 static int gfar_close(struct net_device *dev);
 111 struct sk_buff *gfar_new_skb(struct net_device *dev);
 112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 113                 struct sk_buff *skb);
 114 static int gfar_set_mac_address(struct net_device *dev);
 115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 116 static irqreturn_t gfar_error(int irq, void *dev_id);
 117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 119 static void adjust_link(struct net_device *dev);
 120 static void init_registers(struct net_device *dev);
 121 static int init_phy(struct net_device *dev);
 122 static int gfar_probe(struct platform_device *pdev);
 123 static int gfar_remove(struct platform_device *pdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 135 static void gfar_vlan_rx_register(struct net_device *netdev,
 136                                 struct vlan_group *grp);
 137 void gfar_halt(struct net_device *dev);
 138 static void gfar_halt_nodisable(struct net_device *dev);
 139 void gfar_start(struct net_device *dev);
 140 static void gfar_clear_exact_match(struct net_device *dev);
 141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 142
 143 extern const struct ethtool_ops gfar_ethtool_ops;
 144
 145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 147 MODULE_LICENSE("GPL");
 148
 149 /* Returns 1 if incoming frames use an FCB */
 150 static inline int gfar_uses_fcb(struct gfar_private *priv)
 151 {
 152         return (priv->vlan_enable || priv->rx_csum_enable);
 153 }
 154
 155 /* Set up the ethernet device structure, private data,
 156  * and anything else we need before we start */
 157 static int gfar_probe(struct platform_device *pdev)
 158 {
 159         u32 tempval;
 160         struct net_device *dev = NULL;
 161         struct gfar_private *priv = NULL;
 162         struct gianfar_platform_data *einfo;
 163         struct resource *r;
 164         int err = 0;
 165         DECLARE_MAC_BUF(mac);
 166
 167         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 168
 169         if (NULL == einfo) {
 170                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 171                        pdev->id);
 172
 173                 return -ENODEV;
 174         }
 175
 176         /* Create an ethernet device instance */
 177         dev = alloc_etherdev(sizeof (*priv));
 178
 179         if (NULL == dev)
 180                 return -ENOMEM;
 181
 182         priv = netdev_priv(dev);
 183         priv->dev = dev;
 184
 185         /* Set the info in the priv to the current info */
 186         priv->einfo = einfo;
 187
 188         /* fill out IRQ fields */
 189         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 190                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 191                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 192                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 193                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 194                         goto regs_fail;
 195         } else {
 196                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 197                 if (priv->interruptTransmit < 0)
 198                         goto regs_fail;
 199         }
 200
 201         /* get a pointer to the register memory */
 202         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 203         priv->regs = ioremap(r->start, sizeof (struct gfar));
 204
 205         if (NULL == priv->regs) {
 206                 err = -ENOMEM;
 207                 goto regs_fail;
 208         }
 209
 210         spin_lock_init(&priv->txlock);
 211         spin_lock_init(&priv->rxlock);
 212         spin_lock_init(&priv->bflock);
 213         INIT_WORK(&priv->reset_task, gfar_reset_task);
 214
 215         platform_set_drvdata(pdev, dev);
 216
 217         /* Stop the DMA engine now, in case it was running before */
 218         /* (The firmware could have used it, and left it running). */
 219         /* To do this, we write Graceful Receive Stop and Graceful */
 220         /* Transmit Stop, and then wait until the corresponding bits */
 221         /* in IEVENT indicate the stops have completed. */
 222         tempval = gfar_read(&priv->regs->dmactrl);
 223         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 224         gfar_write(&priv->regs->dmactrl, tempval);
 225
 226         tempval = gfar_read(&priv->regs->dmactrl);
 227         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 228         gfar_write(&priv->regs->dmactrl, tempval);
 229
 230         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 231                 cpu_relax();
 232
 233         /* Reset MAC layer */
 234         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 235
 236         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 237         gfar_write(&priv->regs->maccfg1, tempval);
 238
 239         /* Initialize MACCFG2. */
 240         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 241
 242         /* Initialize ECNTRL */
 243         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 244
 245         /* Copy the station address into the dev structure, */
 246         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 247
 248         /* Set the dev->base_addr to the gfar reg region */
 249         dev->base_addr = (unsigned long) (priv->regs);
 250
 251         SET_NETDEV_DEV(dev, &pdev->dev);
 252
 253         /* Fill in the dev structure */
 254         dev->open = gfar_enet_open;
 255         dev->hard_start_xmit = gfar_start_xmit;
 256         dev->tx_timeout = gfar_timeout;
 257         dev->watchdog_timeo = TX_TIMEOUT;
 258         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 259 #ifdef CONFIG_NET_POLL_CONTROLLER
 260         dev->poll_controller = gfar_netpoll;
 261 #endif
 262         dev->stop = gfar_close;
 263         dev->change_mtu = gfar_change_mtu;
 264         dev->mtu = 1500;
 265         dev->set_multicast_list = gfar_set_multi;
 266
 267         dev->ethtool_ops = &gfar_ethtool_ops;
 268
 269         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 270                 priv->rx_csum_enable = 1;
 271                 dev->features |= NETIF_F_IP_CSUM;
 272         } else
 273                 priv->rx_csum_enable = 0;
 274
 275         priv->vlgrp = NULL;
 276
 277         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 278                 dev->vlan_rx_register = gfar_vlan_rx_register;
 279
 280                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 281
 282                 priv->vlan_enable = 1;
 283         }
 284
 285         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 286                 priv->extended_hash = 1;
 287                 priv->hash_width = 9;
 288
 289                 priv->hash_regs[0] = &priv->regs->igaddr0;
 290                 priv->hash_regs[1] = &priv->regs->igaddr1;
 291                 priv->hash_regs[2] = &priv->regs->igaddr2;
 292                 priv->hash_regs[3] = &priv->regs->igaddr3;
 293                 priv->hash_regs[4] = &priv->regs->igaddr4;
 294                 priv->hash_regs[5] = &priv->regs->igaddr5;
 295                 priv->hash_regs[6] = &priv->regs->igaddr6;
 296                 priv->hash_regs[7] = &priv->regs->igaddr7;
 297                 priv->hash_regs[8] = &priv->regs->gaddr0;
 298                 priv->hash_regs[9] = &priv->regs->gaddr1;
 299                 priv->hash_regs[10] = &priv->regs->gaddr2;
 300                 priv->hash_regs[11] = &priv->regs->gaddr3;
 301                 priv->hash_regs[12] = &priv->regs->gaddr4;
 302                 priv->hash_regs[13] = &priv->regs->gaddr5;
 303                 priv->hash_regs[14] = &priv->regs->gaddr6;
 304                 priv->hash_regs[15] = &priv->regs->gaddr7;
 305
 306         } else {
 307                 priv->extended_hash = 0;
 308                 priv->hash_width = 8;
 309
 310                 priv->hash_regs[0] = &priv->regs->gaddr0;
 311                 priv->hash_regs[1] = &priv->regs->gaddr1;
 312                 priv->hash_regs[2] = &priv->regs->gaddr2;
 313                 priv->hash_regs[3] = &priv->regs->gaddr3;
 314                 priv->hash_regs[4] = &priv->regs->gaddr4;
 315                 priv->hash_regs[5] = &priv->regs->gaddr5;
 316                 priv->hash_regs[6] = &priv->regs->gaddr6;
 317                 priv->hash_regs[7] = &priv->regs->gaddr7;
 318         }
 319
 320         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 321                 priv->padding = DEFAULT_PADDING;
 322         else
 323                 priv->padding = 0;
 324
 325         if (dev->features & NETIF_F_IP_CSUM)
 326                 dev->hard_header_len += GMAC_FCB_LEN;
 327
 328         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 329         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 330         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 331
 332         priv->txcoalescing = DEFAULT_TX_COALESCE;
 333         priv->txcount = DEFAULT_TXCOUNT;
 334         priv->txtime = DEFAULT_TXTIME;
 335         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 336         priv->rxcount = DEFAULT_RXCOUNT;
 337         priv->rxtime = DEFAULT_RXTIME;
 338
 339         /* Enable most messages by default */
 340         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 341
 342         /* Carrier starts down, phylib will bring it up */
 343         netif_carrier_off(dev);
 344
 345         err = register_netdev(dev);
 346
 347         if (err) {
 348                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 349                                 dev->name);
 350                 goto register_fail;
 351         }
 352
 353         /* Create all the sysfs files */
 354         gfar_init_sysfs(dev);
 355
 356         /* Print out the device info */
 357         printk(KERN_INFO DEVICE_NAME "%s\n",
 358                dev->name, print_mac(mac, dev->dev_addr));
 359
 360         /* Even more device info helps when determining which kernel */
 361         /* provided which set of benchmarks. */
 362         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 363         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 364                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 365
 366         return 0;
 367
 368 register_fail:
 369         iounmap(priv->regs);
 370 regs_fail:
 371         free_netdev(dev);
 372         return err;
 373 }
 374
 375 static int gfar_remove(struct platform_device *pdev)
 376 {
 377         struct net_device *dev = platform_get_drvdata(pdev);
 378         struct gfar_private *priv = netdev_priv(dev);
 379
 380         platform_set_drvdata(pdev, NULL);
 381
 382         iounmap(priv->regs);
 383         free_netdev(dev);
 384
 385         return 0;
 386 }
 387
 388 #ifdef CONFIG_PM
 389 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
 390 {
 391         struct net_device *dev = platform_get_drvdata(pdev);
 392         struct gfar_private *priv = netdev_priv(dev);
 393         unsigned long flags;
 394         u32 tempval;
 395
 396         int magic_packet = priv->wol_en &&
 397                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 398
 399         netif_device_detach(dev);
 400
 401         if (netif_running(dev)) {
 402                 spin_lock_irqsave(&priv->txlock, flags);
 403                 spin_lock(&priv->rxlock);
 404
 405                 gfar_halt_nodisable(dev);
 406
 407                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 408                 tempval = gfar_read(&priv->regs->maccfg1);
 409
 410                 tempval &= ~MACCFG1_TX_EN;
 411
 412                 if (!magic_packet)
 413                         tempval &= ~MACCFG1_RX_EN;
 414
 415                 gfar_write(&priv->regs->maccfg1, tempval);
 416
 417                 spin_unlock(&priv->rxlock);
 418                 spin_unlock_irqrestore(&priv->txlock, flags);
 419
 420                 napi_disable(&priv->napi);
 421
 422                 if (magic_packet) {
 423                         /* Enable interrupt on Magic Packet */
 424                         gfar_write(&priv->regs->imask, IMASK_MAG);
 425
 426                         /* Enable Magic Packet mode */
 427                         tempval = gfar_read(&priv->regs->maccfg2);
 428                         tempval |= MACCFG2_MPEN;
 429                         gfar_write(&priv->regs->maccfg2, tempval);
 430                 } else {
 431                         phy_stop(priv->phydev);
 432                 }
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int gfar_resume(struct platform_device *pdev)
 439 {
 440         struct net_device *dev = platform_get_drvdata(pdev);
 441         struct gfar_private *priv = netdev_priv(dev);
 442         unsigned long flags;
 443         u32 tempval;
 444         int magic_packet = priv->wol_en &&
 445                 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 446
 447         if (!netif_running(dev)) {
 448                 netif_device_attach(dev);
 449                 return 0;
 450         }
 451
 452         if (!magic_packet && priv->phydev)
 453                 phy_start(priv->phydev);
 454
 455         /* Disable Magic Packet mode, in case something
 456          * else woke us up.
 457          */
 458
 459         spin_lock_irqsave(&priv->txlock, flags);
 460         spin_lock(&priv->rxlock);
 461
 462         tempval = gfar_read(&priv->regs->maccfg2);
 463         tempval &= ~MACCFG2_MPEN;
 464         gfar_write(&priv->regs->maccfg2, tempval);
 465
 466         gfar_start(dev);
 467
 468         spin_unlock(&priv->rxlock);
 469         spin_unlock_irqrestore(&priv->txlock, flags);
 470
 471         netif_device_attach(dev);
 472
 473         napi_enable(&priv->napi);
 474
 475         return 0;
 476 }
 477 #else
 478 #define gfar_suspend NULL
 479 #define gfar_resume NULL
 480 #endif
 481
 482 /* Reads the controller's registers to determine what interface
 483  * connects it to the PHY.
 484  */
 485 static phy_interface_t gfar_get_interface(struct net_device *dev)
 486 {
 487         struct gfar_private *priv = netdev_priv(dev);
 488         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 489
 490         if (ecntrl & ECNTRL_SGMII_MODE)
 491                 return PHY_INTERFACE_MODE_SGMII;
 492
 493         if (ecntrl & ECNTRL_TBI_MODE) {
 494                 if (ecntrl & ECNTRL_REDUCED_MODE)
 495                         return PHY_INTERFACE_MODE_RTBI;
 496                 else
 497                         return PHY_INTERFACE_MODE_TBI;
 498         }
 499
 500         if (ecntrl & ECNTRL_REDUCED_MODE) {
 501                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 502                         return PHY_INTERFACE_MODE_RMII;
 503                 else {
 504                         phy_interface_t interface = priv->einfo->interface;
 505
 506                         /*
 507                          * This isn't autodetected right now, so it must
 508                          * be set by the device tree or platform code.
 509                          */
 510                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 511                                 return PHY_INTERFACE_MODE_RGMII_ID;
 512
 513                         return PHY_INTERFACE_MODE_RGMII;
 514                 }
 515         }
 516
 517         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 518                 return PHY_INTERFACE_MODE_GMII;
 519
 520         return PHY_INTERFACE_MODE_MII;
 521 }
 522
 523
 524 /* Initializes driver's PHY state, and attaches to the PHY.
 525  * Returns 0 on success.
 526  */
 527 static int init_phy(struct net_device *dev)
 528 {
 529         struct gfar_private *priv = netdev_priv(dev);
 530         uint gigabit_support =
 531                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 532                 SUPPORTED_1000baseT_Full : 0;
 533         struct phy_device *phydev;
 534         char phy_id[BUS_ID_SIZE];
 535         phy_interface_t interface;
 536
 537         priv->oldlink = 0;
 538         priv->oldspeed = 0;
 539         priv->oldduplex = -1;
 540
 541         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 542
 543         interface = gfar_get_interface(dev);
 544
 545         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 546
 547         if (interface == PHY_INTERFACE_MODE_SGMII)
 548                 gfar_configure_serdes(dev);
 549
 550         if (IS_ERR(phydev)) {
 551                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 552                 return PTR_ERR(phydev);
 553         }
 554
 555         /* Remove any features not supported by the controller */
 556         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 557         phydev->advertising = phydev->supported;
 558
 559         priv->phydev = phydev;
 560
 561         return 0;
 562 }
 563
 564 /*
 565  * Initialize TBI PHY interface for communicating with the
 566  * SERDES lynx PHY on the chip.  We communicate with this PHY
 567  * through the MDIO bus on each controller, treating it as a
 568  * "normal" PHY at the address found in the TBIPA register.  We assume
 569  * that the TBIPA register is valid.  Either the MDIO bus code will set
 570  * it to a value that doesn't conflict with other PHYs on the bus, or the
 571  * value doesn't matter, as there are no other PHYs on the bus.
 572  */
 573 static void gfar_configure_serdes(struct net_device *dev)
 574 {
 575         struct gfar_private *priv = netdev_priv(dev);
 576         struct gfar_mii __iomem *regs =
 577                         (void __iomem *)&priv->regs->gfar_mii_regs;
 578         int tbipa = gfar_read(&priv->regs->tbipa);
 579
 580         /* Single clk mode, mii mode off(for serdes communication) */
 581         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
 582
 583         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
 584                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 585                         ADVERTISE_1000XPSE_ASYM);
 586
 587         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
 588                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 589 }
 590
 591 static void init_registers(struct net_device *dev)
 592 {
 593         struct gfar_private *priv = netdev_priv(dev);
 594
 595         /* Clear IEVENT */
 596         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 597
 598         /* Initialize IMASK */
 599         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 600
 601         /* Init hash registers to zero */
 602         gfar_write(&priv->regs->igaddr0, 0);
 603         gfar_write(&priv->regs->igaddr1, 0);
 604         gfar_write(&priv->regs->igaddr2, 0);
 605         gfar_write(&priv->regs->igaddr3, 0);
 606         gfar_write(&priv->regs->igaddr4, 0);
 607         gfar_write(&priv->regs->igaddr5, 0);
 608         gfar_write(&priv->regs->igaddr6, 0);
 609         gfar_write(&priv->regs->igaddr7, 0);
 610
 611         gfar_write(&priv->regs->gaddr0, 0);
 612         gfar_write(&priv->regs->gaddr1, 0);
 613         gfar_write(&priv->regs->gaddr2, 0);
 614         gfar_write(&priv->regs->gaddr3, 0);
 615         gfar_write(&priv->regs->gaddr4, 0);
 616         gfar_write(&priv->regs->gaddr5, 0);
 617         gfar_write(&priv->regs->gaddr6, 0);
 618         gfar_write(&priv->regs->gaddr7, 0);
 619
 620         /* Zero out the rmon mib registers if it has them */
 621         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 622                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 623
 624                 /* Mask off the CAM interrupts */
 625                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 626                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 627         }
 628
 629         /* Initialize the max receive buffer length */
 630         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 631
 632         /* Initialize the Minimum Frame Length Register */
 633         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 634 }
 635
 636
 637 /* Halt the receive and transmit queues */
 638 static void gfar_halt_nodisable(struct net_device *dev)
 639 {
 640         struct gfar_private *priv = netdev_priv(dev);
 641         struct gfar __iomem *regs = priv->regs;
 642         u32 tempval;
 643
 644         /* Mask all interrupts */
 645         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 646
 647         /* Clear all interrupts */
 648         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 649
 650         /* Stop the DMA, and wait for it to stop */
 651         tempval = gfar_read(&priv->regs->dmactrl);
 652         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 653             != (DMACTRL_GRS | DMACTRL_GTS)) {
 654                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 655                 gfar_write(&priv->regs->dmactrl, tempval);
 656
 657                 while (!(gfar_read(&priv->regs->ievent) &
 658                          (IEVENT_GRSC | IEVENT_GTSC)))
 659                         cpu_relax();
 660         }
 661 }
 662
 663 /* Halt the receive and transmit queues */
 664 void gfar_halt(struct net_device *dev)
 665 {
 666         struct gfar_private *priv = netdev_priv(dev);
 667         struct gfar __iomem *regs = priv->regs;
 668         u32 tempval;
 669
 670         gfar_halt_nodisable(dev);
 671
 672         /* Disable Rx and Tx */
 673         tempval = gfar_read(&regs->maccfg1);
 674         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 675         gfar_write(&regs->maccfg1, tempval);
 676 }
 677
 678 void stop_gfar(struct net_device *dev)
 679 {
 680         struct gfar_private *priv = netdev_priv(dev);
 681         struct gfar __iomem *regs = priv->regs;
 682         unsigned long flags;
 683
 684         phy_stop(priv->phydev);
 685
 686         /* Lock it down */
 687         spin_lock_irqsave(&priv->txlock, flags);
 688         spin_lock(&priv->rxlock);
 689
 690         gfar_halt(dev);
 691
 692         spin_unlock(&priv->rxlock);
 693         spin_unlock_irqrestore(&priv->txlock, flags);
 694
 695         /* Free the IRQs */
 696         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 697                 free_irq(priv->interruptError, dev);
 698                 free_irq(priv->interruptTransmit, dev);
 699                 free_irq(priv->interruptReceive, dev);
 700         } else {
 701                 free_irq(priv->interruptTransmit, dev);
 702         }
 703
 704         free_skb_resources(priv);
 705
 706         dma_free_coherent(&dev->dev,
 707                         sizeof(struct txbd8)*priv->tx_ring_size
 708                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 709                         priv->tx_bd_base,
 710                         gfar_read(&regs->tbase0));
 711 }
 712
 713 /* If there are any tx skbs or rx skbs still around, free them.
 714  * Then free tx_skbuff and rx_skbuff */
 715 static void free_skb_resources(struct gfar_private *priv)
 716 {
 717         struct rxbd8 *rxbdp;
 718         struct txbd8 *txbdp;
 719         int i;
 720
 721         /* Go through all the buffer descriptors and free their data buffers */
 722         txbdp = priv->tx_bd_base;
 723
 724         for (i = 0; i < priv->tx_ring_size; i++) {
 725
 726                 if (priv->tx_skbuff[i]) {
 727                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 728                                         txbdp->length,
 729                                         DMA_TO_DEVICE);
 730                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 731                         priv->tx_skbuff[i] = NULL;
 732                 }
 733
 734                 txbdp++;
 735         }
 736
 737         kfree(priv->tx_skbuff);
 738
 739         rxbdp = priv->rx_bd_base;
 740
 741         /* rx_skbuff is not guaranteed to be allocated, so only
 742          * free it and its contents if it is allocated */
 743         if(priv->rx_skbuff != NULL) {
 744                 for (i = 0; i < priv->rx_ring_size; i++) {
 745                         if (priv->rx_skbuff[i]) {
 746                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 747                                                 priv->rx_buffer_size,
 748                                                 DMA_FROM_DEVICE);
 749
 750                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 751                                 priv->rx_skbuff[i] = NULL;
 752                         }
 753
 754                         rxbdp->status = 0;
 755                         rxbdp->length = 0;
 756                         rxbdp->bufPtr = 0;
 757
 758                         rxbdp++;
 759                 }
 760
 761                 kfree(priv->rx_skbuff);
 762         }
 763 }
 764
 765 void gfar_start(struct net_device *dev)
 766 {
 767         struct gfar_private *priv = netdev_priv(dev);
 768         struct gfar __iomem *regs = priv->regs;
 769         u32 tempval;
 770
 771         /* Enable Rx and Tx in MACCFG1 */
 772         tempval = gfar_read(&regs->maccfg1);
 773         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 774         gfar_write(&regs->maccfg1, tempval);
 775
 776         /* Initialize DMACTRL to have WWR and WOP */
 777         tempval = gfar_read(&priv->regs->dmactrl);
 778         tempval |= DMACTRL_INIT_SETTINGS;
 779         gfar_write(&priv->regs->dmactrl, tempval);
 780
 781         /* Make sure we aren't stopped */
 782         tempval = gfar_read(&priv->regs->dmactrl);
 783         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 784         gfar_write(&priv->regs->dmactrl, tempval);
 785
 786         /* Clear THLT/RHLT, so that the DMA starts polling now */
 787         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 788         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 789
 790         /* Unmask the interrupts we look for */
 791         gfar_write(&regs->imask, IMASK_DEFAULT);
 792 }
 793
 794 /* Bring the controller up and running */
 795 int startup_gfar(struct net_device *dev)
 796 {
 797         struct txbd8 *txbdp;
 798         struct rxbd8 *rxbdp;
 799         dma_addr_t addr = 0;
 800         unsigned long vaddr;
 801         int i;
 802         struct gfar_private *priv = netdev_priv(dev);
 803         struct gfar __iomem *regs = priv->regs;
 804         int err = 0;
 805         u32 rctrl = 0;
 806         u32 attrs = 0;
 807
 808         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 809
 810         /* Allocate memory for the buffer descriptors */
 811         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 812                         sizeof (struct txbd8) * priv->tx_ring_size +
 813                         sizeof (struct rxbd8) * priv->rx_ring_size,
 814                         &addr, GFP_KERNEL);
 815
 816         if (vaddr == 0) {
 817                 if (netif_msg_ifup(priv))
 818                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 819                                         dev->name);
 820                 return -ENOMEM;
 821         }
 822
 823         priv->tx_bd_base = (struct txbd8 *) vaddr;
 824
 825         /* enet DMA only understands physical addresses */
 826         gfar_write(&regs->tbase0, addr);
 827
 828         /* Start the rx descriptor ring where the tx ring leaves off */
 829         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 830         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 831         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 832         gfar_write(&regs->rbase0, addr);
 833
 834         /* Setup the skbuff rings */
 835         priv->tx_skbuff =
 836             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 837                                         priv->tx_ring_size, GFP_KERNEL);
 838
 839         if (NULL == priv->tx_skbuff) {
 840                 if (netif_msg_ifup(priv))
 841                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 842                                         dev->name);
 843                 err = -ENOMEM;
 844                 goto tx_skb_fail;
 845         }
 846
 847         for (i = 0; i < priv->tx_ring_size; i++)
 848                 priv->tx_skbuff[i] = NULL;
 849
 850         priv->rx_skbuff =
 851             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 852                                         priv->rx_ring_size, GFP_KERNEL);
 853
 854         if (NULL == priv->rx_skbuff) {
 855                 if (netif_msg_ifup(priv))
 856                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 857                                         dev->name);
 858                 err = -ENOMEM;
 859                 goto rx_skb_fail;
 860         }
 861
 862         for (i = 0; i < priv->rx_ring_size; i++)
 863                 priv->rx_skbuff[i] = NULL;
 864
 865         /* Initialize some variables in our dev structure */
 866         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 867         priv->cur_rx = priv->rx_bd_base;
 868         priv->skb_curtx = priv->skb_dirtytx = 0;
 869         priv->skb_currx = 0;
 870
 871         /* Initialize Transmit Descriptor Ring */
 872         txbdp = priv->tx_bd_base;
 873         for (i = 0; i < priv->tx_ring_size; i++) {
 874                 txbdp->status = 0;
 875                 txbdp->length = 0;
 876                 txbdp->bufPtr = 0;
 877                 txbdp++;
 878         }
 879
 880         /* Set the last descriptor in the ring to indicate wrap */
 881         txbdp--;
 882         txbdp->status |= TXBD_WRAP;
 883
 884         rxbdp = priv->rx_bd_base;
 885         for (i = 0; i < priv->rx_ring_size; i++) {
 886                 struct sk_buff *skb;
 887
 888                 skb = gfar_new_skb(dev);
 889
 890                 if (!skb) {
 891                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
 892                                         dev->name);
 893
 894                         goto err_rxalloc_fail;
 895                 }
 896
 897                 priv->rx_skbuff[i] = skb;
 898
 899                 gfar_new_rxbdp(dev, rxbdp, skb);
 900
 901                 rxbdp++;
 902         }
 903
 904         /* Set the last descriptor in the ring to wrap */
 905         rxbdp--;
 906         rxbdp->status |= RXBD_WRAP;
 907
 908         /* If the device has multiple interrupts, register for
 909          * them.  Otherwise, only register for the one */
 910         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 911                 /* Install our interrupt handlers for Error,
 912                  * Transmit, and Receive */
 913                 if (request_irq(priv->interruptError, gfar_error,
 914                                 0, "enet_error", dev) < 0) {
 915                         if (netif_msg_intr(priv))
 916                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 917                                         dev->name, priv->interruptError);
 918
 919                         err = -1;
 920                         goto err_irq_fail;
 921                 }
 922
 923                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 924                                 0, "enet_tx", dev) < 0) {
 925                         if (netif_msg_intr(priv))
 926                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 927                                         dev->name, priv->interruptTransmit);
 928
 929                         err = -1;
 930
 931                         goto tx_irq_fail;
 932                 }
 933
 934                 if (request_irq(priv->interruptReceive, gfar_receive,
 935                                 0, "enet_rx", dev) < 0) {
 936                         if (netif_msg_intr(priv))
 937                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 938                                                 dev->name, priv->interruptReceive);
 939
 940                         err = -1;
 941                         goto rx_irq_fail;
 942                 }
 943         } else {
 944                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 945                                 0, "gfar_interrupt", dev) < 0) {
 946                         if (netif_msg_intr(priv))
 947                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 948                                         dev->name, priv->interruptError);
 949
 950                         err = -1;
 951                         goto err_irq_fail;
 952                 }
 953         }
 954
 955         phy_start(priv->phydev);
 956
 957         /* Configure the coalescing support */
 958         if (priv->txcoalescing)
 959                 gfar_write(&regs->txic,
 960                            mk_ic_value(priv->txcount, priv->txtime));
 961         else
 962                 gfar_write(&regs->txic, 0);
 963
 964         if (priv->rxcoalescing)
 965                 gfar_write(&regs->rxic,
 966                            mk_ic_value(priv->rxcount, priv->rxtime));
 967         else
 968                 gfar_write(&regs->rxic, 0);
 969
 970         if (priv->rx_csum_enable)
 971                 rctrl |= RCTRL_CHECKSUMMING;
 972
 973         if (priv->extended_hash) {
 974                 rctrl |= RCTRL_EXTHASH;
 975
 976                 gfar_clear_exact_match(dev);
 977                 rctrl |= RCTRL_EMEN;
 978         }
 979
 980         if (priv->vlan_enable)
 981                 rctrl |= RCTRL_VLAN;
 982
 983         if (priv->padding) {
 984                 rctrl &= ~RCTRL_PAL_MASK;
 985                 rctrl |= RCTRL_PADDING(priv->padding);
 986         }
 987
 988         /* Init rctrl based on our settings */
 989         gfar_write(&priv->regs->rctrl, rctrl);
 990
 991         if (dev->features & NETIF_F_IP_CSUM)
 992                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
 993
 994         /* Set the extraction length and index */
 995         attrs = ATTRELI_EL(priv->rx_stash_size) |
 996                 ATTRELI_EI(priv->rx_stash_index);
 997
 998         gfar_write(&priv->regs->attreli, attrs);
 999
1000         /* Start with defaults, and add stashing or locking
1001          * depending on the approprate variables */
1002         attrs = ATTR_INIT_SETTINGS;
1003
1004         if (priv->bd_stash_en)
1005                 attrs |= ATTR_BDSTASH;
1006
1007         if (priv->rx_stash_size != 0)
1008                 attrs |= ATTR_BUFSTASH;
1009
1010         gfar_write(&priv->regs->attr, attrs);
1011
1012         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1013         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1014         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1015
1016         /* Start the controller */
1017         gfar_start(dev);
1018
1019         return 0;
1020
1021 rx_irq_fail:
1022         free_irq(priv->interruptTransmit, dev);
1023 tx_irq_fail:
1024         free_irq(priv->interruptError, dev);
1025 err_irq_fail:
1026 err_rxalloc_fail:
1027 rx_skb_fail:
1028         free_skb_resources(priv);
1029 tx_skb_fail:
1030         dma_free_coherent(&dev->dev,
1031                         sizeof(struct txbd8)*priv->tx_ring_size
1032                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1033                         priv->tx_bd_base,
1034                         gfar_read(&regs->tbase0));
1035
1036         return err;
1037 }
1038
1039 /* Called when something needs to use the ethernet device */
1040 /* Returns 0 for success. */
1041 static int gfar_enet_open(struct net_device *dev)
1042 {
1043         struct gfar_private *priv = netdev_priv(dev);
1044         int err;
1045
1046         napi_enable(&priv->napi);
1047
1048         /* Initialize a bunch of registers */
1049         init_registers(dev);
1050
1051         gfar_set_mac_address(dev);
1052
1053         err = init_phy(dev);
1054
1055         if(err) {
1056                 napi_disable(&priv->napi);
1057                 return err;
1058         }
1059
1060         err = startup_gfar(dev);
1061         if (err) {
1062                 napi_disable(&priv->napi);
1063                 return err;
1064         }
1065
1066         netif_start_queue(dev);
1067
1068         return err;
1069 }
1070
1071 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1072 {
1073         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1074
1075         memset(fcb, 0, GMAC_FCB_LEN);
1076
1077         return fcb;
1078 }
1079
1080 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1081 {
1082         u8 flags = 0;
1083
1084         /* If we're here, it's a IP packet with a TCP or UDP
1085          * payload.  We set it to checksum, using a pseudo-header
1086          * we provide
1087          */
1088         flags = TXFCB_DEFAULT;
1089
1090         /* Tell the controller what the protocol is */
1091         /* And provide the already calculated phcs */
1092         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1093                 flags |= TXFCB_UDP;
1094                 fcb->phcs = udp_hdr(skb)->check;
1095         } else
1096                 fcb->phcs = tcp_hdr(skb)->check;
1097
1098         /* l3os is the distance between the start of the
1099          * frame (skb->data) and the start of the IP hdr.
1100          * l4os is the distance between the start of the
1101          * l3 hdr and the l4 hdr */
1102         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1103         fcb->l4os = skb_network_header_len(skb);
1104
1105         fcb->flags = flags;
1106 }
1107
1108 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1109 {
1110         fcb->flags |= TXFCB_VLN;
1111         fcb->vlctl = vlan_tx_tag_get(skb);
1112 }
1113
1114 /* This is called by the kernel when a frame is ready for transmission. */
1115 /* It is pointed to by the dev->hard_start_xmit function pointer */
1116 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1117 {
1118         struct gfar_private *priv = netdev_priv(dev);
1119         struct txfcb *fcb = NULL;
1120         struct txbd8 *txbdp;
1121         u16 status;
1122         unsigned long flags;
1123
1124         /* Update transmit stats */
1125         dev->stats.tx_bytes += skb->len;
1126
1127         /* Lock priv now */
1128         spin_lock_irqsave(&priv->txlock, flags);
1129
1130         /* Point at the first free tx descriptor */
1131         txbdp = priv->cur_tx;
1132
1133         /* Clear all but the WRAP status flags */
1134         status = txbdp->status & TXBD_WRAP;
1135
1136         /* Set up checksumming */
1137         if (likely((dev->features & NETIF_F_IP_CSUM)
1138                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1139                 fcb = gfar_add_fcb(skb, txbdp);
1140                 status |= TXBD_TOE;
1141                 gfar_tx_checksum(skb, fcb);
1142         }
1143
1144         if (priv->vlan_enable &&
1145                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1146                 if (unlikely(NULL == fcb)) {
1147                         fcb = gfar_add_fcb(skb, txbdp);
1148                         status |= TXBD_TOE;
1149                 }
1150
1151                 gfar_tx_vlan(skb, fcb);
1152         }
1153
1154         /* Set buffer length and pointer */
1155         txbdp->length = skb->len;
1156         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1157                         skb->len, DMA_TO_DEVICE);
1158
1159         /* Save the skb pointer so we can free it later */
1160         priv->tx_skbuff[priv->skb_curtx] = skb;
1161
1162         /* Update the current skb pointer (wrapping if this was the last) */
1163         priv->skb_curtx =
1164             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1165
1166         /* Flag the BD as interrupt-causing */
1167         status |= TXBD_INTERRUPT;
1168
1169         /* Flag the BD as ready to go, last in frame, and  */
1170         /* in need of CRC */
1171         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1172
1173         dev->trans_start = jiffies;
1174
1175         /* The powerpc-specific eieio() is used, as wmb() has too strong
1176          * semantics (it requires synchronization between cacheable and
1177          * uncacheable mappings, which eieio doesn't provide and which we
1178          * don't need), thus requiring a more expensive sync instruction.  At
1179          * some point, the set of architecture-independent barrier functions
1180          * should be expanded to include weaker barriers.
1181          */
1182
1183         eieio();
1184         txbdp->status = status;
1185
1186         /* If this was the last BD in the ring, the next one */
1187         /* is at the beginning of the ring */
1188         if (txbdp->status & TXBD_WRAP)
1189                 txbdp = priv->tx_bd_base;
1190         else
1191                 txbdp++;
1192
1193         /* If the next BD still needs to be cleaned up, then the bds
1194            are full.  We need to tell the kernel to stop sending us stuff. */
1195         if (txbdp == priv->dirty_tx) {
1196                 netif_stop_queue(dev);
1197
1198                 dev->stats.tx_fifo_errors++;
1199         }
1200
1201         /* Update the current txbd to the next one */
1202         priv->cur_tx = txbdp;
1203
1204         /* Tell the DMA to go go go */
1205         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1206
1207         /* Unlock priv */
1208         spin_unlock_irqrestore(&priv->txlock, flags);
1209
1210         return 0;
1211 }
1212
1213 /* Stops the kernel queue, and halts the controller */
1214 static int gfar_close(struct net_device *dev)
1215 {
1216         struct gfar_private *priv = netdev_priv(dev);
1217
1218         napi_disable(&priv->napi);
1219
1220         cancel_work_sync(&priv->reset_task);
1221         stop_gfar(dev);
1222
1223         /* Disconnect from the PHY */
1224         phy_disconnect(priv->phydev);
1225         priv->phydev = NULL;
1226
1227         netif_stop_queue(dev);
1228
1229         return 0;
1230 }
1231
1232 /* Changes the mac address if the controller is not running. */
1233 static int gfar_set_mac_address(struct net_device *dev)
1234 {
1235         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1236
1237         return 0;
1238 }
1239
1240
1241 /* Enables and disables VLAN insertion/extraction */
1242 static void gfar_vlan_rx_register(struct net_device *dev,
1243                 struct vlan_group *grp)
1244 {
1245         struct gfar_private *priv = netdev_priv(dev);
1246         unsigned long flags;
1247         u32 tempval;
1248
1249         spin_lock_irqsave(&priv->rxlock, flags);
1250
1251         priv->vlgrp = grp;
1252
1253         if (grp) {
1254                 /* Enable VLAN tag insertion */
1255                 tempval = gfar_read(&priv->regs->tctrl);
1256                 tempval |= TCTRL_VLINS;
1257
1258                 gfar_write(&priv->regs->tctrl, tempval);
1259
1260                 /* Enable VLAN tag extraction */
1261                 tempval = gfar_read(&priv->regs->rctrl);
1262                 tempval |= RCTRL_VLEX;
1263                 gfar_write(&priv->regs->rctrl, tempval);
1264         } else {
1265                 /* Disable VLAN tag insertion */
1266                 tempval = gfar_read(&priv->regs->tctrl);
1267                 tempval &= ~TCTRL_VLINS;
1268                 gfar_write(&priv->regs->tctrl, tempval);
1269
1270                 /* Disable VLAN tag extraction */
1271                 tempval = gfar_read(&priv->regs->rctrl);
1272                 tempval &= ~RCTRL_VLEX;
1273                 gfar_write(&priv->regs->rctrl, tempval);
1274         }
1275
1276         spin_unlock_irqrestore(&priv->rxlock, flags);
1277 }
1278
1279 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1280 {
1281         int tempsize, tempval;
1282         struct gfar_private *priv = netdev_priv(dev);
1283         int oldsize = priv->rx_buffer_size;
1284         int frame_size = new_mtu + ETH_HLEN;
1285
1286         if (priv->vlan_enable)
1287                 frame_size += VLAN_HLEN;
1288
1289         if (gfar_uses_fcb(priv))
1290                 frame_size += GMAC_FCB_LEN;
1291
1292         frame_size += priv->padding;
1293
1294         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1295                 if (netif_msg_drv(priv))
1296                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1297                                         dev->name);
1298                 return -EINVAL;
1299         }
1300
1301         tempsize =
1302             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1303             INCREMENTAL_BUFFER_SIZE;
1304
1305         /* Only stop and start the controller if it isn't already
1306          * stopped, and we changed something */
1307         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1308                 stop_gfar(dev);
1309
1310         priv->rx_buffer_size = tempsize;
1311
1312         dev->mtu = new_mtu;
1313
1314         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1315         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1316
1317         /* If the mtu is larger than the max size for standard
1318          * ethernet frames (ie, a jumbo frame), then set maccfg2
1319          * to allow huge frames, and to check the length */
1320         tempval = gfar_read(&priv->regs->maccfg2);
1321
1322         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1323                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1324         else
1325                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1326
1327         gfar_write(&priv->regs->maccfg2, tempval);
1328
1329         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1330                 startup_gfar(dev);
1331
1332         return 0;
1333 }
1334
1335 /* gfar_reset_task gets scheduled when a packet has not been
1336  * transmitted after a set amount of time.
1337  * For now, assume that clearing out all the structures, and
1338  * starting over will fix the problem.
1339  */
1340 static void gfar_reset_task(struct work_struct *work)
1341 {
1342         struct gfar_private *priv = container_of(work, struct gfar_private,
1343                         reset_task);
1344         struct net_device *dev = priv->dev;
1345
1346         if (dev->flags & IFF_UP) {
1347                 stop_gfar(dev);
1348                 startup_gfar(dev);
1349         }
1350
1351         netif_tx_schedule_all(dev);
1352 }
1353
1354 static void gfar_timeout(struct net_device *dev)
1355 {
1356         struct gfar_private *priv = netdev_priv(dev);
1357
1358         dev->stats.tx_errors++;
1359         schedule_work(&priv->reset_task);
1360 }
1361
1362 /* Interrupt Handler for Transmit complete */
1363 static int gfar_clean_tx_ring(struct net_device *dev)
1364 {
1365         struct txbd8 *bdp;
1366         struct gfar_private *priv = netdev_priv(dev);
1367         int howmany = 0;
1368
1369         bdp = priv->dirty_tx;
1370         while ((bdp->status & TXBD_READY) == 0) {
1371                 /* If dirty_tx and cur_tx are the same, then either the */
1372                 /* ring is empty or full now (it could only be full in the beginning, */
1373                 /* obviously).  If it is empty, we are done. */
1374                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1375                         break;
1376
1377                 howmany++;
1378
1379                 /* Deferred means some collisions occurred during transmit, */
1380                 /* but we eventually sent the packet. */
1381                 if (bdp->status & TXBD_DEF)
1382                         dev->stats.collisions++;
1383
1384                 /* Free the sk buffer associated with this TxBD */
1385                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1386
1387                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1388                 priv->skb_dirtytx =
1389                     (priv->skb_dirtytx +
1390                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1391
1392                 /* Clean BD length for empty detection */
1393                 bdp->length = 0;
1394
1395                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1396                 if (bdp->status & TXBD_WRAP)
1397                         bdp = priv->tx_bd_base;
1398                 else
1399                         bdp++;
1400
1401                 /* Move dirty_tx to be the next bd */
1402                 priv->dirty_tx = bdp;
1403
1404                 /* We freed a buffer, so now we can restart transmission */
1405                 if (netif_queue_stopped(dev))
1406                         netif_wake_queue(dev);
1407         } /* while ((bdp->status & TXBD_READY) == 0) */
1408
1409         dev->stats.tx_packets += howmany;
1410
1411         return howmany;
1412 }
1413
1414 /* Interrupt Handler for Transmit complete */
1415 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1416 {
1417         struct net_device *dev = (struct net_device *) dev_id;
1418         struct gfar_private *priv = netdev_priv(dev);
1419
1420         /* Clear IEVENT */
1421         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1422
1423         /* Lock priv */
1424         spin_lock(&priv->txlock);
1425
1426         gfar_clean_tx_ring(dev);
1427
1428         /* If we are coalescing the interrupts, reset the timer */
1429         /* Otherwise, clear it */
1430         if (likely(priv->txcoalescing)) {
1431                 gfar_write(&priv->regs->txic, 0);
1432                 gfar_write(&priv->regs->txic,
1433                            mk_ic_value(priv->txcount, priv->txtime));
1434         }
1435
1436         spin_unlock(&priv->txlock);
1437
1438         return IRQ_HANDLED;
1439 }
1440
1441 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1442                 struct sk_buff *skb)
1443 {
1444         struct gfar_private *priv = netdev_priv(dev);
1445         u32 * status_len = (u32 *)bdp;
1446         u16 flags;
1447
1448         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1449                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1450
1451         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1452
1453         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1454                 flags |= RXBD_WRAP;
1455
1456         eieio();
1457
1458         *status_len = (u32)flags << 16;
1459 }
1460
1461
1462 struct sk_buff * gfar_new_skb(struct net_device *dev)
1463 {
1464         unsigned int alignamount;
1465         struct gfar_private *priv = netdev_priv(dev);
1466         struct sk_buff *skb = NULL;
1467
1468         /* We have to allocate the skb, so keep trying till we succeed */
1469         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1470
1471         if (!skb)
1472                 return NULL;
1473
1474         alignamount = RXBUF_ALIGNMENT -
1475                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1476
1477         /* We need the data buffer to be aligned properly.  We will reserve
1478          * as many bytes as needed to align the data properly
1479          */
1480         skb_reserve(skb, alignamount);
1481
1482         return skb;
1483 }
1484
1485 static inline void count_errors(unsigned short status, struct net_device *dev)
1486 {
1487         struct gfar_private *priv = netdev_priv(dev);
1488         struct net_device_stats *stats = &dev->stats;
1489         struct gfar_extra_stats *estats = &priv->extra_stats;
1490
1491         /* If the packet was truncated, none of the other errors
1492          * matter */
1493         if (status & RXBD_TRUNCATED) {
1494                 stats->rx_length_errors++;
1495
1496                 estats->rx_trunc++;
1497
1498                 return;
1499         }
1500         /* Count the errors, if there were any */
1501         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1502                 stats->rx_length_errors++;
1503
1504                 if (status & RXBD_LARGE)
1505                         estats->rx_large++;
1506                 else
1507                         estats->rx_short++;
1508         }
1509         if (status & RXBD_NONOCTET) {
1510                 stats->rx_frame_errors++;
1511                 estats->rx_nonoctet++;
1512         }
1513         if (status & RXBD_CRCERR) {
1514                 estats->rx_crcerr++;
1515                 stats->rx_crc_errors++;
1516         }
1517         if (status & RXBD_OVERRUN) {
1518                 estats->rx_overrun++;
1519                 stats->rx_crc_errors++;
1520         }
1521 }
1522
1523 irqreturn_t gfar_receive(int irq, void *dev_id)
1524 {
1525         struct net_device *dev = (struct net_device *) dev_id;
1526         struct gfar_private *priv = netdev_priv(dev);
1527         u32 tempval;
1528
1529         /* support NAPI */
1530         /* Clear IEVENT, so interrupts aren't called again
1531          * because of the packets that have already arrived */
1532         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1533
1534         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1535                 tempval = gfar_read(&priv->regs->imask);
1536                 tempval &= IMASK_RTX_DISABLED;
1537                 gfar_write(&priv->regs->imask, tempval);
1538
1539                 __netif_rx_schedule(dev, &priv->napi);
1540         } else {
1541                 if (netif_msg_rx_err(priv))
1542                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1543                                 dev->name, gfar_read(&priv->regs->ievent),
1544                                 gfar_read(&priv->regs->imask));
1545         }
1546
1547         return IRQ_HANDLED;
1548 }
1549
1550 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1551 {
1552         /* If valid headers were found, and valid sums
1553          * were verified, then we tell the kernel that no
1554          * checksumming is necessary.  Otherwise, it is */
1555         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1556                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1557         else
1558                 skb->ip_summed = CHECKSUM_NONE;
1559 }
1560
1561
1562 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1563 {
1564         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1565
1566         /* Remove the FCB from the skb */
1567         skb_pull(skb, GMAC_FCB_LEN);
1568
1569         return fcb;
1570 }
1571
1572 /* gfar_process_frame() -- handle one incoming packet if skb
1573  * isn't NULL.  */
1574 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1575                 int length)
1576 {
1577         struct gfar_private *priv = netdev_priv(dev);
1578         struct rxfcb *fcb = NULL;
1579
1580         if (NULL == skb) {
1581                 if (netif_msg_rx_err(priv))
1582                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1583                 dev->stats.rx_dropped++;
1584                 priv->extra_stats.rx_skbmissing++;
1585         } else {
1586                 int ret;
1587
1588                 /* Prep the skb for the packet */
1589                 skb_put(skb, length);
1590
1591                 /* Grab the FCB if there is one */
1592                 if (gfar_uses_fcb(priv))
1593                         fcb = gfar_get_fcb(skb);
1594
1595                 /* Remove the padded bytes, if there are any */
1596                 if (priv->padding)
1597                         skb_pull(skb, priv->padding);
1598
1599                 if (priv->rx_csum_enable)
1600                         gfar_rx_checksum(skb, fcb);
1601
1602                 /* Tell the skb what kind of packet this is */
1603                 skb->protocol = eth_type_trans(skb, dev);
1604
1605                 /* Send the packet up the stack */
1606                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1607                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1608                                                        fcb->vlctl);
1609                 } else
1610                         ret = netif_receive_skb(skb);
1611
1612                 if (NET_RX_DROP == ret)
1613                         priv->extra_stats.kernel_dropped++;
1614         }
1615
1616         return 0;
1617 }
1618
1619 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1620  *   until the budget/quota has been reached. Returns the number
1621  *   of frames handled
1622  */
1623 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1624 {
1625         struct rxbd8 *bdp;
1626         struct sk_buff *skb;
1627         u16 pkt_len;
1628         int howmany = 0;
1629         struct gfar_private *priv = netdev_priv(dev);
1630
1631         /* Get the first full descriptor */
1632         bdp = priv->cur_rx;
1633
1634         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1635                 struct sk_buff *newskb;
1636                 rmb();
1637
1638                 /* Add another skb for the future */
1639                 newskb = gfar_new_skb(dev);
1640
1641                 skb = priv->rx_skbuff[priv->skb_currx];
1642
1643                 /* We drop the frame if we failed to allocate a new buffer */
1644                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1645                                  bdp->status & RXBD_ERR)) {
1646                         count_errors(bdp->status, dev);
1647
1648                         if (unlikely(!newskb))
1649                                 newskb = skb;
1650
1651                         if (skb) {
1652                                 dma_unmap_single(&priv->dev->dev,
1653                                                 bdp->bufPtr,
1654                                                 priv->rx_buffer_size,
1655                                                 DMA_FROM_DEVICE);
1656
1657                                 dev_kfree_skb_any(skb);
1658                         }
1659                 } else {
1660                         /* Increment the number of packets */
1661                         dev->stats.rx_packets++;
1662                         howmany++;
1663
1664                         /* Remove the FCS from the packet length */
1665                         pkt_len = bdp->length - 4;
1666
1667                         gfar_process_frame(dev, skb, pkt_len);
1668
1669                         dev->stats.rx_bytes += pkt_len;
1670                 }
1671
1672                 dev->last_rx = jiffies;
1673
1674                 priv->rx_skbuff[priv->skb_currx] = newskb;
1675
1676                 /* Setup the new bdp */
1677                 gfar_new_rxbdp(dev, bdp, newskb);
1678
1679                 /* Update to the next pointer */
1680                 if (bdp->status & RXBD_WRAP)
1681                         bdp = priv->rx_bd_base;
1682                 else
1683                         bdp++;
1684
1685                 /* update to point at the next skb */
1686                 priv->skb_currx =
1687                     (priv->skb_currx + 1) &
1688                     RX_RING_MOD_MASK(priv->rx_ring_size);
1689         }
1690
1691         /* Update the current rxbd pointer to be the next one */
1692         priv->cur_rx = bdp;
1693
1694         return howmany;
1695 }
1696
1697 static int gfar_poll(struct napi_struct *napi, int budget)
1698 {
1699         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1700         struct net_device *dev = priv->dev;
1701         int howmany;
1702         unsigned long flags;
1703
1704         /* If we fail to get the lock, don't bother with the TX BDs */
1705         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1706                 gfar_clean_tx_ring(dev);
1707                 spin_unlock_irqrestore(&priv->txlock, flags);
1708         }
1709
1710         howmany = gfar_clean_rx_ring(dev, budget);
1711
1712         if (howmany < budget) {
1713                 netif_rx_complete(dev, napi);
1714
1715                 /* Clear the halt bit in RSTAT */
1716                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1717
1718                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1719
1720                 /* If we are coalescing interrupts, update the timer */
1721                 /* Otherwise, clear it */
1722                 if (likely(priv->rxcoalescing)) {
1723                         gfar_write(&priv->regs->rxic, 0);
1724                         gfar_write(&priv->regs->rxic,
1725                                    mk_ic_value(priv->rxcount, priv->rxtime));
1726                 }
1727         }
1728
1729         return howmany;
1730 }
1731
1732 #ifdef CONFIG_NET_POLL_CONTROLLER
1733 /*
1734  * Polling 'interrupt' - used by things like netconsole to send skbs
1735  * without having to re-enable interrupts. It's not called while
1736  * the interrupt routine is executing.
1737  */
1738 static void gfar_netpoll(struct net_device *dev)
1739 {
1740         struct gfar_private *priv = netdev_priv(dev);
1741
1742         /* If the device has multiple interrupts, run tx/rx */
1743         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1744                 disable_irq(priv->interruptTransmit);
1745                 disable_irq(priv->interruptReceive);
1746                 disable_irq(priv->interruptError);
1747                 gfar_interrupt(priv->interruptTransmit, dev);
1748                 enable_irq(priv->interruptError);
1749                 enable_irq(priv->interruptReceive);
1750                 enable_irq(priv->interruptTransmit);
1751         } else {
1752                 disable_irq(priv->interruptTransmit);
1753                 gfar_interrupt(priv->interruptTransmit, dev);
1754                 enable_irq(priv->interruptTransmit);
1755         }
1756 }
1757 #endif
1758
1759 /* The interrupt handler for devices with one interrupt */
1760 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1761 {
1762         struct net_device *dev = dev_id;
1763         struct gfar_private *priv = netdev_priv(dev);
1764
1765         /* Save ievent for future reference */
1766         u32 events = gfar_read(&priv->regs->ievent);
1767
1768         /* Check for reception */
1769         if (events & IEVENT_RX_MASK)
1770                 gfar_receive(irq, dev_id);
1771
1772         /* Check for transmit completion */
1773         if (events & IEVENT_TX_MASK)
1774                 gfar_transmit(irq, dev_id);
1775
1776         /* Check for errors */
1777         if (events & IEVENT_ERR_MASK)
1778                 gfar_error(irq, dev_id);
1779
1780         return IRQ_HANDLED;
1781 }
1782
1783 /* Called every time the controller might need to be made
1784  * aware of new link state.  The PHY code conveys this
1785  * information through variables in the phydev structure, and this
1786  * function converts those variables into the appropriate
1787  * register values, and can bring down the device if needed.
1788  */
1789 static void adjust_link(struct net_device *dev)
1790 {
1791         struct gfar_private *priv = netdev_priv(dev);
1792         struct gfar __iomem *regs = priv->regs;
1793         unsigned long flags;
1794         struct phy_device *phydev = priv->phydev;
1795         int new_state = 0;
1796
1797         spin_lock_irqsave(&priv->txlock, flags);
1798         if (phydev->link) {
1799                 u32 tempval = gfar_read(&regs->maccfg2);
1800                 u32 ecntrl = gfar_read(&regs->ecntrl);
1801
1802                 /* Now we make sure that we can be in full duplex mode.
1803                  * If not, we operate in half-duplex mode. */
1804                 if (phydev->duplex != priv->oldduplex) {
1805                         new_state = 1;
1806                         if (!(phydev->duplex))
1807                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1808                         else
1809                                 tempval |= MACCFG2_FULL_DUPLEX;
1810
1811                         priv->oldduplex = phydev->duplex;
1812                 }
1813
1814                 if (phydev->speed != priv->oldspeed) {
1815                         new_state = 1;
1816                         switch (phydev->speed) {
1817                         case 1000:
1818                                 tempval =
1819                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1820                                 break;
1821                         case 100:
1822                         case 10:
1823                                 tempval =
1824                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1825
1826                                 /* Reduced mode distinguishes
1827                                  * between 10 and 100 */
1828                                 if (phydev->speed == SPEED_100)
1829                                         ecntrl |= ECNTRL_R100;
1830                                 else
1831                                         ecntrl &= ~(ECNTRL_R100);
1832                                 break;
1833                         default:
1834                                 if (netif_msg_link(priv))
1835                                         printk(KERN_WARNING
1836                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1837                                                 dev->name, phydev->speed);
1838                                 break;
1839                         }
1840
1841                         priv->oldspeed = phydev->speed;
1842                 }
1843
1844                 gfar_write(&regs->maccfg2, tempval);
1845                 gfar_write(&regs->ecntrl, ecntrl);
1846
1847                 if (!priv->oldlink) {
1848                         new_state = 1;
1849                         priv->oldlink = 1;
1850                 }
1851         } else if (priv->oldlink) {
1852                 new_state = 1;
1853                 priv->oldlink = 0;
1854                 priv->oldspeed = 0;
1855                 priv->oldduplex = -1;
1856         }
1857
1858         if (new_state && netif_msg_link(priv))
1859                 phy_print_status(phydev);
1860
1861         spin_unlock_irqrestore(&priv->txlock, flags);
1862 }
1863
1864 /* Update the hash table based on the current list of multicast
1865  * addresses we subscribe to.  Also, change the promiscuity of
1866  * the device based on the flags (this function is called
1867  * whenever dev->flags is changed */
1868 static void gfar_set_multi(struct net_device *dev)
1869 {
1870         struct dev_mc_list *mc_ptr;
1871         struct gfar_private *priv = netdev_priv(dev);
1872         struct gfar __iomem *regs = priv->regs;
1873         u32 tempval;
1874
1875         if(dev->flags & IFF_PROMISC) {
1876                 /* Set RCTRL to PROM */
1877                 tempval = gfar_read(&regs->rctrl);
1878                 tempval |= RCTRL_PROM;
1879                 gfar_write(&regs->rctrl, tempval);
1880         } else {
1881                 /* Set RCTRL to not PROM */
1882                 tempval = gfar_read(&regs->rctrl);
1883                 tempval &= ~(RCTRL_PROM);
1884                 gfar_write(&regs->rctrl, tempval);
1885         }
1886
1887         if(dev->flags & IFF_ALLMULTI) {
1888                 /* Set the hash to rx all multicast frames */
1889                 gfar_write(&regs->igaddr0, 0xffffffff);
1890                 gfar_write(&regs->igaddr1, 0xffffffff);
1891                 gfar_write(&regs->igaddr2, 0xffffffff);
1892                 gfar_write(&regs->igaddr3, 0xffffffff);
1893                 gfar_write(&regs->igaddr4, 0xffffffff);
1894                 gfar_write(&regs->igaddr5, 0xffffffff);
1895                 gfar_write(&regs->igaddr6, 0xffffffff);
1896                 gfar_write(&regs->igaddr7, 0xffffffff);
1897                 gfar_write(&regs->gaddr0, 0xffffffff);
1898                 gfar_write(&regs->gaddr1, 0xffffffff);
1899                 gfar_write(&regs->gaddr2, 0xffffffff);
1900                 gfar_write(&regs->gaddr3, 0xffffffff);
1901                 gfar_write(&regs->gaddr4, 0xffffffff);
1902                 gfar_write(&regs->gaddr5, 0xffffffff);
1903                 gfar_write(&regs->gaddr6, 0xffffffff);
1904                 gfar_write(&regs->gaddr7, 0xffffffff);
1905         } else {
1906                 int em_num;
1907                 int idx;
1908
1909                 /* zero out the hash */
1910                 gfar_write(&regs->igaddr0, 0x0);
1911                 gfar_write(&regs->igaddr1, 0x0);
1912                 gfar_write(&regs->igaddr2, 0x0);
1913                 gfar_write(&regs->igaddr3, 0x0);
1914                 gfar_write(&regs->igaddr4, 0x0);
1915                 gfar_write(&regs->igaddr5, 0x0);
1916                 gfar_write(&regs->igaddr6, 0x0);
1917                 gfar_write(&regs->igaddr7, 0x0);
1918                 gfar_write(&regs->gaddr0, 0x0);
1919                 gfar_write(&regs->gaddr1, 0x0);
1920                 gfar_write(&regs->gaddr2, 0x0);
1921                 gfar_write(&regs->gaddr3, 0x0);
1922                 gfar_write(&regs->gaddr4, 0x0);
1923                 gfar_write(&regs->gaddr5, 0x0);
1924                 gfar_write(&regs->gaddr6, 0x0);
1925                 gfar_write(&regs->gaddr7, 0x0);
1926
1927                 /* If we have extended hash tables, we need to
1928                  * clear the exact match registers to prepare for
1929                  * setting them */
1930                 if (priv->extended_hash) {
1931                         em_num = GFAR_EM_NUM + 1;
1932                         gfar_clear_exact_match(dev);
1933                         idx = 1;
1934                 } else {
1935                         idx = 0;
1936                         em_num = 0;
1937                 }
1938
1939                 if(dev->mc_count == 0)
1940                         return;
1941
1942                 /* Parse the list, and set the appropriate bits */
1943                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1944                         if (idx < em_num) {
1945                                 gfar_set_mac_for_addr(dev, idx,
1946                                                 mc_ptr->dmi_addr);
1947                                 idx++;
1948                         } else
1949                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1950                 }
1951         }
1952
1953         return;
1954 }
1955
1956
1957 /* Clears each of the exact match registers to zero, so they
1958  * don't interfere with normal reception */
1959 static void gfar_clear_exact_match(struct net_device *dev)
1960 {
1961         int idx;
1962         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1963
1964         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1965                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1966 }
1967
1968 /* Set the appropriate hash bit for the given addr */
1969 /* The algorithm works like so:
1970  * 1) Take the Destination Address (ie the multicast address), and
1971  * do a CRC on it (little endian), and reverse the bits of the
1972  * result.
1973  * 2) Use the 8 most significant bits as a hash into a 256-entry
1974  * table.  The table is controlled through 8 32-bit registers:
1975  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1976  * gaddr7.  This means that the 3 most significant bits in the
1977  * hash index which gaddr register to use, and the 5 other bits
1978  * indicate which bit (assuming an IBM numbering scheme, which
1979  * for PowerPC (tm) is usually the case) in the register holds
1980  * the entry. */
1981 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1982 {
1983         u32 tempval;
1984         struct gfar_private *priv = netdev_priv(dev);
1985         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1986         int width = priv->hash_width;
1987         u8 whichbit = (result >> (32 - width)) & 0x1f;
1988         u8 whichreg = result >> (32 - width + 5);
1989         u32 value = (1 << (31-whichbit));
1990
1991         tempval = gfar_read(priv->hash_regs[whichreg]);
1992         tempval |= value;
1993         gfar_write(priv->hash_regs[whichreg], tempval);
1994
1995         return;
1996 }
1997
1998
1999 /* There are multiple MAC Address register pairs on some controllers
2000  * This function sets the numth pair to a given address
2001  */
2002 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2003 {
2004         struct gfar_private *priv = netdev_priv(dev);
2005         int idx;
2006         char tmpbuf[MAC_ADDR_LEN];
2007         u32 tempval;
2008         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2009
2010         macptr += num*2;
2011
2012         /* Now copy it into the mac registers backwards, cuz */
2013         /* little endian is silly */
2014         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2015                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2016
2017         gfar_write(macptr, *((u32 *) (tmpbuf)));
2018
2019         tempval = *((u32 *) (tmpbuf + 4));
2020
2021         gfar_write(macptr+1, tempval);
2022 }
2023
2024 /* GFAR error interrupt handler */
2025 static irqreturn_t gfar_error(int irq, void *dev_id)
2026 {
2027         struct net_device *dev = dev_id;
2028         struct gfar_private *priv = netdev_priv(dev);
2029
2030         /* Save ievent for future reference */
2031         u32 events = gfar_read(&priv->regs->ievent);
2032
2033         /* Clear IEVENT */
2034         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2035
2036         /* Magic Packet is not an error. */
2037         if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2038             (events & IEVENT_MAG))
2039                 events &= ~IEVENT_MAG;
2040
2041         /* Hmm... */
2042         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2043                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2044                        dev->name, events, gfar_read(&priv->regs->imask));
2045
2046         /* Update the error counters */
2047         if (events & IEVENT_TXE) {
2048                 dev->stats.tx_errors++;
2049
2050                 if (events & IEVENT_LC)
2051                         dev->stats.tx_window_errors++;
2052                 if (events & IEVENT_CRL)
2053                         dev->stats.tx_aborted_errors++;
2054                 if (events & IEVENT_XFUN) {
2055                         if (netif_msg_tx_err(priv))
2056                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2057                                        "packet dropped.\n", dev->name);
2058                         dev->stats.tx_dropped++;
2059                         priv->extra_stats.tx_underrun++;
2060
2061                         /* Reactivate the Tx Queues */
2062                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2063                 }
2064                 if (netif_msg_tx_err(priv))
2065                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2066         }
2067         if (events & IEVENT_BSY) {
2068                 dev->stats.rx_errors++;
2069                 priv->extra_stats.rx_bsy++;
2070
2071                 gfar_receive(irq, dev_id);
2072
2073                 if (netif_msg_rx_err(priv))
2074                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2075                                dev->name, gfar_read(&priv->regs->rstat));
2076         }
2077         if (events & IEVENT_BABR) {
2078                 dev->stats.rx_errors++;
2079                 priv->extra_stats.rx_babr++;
2080
2081                 if (netif_msg_rx_err(priv))
2082                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2083         }
2084         if (events & IEVENT_EBERR) {
2085                 priv->extra_stats.eberr++;
2086                 if (netif_msg_rx_err(priv))
2087                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2088         }
2089         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2090                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2091
2092         if (events & IEVENT_BABT) {
2093                 priv->extra_stats.tx_babt++;
2094                 if (netif_msg_tx_err(priv))
2095                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2096         }
2097         return IRQ_HANDLED;
2098 }
2099
2100 /* work with hotplug and coldplug */
2101 MODULE_ALIAS("platform:fsl-gianfar");
2102
2103 /* Structure for a device driver */
2104 static struct platform_driver gfar_driver = {
2105         .probe = gfar_probe,
2106         .remove = gfar_remove,
2107         .suspend = gfar_suspend,
2108         .resume = gfar_resume,
2109         .driver = {
2110                 .name = "fsl-gianfar",
2111                 .owner = THIS_MODULE,
2112         },
2113 };
2114
2115 static int __init gfar_init(void)
2116 {
2117         int err = gfar_mdio_init();
2118
2119         if (err)
2120                 return err;
2121
2122         err = platform_driver_register(&gfar_driver);
2123
2124         if (err)
2125                 gfar_mdio_exit();
2126
2127         return err;
2128 }
2129
2130 static void __exit gfar_exit(void)
2131 {
2132         platform_driver_unregister(&gfar_driver);
2133         gfar_mdio_exit();
2134 }
2135
2136 module_init(gfar_init);
2137 module_exit(gfar_exit);
2138