1 /* ITLB ** ICACHE line 1: Context 0 check and TSB load */
2 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
3 ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET
4 srlx %g6, 48, %g5 ! Get context
5 sllx %g6, 22, %g6 ! Zero out context
6 brz,pn %g5, kvmap_itlb ! Context 0 processing
7 srlx %g6, 22, %g6 ! Delay slot
8 TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
9 cmp %g4, %g6 ! Compare TAG
11 /* ITLB ** ICACHE line 2: TSB compare and TLB load */
12 sethi %hi(PAGE_EXEC), %g4 ! Setup exec check
13 ldx [%g4 + %lo(PAGE_EXEC)], %g4
14 bne,pn %xcc, tsb_miss_itlb ! Miss
15 mov FAULT_CODE_ITLB, %g3
16 andcc %g5, %g4, %g0 ! Executable?
17 be,pn %xcc, tsb_do_fault
18 nop ! Delay slot, fill me
21 /* ITLB ** ICACHE line 3: */
22 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
31 /* ITLB ** ICACHE line 4: */