git.oblomov.eu Git - linux-2.6/blob - arch/ppc/syslib/open_pic2.c

   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  *
  10  *  This is a duplicate of open_pic.c that deals with U3s MPIC on
  11  *  G5 PowerMacs. It's the same file except it's using big endian
  12  *  register accesses
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/init.h>
  20 #include <linux/irq.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/sysdev.h>
  23 #include <linux/errno.h>
  24 #include <asm/ptrace.h>
  25 #include <asm/signal.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28 #include <asm/sections.h>
  29 #include <asm/open_pic.h>
  30 #include <asm/i8259.h>
  31
  32 #include "open_pic_defs.h"
  33
  34 void *OpenPIC2_Addr;
  35 static volatile struct OpenPIC *OpenPIC2 = NULL;
  36 /*
  37  * We define OpenPIC_InitSenses table thusly:
  38  * bit 0x1: sense, 0 for edge and 1 for level.
  39  * bit 0x2: polarity, 0 for negative, 1 for positive.
  40  */
  41 extern  u_int OpenPIC_NumInitSenses;
  42 extern u_char *OpenPIC_InitSenses;
  43 extern int use_of_interrupt_tree;
  44
  45 static u_int NumProcessors;
  46 static u_int NumSources;
  47 static int open_pic2_irq_offset;
  48 static volatile OpenPIC_Source *ISR[NR_IRQS];
  49
  50 /* Global Operations */
  51 static void openpic2_disable_8259_pass_through(void);
  52 static void openpic2_set_priority(u_int pri);
  53 static void openpic2_set_spurious(u_int vector);
  54
  55 /* Timer Interrupts */
  56 static void openpic2_inittimer(u_int timer, u_int pri, u_int vector);
  57 static void openpic2_maptimer(u_int timer, u_int cpumask);
  58
  59 /* Interrupt Sources */
  60 static void openpic2_enable_irq(u_int irq);
  61 static void openpic2_disable_irq(u_int irq);
  62 static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  63                             int is_level);
  64 static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask);
  65
  66 /*
  67  * These functions are not used but the code is kept here
  68  * for completeness and future reference.
  69  */
  70 static void openpic2_reset(void);
  71 #ifdef notused
  72 static void openpic2_enable_8259_pass_through(void);
  73 static u_int openpic2_get_priority(void);
  74 static u_int openpic2_get_spurious(void);
  75 static void openpic2_set_sense(u_int irq, int sense);
  76 #endif /* notused */
  77
  78 /*
  79  * Description of the openpic for the higher-level irq code
  80  */
  81 static void openpic2_end_irq(unsigned int irq_nr);
  82 static void openpic2_ack_irq(unsigned int irq_nr);
  83
  84 struct hw_interrupt_type open_pic2 = {
  85         .typename = " OpenPIC2 ",
  86         .enable = openpic2_enable_irq,
  87         .disable = openpic2_disable_irq,
  88         .ack = openpic2_ack_irq,
  89         .end = openpic2_end_irq,
  90 };
  91
  92 /*
  93  *  Accesses to the current processor's openpic registers
  94  *  On cascaded controller, this is only CPU 0
  95  */
  96 #define THIS_CPU                Processor[0]
  97 #define DECL_THIS_CPU
  98 #define CHECK_THIS_CPU
  99
 100 #if 1
 101 #define check_arg_ipi(ipi) \
 102     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 103         printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi);
 104 #define check_arg_timer(timer) \
 105     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 106         printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer);
 107 #define check_arg_vec(vec) \
 108     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 109         printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec);
 110 #define check_arg_pri(pri) \
 111     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 112         printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri);
 113 /*
 114  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 115  * data has probably been corrupted and we're going to panic or deadlock later
 116  * anyway --Troy
 117  */
 118 extern unsigned long* _get_SP(void);
 119 #define check_arg_irq(irq) \
 120     if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \
 121         || ISR[irq - open_pic2_irq_offset] == 0) { \
 122       printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \
 123       /*print_backtrace(_get_SP());*/ }
 124 #define check_arg_cpu(cpu) \
 125     if (cpu < 0 || cpu >= NumProcessors){ \
 126         printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \
 127         /*print_backtrace(_get_SP());*/ }
 128 #else
 129 #define check_arg_ipi(ipi)      do {} while (0)
 130 #define check_arg_timer(timer)  do {} while (0)
 131 #define check_arg_vec(vec)      do {} while (0)
 132 #define check_arg_pri(pri)      do {} while (0)
 133 #define check_arg_irq(irq)      do {} while (0)
 134 #define check_arg_cpu(cpu)      do {} while (0)
 135 #endif
 136
 137 static u_int openpic2_read(volatile u_int *addr)
 138 {
 139         u_int val;
 140
 141         val = in_be32(addr);
 142         return val;
 143 }
 144
 145 static inline void openpic2_write(volatile u_int *addr, u_int val)
 146 {
 147         out_be32(addr, val);
 148 }
 149
 150 static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask)
 151 {
 152         u_int val = openpic2_read(addr);
 153         return val & mask;
 154 }
 155
 156 inline void openpic2_writefield(volatile u_int *addr, u_int mask,
 157                                u_int field)
 158 {
 159         u_int val = openpic2_read(addr);
 160         openpic2_write(addr, (val & ~mask) | (field & mask));
 161 }
 162
 163 static inline void openpic2_clearfield(volatile u_int *addr, u_int mask)
 164 {
 165         openpic2_writefield(addr, mask, 0);
 166 }
 167
 168 static inline void openpic2_setfield(volatile u_int *addr, u_int mask)
 169 {
 170         openpic2_writefield(addr, mask, mask);
 171 }
 172
 173 static void openpic2_safe_writefield(volatile u_int *addr, u_int mask,
 174                                     u_int field)
 175 {
 176         openpic2_setfield(addr, OPENPIC_MASK);
 177         while (openpic2_read(addr) & OPENPIC_ACTIVITY);
 178         openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 179 }
 180
 181 static void openpic2_reset(void)
 182 {
 183         openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
 184                          OPENPIC_CONFIG_RESET);
 185         while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0,
 186                                  OPENPIC_CONFIG_RESET))
 187                 mb();
 188 }
 189
 190 void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR)
 191 {
 192         volatile OpenPIC_Source *src = first_ISR;
 193         int i, last_irq;
 194
 195         last_irq = first_irq + num_irqs;
 196         if (last_irq > NumSources)
 197                 NumSources = last_irq;
 198         if (src == 0)
 199                 src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq];
 200         for (i = first_irq; i < last_irq; ++i, ++src)
 201                 ISR[i] = src;
 202 }
 203
 204 /*
 205  * The `offset' parameter defines where the interrupts handled by the
 206  * OpenPIC start in the space of interrupt numbers that the kernel knows
 207  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 208  * kernel's interrupt numbering scheme.
 209  * We assume there is only one OpenPIC.
 210  */
 211 void __init openpic2_init(int offset)
 212 {
 213         u_int t, i;
 214         u_int timerfreq;
 215         const char *version;
 216
 217         if (!OpenPIC2_Addr) {
 218                 printk("No OpenPIC2 found !\n");
 219                 return;
 220         }
 221         OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr;
 222
 223         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 224
 225         t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0);
 226         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 227         case 1:
 228                 version = "1.0";
 229                 break;
 230         case 2:
 231                 version = "1.2";
 232                 break;
 233         case 3:
 234                 version = "1.3";
 235                 break;
 236         default:
 237                 version = "?";
 238                 break;
 239         }
 240         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 241                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 242         if (NumSources == 0)
 243                 openpic2_set_sources(0,
 244                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 245                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 246                                     NULL);
 247         printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n",
 248                version, NumProcessors, NumSources, OpenPIC2);
 249         timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency);
 250         if (timerfreq)
 251                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 252                        timerfreq / 1000000, timerfreq % 1000000);
 253
 254         open_pic2_irq_offset = offset;
 255
 256         /* Initialize timer interrupts */
 257         if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba);
 258         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 259                 /* Disabled, Priority 0 */
 260                 openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset);
 261                 /* No processor */
 262                 openpic2_maptimer(i, 0);
 263         }
 264
 265         /* Initialize external interrupts */
 266         if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc);
 267
 268         openpic2_set_priority(0xf);
 269
 270         /* Init all external sources, including possibly the cascade. */
 271         for (i = 0; i < NumSources; i++) {
 272                 int sense;
 273
 274                 if (ISR[i] == 0)
 275                         continue;
 276
 277                 /* the bootloader may have left it enabled (bad !) */
 278                 openpic2_disable_irq(i+offset);
 279
 280                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 281                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 282
 283                 if (sense & IRQ_SENSE_MASK)
 284                         irq_desc[i+offset].status = IRQ_LEVEL;
 285
 286                 /* Enabled, Priority 8 */
 287                 openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
 288                                 (sense & IRQ_SENSE_MASK));
 289                 /* Processor 0 */
 290                 openpic2_mapirq(i, 1<<0, 0);
 291         }
 292
 293         /* Init descriptors */
 294         for (i = offset; i < NumSources + offset; i++)
 295                 irq_desc[i].handler = &open_pic2;
 296
 297         /* Initialize the spurious interrupt */
 298         if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd);
 299         openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset);
 300
 301         openpic2_disable_8259_pass_through();
 302         openpic2_set_priority(0);
 303
 304         if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222);
 305 }
 306
 307 #ifdef notused
 308 static void openpic2_enable_8259_pass_through(void)
 309 {
 310         openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0,
 311                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 312 }
 313 #endif /* notused */
 314
 315 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
 316 static void openpic2_disable_8259_pass_through(void)
 317 {
 318         openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
 319                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 320 }
 321
 322 /*
 323  *  Find out the current interrupt
 324  */
 325 u_int openpic2_irq(void)
 326 {
 327         u_int vec;
 328         DECL_THIS_CPU;
 329
 330         CHECK_THIS_CPU;
 331         vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge,
 332                                 OPENPIC_VECTOR_MASK);
 333         return vec;
 334 }
 335
 336 void openpic2_eoi(void)
 337 {
 338         DECL_THIS_CPU;
 339
 340         CHECK_THIS_CPU;
 341         openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0);
 342         /* Handle PCI write posting */
 343         (void)openpic2_read(&OpenPIC2->THIS_CPU.EOI);
 344 }
 345
 346 #ifdef notused
 347 static u_int openpic2_get_priority(void)
 348 {
 349         DECL_THIS_CPU;
 350
 351         CHECK_THIS_CPU;
 352         return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
 353                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 354 }
 355 #endif /* notused */
 356
 357 static void __init openpic2_set_priority(u_int pri)
 358 {
 359         DECL_THIS_CPU;
 360
 361         CHECK_THIS_CPU;
 362         check_arg_pri(pri);
 363         openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
 364                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 365 }
 366
 367 /*
 368  *  Get/set the spurious vector
 369  */
 370 #ifdef notused
 371 static u_int openpic2_get_spurious(void)
 372 {
 373         return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector,
 374                                  OPENPIC_VECTOR_MASK);
 375 }
 376 #endif /* notused */
 377
 378 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
 379 static void openpic2_set_spurious(u_int vec)
 380 {
 381         check_arg_vec(vec);
 382         openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 383                            vec);
 384 }
 385
 386 static DEFINE_SPINLOCK(openpic2_setup_lock);
 387
 388 /*
 389  *  Initialize a timer interrupt (and disable it)
 390  *
 391  *  timer: OpenPIC timer number
 392  *  pri: interrupt source priority
 393  *  vec: the vector it will produce
 394  */
 395 static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec)
 396 {
 397         check_arg_timer(timer);
 398         check_arg_pri(pri);
 399         check_arg_vec(vec);
 400         openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority,
 401                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 402                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 403 }
 404
 405 /*
 406  *  Map a timer interrupt to one or more CPUs
 407  */
 408 static void __init openpic2_maptimer(u_int timer, u_int cpumask)
 409 {
 410         check_arg_timer(timer);
 411         openpic2_write(&OpenPIC2->Global.Timer[timer].Destination,
 412                       cpumask);
 413 }
 414
 415 /*
 416  * Initalize the interrupt source which will generate an NMI.
 417  * This raises the interrupt's priority from 8 to 9.
 418  *
 419  * irq: The logical IRQ which generates an NMI.
 420  */
 421 void __init
 422 openpic2_init_nmi_irq(u_int irq)
 423 {
 424         check_arg_irq(irq);
 425         openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority,
 426                                 OPENPIC_PRIORITY_MASK,
 427                                 9 << OPENPIC_PRIORITY_SHIFT);
 428 }
 429
 430 /*
 431  *
 432  * All functions below take an offset'ed irq argument
 433  *
 434  */
 435
 436
 437 /*
 438  *  Enable/disable an external interrupt source
 439  *
 440  *  Externally called, irq is an offseted system-wide interrupt number
 441  */
 442 static void openpic2_enable_irq(u_int irq)
 443 {
 444         volatile u_int *vpp;
 445
 446         check_arg_irq(irq);
 447         vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
 448         openpic2_clearfield(vpp, OPENPIC_MASK);
 449         /* make sure mask gets to controller before we return to user */
 450         do {
 451                 mb(); /* sync is probably useless here */
 452         } while (openpic2_readfield(vpp, OPENPIC_MASK));
 453 }
 454
 455 static void openpic2_disable_irq(u_int irq)
 456 {
 457         volatile u_int *vpp;
 458         u32 vp;
 459
 460         check_arg_irq(irq);
 461         vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
 462         openpic2_setfield(vpp, OPENPIC_MASK);
 463         /* make sure mask gets to controller before we return to user */
 464         do {
 465                 mb();  /* sync is probably useless here */
 466                 vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 467         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 468 }
 469
 470
 471 /*
 472  *  Initialize an interrupt source (and disable it!)
 473  *
 474  *  irq: OpenPIC interrupt number
 475  *  pri: interrupt source priority
 476  *  vec: the vector it will produce
 477  *  pol: polarity (1 for positive, 0 for negative)
 478  *  sense: 1 for level, 0 for edge
 479  */
 480 static void __init
 481 openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 482 {
 483         openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
 484                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 485                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 486                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 487                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 488                                         OPENPIC_POLARITY_NEGATIVE) |
 489                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 490 }
 491
 492 /*
 493  *  Map an interrupt source to one or more CPUs
 494  */
 495 static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask)
 496 {
 497         if (ISR[irq] == 0)
 498                 return;
 499         if (keepmask != 0)
 500                 physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask;
 501         openpic2_write(&ISR[irq]->Destination, physmask);
 502 }
 503
 504 #ifdef notused
 505 /*
 506  *  Set the sense for an interrupt source (and disable it!)
 507  *
 508  *  sense: 1 for level, 0 for edge
 509  */
 510 static void openpic2_set_sense(u_int irq, int sense)
 511 {
 512         if (ISR[irq] != 0)
 513                 openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
 514                                         OPENPIC_SENSE_LEVEL,
 515                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 516 }
 517 #endif /* notused */
 518
 519 /* No spinlocks, should not be necessary with the OpenPIC
 520  * (1 register = 1 interrupt and we have the desc lock).
 521  */
 522 static void openpic2_ack_irq(unsigned int irq_nr)
 523 {
 524         openpic2_disable_irq(irq_nr);
 525         openpic2_eoi();
 526 }
 527
 528 static void openpic2_end_irq(unsigned int irq_nr)
 529 {
 530         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 531                 openpic2_enable_irq(irq_nr);
 532 }
 533
 534 int
 535 openpic2_get_irq(struct pt_regs *regs)
 536 {
 537         int irq = openpic2_irq();
 538
 539         if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset))
 540                 irq = -1;
 541         return irq;
 542 }
 543
 544 #ifdef CONFIG_PM
 545
 546 /*
 547  * We implement the IRQ controller as a sysdev and put it
 548  * to sleep at powerdown stage (the callback is named suspend,
 549  * but it's old semantics, for the Device Model, it's really
 550  * powerdown). The possible problem is that another sysdev that
 551  * happens to be suspend after this one will have interrupts off,
 552  * that may be an issue... For now, this isn't an issue on pmac
 553  * though...
 554  */
 555
 556 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 557 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 558 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 559 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 560 static int openpic_suspend_count;
 561
 562 static void openpic2_cached_enable_irq(u_int irq)
 563 {
 564         check_arg_irq(irq);
 565         save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK;
 566 }
 567
 568 static void openpic2_cached_disable_irq(u_int irq)
 569 {
 570         check_arg_irq(irq);
 571         save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK;
 572 }
 573
 574 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 575  * we need something better to deal with that... Maybe switch to S1 for
 576  * cpufreq changes
 577  */
 578 int openpic2_suspend(struct sys_device *sysdev, u32 state)
 579 {
 580         int     i;
 581         unsigned long flags;
 582
 583         spin_lock_irqsave(&openpic2_setup_lock, flags);
 584
 585         if (openpic_suspend_count++ > 0) {
 586                 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 587                 return 0;
 588         }
 589
 590         open_pic2.enable = openpic2_cached_enable_irq;
 591         open_pic2.disable = openpic2_cached_disable_irq;
 592
 593         for (i=0; i<NumProcessors; i++) {
 594                 save_cpu_task_pri[i] = openpic2_read(&OpenPIC2->Processor[i].Current_Task_Priority);
 595                 openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority,
 596                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 597         }
 598
 599         for (i=0; i<OPENPIC_NUM_IPI; i++)
 600                 save_ipi_vp[i] = openpic2_read(&OpenPIC2->Global.IPI_Vector_Priority(i));
 601         for (i=0; i<NumSources; i++) {
 602                 if (ISR[i] == 0)
 603                         continue;
 604                 save_irq_src_vp[i] = openpic2_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 605                 save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination);
 606         }
 607
 608         spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 609
 610         return 0;
 611 }
 612
 613 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 614  * we need something better to deal with that... Maybe switch to S1 for
 615  * cpufreq changes
 616  */
 617 int openpic2_resume(struct sys_device *sysdev)
 618 {
 619         int             i;
 620         unsigned long   flags;
 621         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 622                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 623                                         OPENPIC_MASK;
 624
 625         spin_lock_irqsave(&openpic2_setup_lock, flags);
 626
 627         if ((--openpic_suspend_count) > 0) {
 628                 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 629                 return 0;
 630         }
 631
 632         openpic2_reset();
 633
 634         /* OpenPIC sometimes seem to need some time to be fully back up... */
 635         do {
 636                 openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset);
 637         } while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
 638                         != (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset));
 639
 640         openpic2_disable_8259_pass_through();
 641
 642         for (i=0; i<OPENPIC_NUM_IPI; i++)
 643                 openpic2_write(&OpenPIC2->Global.IPI_Vector_Priority(i),
 644                               save_ipi_vp[i]);
 645         for (i=0; i<NumSources; i++) {
 646                 if (ISR[i] == 0)
 647                         continue;
 648                 openpic2_write(&ISR[i]->Destination, save_irq_src_dest[i]);
 649                 openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
 650                 /* make sure mask gets to controller before we return to user */
 651                 do {
 652                         openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
 653                 } while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask)
 654                          != (save_irq_src_vp[i] & vppmask));
 655         }
 656         for (i=0; i<NumProcessors; i++)
 657                 openpic2_write(&OpenPIC2->Processor[i].Current_Task_Priority,
 658                               save_cpu_task_pri[i]);
 659
 660         open_pic2.enable = openpic2_enable_irq;
 661         open_pic2.disable = openpic2_disable_irq;
 662
 663         spin_unlock_irqrestore(&openpic2_setup_lock, flags);
 664
 665         return 0;
 666 }
 667
 668 #endif /* CONFIG_PM */
 669
 670 /* HACK ALERT */
 671 static struct sysdev_class openpic2_sysclass = {
 672         set_kset_name("openpic2"),
 673 };
 674
 675 static struct sys_device device_openpic2 = {
 676         .id             = 0,
 677         .cls            = &openpic2_sysclass,
 678 };
 679
 680 static struct sysdev_driver driver_openpic2 = {
 681 #ifdef CONFIG_PM
 682         .suspend        = &openpic2_suspend,
 683         .resume         = &openpic2_resume,
 684 #endif /* CONFIG_PM */
 685 };
 686
 687 static int __init init_openpic2_sysfs(void)
 688 {
 689         int rc;
 690
 691         if (!OpenPIC2_Addr)
 692                 return -ENODEV;
 693         printk(KERN_DEBUG "Registering openpic2 with sysfs...\n");
 694         rc = sysdev_class_register(&openpic2_sysclass);
 695         if (rc) {
 696                 printk(KERN_ERR "Failed registering openpic sys class\n");
 697                 return -ENODEV;
 698         }
 699         rc = sysdev_register(&device_openpic2);
 700         if (rc) {
 701                 printk(KERN_ERR "Failed registering openpic sys device\n");
 702                 return -ENODEV;
 703         }
 704         rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2);
 705         if (rc) {
 706                 printk(KERN_ERR "Failed registering openpic sys driver\n");
 707                 return -ENODEV;
 708         }
 709         return 0;
 710 }
 711
 712 subsys_initcall(init_openpic2_sysfs);
 713