2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 Power Management routines.
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Some of the routines are right out of init/main.c, whose
9 * copyrights apply here.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/init.h>
34 #include <linux/sysctl.h>
35 #include <linux/jiffies.h>
37 #include <asm/uaccess.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
47 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
49 #define DPRINTK(fmt, args...)
52 extern unsigned long save_local_and_disable(int controller);
53 extern void restore_local_and_enable(int controller, unsigned long mask);
55 static DEFINE_SPINLOCK(pm_lock);
58 * We need to save/restore a bunch of core registers that are
59 * either volatile or reset to some state across a processor sleep.
60 * If reading a register doesn't provide a proper result for a
61 * later restore, we have to provide a function for loading that
62 * register and save a copy.
64 * We only have to save/restore registers that aren't otherwise
65 * done as part of a driver pm_* function.
67 static unsigned int sleep_uart0_inten;
68 static unsigned int sleep_uart0_fifoctl;
69 static unsigned int sleep_uart0_linectl;
70 static unsigned int sleep_uart0_clkdiv;
71 static unsigned int sleep_uart0_enable;
72 static unsigned int sleep_usb[2];
73 static unsigned int sleep_sys_clocks[5];
74 static unsigned int sleep_sys_pinfunc;
75 static unsigned int sleep_static_memctlr[4][3];
78 * Define this to cause the value you write to /proc/sys/pm/sleep to
79 * set the TOY timer for the amount of time you want to sleep.
80 * This is done mainly for testing, but may be useful in other cases.
81 * The value is number of 32KHz ticks to sleep.
83 #define SLEEP_TEST_TIMEOUT 1
84 #ifdef SLEEP_TEST_TIMEOUT
85 static int sleep_ticks;
86 static void wakeup_counter0_set(int ticks)
88 au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2);
93 static void save_core_regs(void)
95 extern void save_au1xxx_intctl(void);
96 extern void pm_eth0_shutdown(void);
99 * Do the serial ports.....these really should be a pm_*
100 * registered function by the driver......but of course the
101 * standard serial driver doesn't understand our Au1xxx
104 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
105 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
106 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
107 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
108 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
111 #ifndef CONFIG_SOC_AU1200
112 /* Shutdown USB host/device. */
113 sleep_usb[0] = au_readl(USB_HOST_CONFIG);
115 /* There appears to be some undocumented reset register.... */
116 au_writel(0, 0xb0100004);
118 au_writel(0, USB_HOST_CONFIG);
121 sleep_usb[1] = au_readl(USBD_ENABLE);
122 au_writel(0, USBD_ENABLE);
127 /* enable access to OTG mmio so we can save OTG CAP/MUX.
128 * FIXME: write an OTG driver and move this stuff there!
130 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
132 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
133 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
136 /* Save interrupt controller state. */
137 save_au1xxx_intctl();
139 /* Clocks and PLLs. */
140 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
141 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
142 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
143 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
144 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
147 sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
149 /* Save the static memory controller configuration. */
150 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
151 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
152 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
153 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
154 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
155 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
156 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
157 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
158 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
159 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
160 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
161 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
163 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
164 au1xxx_dbdma_suspend();
168 static void restore_core_regs(void)
170 /* restore clock configuration. Writing CPUPLL last will
171 * stall a bit and stabilize other clocks (unless this is
172 * one of those Au1000 with a write-only PLL, where we dont
173 * have a valid value)
175 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
176 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
177 au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
178 au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
179 if (!au1xxx_cpu_has_pll_wo())
180 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
183 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
186 #ifndef CONFIG_SOC_AU1200
187 au_writel(sleep_usb[0], USB_HOST_CONFIG);
188 au_writel(sleep_usb[1], USBD_ENABLE);
191 /* enable accces to OTG memory */
192 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
195 /* restore OTG caps and port mux. */
196 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
198 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
202 /* Restore the static memory controller configuration. */
203 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
204 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
205 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
206 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
207 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
208 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
209 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
210 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
211 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
212 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
213 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
214 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
217 * Enable the UART if it was enabled before sleep.
218 * I guess I should define module control bits........
220 if (sleep_uart0_enable & 0x02) {
221 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
222 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
223 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
224 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
225 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
226 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
227 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
230 restore_au1xxx_intctl();
232 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
233 au1xxx_dbdma_resume();
237 unsigned long suspend_mode;
239 void wakeup_from_suspend(void)
247 au1xxx_save_and_sleep();
251 static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
252 void __user *buffer, size_t *len, loff_t *ppos)
254 unsigned long wakeup, flags;
256 #ifdef SLEEP_TEST_TIMEOUT
257 #define TMPBUFLEN2 16
258 char buf[TMPBUFLEN2], *p;
261 spin_lock_irqsave(&pm_lock, flags);
269 #ifdef SLEEP_TEST_TIMEOUT
270 if (*len > TMPBUFLEN2 - 1) {
274 if (copy_from_user(buf, buffer, *len)) {
280 sleep_ticks = simple_strtoul(p, &p, 0);
281 wakeup_counter0_set(sleep_ticks);
285 ** The code below is all system dependent and we should probably
286 ** have a function call out of here to set this up. You need
287 ** to configure the GPIO or timer interrupts that will bring
289 ** For testing, the TOY counter wakeup is useful.
292 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
294 /* GPIO 6 can cause a wake up event */
295 wakeup = au_readl(SYS_WAKEMSK);
296 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
297 wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */
299 /* For testing, allow match20 to wake us up. */
300 wakeup = 1 << 8; /* turn on match20 wakeup */
303 au_writel(1, SYS_WAKESRC); /* clear cause */
305 au_writel(wakeup, SYS_WAKEMSK);
312 spin_unlock_irqrestore(&pm_lock, flags);
316 #if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550)
319 * This is right out of init/main.c
323 * This is the number of bits of precision for the loops_per_jiffy.
324 * Each bit takes on average 1.5/HZ seconds. This (like the original)
325 * is a little better than 1%.
329 static void au1000_calibrate_delay(void)
331 unsigned long ticks, loopbit;
332 int lps_precision = LPS_PREC;
334 loops_per_jiffy = 1 << 12;
336 while (loops_per_jiffy <<= 1) {
337 /* Wait for "start of" clock tick */
339 while (ticks == jiffies)
343 __delay(loops_per_jiffy);
344 ticks = jiffies - ticks;
350 * Do a binary approximation to get loops_per_jiffy set to be equal
351 * one clock (up to lps_precision bits)
353 loops_per_jiffy >>= 1;
354 loopbit = loops_per_jiffy;
355 while (lps_precision-- && (loopbit >>= 1)) {
356 loops_per_jiffy |= loopbit;
358 while (ticks == jiffies);
360 __delay(loops_per_jiffy);
361 if (jiffies != ticks) /* longer than 1 tick */
362 loops_per_jiffy &= ~loopbit;
366 static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
367 void __user *buffer, size_t *len, loff_t *ppos)
370 unsigned long val, pll;
372 #define MAX_CPU_FREQ 396
373 char buf[TMPBUFLEN], *p;
374 unsigned long flags, intc0_mask, intc1_mask;
375 unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
376 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
377 unsigned long baud_rate;
379 spin_lock_irqsave(&pm_lock, flags);
383 /* Parse the new frequency */
384 if (*len > TMPBUFLEN - 1) {
385 spin_unlock_irqrestore(&pm_lock, flags);
388 if (copy_from_user(buf, buffer, *len)) {
389 spin_unlock_irqrestore(&pm_lock, flags);
394 val = simple_strtoul(p, &p, 0);
395 if (val > MAX_CPU_FREQ) {
396 spin_unlock_irqrestore(&pm_lock, flags);
401 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
402 /* Revisit this for higher speed CPUs */
403 spin_unlock_irqrestore(&pm_lock, flags);
407 old_baud_base = get_au1x00_uart_baud_base();
408 old_cpu_freq = get_au1x00_speed();
410 new_cpu_freq = pll * 12 * 1000000;
411 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
413 set_au1x00_speed(new_cpu_freq);
414 set_au1x00_uart_baud_base(new_baud_base);
416 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
417 new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
418 (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
420 au_writel(pll, SYS_CPUPLL);
422 au_writel(new_refresh, MEM_SDREFCFG);
425 for (i = 0; i < 4; i++)
426 if (au_readl(UART_BASE + UART_MOD_CNTRL +
427 i * 0x00100000) == 3) {
428 old_clk = au_readl(UART_BASE + UART_CLK +
430 baud_rate = old_baud_base / old_clk;
432 * We won't get an exact baud rate and the error
433 * could be significant enough that our new
434 * calculation will result in a clock that will
435 * give us a baud rate that's too far off from
436 * what we really want.
438 if (baud_rate > 100000)
440 else if (baud_rate > 50000)
442 else if (baud_rate > 30000)
444 else if (baud_rate > 17000)
448 new_clk = new_baud_base / baud_rate;
449 au_writel(new_clk, UART_BASE + UART_CLK +
456 * We don't want _any_ interrupts other than match20. Otherwise our
457 * au1000_calibrate_delay() calculation will be off, potentially a lot.
459 intc0_mask = save_local_and_disable(0);
460 intc1_mask = save_local_and_disable(1);
461 val = 1 << (AU1000_TOY_MATCH2_INT - AU1000_INTC0_INT_BASE);
462 au_writel(val, IC0_MASKSET); /* unmask */
463 au_writel(val, IC0_WAKESET); /* enable wake-from-sleep */
465 spin_unlock_irqrestore(&pm_lock, flags);
466 au1000_calibrate_delay();
467 restore_local_and_enable(0, intc0_mask);
468 restore_local_and_enable(1, intc1_mask);
474 static struct ctl_table pm_table[] = {
476 .ctl_name = CTL_UNNUMBERED,
481 .proc_handler = &pm_do_sleep
483 #if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550)
485 .ctl_name = CTL_UNNUMBERED,
490 .proc_handler = &pm_do_freq
496 static struct ctl_table pm_dir_table[] = {
498 .ctl_name = CTL_UNNUMBERED,
507 * Initialize power interface
509 static int __init pm_init(void)
511 /* init TOY to tick at 1Hz. No need to wait for access bits
512 * since there's plenty of time between here and the first
515 if (au_readl(SYS_TOYTRIM) != 32767) {
516 au_writel(32767, SYS_TOYTRIM);
520 register_sysctl_table(pm_dir_table);
526 #endif /* CONFIG_PM */