2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
4 * Maintained by: Jeremy Higdon @ SGI
5 * Please ALWAYS copy linux-ide@vger.kernel.org
10 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
28 * libata documentation is available via 'make {ps|pdf}docs',
29 * as Documentation/DocBook/libata.*
31 * Vitesse hardware documentation presumably available under NDA.
32 * Intel 31244 (same hardware interface) documentation presumably
33 * available from http://developer.intel.com/
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "sata_vsc"
50 #define DRV_VERSION "2.3"
55 /* Interrupt register offsets (from chip base address) */
56 VSC_SATA_INT_STAT_OFFSET = 0x00,
57 VSC_SATA_INT_MASK_OFFSET = 0x04,
59 /* Taskfile registers offsets */
60 VSC_SATA_TF_CMD_OFFSET = 0x00,
61 VSC_SATA_TF_DATA_OFFSET = 0x00,
62 VSC_SATA_TF_ERROR_OFFSET = 0x04,
63 VSC_SATA_TF_FEATURE_OFFSET = 0x06,
64 VSC_SATA_TF_NSECT_OFFSET = 0x08,
65 VSC_SATA_TF_LBAL_OFFSET = 0x0c,
66 VSC_SATA_TF_LBAM_OFFSET = 0x10,
67 VSC_SATA_TF_LBAH_OFFSET = 0x14,
68 VSC_SATA_TF_DEVICE_OFFSET = 0x18,
69 VSC_SATA_TF_STATUS_OFFSET = 0x1c,
70 VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
71 VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
72 VSC_SATA_TF_CTL_OFFSET = 0x29,
75 VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
76 VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
77 VSC_SATA_DMA_CMD_OFFSET = 0x70,
80 VSC_SATA_SCR_STATUS_OFFSET = 0x100,
81 VSC_SATA_SCR_ERROR_OFFSET = 0x104,
82 VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
85 VSC_SATA_PORT_OFFSET = 0x200,
87 /* Error interrupt status bit offsets */
88 VSC_SATA_INT_ERROR_CRC = 0x40,
89 VSC_SATA_INT_ERROR_T = 0x20,
90 VSC_SATA_INT_ERROR_P = 0x10,
91 VSC_SATA_INT_ERROR_R = 0x8,
92 VSC_SATA_INT_ERROR_E = 0x4,
93 VSC_SATA_INT_ERROR_M = 0x2,
94 VSC_SATA_INT_PHY_CHANGE = 0x1,
95 VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
96 VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
97 VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
98 VSC_SATA_INT_PHY_CHANGE),
101 static int vsc_sata_scr_read(struct ata_link *link,
102 unsigned int sc_reg, u32 *val)
104 if (sc_reg > SCR_CONTROL)
106 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
111 static int vsc_sata_scr_write(struct ata_link *link,
112 unsigned int sc_reg, u32 val)
114 if (sc_reg > SCR_CONTROL)
116 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
121 static void vsc_freeze(struct ata_port *ap)
123 void __iomem *mask_addr;
125 mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
126 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
128 writeb(0, mask_addr);
132 static void vsc_thaw(struct ata_port *ap)
134 void __iomem *mask_addr;
136 mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
137 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
139 writeb(0xff, mask_addr);
143 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
145 void __iomem *mask_addr;
148 mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
149 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
150 mask = readb(mask_addr);
155 writeb(mask, mask_addr);
159 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
161 struct ata_ioports *ioaddr = &ap->ioaddr;
162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
165 * The only thing the ctl register is used for is SRST.
166 * That is not enabled or disabled via tf_load.
167 * However, if ATA_NIEN is changed, then we need to change
168 * the interrupt register.
170 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
171 ap->last_ctl = tf->ctl;
172 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
174 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
175 writew(tf->feature | (((u16)tf->hob_feature) << 8),
176 ioaddr->feature_addr);
177 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
179 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
181 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
183 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
185 } else if (is_addr) {
186 writew(tf->feature, ioaddr->feature_addr);
187 writew(tf->nsect, ioaddr->nsect_addr);
188 writew(tf->lbal, ioaddr->lbal_addr);
189 writew(tf->lbam, ioaddr->lbam_addr);
190 writew(tf->lbah, ioaddr->lbah_addr);
193 if (tf->flags & ATA_TFLAG_DEVICE)
194 writeb(tf->device, ioaddr->device_addr);
200 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
202 struct ata_ioports *ioaddr = &ap->ioaddr;
203 u16 nsect, lbal, lbam, lbah, feature;
205 tf->command = ata_sff_check_status(ap);
206 tf->device = readw(ioaddr->device_addr);
207 feature = readw(ioaddr->error_addr);
208 nsect = readw(ioaddr->nsect_addr);
209 lbal = readw(ioaddr->lbal_addr);
210 lbam = readw(ioaddr->lbam_addr);
211 lbah = readw(ioaddr->lbah_addr);
213 tf->feature = feature;
219 if (tf->flags & ATA_TFLAG_LBA48) {
220 tf->hob_feature = feature >> 8;
221 tf->hob_nsect = nsect >> 8;
222 tf->hob_lbal = lbal >> 8;
223 tf->hob_lbam = lbam >> 8;
224 tf->hob_lbah = lbah >> 8;
228 static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
230 if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
236 static void vsc_port_intr(u8 port_status, struct ata_port *ap)
238 struct ata_queued_cmd *qc;
241 if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
242 vsc_error_intr(port_status, ap);
246 qc = ata_qc_from_tag(ap, ap->link.active_tag);
247 if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
248 handled = ata_sff_host_intr(ap, qc);
250 /* We received an interrupt during a polled command,
251 * or some other spurious condition. Interrupt reporting
252 * with this hardware is fairly reliable so it is safe to
253 * simply clear the interrupt
255 if (unlikely(!handled))
256 ap->ops->sff_check_status(ap);
262 * Read the interrupt register and process for the devices that have
265 static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
267 struct ata_host *host = dev_instance;
269 unsigned int handled = 0;
272 status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
274 if (unlikely(status == 0xffffffff || status == 0)) {
276 dev_printk(KERN_ERR, host->dev,
277 ": IRQ status == 0xffffffff, "
278 "PCI fault or device removal?\n");
282 spin_lock(&host->lock);
284 for (i = 0; i < host->n_ports; i++) {
285 u8 port_status = (status >> (8 * i)) & 0xff;
287 struct ata_port *ap = host->ports[i];
289 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
290 vsc_port_intr(port_status, ap);
293 dev_printk(KERN_ERR, host->dev,
294 "interrupt from disabled port %d\n", i);
298 spin_unlock(&host->lock);
300 return IRQ_RETVAL(handled);
304 static struct scsi_host_template vsc_sata_sht = {
305 ATA_BMDMA_SHT(DRV_NAME),
309 static struct ata_port_operations vsc_sata_ops = {
310 .inherits = &ata_bmdma_port_ops,
311 /* The IRQ handling is not quite standard SFF behaviour so we
312 cannot use the default lost interrupt handler */
313 .lost_interrupt = ATA_OP_NULL,
314 .sff_tf_load = vsc_sata_tf_load,
315 .sff_tf_read = vsc_sata_tf_read,
316 .freeze = vsc_freeze,
318 .scr_read = vsc_sata_scr_read,
319 .scr_write = vsc_sata_scr_write,
322 static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
325 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
326 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
327 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
328 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
329 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
330 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
331 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
332 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
333 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
334 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
335 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
336 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
337 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
338 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
339 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
340 writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
341 writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
345 static int __devinit vsc_sata_init_one(struct pci_dev *pdev,
346 const struct pci_device_id *ent)
348 static const struct ata_port_info pi = {
349 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
351 .pio_mask = ATA_PIO4,
352 .mwdma_mask = ATA_MWDMA2,
353 .udma_mask = ATA_UDMA6,
354 .port_ops = &vsc_sata_ops,
356 const struct ata_port_info *ppi[] = { &pi, NULL };
357 static int printed_version;
358 struct ata_host *host;
359 void __iomem *mmio_base;
363 if (!printed_version++)
364 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
367 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
371 rc = pcim_enable_device(pdev);
375 /* check if we have needed resource mapped */
376 if (pci_resource_len(pdev, 0) == 0)
379 /* map IO regions and intialize host accordingly */
380 rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
382 pcim_pin_device(pdev);
385 host->iomap = pcim_iomap_table(pdev);
387 mmio_base = host->iomap[VSC_MMIO_BAR];
389 for (i = 0; i < host->n_ports; i++) {
390 struct ata_port *ap = host->ports[i];
391 unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
393 vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
395 ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
396 ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
400 * Use 32 bit DMA mask, because 64 bit address support is poor.
402 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
405 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
410 * Due to a bug in the chip, the default cache line size can't be
411 * used (unless the default is non-zero).
413 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
415 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
417 if (pci_enable_msi(pdev) == 0)
421 * Config offset 0x98 is "Extended Control and Status Register 0"
422 * Default value is (1 << 28). All bits except bit 28 are reserved in
423 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
424 * If bit 28 is clear, each port has its own LED.
426 pci_write_config_dword(pdev, 0x98, 0);
428 pci_set_master(pdev);
429 return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
430 IRQF_SHARED, &vsc_sata_sht);
433 static const struct pci_device_id vsc_sata_pci_tbl[] = {
434 { PCI_VENDOR_ID_VITESSE, 0x7174,
435 PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
436 { PCI_VENDOR_ID_INTEL, 0x3200,
437 PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
439 { } /* terminate list */
442 static struct pci_driver vsc_sata_pci_driver = {
444 .id_table = vsc_sata_pci_tbl,
445 .probe = vsc_sata_init_one,
446 .remove = ata_pci_remove_one,
449 static int __init vsc_sata_init(void)
451 return pci_register_driver(&vsc_sata_pci_driver);
454 static void __exit vsc_sata_exit(void)
456 pci_unregister_driver(&vsc_sata_pci_driver);
459 MODULE_AUTHOR("Jeremy Higdon");
460 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
461 MODULE_LICENSE("GPL");
462 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
463 MODULE_VERSION(DRV_VERSION);
465 module_init(vsc_sata_init);
466 module_exit(vsc_sata_exit);