2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug = -1;
72 static DEFINE_SPINLOCK(ioapic_lock);
73 static DEFINE_SPINLOCK(vector_lock);
76 * # of IRQ routing registers
78 int nr_ioapic_registers[MAX_IO_APICS];
80 /* I/O APIC entries */
81 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
84 /* MP IRQ source entries */
85 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
87 /* # of MP IRQ source entries */
90 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
91 int mp_bus_id_to_type[MAX_MP_BUSSES];
94 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
96 int skip_ioapic_setup;
98 static int __init parse_noapic(char *str)
100 /* disable IO-APIC */
101 disable_ioapic_setup();
104 early_param("noapic", parse_noapic);
110 #ifdef CONFIG_HAVE_SPARSE_IRQ
111 struct irq_cfg *next;
113 struct irq_pin_list *irq_2_pin;
115 cpumask_t old_domain;
116 unsigned move_cleanup_count;
118 u8 move_in_progress : 1;
121 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
122 static struct irq_cfg irq_cfg_legacy[] __initdata = {
123 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
124 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
125 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
126 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
127 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
128 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
129 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
130 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
131 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
132 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
133 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
134 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
135 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
136 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
137 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
138 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
141 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
143 static void init_one_irq_cfg(struct irq_cfg *cfg)
145 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
148 static struct irq_cfg *irq_cfgx;
150 #ifdef CONFIG_HAVE_SPARSE_IRQ
152 * Protect the irq_cfgx_free freelist:
154 static DEFINE_SPINLOCK(irq_cfg_lock);
156 static struct irq_cfg *irq_cfgx_free;
159 static void __init init_work(void *data)
161 struct dyn_array *da = data;
168 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
170 legacy_count = ARRAY_SIZE(irq_cfg_legacy);
171 for (i = legacy_count; i < *da->nr; i++)
172 init_one_irq_cfg(&cfg[i]);
174 #ifdef CONFIG_HAVE_SPARSE_IRQ
175 for (i = 1; i < *da->nr; i++)
176 cfg[i-1].next = &cfg[i];
178 irq_cfgx_free = &irq_cfgx[legacy_count];
179 irq_cfgx[legacy_count - 1].next = NULL;
183 #ifdef CONFIG_HAVE_SPARSE_IRQ
184 /* need to be biger than size of irq_cfg_legacy */
185 static int nr_irq_cfg = 32;
187 static int __init parse_nr_irq_cfg(char *arg)
190 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
197 early_param("nr_irq_cfg", parse_nr_irq_cfg);
199 #define for_each_irq_cfg(irqX, cfg) \
200 for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
203 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
205 static struct irq_cfg *irq_cfg(unsigned int irq)
220 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
222 struct irq_cfg *cfg, *cfg_pri;
227 cfg_pri = cfg = irq_cfgx;
237 spin_lock_irqsave(&irq_cfg_lock, flags);
238 if (!irq_cfgx_free) {
240 unsigned long total_bytes;
242 * we run out of pre-allocate ones, allocate more
244 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
246 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
248 cfg = kzalloc(total_bytes, GFP_ATOMIC);
250 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
253 panic("please boot with nr_irq_cfg= %d\n", count * 2);
256 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
258 for (i = 0; i < nr_irq_cfg; i++)
259 init_one_irq_cfg(&cfg[i]);
261 for (i = 1; i < nr_irq_cfg; i++)
262 cfg[i-1].next = &cfg[i];
268 irq_cfgx_free = irq_cfgx_free->next;
276 spin_unlock_irqrestore(&irq_cfg_lock, flags);
278 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
279 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
281 /* dump the results */
284 unsigned long bytes = sizeof(struct irq_cfg);
286 printk(KERN_DEBUG "=========================== %d\n", irq);
287 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
288 for_each_irq_cfg(cfg) {
290 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
292 printk(KERN_DEBUG "===========================\n");
299 #define for_each_irq_cfg(irq, cfg) \
300 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
302 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
304 struct irq_cfg *irq_cfg(unsigned int irq)
307 return &irq_cfgx[irq];
311 struct irq_cfg *irq_cfg_alloc(unsigned int irq)
318 * This is performance-critical, we want to do it O(1)
320 * the indexing order of this array favors 1:1 mappings
321 * between pins and IRQs.
324 struct irq_pin_list {
326 struct irq_pin_list *next;
329 static struct irq_pin_list *irq_2_pin_head;
330 /* fill one page ? */
331 static int nr_irq_2_pin = 0x100;
332 static struct irq_pin_list *irq_2_pin_ptr;
333 static void __init irq_2_pin_init_work(void *data)
335 struct dyn_array *da = data;
336 struct irq_pin_list *pin;
341 for (i = 1; i < *da->nr; i++)
342 pin[i-1].next = &pin[i];
344 irq_2_pin_ptr = &pin[0];
346 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
348 static struct irq_pin_list *get_one_free_irq_2_pin(void)
350 struct irq_pin_list *pin;
356 irq_2_pin_ptr = pin->next;
362 * we run out of pre-allocate ones, allocate more
364 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
367 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
370 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
371 nr_irq_2_pin, PAGE_SIZE, 0);
374 panic("can not get more irq_2_pin\n");
376 for (i = 1; i < nr_irq_2_pin; i++)
377 pin[i-1].next = &pin[i];
379 irq_2_pin_ptr = pin->next;
387 unsigned int unused[3];
391 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
393 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
394 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
397 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
399 struct io_apic __iomem *io_apic = io_apic_base(apic);
400 writel(reg, &io_apic->index);
401 return readl(&io_apic->data);
404 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
406 struct io_apic __iomem *io_apic = io_apic_base(apic);
407 writel(reg, &io_apic->index);
408 writel(value, &io_apic->data);
412 * Re-write a value: to be used for read-modify-write
413 * cycles where the read already set up the index register.
415 * Older SiS APIC requires we rewrite the index register
417 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
419 struct io_apic __iomem *io_apic = io_apic_base(apic);
421 writel(reg, &io_apic->index);
422 writel(value, &io_apic->data);
425 static bool io_apic_level_ack_pending(unsigned int irq)
427 struct irq_pin_list *entry;
429 struct irq_cfg *cfg = irq_cfg(irq);
431 spin_lock_irqsave(&ioapic_lock, flags);
432 entry = cfg->irq_2_pin;
440 reg = io_apic_read(entry->apic, 0x10 + pin*2);
441 /* Is the remote IRR bit set? */
442 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
443 spin_unlock_irqrestore(&ioapic_lock, flags);
450 spin_unlock_irqrestore(&ioapic_lock, flags);
456 struct { u32 w1, w2; };
457 struct IO_APIC_route_entry entry;
460 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
462 union entry_union eu;
464 spin_lock_irqsave(&ioapic_lock, flags);
465 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
466 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
467 spin_unlock_irqrestore(&ioapic_lock, flags);
472 * When we write a new IO APIC routing entry, we need to write the high
473 * word first! If the mask bit in the low word is clear, we will enable
474 * the interrupt, and we need to make sure the entry is fully populated
475 * before that happens.
478 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
480 union entry_union eu;
482 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
483 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
486 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
489 spin_lock_irqsave(&ioapic_lock, flags);
490 __ioapic_write_entry(apic, pin, e);
491 spin_unlock_irqrestore(&ioapic_lock, flags);
495 * When we mask an IO APIC routing entry, we need to write the low
496 * word first, in order to set the mask bit before we change the
499 static void ioapic_mask_entry(int apic, int pin)
502 union entry_union eu = { .entry.mask = 1 };
504 spin_lock_irqsave(&ioapic_lock, flags);
505 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
506 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
507 spin_unlock_irqrestore(&ioapic_lock, flags);
511 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
515 struct irq_pin_list *entry;
518 entry = cfg->irq_2_pin;
527 #ifdef CONFIG_INTR_REMAP
529 * With interrupt-remapping, destination information comes
530 * from interrupt-remapping table entry.
532 if (!irq_remapped(irq))
533 io_apic_write(apic, 0x11 + pin*2, dest);
535 io_apic_write(apic, 0x11 + pin*2, dest);
537 reg = io_apic_read(apic, 0x10 + pin*2);
538 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
540 io_apic_modify(apic, 0x10 + pin*2, reg);
547 static int assign_irq_vector(int irq, cpumask_t mask);
549 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
555 struct irq_desc *desc;
557 cpus_and(tmp, mask, cpu_online_map);
562 if (assign_irq_vector(irq, mask))
565 cpus_and(tmp, cfg->domain, mask);
566 dest = cpu_mask_to_apicid(tmp);
568 * Only the high 8 bits are valid.
570 dest = SET_APIC_LOGICAL_ID(dest);
572 desc = irq_to_desc(irq);
573 spin_lock_irqsave(&ioapic_lock, flags);
574 __target_IO_APIC_irq(irq, dest, cfg->vector);
575 desc->affinity = mask;
576 spin_unlock_irqrestore(&ioapic_lock, flags);
578 #endif /* CONFIG_SMP */
581 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
582 * shared ISA-space IRQs, so we have to support them. We are super
583 * fast in the common case, and fast for shared ISA-space IRQs.
585 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
588 struct irq_pin_list *entry;
590 /* first time to refer irq_cfg, so with new */
591 cfg = irq_cfg_alloc(irq);
592 entry = cfg->irq_2_pin;
594 entry = get_one_free_irq_2_pin();
595 cfg->irq_2_pin = entry;
598 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
602 while (entry->next) {
603 /* not again, please */
604 if (entry->apic == apic && entry->pin == pin)
610 entry->next = get_one_free_irq_2_pin();
614 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
618 * Reroute an IRQ to a different pin.
620 static void __init replace_pin_at_irq(unsigned int irq,
621 int oldapic, int oldpin,
622 int newapic, int newpin)
624 struct irq_cfg *cfg = irq_cfg(irq);
625 struct irq_pin_list *entry = cfg->irq_2_pin;
629 if (entry->apic == oldapic && entry->pin == oldpin) {
630 entry->apic = newapic;
633 /* every one is different, right? */
639 /* why? call replace before add? */
641 add_pin_to_irq(irq, newapic, newpin);
644 #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
648 struct irq_cfg *cfg; \
649 struct irq_pin_list *entry; \
651 cfg = irq_cfg(irq); \
652 entry = cfg->irq_2_pin; \
658 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
659 reg ACTION_DISABLE; \
661 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
665 entry = entry->next; \
669 #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
671 static void name##_IO_APIC_irq (unsigned int irq) \
672 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
675 DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, )
679 * Synchronize the IO-APIC and the CPU by doing
680 * a dummy read from the IO-APIC
682 static inline void io_apic_sync(unsigned int apic)
684 struct io_apic __iomem *io_apic = io_apic_base(apic);
685 readl(&io_apic->data);
689 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic))
694 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, )
696 /* mask = 1, trigger = 0 */
697 DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, )
699 /* mask = 0, trigger = 1 */
700 DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, )
704 static void mask_IO_APIC_irq (unsigned int irq)
708 spin_lock_irqsave(&ioapic_lock, flags);
709 __mask_IO_APIC_irq(irq);
710 spin_unlock_irqrestore(&ioapic_lock, flags);
713 static void unmask_IO_APIC_irq (unsigned int irq)
717 spin_lock_irqsave(&ioapic_lock, flags);
718 __unmask_IO_APIC_irq(irq);
719 spin_unlock_irqrestore(&ioapic_lock, flags);
722 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
724 struct IO_APIC_route_entry entry;
726 /* Check delivery_mode to be sure we're not clearing an SMI pin */
727 entry = ioapic_read_entry(apic, pin);
728 if (entry.delivery_mode == dest_SMI)
731 * Disable it in the IO-APIC irq-routing table:
733 ioapic_mask_entry(apic, pin);
736 static void clear_IO_APIC (void)
740 for (apic = 0; apic < nr_ioapics; apic++)
741 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
742 clear_IO_APIC_pin(apic, pin);
745 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
746 void send_IPI_self(int vector)
753 apic_wait_icr_idle();
754 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
756 * Send the IPI. The write to APIC_ICR fires this off.
758 apic_write(APIC_ICR, cfg);
760 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
764 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
765 * specific CPU-side IRQs.
769 static int pirq_entries [MAX_PIRQS];
770 static int pirqs_enabled;
772 static int __init ioapic_pirq_setup(char *str)
775 int ints[MAX_PIRQS+1];
777 get_options(str, ARRAY_SIZE(ints), ints);
779 for (i = 0; i < MAX_PIRQS; i++)
780 pirq_entries[i] = -1;
783 apic_printk(APIC_VERBOSE, KERN_INFO
784 "PIRQ redirection, working around broken MP-BIOS.\n");
786 if (ints[0] < MAX_PIRQS)
789 for (i = 0; i < max; i++) {
790 apic_printk(APIC_VERBOSE, KERN_DEBUG
791 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
793 * PIRQs are mapped upside down, usually.
795 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
800 __setup("pirq=", ioapic_pirq_setup);
801 #endif /* CONFIG_X86_32 */
803 #ifdef CONFIG_INTR_REMAP
804 /* I/O APIC RTE contents at the OS boot up */
805 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
808 * Saves and masks all the unmasked IO-APIC RTE's
810 int save_mask_IO_APIC_setup(void)
812 union IO_APIC_reg_01 reg_01;
817 * The number of IO-APIC IRQ registers (== #pins):
819 for (apic = 0; apic < nr_ioapics; apic++) {
820 spin_lock_irqsave(&ioapic_lock, flags);
821 reg_01.raw = io_apic_read(apic, 1);
822 spin_unlock_irqrestore(&ioapic_lock, flags);
823 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
826 for (apic = 0; apic < nr_ioapics; apic++) {
827 early_ioapic_entries[apic] =
828 kzalloc(sizeof(struct IO_APIC_route_entry) *
829 nr_ioapic_registers[apic], GFP_KERNEL);
830 if (!early_ioapic_entries[apic])
834 for (apic = 0; apic < nr_ioapics; apic++)
835 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
836 struct IO_APIC_route_entry entry;
838 entry = early_ioapic_entries[apic][pin] =
839 ioapic_read_entry(apic, pin);
842 ioapic_write_entry(apic, pin, entry);
848 void restore_IO_APIC_setup(void)
852 for (apic = 0; apic < nr_ioapics; apic++)
853 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
854 ioapic_write_entry(apic, pin,
855 early_ioapic_entries[apic][pin]);
858 void reinit_intr_remapped_IO_APIC(int intr_remapping)
861 * for now plain restore of previous settings.
862 * TBD: In the case of OS enabling interrupt-remapping,
863 * IO-APIC RTE's need to be setup to point to interrupt-remapping
864 * table entries. for now, do a plain restore, and wait for
865 * the setup_IO_APIC_irqs() to do proper initialization.
867 restore_IO_APIC_setup();
872 * Find the IRQ entry number of a certain pin.
874 static int find_irq_entry(int apic, int pin, int type)
878 for (i = 0; i < mp_irq_entries; i++)
879 if (mp_irqs[i].mp_irqtype == type &&
880 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
881 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
882 mp_irqs[i].mp_dstirq == pin)
889 * Find the pin to which IRQ[irq] (ISA) is connected
891 static int __init find_isa_irq_pin(int irq, int type)
895 for (i = 0; i < mp_irq_entries; i++) {
896 int lbus = mp_irqs[i].mp_srcbus;
898 if (test_bit(lbus, mp_bus_not_pci) &&
899 (mp_irqs[i].mp_irqtype == type) &&
900 (mp_irqs[i].mp_srcbusirq == irq))
902 return mp_irqs[i].mp_dstirq;
907 static int __init find_isa_irq_apic(int irq, int type)
911 for (i = 0; i < mp_irq_entries; i++) {
912 int lbus = mp_irqs[i].mp_srcbus;
914 if (test_bit(lbus, mp_bus_not_pci) &&
915 (mp_irqs[i].mp_irqtype == type) &&
916 (mp_irqs[i].mp_srcbusirq == irq))
919 if (i < mp_irq_entries) {
921 for(apic = 0; apic < nr_ioapics; apic++) {
922 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
931 * Find a specific PCI IRQ entry.
932 * Not an __init, possibly needed by modules
934 static int pin_2_irq(int idx, int apic, int pin);
936 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
938 int apic, i, best_guess = -1;
940 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
942 if (test_bit(bus, mp_bus_not_pci)) {
943 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
946 for (i = 0; i < mp_irq_entries; i++) {
947 int lbus = mp_irqs[i].mp_srcbus;
949 for (apic = 0; apic < nr_ioapics; apic++)
950 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
951 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
954 if (!test_bit(lbus, mp_bus_not_pci) &&
955 !mp_irqs[i].mp_irqtype &&
957 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
958 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
960 if (!(apic || IO_APIC_IRQ(irq)))
963 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
966 * Use the first all-but-pin matching entry as a
967 * best-guess fuzzy result for broken mptables.
976 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
978 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
980 * EISA Edge/Level control register, ELCR
982 static int EISA_ELCR(unsigned int irq)
985 unsigned int port = 0x4d0 + (irq >> 3);
986 return (inb(port) >> (irq & 7)) & 1;
988 apic_printk(APIC_VERBOSE, KERN_INFO
989 "Broken MPtable reports ISA irq %d\n", irq);
995 /* ISA interrupts are always polarity zero edge triggered,
996 * when listed as conforming in the MP table. */
998 #define default_ISA_trigger(idx) (0)
999 #define default_ISA_polarity(idx) (0)
1001 /* EISA interrupts are always polarity zero and can be edge or level
1002 * trigger depending on the ELCR value. If an interrupt is listed as
1003 * EISA conforming in the MP table, that means its trigger type must
1004 * be read in from the ELCR */
1006 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1007 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1009 /* PCI interrupts are always polarity one level triggered,
1010 * when listed as conforming in the MP table. */
1012 #define default_PCI_trigger(idx) (1)
1013 #define default_PCI_polarity(idx) (1)
1015 /* MCA interrupts are always polarity zero level triggered,
1016 * when listed as conforming in the MP table. */
1018 #define default_MCA_trigger(idx) (1)
1019 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1021 static int MPBIOS_polarity(int idx)
1023 int bus = mp_irqs[idx].mp_srcbus;
1027 * Determine IRQ line polarity (high active or low active):
1029 switch (mp_irqs[idx].mp_irqflag & 3)
1031 case 0: /* conforms, ie. bus-type dependent polarity */
1032 if (test_bit(bus, mp_bus_not_pci))
1033 polarity = default_ISA_polarity(idx);
1035 polarity = default_PCI_polarity(idx);
1037 case 1: /* high active */
1042 case 2: /* reserved */
1044 printk(KERN_WARNING "broken BIOS!!\n");
1048 case 3: /* low active */
1053 default: /* invalid */
1055 printk(KERN_WARNING "broken BIOS!!\n");
1063 static int MPBIOS_trigger(int idx)
1065 int bus = mp_irqs[idx].mp_srcbus;
1069 * Determine IRQ trigger mode (edge or level sensitive):
1071 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1073 case 0: /* conforms, ie. bus-type dependent */
1074 if (test_bit(bus, mp_bus_not_pci))
1075 trigger = default_ISA_trigger(idx);
1077 trigger = default_PCI_trigger(idx);
1078 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1079 switch (mp_bus_id_to_type[bus]) {
1080 case MP_BUS_ISA: /* ISA pin */
1082 /* set before the switch */
1085 case MP_BUS_EISA: /* EISA pin */
1087 trigger = default_EISA_trigger(idx);
1090 case MP_BUS_PCI: /* PCI pin */
1092 /* set before the switch */
1095 case MP_BUS_MCA: /* MCA pin */
1097 trigger = default_MCA_trigger(idx);
1102 printk(KERN_WARNING "broken BIOS!!\n");
1114 case 2: /* reserved */
1116 printk(KERN_WARNING "broken BIOS!!\n");
1125 default: /* invalid */
1127 printk(KERN_WARNING "broken BIOS!!\n");
1135 static inline int irq_polarity(int idx)
1137 return MPBIOS_polarity(idx);
1140 static inline int irq_trigger(int idx)
1142 return MPBIOS_trigger(idx);
1145 int (*ioapic_renumber_irq)(int ioapic, int irq);
1146 static int pin_2_irq(int idx, int apic, int pin)
1149 int bus = mp_irqs[idx].mp_srcbus;
1152 * Debugging check, we are in big trouble if this message pops up!
1154 if (mp_irqs[idx].mp_dstirq != pin)
1155 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1157 if (test_bit(bus, mp_bus_not_pci)) {
1158 irq = mp_irqs[idx].mp_srcbusirq;
1161 * PCI IRQs are mapped in order
1165 irq += nr_ioapic_registers[i++];
1168 * For MPS mode, so far only needed by ES7000 platform
1170 if (ioapic_renumber_irq)
1171 irq = ioapic_renumber_irq(apic, irq);
1174 #ifdef CONFIG_X86_32
1176 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1178 if ((pin >= 16) && (pin <= 23)) {
1179 if (pirq_entries[pin-16] != -1) {
1180 if (!pirq_entries[pin-16]) {
1181 apic_printk(APIC_VERBOSE, KERN_DEBUG
1182 "disabling PIRQ%d\n", pin-16);
1184 irq = pirq_entries[pin-16];
1185 apic_printk(APIC_VERBOSE, KERN_DEBUG
1186 "using PIRQ%d -> IRQ %d\n",
1196 void lock_vector_lock(void)
1198 /* Used to the online set of cpus does not change
1199 * during assign_irq_vector.
1201 spin_lock(&vector_lock);
1204 void unlock_vector_lock(void)
1206 spin_unlock(&vector_lock);
1209 static int __assign_irq_vector(int irq, cpumask_t mask)
1212 * NOTE! The local APIC isn't very good at handling
1213 * multiple interrupts at the same interrupt level.
1214 * As the interrupt level is determined by taking the
1215 * vector number and shifting that right by 4, we
1216 * want to spread these out a bit so that they don't
1217 * all fall in the same interrupt level.
1219 * Also, we've got to be careful not to trash gate
1220 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1222 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1223 unsigned int old_vector;
1225 struct irq_cfg *cfg;
1229 /* Only try and allocate irqs on cpus that are present */
1230 cpus_and(mask, mask, cpu_online_map);
1232 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1235 old_vector = cfg->vector;
1238 cpus_and(tmp, cfg->domain, mask);
1239 if (!cpus_empty(tmp))
1243 for_each_cpu_mask_nr(cpu, mask) {
1244 cpumask_t domain, new_mask;
1248 domain = vector_allocation_domain(cpu);
1249 cpus_and(new_mask, domain, cpu_online_map);
1251 vector = current_vector;
1252 offset = current_offset;
1255 if (vector >= first_system_vector) {
1256 /* If we run out of vectors on large boxen, must share them. */
1257 offset = (offset + 1) % 8;
1258 vector = FIRST_DEVICE_VECTOR + offset;
1260 if (unlikely(current_vector == vector))
1262 #ifdef CONFIG_X86_64
1263 if (vector == IA32_SYSCALL_VECTOR)
1266 if (vector == SYSCALL_VECTOR)
1269 for_each_cpu_mask_nr(new_cpu, new_mask)
1270 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1273 current_vector = vector;
1274 current_offset = offset;
1276 cfg->move_in_progress = 1;
1277 cfg->old_domain = cfg->domain;
1279 for_each_cpu_mask_nr(new_cpu, new_mask)
1280 per_cpu(vector_irq, new_cpu)[vector] = irq;
1281 cfg->vector = vector;
1282 cfg->domain = domain;
1288 static int assign_irq_vector(int irq, cpumask_t mask)
1291 unsigned long flags;
1293 spin_lock_irqsave(&vector_lock, flags);
1294 err = __assign_irq_vector(irq, mask);
1295 spin_unlock_irqrestore(&vector_lock, flags);
1299 static void __clear_irq_vector(int irq)
1301 struct irq_cfg *cfg;
1306 BUG_ON(!cfg->vector);
1308 vector = cfg->vector;
1309 cpus_and(mask, cfg->domain, cpu_online_map);
1310 for_each_cpu_mask_nr(cpu, mask)
1311 per_cpu(vector_irq, cpu)[vector] = -1;
1314 cpus_clear(cfg->domain);
1317 void __setup_vector_irq(int cpu)
1319 /* Initialize vector_irq on a new cpu */
1320 /* This function must be called with vector_lock held */
1322 struct irq_cfg *cfg;
1324 /* Mark the inuse vectors */
1325 for_each_irq_cfg(irq, cfg) {
1326 if (!cpu_isset(cpu, cfg->domain))
1328 vector = cfg->vector;
1329 per_cpu(vector_irq, cpu)[vector] = irq;
1331 /* Mark the free vectors */
1332 for (vector = 0; vector < NR_VECTORS; ++vector) {
1333 irq = per_cpu(vector_irq, cpu)[vector];
1338 if (!cpu_isset(cpu, cfg->domain))
1339 per_cpu(vector_irq, cpu)[vector] = -1;
1343 static struct irq_chip ioapic_chip;
1344 #ifdef CONFIG_INTR_REMAP
1345 static struct irq_chip ir_ioapic_chip;
1348 #define IOAPIC_AUTO -1
1349 #define IOAPIC_EDGE 0
1350 #define IOAPIC_LEVEL 1
1352 #ifdef CONFIG_X86_32
1353 static inline int IO_APIC_irq_trigger(int irq)
1357 for (apic = 0; apic < nr_ioapics; apic++) {
1358 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1359 idx = find_irq_entry(apic, pin, mp_INT);
1360 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1361 return irq_trigger(idx);
1365 * nonexistent IRQs are edge default
1370 static inline int IO_APIC_irq_trigger(int irq)
1376 static void ioapic_register_intr(int irq, unsigned long trigger)
1378 struct irq_desc *desc;
1380 /* first time to use this irq_desc */
1382 desc = irq_to_desc(irq);
1384 desc = irq_to_desc_alloc(irq);
1386 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1387 trigger == IOAPIC_LEVEL)
1388 desc->status |= IRQ_LEVEL;
1390 desc->status &= ~IRQ_LEVEL;
1392 #ifdef CONFIG_INTR_REMAP
1393 if (irq_remapped(irq)) {
1394 desc->status |= IRQ_MOVE_PCNTXT;
1396 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1400 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1401 handle_edge_irq, "edge");
1405 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1406 trigger == IOAPIC_LEVEL)
1407 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1411 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1412 handle_edge_irq, "edge");
1415 static int setup_ioapic_entry(int apic, int irq,
1416 struct IO_APIC_route_entry *entry,
1417 unsigned int destination, int trigger,
1418 int polarity, int vector)
1421 * add it to the IO-APIC irq-routing table:
1423 memset(entry,0,sizeof(*entry));
1425 #ifdef CONFIG_INTR_REMAP
1426 if (intr_remapping_enabled) {
1427 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1429 struct IR_IO_APIC_route_entry *ir_entry =
1430 (struct IR_IO_APIC_route_entry *) entry;
1434 panic("No mapping iommu for ioapic %d\n", apic);
1436 index = alloc_irte(iommu, irq, 1);
1438 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1440 memset(&irte, 0, sizeof(irte));
1443 irte.dst_mode = INT_DEST_MODE;
1444 irte.trigger_mode = trigger;
1445 irte.dlvry_mode = INT_DELIVERY_MODE;
1446 irte.vector = vector;
1447 irte.dest_id = IRTE_DEST(destination);
1449 modify_irte(irq, &irte);
1451 ir_entry->index2 = (index >> 15) & 0x1;
1453 ir_entry->format = 1;
1454 ir_entry->index = (index & 0x7fff);
1458 entry->delivery_mode = INT_DELIVERY_MODE;
1459 entry->dest_mode = INT_DEST_MODE;
1460 entry->dest = destination;
1463 entry->mask = 0; /* enable IRQ */
1464 entry->trigger = trigger;
1465 entry->polarity = polarity;
1466 entry->vector = vector;
1468 /* Mask level triggered irqs.
1469 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1476 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1477 int trigger, int polarity)
1479 struct irq_cfg *cfg;
1480 struct IO_APIC_route_entry entry;
1483 if (!IO_APIC_IRQ(irq))
1489 if (assign_irq_vector(irq, mask))
1492 cpus_and(mask, cfg->domain, mask);
1494 apic_printk(APIC_VERBOSE,KERN_DEBUG
1495 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1496 "IRQ %d Mode:%i Active:%i)\n",
1497 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1498 irq, trigger, polarity);
1501 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1502 cpu_mask_to_apicid(mask), trigger, polarity,
1504 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1505 mp_ioapics[apic].mp_apicid, pin);
1506 __clear_irq_vector(irq);
1510 ioapic_register_intr(irq, trigger);
1512 disable_8259A_irq(irq);
1514 ioapic_write_entry(apic, pin, entry);
1517 static void __init setup_IO_APIC_irqs(void)
1519 int apic, pin, idx, irq, first_notcon = 1;
1521 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1523 for (apic = 0; apic < nr_ioapics; apic++) {
1524 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1526 idx = find_irq_entry(apic,pin,mp_INT);
1529 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1532 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1535 if (!first_notcon) {
1536 apic_printk(APIC_VERBOSE, " not connected.\n");
1540 irq = pin_2_irq(idx, apic, pin);
1541 #ifdef CONFIG_X86_32
1542 if (multi_timer_check(apic, irq))
1545 add_pin_to_irq(irq, apic, pin);
1547 setup_IO_APIC_irq(apic, pin, irq,
1548 irq_trigger(idx), irq_polarity(idx));
1553 apic_printk(APIC_VERBOSE, " not connected.\n");
1557 * Set up the timer pin, possibly with the 8259A-master behind.
1559 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1562 struct IO_APIC_route_entry entry;
1564 #ifdef CONFIG_INTR_REMAP
1565 if (intr_remapping_enabled)
1569 memset(&entry, 0, sizeof(entry));
1572 * We use logical delivery to get the timer IRQ
1575 entry.dest_mode = INT_DEST_MODE;
1576 entry.mask = 1; /* mask IRQ now */
1577 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1578 entry.delivery_mode = INT_DELIVERY_MODE;
1581 entry.vector = vector;
1584 * The timer IRQ doesn't have to know that behind the
1585 * scene we may have a 8259A-master in AEOI mode ...
1587 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1590 * Add it to the IO-APIC irq-routing table:
1592 ioapic_write_entry(apic, pin, entry);
1596 __apicdebuginit(void) print_IO_APIC(void)
1599 union IO_APIC_reg_00 reg_00;
1600 union IO_APIC_reg_01 reg_01;
1601 union IO_APIC_reg_02 reg_02;
1602 union IO_APIC_reg_03 reg_03;
1603 unsigned long flags;
1604 struct irq_cfg *cfg;
1607 if (apic_verbosity == APIC_QUIET)
1610 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1611 for (i = 0; i < nr_ioapics; i++)
1612 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1613 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1616 * We are a bit conservative about what we expect. We have to
1617 * know about every hardware change ASAP.
1619 printk(KERN_INFO "testing the IO APIC.......................\n");
1621 for (apic = 0; apic < nr_ioapics; apic++) {
1623 spin_lock_irqsave(&ioapic_lock, flags);
1624 reg_00.raw = io_apic_read(apic, 0);
1625 reg_01.raw = io_apic_read(apic, 1);
1626 if (reg_01.bits.version >= 0x10)
1627 reg_02.raw = io_apic_read(apic, 2);
1628 if (reg_01.bits.version >= 0x20)
1629 reg_03.raw = io_apic_read(apic, 3);
1630 spin_unlock_irqrestore(&ioapic_lock, flags);
1633 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1634 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1635 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1636 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1637 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1639 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1640 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1642 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1643 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1646 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1647 * but the value of reg_02 is read as the previous read register
1648 * value, so ignore it if reg_02 == reg_01.
1650 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1651 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1652 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1656 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1657 * or reg_03, but the value of reg_0[23] is read as the previous read
1658 * register value, so ignore it if reg_03 == reg_0[12].
1660 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1661 reg_03.raw != reg_01.raw) {
1662 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1663 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1666 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1668 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1669 " Stat Dmod Deli Vect: \n");
1671 for (i = 0; i <= reg_01.bits.entries; i++) {
1672 struct IO_APIC_route_entry entry;
1674 entry = ioapic_read_entry(apic, i);
1676 printk(KERN_DEBUG " %02x %03X ",
1681 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1686 entry.delivery_status,
1688 entry.delivery_mode,
1693 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1694 for_each_irq_cfg(irq, cfg) {
1695 struct irq_pin_list *entry = cfg->irq_2_pin;
1698 printk(KERN_DEBUG "IRQ%d ", irq);
1700 printk("-> %d:%d", entry->apic, entry->pin);
1703 entry = entry->next;
1708 printk(KERN_INFO ".................................... done.\n");
1713 __apicdebuginit(void) print_APIC_bitfield(int base)
1718 if (apic_verbosity == APIC_QUIET)
1721 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1722 for (i = 0; i < 8; i++) {
1723 v = apic_read(base + i*0x10);
1724 for (j = 0; j < 32; j++) {
1734 __apicdebuginit(void) print_local_APIC(void *dummy)
1736 unsigned int v, ver, maxlvt;
1739 if (apic_verbosity == APIC_QUIET)
1742 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1743 smp_processor_id(), hard_smp_processor_id());
1744 v = apic_read(APIC_ID);
1745 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1746 v = apic_read(APIC_LVR);
1747 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1748 ver = GET_APIC_VERSION(v);
1749 maxlvt = lapic_get_maxlvt();
1751 v = apic_read(APIC_TASKPRI);
1752 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1754 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1755 if (!APIC_XAPIC(ver)) {
1756 v = apic_read(APIC_ARBPRI);
1757 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1758 v & APIC_ARBPRI_MASK);
1760 v = apic_read(APIC_PROCPRI);
1761 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1765 * Remote read supported only in the 82489DX and local APIC for
1766 * Pentium processors.
1768 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1769 v = apic_read(APIC_RRR);
1770 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1773 v = apic_read(APIC_LDR);
1774 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1775 if (!x2apic_enabled()) {
1776 v = apic_read(APIC_DFR);
1777 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1779 v = apic_read(APIC_SPIV);
1780 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1782 printk(KERN_DEBUG "... APIC ISR field:\n");
1783 print_APIC_bitfield(APIC_ISR);
1784 printk(KERN_DEBUG "... APIC TMR field:\n");
1785 print_APIC_bitfield(APIC_TMR);
1786 printk(KERN_DEBUG "... APIC IRR field:\n");
1787 print_APIC_bitfield(APIC_IRR);
1789 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1790 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1791 apic_write(APIC_ESR, 0);
1793 v = apic_read(APIC_ESR);
1794 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1797 icr = apic_icr_read();
1798 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1799 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1801 v = apic_read(APIC_LVTT);
1802 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1804 if (maxlvt > 3) { /* PC is LVT#4. */
1805 v = apic_read(APIC_LVTPC);
1806 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1808 v = apic_read(APIC_LVT0);
1809 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1810 v = apic_read(APIC_LVT1);
1811 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1813 if (maxlvt > 2) { /* ERR is LVT#3. */
1814 v = apic_read(APIC_LVTERR);
1815 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1818 v = apic_read(APIC_TMICT);
1819 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1820 v = apic_read(APIC_TMCCT);
1821 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1822 v = apic_read(APIC_TDCR);
1823 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1827 __apicdebuginit(void) print_all_local_APICs(void)
1832 for_each_online_cpu(cpu)
1833 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1837 __apicdebuginit(void) print_PIC(void)
1840 unsigned long flags;
1842 if (apic_verbosity == APIC_QUIET)
1845 printk(KERN_DEBUG "\nprinting PIC contents\n");
1847 spin_lock_irqsave(&i8259A_lock, flags);
1849 v = inb(0xa1) << 8 | inb(0x21);
1850 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1852 v = inb(0xa0) << 8 | inb(0x20);
1853 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1857 v = inb(0xa0) << 8 | inb(0x20);
1861 spin_unlock_irqrestore(&i8259A_lock, flags);
1863 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1865 v = inb(0x4d1) << 8 | inb(0x4d0);
1866 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1869 __apicdebuginit(int) print_all_ICs(void)
1872 print_all_local_APICs();
1878 fs_initcall(print_all_ICs);
1881 /* Where if anywhere is the i8259 connect in external int mode */
1882 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1884 void __init enable_IO_APIC(void)
1886 union IO_APIC_reg_01 reg_01;
1887 int i8259_apic, i8259_pin;
1889 unsigned long flags;
1891 #ifdef CONFIG_X86_32
1894 for (i = 0; i < MAX_PIRQS; i++)
1895 pirq_entries[i] = -1;
1899 * The number of IO-APIC IRQ registers (== #pins):
1901 for (apic = 0; apic < nr_ioapics; apic++) {
1902 spin_lock_irqsave(&ioapic_lock, flags);
1903 reg_01.raw = io_apic_read(apic, 1);
1904 spin_unlock_irqrestore(&ioapic_lock, flags);
1905 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1907 for(apic = 0; apic < nr_ioapics; apic++) {
1909 /* See if any of the pins is in ExtINT mode */
1910 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1911 struct IO_APIC_route_entry entry;
1912 entry = ioapic_read_entry(apic, pin);
1914 /* If the interrupt line is enabled and in ExtInt mode
1915 * I have found the pin where the i8259 is connected.
1917 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1918 ioapic_i8259.apic = apic;
1919 ioapic_i8259.pin = pin;
1925 /* Look to see what if the MP table has reported the ExtINT */
1926 /* If we could not find the appropriate pin by looking at the ioapic
1927 * the i8259 probably is not connected the ioapic but give the
1928 * mptable a chance anyway.
1930 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1931 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1932 /* Trust the MP table if nothing is setup in the hardware */
1933 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1934 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1935 ioapic_i8259.pin = i8259_pin;
1936 ioapic_i8259.apic = i8259_apic;
1938 /* Complain if the MP table and the hardware disagree */
1939 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1940 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1942 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1946 * Do not trust the IO-APIC being empty at bootup
1952 * Not an __init, needed by the reboot code
1954 void disable_IO_APIC(void)
1957 * Clear the IO-APIC before rebooting:
1962 * If the i8259 is routed through an IOAPIC
1963 * Put that IOAPIC in virtual wire mode
1964 * so legacy interrupts can be delivered.
1966 if (ioapic_i8259.pin != -1) {
1967 struct IO_APIC_route_entry entry;
1969 memset(&entry, 0, sizeof(entry));
1970 entry.mask = 0; /* Enabled */
1971 entry.trigger = 0; /* Edge */
1973 entry.polarity = 0; /* High */
1974 entry.delivery_status = 0;
1975 entry.dest_mode = 0; /* Physical */
1976 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1978 entry.dest = read_apic_id();
1981 * Add it to the IO-APIC irq-routing table:
1983 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1986 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1989 #ifdef CONFIG_X86_32
1991 * function to set the IO-APIC physical IDs based on the
1992 * values stored in the MPC table.
1994 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1997 static void __init setup_ioapic_ids_from_mpc(void)
1999 union IO_APIC_reg_00 reg_00;
2000 physid_mask_t phys_id_present_map;
2003 unsigned char old_id;
2004 unsigned long flags;
2006 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2010 * Don't check I/O APIC IDs for xAPIC systems. They have
2011 * no meaning without the serial APIC bus.
2013 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2014 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2017 * This is broken; anything with a real cpu count has to
2018 * circumvent this idiocy regardless.
2020 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2023 * Set the IOAPIC ID to the value stored in the MPC table.
2025 for (apic = 0; apic < nr_ioapics; apic++) {
2027 /* Read the register 0 value */
2028 spin_lock_irqsave(&ioapic_lock, flags);
2029 reg_00.raw = io_apic_read(apic, 0);
2030 spin_unlock_irqrestore(&ioapic_lock, flags);
2032 old_id = mp_ioapics[apic].mp_apicid;
2034 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2035 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2036 apic, mp_ioapics[apic].mp_apicid);
2037 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2039 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2043 * Sanity check, is the ID really free? Every APIC in a
2044 * system must have a unique ID or we get lots of nice
2045 * 'stuck on smp_invalidate_needed IPI wait' messages.
2047 if (check_apicid_used(phys_id_present_map,
2048 mp_ioapics[apic].mp_apicid)) {
2049 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2050 apic, mp_ioapics[apic].mp_apicid);
2051 for (i = 0; i < get_physical_broadcast(); i++)
2052 if (!physid_isset(i, phys_id_present_map))
2054 if (i >= get_physical_broadcast())
2055 panic("Max APIC ID exceeded!\n");
2056 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2058 physid_set(i, phys_id_present_map);
2059 mp_ioapics[apic].mp_apicid = i;
2062 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2063 apic_printk(APIC_VERBOSE, "Setting %d in the "
2064 "phys_id_present_map\n",
2065 mp_ioapics[apic].mp_apicid);
2066 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2071 * We need to adjust the IRQ routing table
2072 * if the ID changed.
2074 if (old_id != mp_ioapics[apic].mp_apicid)
2075 for (i = 0; i < mp_irq_entries; i++)
2076 if (mp_irqs[i].mp_dstapic == old_id)
2077 mp_irqs[i].mp_dstapic
2078 = mp_ioapics[apic].mp_apicid;
2081 * Read the right value from the MPC table and
2082 * write it into the ID register.
2084 apic_printk(APIC_VERBOSE, KERN_INFO
2085 "...changing IO-APIC physical APIC ID to %d ...",
2086 mp_ioapics[apic].mp_apicid);
2088 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2089 spin_lock_irqsave(&ioapic_lock, flags);
2090 io_apic_write(apic, 0, reg_00.raw);
2091 spin_unlock_irqrestore(&ioapic_lock, flags);
2096 spin_lock_irqsave(&ioapic_lock, flags);
2097 reg_00.raw = io_apic_read(apic, 0);
2098 spin_unlock_irqrestore(&ioapic_lock, flags);
2099 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2100 printk("could not set ID!\n");
2102 apic_printk(APIC_VERBOSE, " ok.\n");
2107 int no_timer_check __initdata;
2109 static int __init notimercheck(char *s)
2114 __setup("no_timer_check", notimercheck);
2117 * There is a nasty bug in some older SMP boards, their mptable lies
2118 * about the timer IRQ. We do the following to work around the situation:
2120 * - timer IRQ defaults to IO-APIC IRQ
2121 * - if this function detects that timer IRQs are defunct, then we fall
2122 * back to ISA timer IRQs
2124 static int __init timer_irq_works(void)
2126 unsigned long t1 = jiffies;
2127 unsigned long flags;
2132 local_save_flags(flags);
2134 /* Let ten ticks pass... */
2135 mdelay((10 * 1000) / HZ);
2136 local_irq_restore(flags);
2139 * Expect a few ticks at least, to be sure some possible
2140 * glue logic does not lock up after one or two first
2141 * ticks in a non-ExtINT mode. Also the local APIC
2142 * might have cached one ExtINT interrupt. Finally, at
2143 * least one tick may be lost due to delays.
2147 if (time_after(jiffies, t1 + 4))
2153 * In the SMP+IOAPIC case it might happen that there are an unspecified
2154 * number of pending IRQ events unhandled. These cases are very rare,
2155 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2156 * better to do it this way as thus we do not have to be aware of
2157 * 'pending' interrupts in the IRQ path, except at this point.
2160 * Edge triggered needs to resend any interrupt
2161 * that was delayed but this is now handled in the device
2166 * Starting up a edge-triggered IO-APIC interrupt is
2167 * nasty - we need to make sure that we get the edge.
2168 * If it is already asserted for some reason, we need
2169 * return 1 to indicate that is was pending.
2171 * This is not complete - we should be able to fake
2172 * an edge even if it isn't on the 8259A...
2175 static unsigned int startup_ioapic_irq(unsigned int irq)
2177 int was_pending = 0;
2178 unsigned long flags;
2180 spin_lock_irqsave(&ioapic_lock, flags);
2182 disable_8259A_irq(irq);
2183 if (i8259A_irq_pending(irq))
2186 __unmask_IO_APIC_irq(irq);
2187 spin_unlock_irqrestore(&ioapic_lock, flags);
2192 #ifdef CONFIG_X86_64
2193 static int ioapic_retrigger_irq(unsigned int irq)
2196 struct irq_cfg *cfg = irq_cfg(irq);
2197 unsigned long flags;
2199 spin_lock_irqsave(&vector_lock, flags);
2200 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2201 spin_unlock_irqrestore(&vector_lock, flags);
2206 static int ioapic_retrigger_irq(unsigned int irq)
2208 send_IPI_self(irq_cfg(irq)->vector);
2215 * Level and edge triggered IO-APIC interrupts need different handling,
2216 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2217 * handled with the level-triggered descriptor, but that one has slightly
2218 * more overhead. Level-triggered interrupts cannot be handled with the
2219 * edge-triggered handler, without risking IRQ storms and other ugly
2225 #ifdef CONFIG_INTR_REMAP
2226 static void ir_irq_migration(struct work_struct *work);
2228 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2231 * Migrate the IO-APIC irq in the presence of intr-remapping.
2233 * For edge triggered, irq migration is a simple atomic update(of vector
2234 * and cpu destination) of IRTE and flush the hardware cache.
2236 * For level triggered, we need to modify the io-apic RTE aswell with the update
2237 * vector information, along with modifying IRTE with vector and destination.
2238 * So irq migration for level triggered is little bit more complex compared to
2239 * edge triggered migration. But the good news is, we use the same algorithm
2240 * for level triggered migration as we have today, only difference being,
2241 * we now initiate the irq migration from process context instead of the
2242 * interrupt context.
2244 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2245 * suppression) to the IO-APIC, level triggered irq migration will also be
2246 * as simple as edge triggered migration and we can do the irq migration
2247 * with a simple atomic update to IO-APIC RTE.
2249 static void migrate_ioapic_irq(int irq, cpumask_t mask)
2251 struct irq_cfg *cfg;
2252 struct irq_desc *desc;
2253 cpumask_t tmp, cleanup_mask;
2255 int modify_ioapic_rte;
2257 unsigned long flags;
2259 cpus_and(tmp, mask, cpu_online_map);
2260 if (cpus_empty(tmp))
2263 if (get_irte(irq, &irte))
2266 if (assign_irq_vector(irq, mask))
2270 cpus_and(tmp, cfg->domain, mask);
2271 dest = cpu_mask_to_apicid(tmp);
2273 desc = irq_to_desc(irq);
2274 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2275 if (modify_ioapic_rte) {
2276 spin_lock_irqsave(&ioapic_lock, flags);
2277 __target_IO_APIC_irq(irq, dest, cfg->vector);
2278 spin_unlock_irqrestore(&ioapic_lock, flags);
2281 irte.vector = cfg->vector;
2282 irte.dest_id = IRTE_DEST(dest);
2285 * Modified the IRTE and flushes the Interrupt entry cache.
2287 modify_irte(irq, &irte);
2289 if (cfg->move_in_progress) {
2290 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2291 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2292 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2293 cfg->move_in_progress = 0;
2296 desc->affinity = mask;
2299 static int migrate_irq_remapped_level(int irq)
2302 struct irq_desc *desc = irq_to_desc(irq);
2304 mask_IO_APIC_irq(irq);
2306 if (io_apic_level_ack_pending(irq)) {
2308 * Interrupt in progress. Migrating irq now will change the
2309 * vector information in the IO-APIC RTE and that will confuse
2310 * the EOI broadcast performed by cpu.
2311 * So, delay the irq migration to the next instance.
2313 schedule_delayed_work(&ir_migration_work, 1);
2317 /* everthing is clear. we have right of way */
2318 migrate_ioapic_irq(irq, desc->pending_mask);
2321 desc->status &= ~IRQ_MOVE_PENDING;
2322 cpus_clear(desc->pending_mask);
2325 unmask_IO_APIC_irq(irq);
2329 static void ir_irq_migration(struct work_struct *work)
2332 struct irq_desc *desc;
2334 for_each_irq_desc(irq, desc) {
2335 if (desc->status & IRQ_MOVE_PENDING) {
2336 unsigned long flags;
2338 spin_lock_irqsave(&desc->lock, flags);
2339 if (!desc->chip->set_affinity ||
2340 !(desc->status & IRQ_MOVE_PENDING)) {
2341 desc->status &= ~IRQ_MOVE_PENDING;
2342 spin_unlock_irqrestore(&desc->lock, flags);
2346 desc->chip->set_affinity(irq, desc->pending_mask);
2347 spin_unlock_irqrestore(&desc->lock, flags);
2353 * Migrates the IRQ destination in the process context.
2355 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2357 struct irq_desc *desc = irq_to_desc(irq);
2359 if (desc->status & IRQ_LEVEL) {
2360 desc->status |= IRQ_MOVE_PENDING;
2361 desc->pending_mask = mask;
2362 migrate_irq_remapped_level(irq);
2366 migrate_ioapic_irq(irq, mask);
2370 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2372 unsigned vector, me;
2374 #ifdef CONFIG_X86_64
2379 me = smp_processor_id();
2380 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2382 struct irq_desc *desc;
2383 struct irq_cfg *cfg;
2384 irq = __get_cpu_var(vector_irq)[vector];
2386 desc = irq_to_desc(irq);
2391 spin_lock(&desc->lock);
2392 if (!cfg->move_cleanup_count)
2395 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2398 __get_cpu_var(vector_irq)[vector] = -1;
2399 cfg->move_cleanup_count--;
2401 spin_unlock(&desc->lock);
2407 static void irq_complete_move(unsigned int irq)
2409 struct irq_cfg *cfg = irq_cfg(irq);
2410 unsigned vector, me;
2412 if (likely(!cfg->move_in_progress))
2415 vector = ~get_irq_regs()->orig_ax;
2416 me = smp_processor_id();
2417 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2418 cpumask_t cleanup_mask;
2420 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2421 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2422 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2423 cfg->move_in_progress = 0;
2427 static inline void irq_complete_move(unsigned int irq) {}
2429 #ifdef CONFIG_INTR_REMAP
2430 static void ack_x2apic_level(unsigned int irq)
2435 static void ack_x2apic_edge(unsigned int irq)
2441 static void ack_apic_edge(unsigned int irq)
2443 irq_complete_move(irq);
2444 move_native_irq(irq);
2448 #ifdef CONFIG_X86_32
2449 atomic_t irq_mis_count;
2452 static void ack_apic_level(unsigned int irq)
2454 #ifdef CONFIG_X86_32
2458 int do_unmask_irq = 0;
2460 irq_complete_move(irq);
2461 #ifdef CONFIG_GENERIC_PENDING_IRQ
2462 /* If we are moving the irq we need to mask it */
2463 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2465 mask_IO_APIC_irq(irq);
2469 #ifdef CONFIG_X86_32
2471 * It appears there is an erratum which affects at least version 0x11
2472 * of I/O APIC (that's the 82093AA and cores integrated into various
2473 * chipsets). Under certain conditions a level-triggered interrupt is
2474 * erroneously delivered as edge-triggered one but the respective IRR
2475 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2476 * message but it will never arrive and further interrupts are blocked
2477 * from the source. The exact reason is so far unknown, but the
2478 * phenomenon was observed when two consecutive interrupt requests
2479 * from a given source get delivered to the same CPU and the source is
2480 * temporarily disabled in between.
2482 * A workaround is to simulate an EOI message manually. We achieve it
2483 * by setting the trigger mode to edge and then to level when the edge
2484 * trigger mode gets detected in the TMR of a local APIC for a
2485 * level-triggered interrupt. We mask the source for the time of the
2486 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2487 * The idea is from Manfred Spraul. --macro
2489 i = irq_cfg(irq)->vector;
2491 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2495 * We must acknowledge the irq before we move it or the acknowledge will
2496 * not propagate properly.
2500 /* Now we can move and renable the irq */
2501 if (unlikely(do_unmask_irq)) {
2502 /* Only migrate the irq if the ack has been received.
2504 * On rare occasions the broadcast level triggered ack gets
2505 * delayed going to ioapics, and if we reprogram the
2506 * vector while Remote IRR is still set the irq will never
2509 * To prevent this scenario we read the Remote IRR bit
2510 * of the ioapic. This has two effects.
2511 * - On any sane system the read of the ioapic will
2512 * flush writes (and acks) going to the ioapic from
2514 * - We get to see if the ACK has actually been delivered.
2516 * Based on failed experiments of reprogramming the
2517 * ioapic entry from outside of irq context starting
2518 * with masking the ioapic entry and then polling until
2519 * Remote IRR was clear before reprogramming the
2520 * ioapic I don't trust the Remote IRR bit to be
2521 * completey accurate.
2523 * However there appears to be no other way to plug
2524 * this race, so if the Remote IRR bit is not
2525 * accurate and is causing problems then it is a hardware bug
2526 * and you can go talk to the chipset vendor about it.
2528 if (!io_apic_level_ack_pending(irq))
2529 move_masked_irq(irq);
2530 unmask_IO_APIC_irq(irq);
2533 #ifdef CONFIG_X86_32
2534 if (!(v & (1 << (i & 0x1f)))) {
2535 atomic_inc(&irq_mis_count);
2536 spin_lock(&ioapic_lock);
2537 __mask_and_edge_IO_APIC_irq(irq);
2538 __unmask_and_level_IO_APIC_irq(irq);
2539 spin_unlock(&ioapic_lock);
2544 static struct irq_chip ioapic_chip __read_mostly = {
2546 .startup = startup_ioapic_irq,
2547 .mask = mask_IO_APIC_irq,
2548 .unmask = unmask_IO_APIC_irq,
2549 .ack = ack_apic_edge,
2550 .eoi = ack_apic_level,
2552 .set_affinity = set_ioapic_affinity_irq,
2554 .retrigger = ioapic_retrigger_irq,
2557 #ifdef CONFIG_INTR_REMAP
2558 static struct irq_chip ir_ioapic_chip __read_mostly = {
2559 .name = "IR-IO-APIC",
2560 .startup = startup_ioapic_irq,
2561 .mask = mask_IO_APIC_irq,
2562 .unmask = unmask_IO_APIC_irq,
2563 .ack = ack_x2apic_edge,
2564 .eoi = ack_x2apic_level,
2566 .set_affinity = set_ir_ioapic_affinity_irq,
2568 .retrigger = ioapic_retrigger_irq,
2572 static inline void init_IO_APIC_traps(void)
2575 struct irq_desc *desc;
2576 struct irq_cfg *cfg;
2579 * NOTE! The local APIC isn't very good at handling
2580 * multiple interrupts at the same interrupt level.
2581 * As the interrupt level is determined by taking the
2582 * vector number and shifting that right by 4, we
2583 * want to spread these out a bit so that they don't
2584 * all fall in the same interrupt level.
2586 * Also, we've got to be careful not to trash gate
2587 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2589 for_each_irq_cfg(irq, cfg) {
2590 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2592 * Hmm.. We don't have an entry for this,
2593 * so default to an old-fashioned 8259
2594 * interrupt if we can..
2597 make_8259A_irq(irq);
2599 desc = irq_to_desc(irq);
2600 /* Strange. Oh, well.. */
2601 desc->chip = &no_irq_chip;
2608 * The local APIC irq-chip implementation:
2611 static void mask_lapic_irq(unsigned int irq)
2615 v = apic_read(APIC_LVT0);
2616 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2619 static void unmask_lapic_irq(unsigned int irq)
2623 v = apic_read(APIC_LVT0);
2624 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2627 static void ack_lapic_irq (unsigned int irq)
2632 static struct irq_chip lapic_chip __read_mostly = {
2633 .name = "local-APIC",
2634 .mask = mask_lapic_irq,
2635 .unmask = unmask_lapic_irq,
2636 .ack = ack_lapic_irq,
2639 static void lapic_register_intr(int irq)
2641 struct irq_desc *desc;
2643 desc = irq_to_desc(irq);
2644 desc->status &= ~IRQ_LEVEL;
2645 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2649 static void __init setup_nmi(void)
2652 * Dirty trick to enable the NMI watchdog ...
2653 * We put the 8259A master into AEOI mode and
2654 * unmask on all local APICs LVT0 as NMI.
2656 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2657 * is from Maciej W. Rozycki - so we do not have to EOI from
2658 * the NMI handler or the timer interrupt.
2660 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2662 enable_NMI_through_LVT0();
2664 apic_printk(APIC_VERBOSE, " done.\n");
2668 * This looks a bit hackish but it's about the only one way of sending
2669 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2670 * not support the ExtINT mode, unfortunately. We need to send these
2671 * cycles as some i82489DX-based boards have glue logic that keeps the
2672 * 8259A interrupt line asserted until INTA. --macro
2674 static inline void __init unlock_ExtINT_logic(void)
2677 struct IO_APIC_route_entry entry0, entry1;
2678 unsigned char save_control, save_freq_select;
2680 pin = find_isa_irq_pin(8, mp_INT);
2685 apic = find_isa_irq_apic(8, mp_INT);
2691 entry0 = ioapic_read_entry(apic, pin);
2692 clear_IO_APIC_pin(apic, pin);
2694 memset(&entry1, 0, sizeof(entry1));
2696 entry1.dest_mode = 0; /* physical delivery */
2697 entry1.mask = 0; /* unmask IRQ now */
2698 entry1.dest = hard_smp_processor_id();
2699 entry1.delivery_mode = dest_ExtINT;
2700 entry1.polarity = entry0.polarity;
2704 ioapic_write_entry(apic, pin, entry1);
2706 save_control = CMOS_READ(RTC_CONTROL);
2707 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2708 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2710 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2715 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2719 CMOS_WRITE(save_control, RTC_CONTROL);
2720 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2721 clear_IO_APIC_pin(apic, pin);
2723 ioapic_write_entry(apic, pin, entry0);
2726 static int disable_timer_pin_1 __initdata;
2727 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2728 static int __init disable_timer_pin_setup(char *arg)
2730 disable_timer_pin_1 = 1;
2733 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2735 int timer_through_8259 __initdata;
2738 * This code may look a bit paranoid, but it's supposed to cooperate with
2739 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2740 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2741 * fanatically on his truly buggy board.
2743 * FIXME: really need to revamp this for all platforms.
2745 static inline void __init check_timer(void)
2747 struct irq_cfg *cfg = irq_cfg(0);
2748 int apic1, pin1, apic2, pin2;
2749 unsigned long flags;
2753 local_irq_save(flags);
2755 ver = apic_read(APIC_LVR);
2756 ver = GET_APIC_VERSION(ver);
2759 * get/set the timer IRQ vector:
2761 disable_8259A_irq(0);
2762 assign_irq_vector(0, TARGET_CPUS);
2765 * As IRQ0 is to be enabled in the 8259A, the virtual
2766 * wire has to be disabled in the local APIC. Also
2767 * timer interrupts need to be acknowledged manually in
2768 * the 8259A for the i82489DX when using the NMI
2769 * watchdog as that APIC treats NMIs as level-triggered.
2770 * The AEOI mode will finish them in the 8259A
2773 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2775 #ifdef CONFIG_X86_32
2776 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2779 pin1 = find_isa_irq_pin(0, mp_INT);
2780 apic1 = find_isa_irq_apic(0, mp_INT);
2781 pin2 = ioapic_i8259.pin;
2782 apic2 = ioapic_i8259.apic;
2784 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2785 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2786 cfg->vector, apic1, pin1, apic2, pin2);
2789 * Some BIOS writers are clueless and report the ExtINTA
2790 * I/O APIC input from the cascaded 8259A as the timer
2791 * interrupt input. So just in case, if only one pin
2792 * was found above, try it both directly and through the
2796 #ifdef CONFIG_INTR_REMAP
2797 if (intr_remapping_enabled)
2798 panic("BIOS bug: timer not connected to IO-APIC");
2803 } else if (pin2 == -1) {
2810 * Ok, does IRQ0 through the IOAPIC work?
2813 add_pin_to_irq(0, apic1, pin1);
2814 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2816 unmask_IO_APIC_irq(0);
2817 if (timer_irq_works()) {
2818 if (nmi_watchdog == NMI_IO_APIC) {
2820 enable_8259A_irq(0);
2822 if (disable_timer_pin_1 > 0)
2823 clear_IO_APIC_pin(0, pin1);
2826 #ifdef CONFIG_INTR_REMAP
2827 if (intr_remapping_enabled)
2828 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2830 clear_IO_APIC_pin(apic1, pin1);
2832 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2833 "8254 timer not connected to IO-APIC\n");
2835 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2836 "(IRQ0) through the 8259A ...\n");
2837 apic_printk(APIC_QUIET, KERN_INFO
2838 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2840 * legacy devices should be connected to IO APIC #0
2842 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2843 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2844 unmask_IO_APIC_irq(0);
2845 enable_8259A_irq(0);
2846 if (timer_irq_works()) {
2847 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2848 timer_through_8259 = 1;
2849 if (nmi_watchdog == NMI_IO_APIC) {
2850 disable_8259A_irq(0);
2852 enable_8259A_irq(0);
2857 * Cleanup, just in case ...
2859 disable_8259A_irq(0);
2860 clear_IO_APIC_pin(apic2, pin2);
2861 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2864 if (nmi_watchdog == NMI_IO_APIC) {
2865 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2866 "through the IO-APIC - disabling NMI Watchdog!\n");
2867 nmi_watchdog = NMI_NONE;
2869 #ifdef CONFIG_X86_32
2873 apic_printk(APIC_QUIET, KERN_INFO
2874 "...trying to set up timer as Virtual Wire IRQ...\n");
2876 lapic_register_intr(0);
2877 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2878 enable_8259A_irq(0);
2880 if (timer_irq_works()) {
2881 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2884 disable_8259A_irq(0);
2885 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2886 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2888 apic_printk(APIC_QUIET, KERN_INFO
2889 "...trying to set up timer as ExtINT IRQ...\n");
2893 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2895 unlock_ExtINT_logic();
2897 if (timer_irq_works()) {
2898 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2901 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2902 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2903 "report. Then try booting with the 'noapic' option.\n");
2905 local_irq_restore(flags);
2909 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2910 * to devices. However there may be an I/O APIC pin available for
2911 * this interrupt regardless. The pin may be left unconnected, but
2912 * typically it will be reused as an ExtINT cascade interrupt for
2913 * the master 8259A. In the MPS case such a pin will normally be
2914 * reported as an ExtINT interrupt in the MP table. With ACPI
2915 * there is no provision for ExtINT interrupts, and in the absence
2916 * of an override it would be treated as an ordinary ISA I/O APIC
2917 * interrupt, that is edge-triggered and unmasked by default. We
2918 * used to do this, but it caused problems on some systems because
2919 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2920 * the same ExtINT cascade interrupt to drive the local APIC of the
2921 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2922 * the I/O APIC in all cases now. No actual device should request
2923 * it anyway. --macro
2925 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2927 void __init setup_IO_APIC(void)
2930 #ifdef CONFIG_X86_32
2934 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2938 io_apic_irqs = ~PIC_IRQS;
2940 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2942 * Set up IO-APIC IRQ routing.
2944 #ifdef CONFIG_X86_32
2946 setup_ioapic_ids_from_mpc();
2949 setup_IO_APIC_irqs();
2950 init_IO_APIC_traps();
2955 * Called after all the initialization is done. If we didnt find any
2956 * APIC bugs then we can allow the modify fast path
2959 static int __init io_apic_bug_finalize(void)
2961 if (sis_apic_bug == -1)
2966 late_initcall(io_apic_bug_finalize);
2968 struct sysfs_ioapic_data {
2969 struct sys_device dev;
2970 struct IO_APIC_route_entry entry[0];
2972 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2974 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2976 struct IO_APIC_route_entry *entry;
2977 struct sysfs_ioapic_data *data;
2980 data = container_of(dev, struct sysfs_ioapic_data, dev);
2981 entry = data->entry;
2982 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2983 *entry = ioapic_read_entry(dev->id, i);
2988 static int ioapic_resume(struct sys_device *dev)
2990 struct IO_APIC_route_entry *entry;
2991 struct sysfs_ioapic_data *data;
2992 unsigned long flags;
2993 union IO_APIC_reg_00 reg_00;
2996 data = container_of(dev, struct sysfs_ioapic_data, dev);
2997 entry = data->entry;
2999 spin_lock_irqsave(&ioapic_lock, flags);
3000 reg_00.raw = io_apic_read(dev->id, 0);
3001 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
3002 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
3003 io_apic_write(dev->id, 0, reg_00.raw);
3005 spin_unlock_irqrestore(&ioapic_lock, flags);
3006 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3007 ioapic_write_entry(dev->id, i, entry[i]);
3012 static struct sysdev_class ioapic_sysdev_class = {
3014 .suspend = ioapic_suspend,
3015 .resume = ioapic_resume,
3018 static int __init ioapic_init_sysfs(void)
3020 struct sys_device * dev;
3023 error = sysdev_class_register(&ioapic_sysdev_class);
3027 for (i = 0; i < nr_ioapics; i++ ) {
3028 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3029 * sizeof(struct IO_APIC_route_entry);
3030 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3031 if (!mp_ioapic_data[i]) {
3032 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3035 dev = &mp_ioapic_data[i]->dev;
3037 dev->cls = &ioapic_sysdev_class;
3038 error = sysdev_register(dev);
3040 kfree(mp_ioapic_data[i]);
3041 mp_ioapic_data[i] = NULL;
3042 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3050 device_initcall(ioapic_init_sysfs);
3053 * Dynamic irq allocate and deallocation
3055 unsigned int create_irq_nr(unsigned int irq_want)
3057 /* Allocate an unused irq */
3060 unsigned long flags;
3061 struct irq_cfg *cfg_new;
3063 #ifndef CONFIG_HAVE_SPARSE_IRQ
3064 irq_want = nr_irqs - 1;
3068 spin_lock_irqsave(&vector_lock, flags);
3069 for (new = irq_want; new > 0; new--) {
3070 if (platform_legacy_irq(new))
3072 cfg_new = irq_cfg(new);
3073 if (cfg_new && cfg_new->vector != 0)
3075 /* check if need to create one */
3077 cfg_new = irq_cfg_alloc(new);
3078 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
3082 spin_unlock_irqrestore(&vector_lock, flags);
3085 dynamic_irq_init(irq);
3090 int create_irq(void)
3094 irq = create_irq_nr(nr_irqs - 1);
3102 void destroy_irq(unsigned int irq)
3104 unsigned long flags;
3106 dynamic_irq_cleanup(irq);
3108 #ifdef CONFIG_INTR_REMAP
3111 spin_lock_irqsave(&vector_lock, flags);
3112 __clear_irq_vector(irq);
3113 spin_unlock_irqrestore(&vector_lock, flags);
3117 * MSI message composition
3119 #ifdef CONFIG_PCI_MSI
3120 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3122 struct irq_cfg *cfg;
3128 err = assign_irq_vector(irq, tmp);
3133 cpus_and(tmp, cfg->domain, tmp);
3134 dest = cpu_mask_to_apicid(tmp);
3136 #ifdef CONFIG_INTR_REMAP
3137 if (irq_remapped(irq)) {
3142 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3143 BUG_ON(ir_index == -1);
3145 memset (&irte, 0, sizeof(irte));
3148 irte.dst_mode = INT_DEST_MODE;
3149 irte.trigger_mode = 0; /* edge */
3150 irte.dlvry_mode = INT_DELIVERY_MODE;
3151 irte.vector = cfg->vector;
3152 irte.dest_id = IRTE_DEST(dest);
3154 modify_irte(irq, &irte);
3156 msg->address_hi = MSI_ADDR_BASE_HI;
3157 msg->data = sub_handle;
3158 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3160 MSI_ADDR_IR_INDEX1(ir_index) |
3161 MSI_ADDR_IR_INDEX2(ir_index);
3165 msg->address_hi = MSI_ADDR_BASE_HI;
3168 ((INT_DEST_MODE == 0) ?
3169 MSI_ADDR_DEST_MODE_PHYSICAL:
3170 MSI_ADDR_DEST_MODE_LOGICAL) |
3171 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3172 MSI_ADDR_REDIRECTION_CPU:
3173 MSI_ADDR_REDIRECTION_LOWPRI) |
3174 MSI_ADDR_DEST_ID(dest);
3177 MSI_DATA_TRIGGER_EDGE |
3178 MSI_DATA_LEVEL_ASSERT |
3179 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3180 MSI_DATA_DELIVERY_FIXED:
3181 MSI_DATA_DELIVERY_LOWPRI) |
3182 MSI_DATA_VECTOR(cfg->vector);
3188 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3190 struct irq_cfg *cfg;
3194 struct irq_desc *desc;
3196 cpus_and(tmp, mask, cpu_online_map);
3197 if (cpus_empty(tmp))
3200 if (assign_irq_vector(irq, mask))
3204 cpus_and(tmp, cfg->domain, mask);
3205 dest = cpu_mask_to_apicid(tmp);
3207 read_msi_msg(irq, &msg);
3209 msg.data &= ~MSI_DATA_VECTOR_MASK;
3210 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3211 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3212 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3214 write_msi_msg(irq, &msg);
3215 desc = irq_to_desc(irq);
3216 desc->affinity = mask;
3219 #ifdef CONFIG_INTR_REMAP
3221 * Migrate the MSI irq to another cpumask. This migration is
3222 * done in the process context using interrupt-remapping hardware.
3224 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3226 struct irq_cfg *cfg;
3228 cpumask_t tmp, cleanup_mask;
3230 struct irq_desc *desc;
3232 cpus_and(tmp, mask, cpu_online_map);
3233 if (cpus_empty(tmp))
3236 if (get_irte(irq, &irte))
3239 if (assign_irq_vector(irq, mask))
3243 cpus_and(tmp, cfg->domain, mask);
3244 dest = cpu_mask_to_apicid(tmp);
3246 irte.vector = cfg->vector;
3247 irte.dest_id = IRTE_DEST(dest);
3250 * atomically update the IRTE with the new destination and vector.
3252 modify_irte(irq, &irte);
3255 * After this point, all the interrupts will start arriving
3256 * at the new destination. So, time to cleanup the previous
3257 * vector allocation.
3259 if (cfg->move_in_progress) {
3260 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3261 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3262 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3263 cfg->move_in_progress = 0;
3266 desc = irq_to_desc(irq);
3267 desc->affinity = mask;
3270 #endif /* CONFIG_SMP */
3273 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3274 * which implement the MSI or MSI-X Capability Structure.
3276 static struct irq_chip msi_chip = {
3278 .unmask = unmask_msi_irq,
3279 .mask = mask_msi_irq,
3280 .ack = ack_apic_edge,
3282 .set_affinity = set_msi_irq_affinity,
3284 .retrigger = ioapic_retrigger_irq,
3287 #ifdef CONFIG_INTR_REMAP
3288 static struct irq_chip msi_ir_chip = {
3289 .name = "IR-PCI-MSI",
3290 .unmask = unmask_msi_irq,
3291 .mask = mask_msi_irq,
3292 .ack = ack_x2apic_edge,
3294 .set_affinity = ir_set_msi_irq_affinity,
3296 .retrigger = ioapic_retrigger_irq,
3300 * Map the PCI dev to the corresponding remapping hardware unit
3301 * and allocate 'nvec' consecutive interrupt-remapping table entries
3304 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3306 struct intel_iommu *iommu;
3309 iommu = map_dev_to_ir(dev);
3312 "Unable to map PCI %s to iommu\n", pci_name(dev));
3316 index = alloc_irte(iommu, irq, nvec);
3319 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3327 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3332 ret = msi_compose_msg(dev, irq, &msg);
3336 set_irq_msi(irq, desc);
3337 write_msi_msg(irq, &msg);
3339 #ifdef CONFIG_INTR_REMAP
3340 if (irq_remapped(irq)) {
3341 struct irq_desc *desc = irq_to_desc(irq);
3343 * irq migration in process context
3345 desc->status |= IRQ_MOVE_PCNTXT;
3346 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3349 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3354 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3358 irq = dev->bus->number;
3366 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3370 unsigned int irq_want;
3372 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3374 irq = create_irq_nr(irq_want);
3378 #ifdef CONFIG_INTR_REMAP
3379 if (!intr_remapping_enabled)
3382 ret = msi_alloc_irte(dev, irq, 1);
3387 ret = setup_msi_irq(dev, desc, irq);
3394 #ifdef CONFIG_INTR_REMAP
3401 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3404 int ret, sub_handle;
3405 struct msi_desc *desc;
3406 unsigned int irq_want;
3408 #ifdef CONFIG_INTR_REMAP
3409 struct intel_iommu *iommu = 0;
3413 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3415 list_for_each_entry(desc, &dev->msi_list, list) {
3416 irq = create_irq_nr(irq_want--);
3419 #ifdef CONFIG_INTR_REMAP
3420 if (!intr_remapping_enabled)
3425 * allocate the consecutive block of IRTE's
3428 index = msi_alloc_irte(dev, irq, nvec);
3434 iommu = map_dev_to_ir(dev);
3440 * setup the mapping between the irq and the IRTE
3441 * base index, the sub_handle pointing to the
3442 * appropriate interrupt remap table entry.
3444 set_irte_irq(irq, iommu, index, sub_handle);
3448 ret = setup_msi_irq(dev, desc, irq);
3460 void arch_teardown_msi_irq(unsigned int irq)
3467 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3469 struct irq_cfg *cfg;
3473 struct irq_desc *desc;
3475 cpus_and(tmp, mask, cpu_online_map);
3476 if (cpus_empty(tmp))
3479 if (assign_irq_vector(irq, mask))
3483 cpus_and(tmp, cfg->domain, mask);
3484 dest = cpu_mask_to_apicid(tmp);
3486 dmar_msi_read(irq, &msg);
3488 msg.data &= ~MSI_DATA_VECTOR_MASK;
3489 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3490 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3491 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3493 dmar_msi_write(irq, &msg);
3494 desc = irq_to_desc(irq);
3495 desc->affinity = mask;
3497 #endif /* CONFIG_SMP */
3499 struct irq_chip dmar_msi_type = {
3501 .unmask = dmar_msi_unmask,
3502 .mask = dmar_msi_mask,
3503 .ack = ack_apic_edge,
3505 .set_affinity = dmar_msi_set_affinity,
3507 .retrigger = ioapic_retrigger_irq,
3510 int arch_setup_dmar_msi(unsigned int irq)
3515 ret = msi_compose_msg(NULL, irq, &msg);
3518 dmar_msi_write(irq, &msg);
3519 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3525 #endif /* CONFIG_PCI_MSI */
3527 * Hypertransport interrupt support
3529 #ifdef CONFIG_HT_IRQ
3533 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3535 struct ht_irq_msg msg;
3536 fetch_ht_irq_msg(irq, &msg);
3538 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3539 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3541 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3542 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3544 write_ht_irq_msg(irq, &msg);
3547 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3549 struct irq_cfg *cfg;
3552 struct irq_desc *desc;
3554 cpus_and(tmp, mask, cpu_online_map);
3555 if (cpus_empty(tmp))
3558 if (assign_irq_vector(irq, mask))
3562 cpus_and(tmp, cfg->domain, mask);
3563 dest = cpu_mask_to_apicid(tmp);
3565 target_ht_irq(irq, dest, cfg->vector);
3566 desc = irq_to_desc(irq);
3567 desc->affinity = mask;
3571 static struct irq_chip ht_irq_chip = {
3573 .mask = mask_ht_irq,
3574 .unmask = unmask_ht_irq,
3575 .ack = ack_apic_edge,
3577 .set_affinity = set_ht_irq_affinity,
3579 .retrigger = ioapic_retrigger_irq,
3582 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3584 struct irq_cfg *cfg;
3589 err = assign_irq_vector(irq, tmp);
3591 struct ht_irq_msg msg;
3595 cpus_and(tmp, cfg->domain, tmp);
3596 dest = cpu_mask_to_apicid(tmp);
3598 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3602 HT_IRQ_LOW_DEST_ID(dest) |
3603 HT_IRQ_LOW_VECTOR(cfg->vector) |
3604 ((INT_DEST_MODE == 0) ?
3605 HT_IRQ_LOW_DM_PHYSICAL :
3606 HT_IRQ_LOW_DM_LOGICAL) |
3607 HT_IRQ_LOW_RQEOI_EDGE |
3608 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3609 HT_IRQ_LOW_MT_FIXED :
3610 HT_IRQ_LOW_MT_ARBITRATED) |
3611 HT_IRQ_LOW_IRQ_MASKED;
3613 write_ht_irq_msg(irq, &msg);
3615 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3616 handle_edge_irq, "edge");
3620 #endif /* CONFIG_HT_IRQ */
3622 int __init io_apic_get_redir_entries (int ioapic)
3624 union IO_APIC_reg_01 reg_01;
3625 unsigned long flags;
3627 spin_lock_irqsave(&ioapic_lock, flags);
3628 reg_01.raw = io_apic_read(ioapic, 1);
3629 spin_unlock_irqrestore(&ioapic_lock, flags);
3631 return reg_01.bits.entries;
3634 int __init probe_nr_irqs(void)
3641 int nr_min = NR_IRQS;
3644 for (idx = 0; idx < nr_ioapics; idx++)
3645 nr += io_apic_get_redir_entries(idx) + 1;
3647 /* double it for hotplug and msi and nmi */
3650 /* something wrong ? */
3657 /* --------------------------------------------------------------------------
3658 ACPI-based IOAPIC Configuration
3659 -------------------------------------------------------------------------- */
3663 #ifdef CONFIG_X86_32
3664 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3666 union IO_APIC_reg_00 reg_00;
3667 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3669 unsigned long flags;
3673 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3674 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3675 * supports up to 16 on one shared APIC bus.
3677 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3678 * advantage of new APIC bus architecture.
3681 if (physids_empty(apic_id_map))
3682 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3684 spin_lock_irqsave(&ioapic_lock, flags);
3685 reg_00.raw = io_apic_read(ioapic, 0);
3686 spin_unlock_irqrestore(&ioapic_lock, flags);
3688 if (apic_id >= get_physical_broadcast()) {
3689 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3690 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3691 apic_id = reg_00.bits.ID;
3695 * Every APIC in a system must have a unique ID or we get lots of nice
3696 * 'stuck on smp_invalidate_needed IPI wait' messages.
3698 if (check_apicid_used(apic_id_map, apic_id)) {
3700 for (i = 0; i < get_physical_broadcast(); i++) {
3701 if (!check_apicid_used(apic_id_map, i))
3705 if (i == get_physical_broadcast())
3706 panic("Max apic_id exceeded!\n");
3708 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3709 "trying %d\n", ioapic, apic_id, i);
3714 tmp = apicid_to_cpu_present(apic_id);
3715 physids_or(apic_id_map, apic_id_map, tmp);
3717 if (reg_00.bits.ID != apic_id) {
3718 reg_00.bits.ID = apic_id;
3720 spin_lock_irqsave(&ioapic_lock, flags);
3721 io_apic_write(ioapic, 0, reg_00.raw);
3722 reg_00.raw = io_apic_read(ioapic, 0);
3723 spin_unlock_irqrestore(&ioapic_lock, flags);
3726 if (reg_00.bits.ID != apic_id) {
3727 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3732 apic_printk(APIC_VERBOSE, KERN_INFO
3733 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3738 int __init io_apic_get_version(int ioapic)
3740 union IO_APIC_reg_01 reg_01;
3741 unsigned long flags;
3743 spin_lock_irqsave(&ioapic_lock, flags);
3744 reg_01.raw = io_apic_read(ioapic, 1);
3745 spin_unlock_irqrestore(&ioapic_lock, flags);
3747 return reg_01.bits.version;
3751 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3753 if (!IO_APIC_IRQ(irq)) {
3754 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3760 * IRQs < 16 are already in the irq_2_pin[] map
3763 add_pin_to_irq(irq, ioapic, pin);
3765 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3771 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3775 if (skip_ioapic_setup)
3778 for (i = 0; i < mp_irq_entries; i++)
3779 if (mp_irqs[i].mp_irqtype == mp_INT &&
3780 mp_irqs[i].mp_srcbusirq == bus_irq)
3782 if (i >= mp_irq_entries)
3785 *trigger = irq_trigger(i);
3786 *polarity = irq_polarity(i);
3790 #endif /* CONFIG_ACPI */
3793 * This function currently is only a helper for the i386 smp boot process where
3794 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3795 * so mask in all cases should simply be TARGET_CPUS
3798 void __init setup_ioapic_dest(void)
3800 int pin, ioapic, irq, irq_entry;
3801 struct irq_cfg *cfg;
3803 if (skip_ioapic_setup == 1)
3806 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3807 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3808 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3809 if (irq_entry == -1)
3811 irq = pin_2_irq(irq_entry, ioapic, pin);
3813 /* setup_IO_APIC_irqs could fail to get vector for some device
3814 * when you have too many devices, because at that time only boot
3819 setup_IO_APIC_irq(ioapic, pin, irq,
3820 irq_trigger(irq_entry),
3821 irq_polarity(irq_entry));
3822 #ifdef CONFIG_INTR_REMAP
3823 else if (intr_remapping_enabled)
3824 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3827 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3834 #define IOAPIC_RESOURCE_NAME_SIZE 11
3836 static struct resource *ioapic_resources;
3838 static struct resource * __init ioapic_setup_resources(void)
3841 struct resource *res;
3845 if (nr_ioapics <= 0)
3848 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3851 mem = alloc_bootmem(n);
3855 mem += sizeof(struct resource) * nr_ioapics;
3857 for (i = 0; i < nr_ioapics; i++) {
3859 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3860 sprintf(mem, "IOAPIC %u", i);
3861 mem += IOAPIC_RESOURCE_NAME_SIZE;
3865 ioapic_resources = res;
3870 void __init ioapic_init_mappings(void)
3872 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3874 struct resource *ioapic_res;
3876 ioapic_res = ioapic_setup_resources();
3877 for (i = 0; i < nr_ioapics; i++) {
3878 if (smp_found_config) {
3879 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3880 #ifdef CONFIG_X86_32
3883 "WARNING: bogus zero IO-APIC "
3884 "address found in MPTABLE, "
3885 "disabling IO/APIC support!\n");
3886 smp_found_config = 0;
3887 skip_ioapic_setup = 1;
3888 goto fake_ioapic_page;
3892 #ifdef CONFIG_X86_32
3895 ioapic_phys = (unsigned long)
3896 alloc_bootmem_pages(PAGE_SIZE);
3897 ioapic_phys = __pa(ioapic_phys);
3899 set_fixmap_nocache(idx, ioapic_phys);
3900 apic_printk(APIC_VERBOSE,
3901 "mapped IOAPIC to %08lx (%08lx)\n",
3902 __fix_to_virt(idx), ioapic_phys);
3905 if (ioapic_res != NULL) {
3906 ioapic_res->start = ioapic_phys;
3907 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3913 static int __init ioapic_insert_resources(void)
3916 struct resource *r = ioapic_resources;
3920 "IO APIC resources could be not be allocated.\n");
3924 for (i = 0; i < nr_ioapics; i++) {
3925 insert_resource(&iomem_resource, r);
3932 /* Insert the IO APIC resources after PCI initialization has occured to handle
3933 * IO APICS that are mapped in on a BAR in PCI space. */
3934 late_initcall(ioapic_insert_resources);