2 * MPC8641 HPCN Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <32768>; // L1
42 i-cache-size = <32768>; // L1
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>; // From uboot
45 clock-frequency = <0>; // From uboot
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <32768>;
53 i-cache-size = <32768>;
54 timebase-frequency = <0>; // From uboot
55 bus-frequency = <0>; // From uboot
56 clock-frequency = <0>; // From uboot
61 device_type = "memory";
62 reg = <0x00000000 0x40000000>; // 1G at 0x0
68 compatible = "fsl,mpc8641-localbus", "simple-bus";
69 reg = <0xf8005000 0x1000>;
71 interrupt-parent = <&mpic>;
73 ranges = <0 0 0xff800000 0x00800000
74 1 0 0xfe000000 0x01000000
75 2 0 0xf8200000 0x00100000
76 3 0 0xf8100000 0x00100000>;
79 compatible = "cfi-flash";
80 reg = <0 0 0x00800000>;
87 reg = <0x00000000 0x00300000>;
91 reg = <0x00300000 0x00100000>;
96 reg = <0x00400000 0x00300000>;
100 reg = <0x00700000 0x00100000>;
107 #address-cells = <1>;
110 compatible = "simple-bus";
111 ranges = <0x00000000 0xf8000000 0x00100000>;
112 reg = <0xf8000000 0x00001000>; // CCSRBAR
116 #address-cells = <1>;
119 compatible = "fsl-i2c";
120 reg = <0x3000 0x100>;
122 interrupt-parent = <&mpic>;
127 #address-cells = <1>;
130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>;
133 interrupt-parent = <&mpic>;
138 #address-cells = <1>;
140 compatible = "fsl,gianfar-mdio";
141 reg = <0x24520 0x20>;
143 phy0: ethernet-phy@0 {
144 interrupt-parent = <&mpic>;
147 device_type = "ethernet-phy";
149 phy1: ethernet-phy@1 {
150 interrupt-parent = <&mpic>;
153 device_type = "ethernet-phy";
155 phy2: ethernet-phy@2 {
156 interrupt-parent = <&mpic>;
159 device_type = "ethernet-phy";
161 phy3: ethernet-phy@3 {
162 interrupt-parent = <&mpic>;
165 device_type = "ethernet-phy";
169 enet0: ethernet@24000 {
171 device_type = "network";
173 compatible = "gianfar";
174 reg = <0x24000 0x1000>;
175 local-mac-address = [ 00 00 00 00 00 00 ];
176 interrupts = <29 2 30 2 34 2>;
177 interrupt-parent = <&mpic>;
178 phy-handle = <&phy0>;
179 phy-connection-type = "rgmii-id";
182 enet1: ethernet@25000 {
184 device_type = "network";
186 compatible = "gianfar";
187 reg = <0x25000 0x1000>;
188 local-mac-address = [ 00 00 00 00 00 00 ];
189 interrupts = <35 2 36 2 40 2>;
190 interrupt-parent = <&mpic>;
191 phy-handle = <&phy1>;
192 phy-connection-type = "rgmii-id";
195 enet2: ethernet@26000 {
197 device_type = "network";
199 compatible = "gianfar";
200 reg = <0x26000 0x1000>;
201 local-mac-address = [ 00 00 00 00 00 00 ];
202 interrupts = <31 2 32 2 33 2>;
203 interrupt-parent = <&mpic>;
204 phy-handle = <&phy2>;
205 phy-connection-type = "rgmii-id";
208 enet3: ethernet@27000 {
210 device_type = "network";
212 compatible = "gianfar";
213 reg = <0x27000 0x1000>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <37 2 38 2 39 2>;
216 interrupt-parent = <&mpic>;
217 phy-handle = <&phy3>;
218 phy-connection-type = "rgmii-id";
221 serial0: serial@4500 {
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
228 interrupt-parent = <&mpic>;
231 serial1: serial@4600 {
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
238 interrupt-parent = <&mpic>;
242 interrupt-controller;
243 #address-cells = <0>;
244 #interrupt-cells = <2>;
245 reg = <0x40000 0x40000>;
246 compatible = "chrp,open-pic";
247 device_type = "open-pic";
250 global-utilities@e0000 {
251 compatible = "fsl,mpc8641-guts";
252 reg = <0xe0000 0x1000>;
257 pci0: pcie@f8008000 {
259 compatible = "fsl,mpc8641-pcie";
261 #interrupt-cells = <1>;
263 #address-cells = <3>;
264 reg = <0xf8008000 0x1000>;
265 bus-range = <0x0 0xff>;
266 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
267 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
268 clock-frequency = <33333333>;
269 interrupt-parent = <&mpic>;
271 interrupt-map-mask = <0xff00 0 0 7>;
273 /* IDSEL 0x11 func 0 - PCI slot 1 */
274 0x8800 0 0 1 &mpic 2 1
275 0x8800 0 0 2 &mpic 3 1
276 0x8800 0 0 3 &mpic 4 1
277 0x8800 0 0 4 &mpic 1 1
279 /* IDSEL 0x11 func 1 - PCI slot 1 */
280 0x8900 0 0 1 &mpic 2 1
281 0x8900 0 0 2 &mpic 3 1
282 0x8900 0 0 3 &mpic 4 1
283 0x8900 0 0 4 &mpic 1 1
285 /* IDSEL 0x11 func 2 - PCI slot 1 */
286 0x8a00 0 0 1 &mpic 2 1
287 0x8a00 0 0 2 &mpic 3 1
288 0x8a00 0 0 3 &mpic 4 1
289 0x8a00 0 0 4 &mpic 1 1
291 /* IDSEL 0x11 func 3 - PCI slot 1 */
292 0x8b00 0 0 1 &mpic 2 1
293 0x8b00 0 0 2 &mpic 3 1
294 0x8b00 0 0 3 &mpic 4 1
295 0x8b00 0 0 4 &mpic 1 1
297 /* IDSEL 0x11 func 4 - PCI slot 1 */
298 0x8c00 0 0 1 &mpic 2 1
299 0x8c00 0 0 2 &mpic 3 1
300 0x8c00 0 0 3 &mpic 4 1
301 0x8c00 0 0 4 &mpic 1 1
303 /* IDSEL 0x11 func 5 - PCI slot 1 */
304 0x8d00 0 0 1 &mpic 2 1
305 0x8d00 0 0 2 &mpic 3 1
306 0x8d00 0 0 3 &mpic 4 1
307 0x8d00 0 0 4 &mpic 1 1
309 /* IDSEL 0x11 func 6 - PCI slot 1 */
310 0x8e00 0 0 1 &mpic 2 1
311 0x8e00 0 0 2 &mpic 3 1
312 0x8e00 0 0 3 &mpic 4 1
313 0x8e00 0 0 4 &mpic 1 1
315 /* IDSEL 0x11 func 7 - PCI slot 1 */
316 0x8f00 0 0 1 &mpic 2 1
317 0x8f00 0 0 2 &mpic 3 1
318 0x8f00 0 0 3 &mpic 4 1
319 0x8f00 0 0 4 &mpic 1 1
321 /* IDSEL 0x12 func 0 - PCI slot 2 */
322 0x9000 0 0 1 &mpic 3 1
323 0x9000 0 0 2 &mpic 4 1
324 0x9000 0 0 3 &mpic 1 1
325 0x9000 0 0 4 &mpic 2 1
327 /* IDSEL 0x12 func 1 - PCI slot 2 */
328 0x9100 0 0 1 &mpic 3 1
329 0x9100 0 0 2 &mpic 4 1
330 0x9100 0 0 3 &mpic 1 1
331 0x9100 0 0 4 &mpic 2 1
333 /* IDSEL 0x12 func 2 - PCI slot 2 */
334 0x9200 0 0 1 &mpic 3 1
335 0x9200 0 0 2 &mpic 4 1
336 0x9200 0 0 3 &mpic 1 1
337 0x9200 0 0 4 &mpic 2 1
339 /* IDSEL 0x12 func 3 - PCI slot 2 */
340 0x9300 0 0 1 &mpic 3 1
341 0x9300 0 0 2 &mpic 4 1
342 0x9300 0 0 3 &mpic 1 1
343 0x9300 0 0 4 &mpic 2 1
345 /* IDSEL 0x12 func 4 - PCI slot 2 */
346 0x9400 0 0 1 &mpic 3 1
347 0x9400 0 0 2 &mpic 4 1
348 0x9400 0 0 3 &mpic 1 1
349 0x9400 0 0 4 &mpic 2 1
351 /* IDSEL 0x12 func 5 - PCI slot 2 */
352 0x9500 0 0 1 &mpic 3 1
353 0x9500 0 0 2 &mpic 4 1
354 0x9500 0 0 3 &mpic 1 1
355 0x9500 0 0 4 &mpic 2 1
357 /* IDSEL 0x12 func 6 - PCI slot 2 */
358 0x9600 0 0 1 &mpic 3 1
359 0x9600 0 0 2 &mpic 4 1
360 0x9600 0 0 3 &mpic 1 1
361 0x9600 0 0 4 &mpic 2 1
363 /* IDSEL 0x12 func 7 - PCI slot 2 */
364 0x9700 0 0 1 &mpic 3 1
365 0x9700 0 0 2 &mpic 4 1
366 0x9700 0 0 3 &mpic 1 1
367 0x9700 0 0 4 &mpic 2 1
370 0xe000 0 0 1 &i8259 12 2
371 0xe100 0 0 2 &i8259 9 2
372 0xe200 0 0 3 &i8259 10 2
373 0xe300 0 0 4 &i8259 112
376 0xe800 0 0 1 &i8259 6 2
379 0xf000 0 0 1 &i8259 7 2
380 0xf100 0 0 1 &i8259 7 2
382 // IDSEL 0x1f IDE/SATA
383 0xf800 0 0 1 &i8259 14 2
384 0xf900 0 0 1 &i8259 5 2
390 #address-cells = <3>;
392 ranges = <0x02000000 0x0 0x80000000
393 0x02000000 0x0 0x80000000
396 0x01000000 0x0 0x00000000
397 0x01000000 0x0 0x00000000
402 #address-cells = <3>;
403 ranges = <0x02000000 0x0 0x80000000
404 0x02000000 0x0 0x80000000
406 0x01000000 0x0 0x00000000
407 0x01000000 0x0 0x00000000
411 #interrupt-cells = <2>;
413 #address-cells = <2>;
414 reg = <0xf000 0 0 0 0>;
415 ranges = <1 0 0x01000000 0 0
417 interrupt-parent = <&i8259>;
419 i8259: interrupt-controller@20 {
423 interrupt-controller;
424 device_type = "interrupt-controller";
425 #address-cells = <0>;
426 #interrupt-cells = <2>;
427 compatible = "chrp,iic";
429 interrupt-parent = <&mpic>;
434 #address-cells = <1>;
435 reg = <1 0x60 1 1 0x64 1>;
436 interrupts = <1 3 12 3>;
442 compatible = "pnpPNP,303";
447 compatible = "pnpPNP,f03";
458 reg = <1 0x400 0x80>;
466 pci1: pcie@f8009000 {
468 compatible = "fsl,mpc8641-pcie";
470 #interrupt-cells = <1>;
472 #address-cells = <3>;
473 reg = <0xf8009000 0x1000>;
474 bus-range = <0 0xff>;
475 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
476 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
477 clock-frequency = <33333333>;
478 interrupt-parent = <&mpic>;
480 interrupt-map-mask = <0xf800 0 0 7>;
483 0x0000 0 0 1 &mpic 4 1
484 0x0000 0 0 2 &mpic 5 1
485 0x0000 0 0 3 &mpic 6 1
486 0x0000 0 0 4 &mpic 7 1
491 #address-cells = <3>;
493 ranges = <0x02000000 0x0 0xa0000000
494 0x02000000 0x0 0xa0000000
497 0x01000000 0x0 0x00000000
498 0x01000000 0x0 0x00000000
502 rapidio0: rapidio@f80c0000 {
503 #address-cells = <2>;
505 compatible = "fsl,rapidio-delta";
506 reg = <0xf80c0000 0x20000>;
507 ranges = <0 0 0xc0000000 0 0x20000000>;
508 interrupt-parent = <&mpic>;
509 /* err_irq bell_outb_irq bell_inb_irq
510 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
511 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;