Merge branches 'release', 'cpuidle-2.6.25' and 'idle' into release
[linux-2.6] / drivers / char / agp / intel-agp.c
1 /*
2  * Intel AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
17 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
18 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
35 #define PCI_DEVICE_ID_INTEL_IGD_HB          0x2A40
36 #define PCI_DEVICE_ID_INTEL_IGD_IG          0x2A42
37
38 /* cover 915 and 945 variants */
39 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
40                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
41                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
42                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
43                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
44                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
45
46 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
47                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
48                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
49                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
50                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
51                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
52                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
53
54 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
55                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
56                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
57
58 extern int agp_memory_reserved;
59
60
61 /* Intel 815 register */
62 #define INTEL_815_APCONT        0x51
63 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
64
65 /* Intel i820 registers */
66 #define INTEL_I820_RDCR         0x51
67 #define INTEL_I820_ERRSTS       0xc8
68
69 /* Intel i840 registers */
70 #define INTEL_I840_MCHCFG       0x50
71 #define INTEL_I840_ERRSTS       0xc8
72
73 /* Intel i850 registers */
74 #define INTEL_I850_MCHCFG       0x50
75 #define INTEL_I850_ERRSTS       0xc8
76
77 /* intel 915G registers */
78 #define I915_GMADDR     0x18
79 #define I915_MMADDR     0x10
80 #define I915_PTEADDR    0x1C
81 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
82 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
83 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
84 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
85 #define I915_IFPADDR    0x60
86
87 /* Intel 965G registers */
88 #define I965_MSAC 0x62
89 #define I965_IFPADDR    0x70
90
91 /* Intel 7505 registers */
92 #define INTEL_I7505_APSIZE      0x74
93 #define INTEL_I7505_NCAPID      0x60
94 #define INTEL_I7505_NISTAT      0x6c
95 #define INTEL_I7505_ATTBASE     0x78
96 #define INTEL_I7505_ERRSTS      0x42
97 #define INTEL_I7505_AGPCTRL     0x70
98 #define INTEL_I7505_MCHCFG      0x50
99
100 static const struct aper_size_info_fixed intel_i810_sizes[] =
101 {
102         {64, 16384, 4},
103         /* The 32M mode still requires a 64k gatt */
104         {32, 8192, 4}
105 };
106
107 #define AGP_DCACHE_MEMORY       1
108 #define AGP_PHYS_MEMORY         2
109 #define INTEL_AGP_CACHED_MEMORY 3
110
111 static struct gatt_mask intel_i810_masks[] =
112 {
113         {.mask = I810_PTE_VALID, .type = 0},
114         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
115         {.mask = I810_PTE_VALID, .type = 0},
116         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
117          .type = INTEL_AGP_CACHED_MEMORY}
118 };
119
120 static struct _intel_private {
121         struct pci_dev *pcidev; /* device one */
122         u8 __iomem *registers;
123         u32 __iomem *gtt;               /* I915G */
124         int num_dcache_entries;
125         /* gtt_entries is the number of gtt entries that are already mapped
126          * to stolen memory.  Stolen memory is larger than the memory mapped
127          * through gtt_entries, as it includes some reserved space for the BIOS
128          * popup and for the GTT.
129          */
130         int gtt_entries;                        /* i830+ */
131         union {
132                 void __iomem *i9xx_flush_page;
133                 void *i8xx_flush_page;
134         };
135         struct page *i8xx_page;
136         struct resource ifp_resource;
137         int resource_valid;
138 } intel_private;
139
140 static int intel_i810_fetch_size(void)
141 {
142         u32 smram_miscc;
143         struct aper_size_info_fixed *values;
144
145         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
146         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
147
148         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
149                 printk(KERN_WARNING PFX "i810 is disabled\n");
150                 return 0;
151         }
152         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
153                 agp_bridge->previous_size =
154                         agp_bridge->current_size = (void *) (values + 1);
155                 agp_bridge->aperture_size_idx = 1;
156                 return values[1].size;
157         } else {
158                 agp_bridge->previous_size =
159                         agp_bridge->current_size = (void *) (values);
160                 agp_bridge->aperture_size_idx = 0;
161                 return values[0].size;
162         }
163
164         return 0;
165 }
166
167 static int intel_i810_configure(void)
168 {
169         struct aper_size_info_fixed *current_size;
170         u32 temp;
171         int i;
172
173         current_size = A_SIZE_FIX(agp_bridge->current_size);
174
175         if (!intel_private.registers) {
176                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
177                 temp &= 0xfff80000;
178
179                 intel_private.registers = ioremap(temp, 128 * 4096);
180                 if (!intel_private.registers) {
181                         printk(KERN_ERR PFX "Unable to remap memory.\n");
182                         return -ENOMEM;
183                 }
184         }
185
186         if ((readl(intel_private.registers+I810_DRAM_CTL)
187                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
188                 /* This will need to be dynamically assigned */
189                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
190                 intel_private.num_dcache_entries = 1024;
191         }
192         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
193         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
194         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
195         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
196
197         if (agp_bridge->driver->needs_scratch_page) {
198                 for (i = 0; i < current_size->num_entries; i++) {
199                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
200                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
201                 }
202         }
203         global_cache_flush();
204         return 0;
205 }
206
207 static void intel_i810_cleanup(void)
208 {
209         writel(0, intel_private.registers+I810_PGETBL_CTL);
210         readl(intel_private.registers); /* PCI Posting. */
211         iounmap(intel_private.registers);
212 }
213
214 static void intel_i810_tlbflush(struct agp_memory *mem)
215 {
216         return;
217 }
218
219 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
220 {
221         return;
222 }
223
224 /* Exists to support ARGB cursors */
225 static void *i8xx_alloc_pages(void)
226 {
227         struct page *page;
228
229         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
230         if (page == NULL)
231                 return NULL;
232
233         if (set_pages_uc(page, 4) < 0) {
234                 set_pages_wb(page, 4);
235                 __free_pages(page, 2);
236                 return NULL;
237         }
238         get_page(page);
239         atomic_inc(&agp_bridge->current_memory_agp);
240         return page_address(page);
241 }
242
243 static void i8xx_destroy_pages(void *addr)
244 {
245         struct page *page;
246
247         if (addr == NULL)
248                 return;
249
250         page = virt_to_page(addr);
251         set_pages_wb(page, 4);
252         put_page(page);
253         __free_pages(page, 2);
254         atomic_dec(&agp_bridge->current_memory_agp);
255 }
256
257 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
258                                         int type)
259 {
260         if (type < AGP_USER_TYPES)
261                 return type;
262         else if (type == AGP_USER_CACHED_MEMORY)
263                 return INTEL_AGP_CACHED_MEMORY;
264         else
265                 return 0;
266 }
267
268 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
269                                 int type)
270 {
271         int i, j, num_entries;
272         void *temp;
273         int ret = -EINVAL;
274         int mask_type;
275
276         if (mem->page_count == 0)
277                 goto out;
278
279         temp = agp_bridge->current_size;
280         num_entries = A_SIZE_FIX(temp)->num_entries;
281
282         if ((pg_start + mem->page_count) > num_entries)
283                 goto out_err;
284
285
286         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
287                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
288                         ret = -EBUSY;
289                         goto out_err;
290                 }
291         }
292
293         if (type != mem->type)
294                 goto out_err;
295
296         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
297
298         switch (mask_type) {
299         case AGP_DCACHE_MEMORY:
300                 if (!mem->is_flushed)
301                         global_cache_flush();
302                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
303                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
304                                intel_private.registers+I810_PTE_BASE+(i*4));
305                 }
306                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
307                 break;
308         case AGP_PHYS_MEMORY:
309         case AGP_NORMAL_MEMORY:
310                 if (!mem->is_flushed)
311                         global_cache_flush();
312                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
313                         writel(agp_bridge->driver->mask_memory(agp_bridge,
314                                                                mem->memory[i],
315                                                                mask_type),
316                                intel_private.registers+I810_PTE_BASE+(j*4));
317                 }
318                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
319                 break;
320         default:
321                 goto out_err;
322         }
323
324         agp_bridge->driver->tlb_flush(mem);
325 out:
326         ret = 0;
327 out_err:
328         mem->is_flushed = 1;
329         return ret;
330 }
331
332 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
333                                 int type)
334 {
335         int i;
336
337         if (mem->page_count == 0)
338                 return 0;
339
340         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
341                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
342         }
343         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
344
345         agp_bridge->driver->tlb_flush(mem);
346         return 0;
347 }
348
349 /*
350  * The i810/i830 requires a physical address to program its mouse
351  * pointer into hardware.
352  * However the Xserver still writes to it through the agp aperture.
353  */
354 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
355 {
356         struct agp_memory *new;
357         void *addr;
358
359         switch (pg_count) {
360         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
361                 break;
362         case 4:
363                 /* kludge to get 4 physical pages for ARGB cursor */
364                 addr = i8xx_alloc_pages();
365                 break;
366         default:
367                 return NULL;
368         }
369
370         if (addr == NULL)
371                 return NULL;
372
373         new = agp_create_memory(pg_count);
374         if (new == NULL)
375                 return NULL;
376
377         new->memory[0] = virt_to_gart(addr);
378         if (pg_count == 4) {
379                 /* kludge to get 4 physical pages for ARGB cursor */
380                 new->memory[1] = new->memory[0] + PAGE_SIZE;
381                 new->memory[2] = new->memory[1] + PAGE_SIZE;
382                 new->memory[3] = new->memory[2] + PAGE_SIZE;
383         }
384         new->page_count = pg_count;
385         new->num_scratch_pages = pg_count;
386         new->type = AGP_PHYS_MEMORY;
387         new->physical = new->memory[0];
388         return new;
389 }
390
391 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
392 {
393         struct agp_memory *new;
394
395         if (type == AGP_DCACHE_MEMORY) {
396                 if (pg_count != intel_private.num_dcache_entries)
397                         return NULL;
398
399                 new = agp_create_memory(1);
400                 if (new == NULL)
401                         return NULL;
402
403                 new->type = AGP_DCACHE_MEMORY;
404                 new->page_count = pg_count;
405                 new->num_scratch_pages = 0;
406                 agp_free_page_array(new);
407                 return new;
408         }
409         if (type == AGP_PHYS_MEMORY)
410                 return alloc_agpphysmem_i8xx(pg_count, type);
411         return NULL;
412 }
413
414 static void intel_i810_free_by_type(struct agp_memory *curr)
415 {
416         agp_free_key(curr->key);
417         if (curr->type == AGP_PHYS_MEMORY) {
418                 if (curr->page_count == 4)
419                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
420                 else {
421                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
422                                                              AGP_PAGE_DESTROY_UNMAP);
423                         agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
424                                                              AGP_PAGE_DESTROY_FREE);
425                 }
426                 agp_free_page_array(curr);
427         }
428         kfree(curr);
429 }
430
431 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
432         unsigned long addr, int type)
433 {
434         /* Type checking must be done elsewhere */
435         return addr | bridge->driver->masks[type].mask;
436 }
437
438 static struct aper_size_info_fixed intel_i830_sizes[] =
439 {
440         {128, 32768, 5},
441         /* The 64M mode still requires a 128k gatt */
442         {64, 16384, 5},
443         {256, 65536, 6},
444         {512, 131072, 7},
445 };
446
447 static void intel_i830_init_gtt_entries(void)
448 {
449         u16 gmch_ctrl;
450         int gtt_entries;
451         u8 rdct;
452         int local = 0;
453         static const int ddt[4] = { 0, 16, 32, 64 };
454         int size; /* reserved space (in kb) at the top of stolen memory */
455
456         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
457
458         if (IS_I965) {
459                 u32 pgetbl_ctl;
460                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
461
462                 /* The 965 has a field telling us the size of the GTT,
463                  * which may be larger than what is necessary to map the
464                  * aperture.
465                  */
466                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
467                 case I965_PGETBL_SIZE_128KB:
468                         size = 128;
469                         break;
470                 case I965_PGETBL_SIZE_256KB:
471                         size = 256;
472                         break;
473                 case I965_PGETBL_SIZE_512KB:
474                         size = 512;
475                         break;
476                 case I965_PGETBL_SIZE_1MB:
477                         size = 1024;
478                         break;
479                 case I965_PGETBL_SIZE_2MB:
480                         size = 2048;
481                         break;
482                 case I965_PGETBL_SIZE_1_5MB:
483                         size = 1024 + 512;
484                         break;
485                 default:
486                         printk(KERN_INFO PFX "Unknown page table size, "
487                                "assuming 512KB\n");
488                         size = 512;
489                 }
490                 size += 4; /* add in BIOS popup space */
491         } else if (IS_G33) {
492         /* G33's GTT size defined in gmch_ctrl */
493                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
494                 case G33_PGETBL_SIZE_1M:
495                         size = 1024;
496                         break;
497                 case G33_PGETBL_SIZE_2M:
498                         size = 2048;
499                         break;
500                 default:
501                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
502                                 "assuming 512KB\n",
503                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
504                         size = 512;
505                 }
506                 size += 4;
507         } else {
508                 /* On previous hardware, the GTT size was just what was
509                  * required to map the aperture.
510                  */
511                 size = agp_bridge->driver->fetch_size() + 4;
512         }
513
514         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
515             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
516                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
517                 case I830_GMCH_GMS_STOLEN_512:
518                         gtt_entries = KB(512) - KB(size);
519                         break;
520                 case I830_GMCH_GMS_STOLEN_1024:
521                         gtt_entries = MB(1) - KB(size);
522                         break;
523                 case I830_GMCH_GMS_STOLEN_8192:
524                         gtt_entries = MB(8) - KB(size);
525                         break;
526                 case I830_GMCH_GMS_LOCAL:
527                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
528                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
529                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
530                         local = 1;
531                         break;
532                 default:
533                         gtt_entries = 0;
534                         break;
535                 }
536         } else {
537                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
538                 case I855_GMCH_GMS_STOLEN_1M:
539                         gtt_entries = MB(1) - KB(size);
540                         break;
541                 case I855_GMCH_GMS_STOLEN_4M:
542                         gtt_entries = MB(4) - KB(size);
543                         break;
544                 case I855_GMCH_GMS_STOLEN_8M:
545                         gtt_entries = MB(8) - KB(size);
546                         break;
547                 case I855_GMCH_GMS_STOLEN_16M:
548                         gtt_entries = MB(16) - KB(size);
549                         break;
550                 case I855_GMCH_GMS_STOLEN_32M:
551                         gtt_entries = MB(32) - KB(size);
552                         break;
553                 case I915_GMCH_GMS_STOLEN_48M:
554                         /* Check it's really I915G */
555                         if (IS_I915 || IS_I965 || IS_G33)
556                                 gtt_entries = MB(48) - KB(size);
557                         else
558                                 gtt_entries = 0;
559                         break;
560                 case I915_GMCH_GMS_STOLEN_64M:
561                         /* Check it's really I915G */
562                         if (IS_I915 || IS_I965 || IS_G33)
563                                 gtt_entries = MB(64) - KB(size);
564                         else
565                                 gtt_entries = 0;
566                         break;
567                 case G33_GMCH_GMS_STOLEN_128M:
568                         if (IS_G33)
569                                 gtt_entries = MB(128) - KB(size);
570                         else
571                                 gtt_entries = 0;
572                         break;
573                 case G33_GMCH_GMS_STOLEN_256M:
574                         if (IS_G33)
575                                 gtt_entries = MB(256) - KB(size);
576                         else
577                                 gtt_entries = 0;
578                         break;
579                 default:
580                         gtt_entries = 0;
581                         break;
582                 }
583         }
584         if (gtt_entries > 0)
585                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
586                        gtt_entries / KB(1), local ? "local" : "stolen");
587         else
588                 printk(KERN_INFO PFX
589                        "No pre-allocated video memory detected.\n");
590         gtt_entries /= KB(4);
591
592         intel_private.gtt_entries = gtt_entries;
593 }
594
595 static void intel_i830_fini_flush(void)
596 {
597         kunmap(intel_private.i8xx_page);
598         intel_private.i8xx_flush_page = NULL;
599         unmap_page_from_agp(intel_private.i8xx_page);
600
601         __free_page(intel_private.i8xx_page);
602         intel_private.i8xx_page = NULL;
603 }
604
605 static void intel_i830_setup_flush(void)
606 {
607         /* return if we've already set the flush mechanism up */
608         if (intel_private.i8xx_page)
609                 return;
610
611         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
612         if (!intel_private.i8xx_page)
613                 return;
614
615         /* make page uncached */
616         map_page_into_agp(intel_private.i8xx_page);
617
618         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
619         if (!intel_private.i8xx_flush_page)
620                 intel_i830_fini_flush();
621 }
622
623 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
624 {
625         unsigned int *pg = intel_private.i8xx_flush_page;
626         int i;
627
628         for (i = 0; i < 256; i += 2)
629                 *(pg + i) = i;
630
631         wmb();
632 }
633
634 /* The intel i830 automatically initializes the agp aperture during POST.
635  * Use the memory already set aside for in the GTT.
636  */
637 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
638 {
639         int page_order;
640         struct aper_size_info_fixed *size;
641         int num_entries;
642         u32 temp;
643
644         size = agp_bridge->current_size;
645         page_order = size->page_order;
646         num_entries = size->num_entries;
647         agp_bridge->gatt_table_real = NULL;
648
649         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
650         temp &= 0xfff80000;
651
652         intel_private.registers = ioremap(temp, 128 * 4096);
653         if (!intel_private.registers)
654                 return -ENOMEM;
655
656         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
657         global_cache_flush();   /* FIXME: ?? */
658
659         /* we have to call this as early as possible after the MMIO base address is known */
660         intel_i830_init_gtt_entries();
661
662         agp_bridge->gatt_table = NULL;
663
664         agp_bridge->gatt_bus_addr = temp;
665
666         return 0;
667 }
668
669 /* Return the gatt table to a sane state. Use the top of stolen
670  * memory for the GTT.
671  */
672 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
673 {
674         return 0;
675 }
676
677 static int intel_i830_fetch_size(void)
678 {
679         u16 gmch_ctrl;
680         struct aper_size_info_fixed *values;
681
682         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
683
684         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
685             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
686                 /* 855GM/852GM/865G has 128MB aperture size */
687                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
688                 agp_bridge->aperture_size_idx = 0;
689                 return values[0].size;
690         }
691
692         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
693
694         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
695                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
696                 agp_bridge->aperture_size_idx = 0;
697                 return values[0].size;
698         } else {
699                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
700                 agp_bridge->aperture_size_idx = 1;
701                 return values[1].size;
702         }
703
704         return 0;
705 }
706
707 static int intel_i830_configure(void)
708 {
709         struct aper_size_info_fixed *current_size;
710         u32 temp;
711         u16 gmch_ctrl;
712         int i;
713
714         current_size = A_SIZE_FIX(agp_bridge->current_size);
715
716         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
717         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
718
719         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
720         gmch_ctrl |= I830_GMCH_ENABLED;
721         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
722
723         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
724         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
725
726         if (agp_bridge->driver->needs_scratch_page) {
727                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
728                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
729                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
730                 }
731         }
732
733         global_cache_flush();
734
735         intel_i830_setup_flush();
736         return 0;
737 }
738
739 static void intel_i830_cleanup(void)
740 {
741         iounmap(intel_private.registers);
742 }
743
744 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
745                                      int type)
746 {
747         int i, j, num_entries;
748         void *temp;
749         int ret = -EINVAL;
750         int mask_type;
751
752         if (mem->page_count == 0)
753                 goto out;
754
755         temp = agp_bridge->current_size;
756         num_entries = A_SIZE_FIX(temp)->num_entries;
757
758         if (pg_start < intel_private.gtt_entries) {
759                 printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
760                                 pg_start, intel_private.gtt_entries);
761
762                 printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n");
763                 goto out_err;
764         }
765
766         if ((pg_start + mem->page_count) > num_entries)
767                 goto out_err;
768
769         /* The i830 can't check the GTT for entries since its read only,
770          * depend on the caller to make the correct offset decisions.
771          */
772
773         if (type != mem->type)
774                 goto out_err;
775
776         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
777
778         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
779             mask_type != INTEL_AGP_CACHED_MEMORY)
780                 goto out_err;
781
782         if (!mem->is_flushed)
783                 global_cache_flush();
784
785         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
786                 writel(agp_bridge->driver->mask_memory(agp_bridge,
787                                                        mem->memory[i], mask_type),
788                        intel_private.registers+I810_PTE_BASE+(j*4));
789         }
790         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
791         agp_bridge->driver->tlb_flush(mem);
792
793 out:
794         ret = 0;
795 out_err:
796         mem->is_flushed = 1;
797         return ret;
798 }
799
800 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
801                                      int type)
802 {
803         int i;
804
805         if (mem->page_count == 0)
806                 return 0;
807
808         if (pg_start < intel_private.gtt_entries) {
809                 printk(KERN_INFO PFX "Trying to disable local/stolen memory\n");
810                 return -EINVAL;
811         }
812
813         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
814                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
815         }
816         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
817
818         agp_bridge->driver->tlb_flush(mem);
819         return 0;
820 }
821
822 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
823 {
824         if (type == AGP_PHYS_MEMORY)
825                 return alloc_agpphysmem_i8xx(pg_count, type);
826         /* always return NULL for other allocation types for now */
827         return NULL;
828 }
829
830 static int intel_alloc_chipset_flush_resource(void)
831 {
832         int ret;
833         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
834                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
835                                      pcibios_align_resource, agp_bridge->dev);
836
837         return ret;
838 }
839
840 static void intel_i915_setup_chipset_flush(void)
841 {
842         int ret;
843         u32 temp;
844
845         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
846         if (!(temp & 0x1)) {
847                 intel_alloc_chipset_flush_resource();
848                 intel_private.resource_valid = 1;
849                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
850         } else {
851                 temp &= ~1;
852
853                 intel_private.resource_valid = 1;
854                 intel_private.ifp_resource.start = temp;
855                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
856                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
857                 /* some BIOSes reserve this area in a pnp some don't */
858                 if (ret)
859                         intel_private.resource_valid = 0;
860         }
861 }
862
863 static void intel_i965_g33_setup_chipset_flush(void)
864 {
865         u32 temp_hi, temp_lo;
866         int ret;
867
868         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
869         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
870
871         if (!(temp_lo & 0x1)) {
872
873                 intel_alloc_chipset_flush_resource();
874
875                 intel_private.resource_valid = 1;
876                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
877                         upper_32_bits(intel_private.ifp_resource.start));
878                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
879         } else {
880                 u64 l64;
881
882                 temp_lo &= ~0x1;
883                 l64 = ((u64)temp_hi << 32) | temp_lo;
884
885                 intel_private.resource_valid = 1;
886                 intel_private.ifp_resource.start = l64;
887                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
888                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
889                 /* some BIOSes reserve this area in a pnp some don't */
890                 if (ret)
891                         intel_private.resource_valid = 0;
892         }
893 }
894
895 static void intel_i9xx_setup_flush(void)
896 {
897         /* return if already configured */
898         if (intel_private.ifp_resource.start)
899                 return;
900
901         /* setup a resource for this object */
902         intel_private.ifp_resource.name = "Intel Flush Page";
903         intel_private.ifp_resource.flags = IORESOURCE_MEM;
904
905         /* Setup chipset flush for 915 */
906         if (IS_I965 || IS_G33) {
907                 intel_i965_g33_setup_chipset_flush();
908         } else {
909                 intel_i915_setup_chipset_flush();
910         }
911
912         if (intel_private.ifp_resource.start) {
913                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
914                 if (!intel_private.i9xx_flush_page)
915                         printk(KERN_INFO "unable to ioremap flush  page - no chipset flushing");
916         }
917 }
918
919 static int intel_i915_configure(void)
920 {
921         struct aper_size_info_fixed *current_size;
922         u32 temp;
923         u16 gmch_ctrl;
924         int i;
925
926         current_size = A_SIZE_FIX(agp_bridge->current_size);
927
928         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
929
930         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
931
932         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
933         gmch_ctrl |= I830_GMCH_ENABLED;
934         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
935
936         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
937         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
938
939         if (agp_bridge->driver->needs_scratch_page) {
940                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
941                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
942                         readl(intel_private.gtt+i);     /* PCI Posting. */
943                 }
944         }
945
946         global_cache_flush();
947
948         intel_i9xx_setup_flush();
949
950         return 0;
951 }
952
953 static void intel_i915_cleanup(void)
954 {
955         if (intel_private.i9xx_flush_page)
956                 iounmap(intel_private.i9xx_flush_page);
957         if (intel_private.resource_valid)
958                 release_resource(&intel_private.ifp_resource);
959         intel_private.ifp_resource.start = 0;
960         intel_private.resource_valid = 0;
961         iounmap(intel_private.gtt);
962         iounmap(intel_private.registers);
963 }
964
965 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
966 {
967         if (intel_private.i9xx_flush_page)
968                 writel(1, intel_private.i9xx_flush_page);
969 }
970
971 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
972                                      int type)
973 {
974         int i, j, num_entries;
975         void *temp;
976         int ret = -EINVAL;
977         int mask_type;
978
979         if (mem->page_count == 0)
980                 goto out;
981
982         temp = agp_bridge->current_size;
983         num_entries = A_SIZE_FIX(temp)->num_entries;
984
985         if (pg_start < intel_private.gtt_entries) {
986                 printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
987                                 pg_start, intel_private.gtt_entries);
988
989                 printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n");
990                 goto out_err;
991         }
992
993         if ((pg_start + mem->page_count) > num_entries)
994                 goto out_err;
995
996         /* The i915 can't check the GTT for entries since its read only,
997          * depend on the caller to make the correct offset decisions.
998          */
999
1000         if (type != mem->type)
1001                 goto out_err;
1002
1003         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1004
1005         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1006             mask_type != INTEL_AGP_CACHED_MEMORY)
1007                 goto out_err;
1008
1009         if (!mem->is_flushed)
1010                 global_cache_flush();
1011
1012         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1013                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1014                         mem->memory[i], mask_type), intel_private.gtt+j);
1015         }
1016
1017         readl(intel_private.gtt+j-1);
1018         agp_bridge->driver->tlb_flush(mem);
1019
1020  out:
1021         ret = 0;
1022  out_err:
1023         mem->is_flushed = 1;
1024         return ret;
1025 }
1026
1027 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1028                                      int type)
1029 {
1030         int i;
1031
1032         if (mem->page_count == 0)
1033                 return 0;
1034
1035         if (pg_start < intel_private.gtt_entries) {
1036                 printk(KERN_INFO PFX "Trying to disable local/stolen memory\n");
1037                 return -EINVAL;
1038         }
1039
1040         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1041                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1042
1043         readl(intel_private.gtt+i-1);
1044
1045         agp_bridge->driver->tlb_flush(mem);
1046         return 0;
1047 }
1048
1049 /* Return the aperture size by just checking the resource length.  The effect
1050  * described in the spec of the MSAC registers is just changing of the
1051  * resource size.
1052  */
1053 static int intel_i9xx_fetch_size(void)
1054 {
1055         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1056         int aper_size; /* size in megabytes */
1057         int i;
1058
1059         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1060
1061         for (i = 0; i < num_sizes; i++) {
1062                 if (aper_size == intel_i830_sizes[i].size) {
1063                         agp_bridge->current_size = intel_i830_sizes + i;
1064                         agp_bridge->previous_size = agp_bridge->current_size;
1065                         return aper_size;
1066                 }
1067         }
1068
1069         return 0;
1070 }
1071
1072 /* The intel i915 automatically initializes the agp aperture during POST.
1073  * Use the memory already set aside for in the GTT.
1074  */
1075 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1076 {
1077         int page_order;
1078         struct aper_size_info_fixed *size;
1079         int num_entries;
1080         u32 temp, temp2;
1081         int gtt_map_size = 256 * 1024;
1082
1083         size = agp_bridge->current_size;
1084         page_order = size->page_order;
1085         num_entries = size->num_entries;
1086         agp_bridge->gatt_table_real = NULL;
1087
1088         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1089         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1090
1091         if (IS_G33)
1092             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1093         intel_private.gtt = ioremap(temp2, gtt_map_size);
1094         if (!intel_private.gtt)
1095                 return -ENOMEM;
1096
1097         temp &= 0xfff80000;
1098
1099         intel_private.registers = ioremap(temp, 128 * 4096);
1100         if (!intel_private.registers) {
1101                 iounmap(intel_private.gtt);
1102                 return -ENOMEM;
1103         }
1104
1105         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1106         global_cache_flush();   /* FIXME: ? */
1107
1108         /* we have to call this as early as possible after the MMIO base address is known */
1109         intel_i830_init_gtt_entries();
1110
1111         agp_bridge->gatt_table = NULL;
1112
1113         agp_bridge->gatt_bus_addr = temp;
1114
1115         return 0;
1116 }
1117
1118 /*
1119  * The i965 supports 36-bit physical addresses, but to keep
1120  * the format of the GTT the same, the bits that don't fit
1121  * in a 32-bit word are shifted down to bits 4..7.
1122  *
1123  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1124  * is always zero on 32-bit architectures, so no need to make
1125  * this conditional.
1126  */
1127 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1128         unsigned long addr, int type)
1129 {
1130         /* Shift high bits down */
1131         addr |= (addr >> 28) & 0xf0;
1132
1133         /* Type checking must be done elsewhere */
1134         return addr | bridge->driver->masks[type].mask;
1135 }
1136
1137 /* The intel i965 automatically initializes the agp aperture during POST.
1138  * Use the memory already set aside for in the GTT.
1139  */
1140 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1141 {
1142        int page_order;
1143        struct aper_size_info_fixed *size;
1144        int num_entries;
1145        u32 temp;
1146        int gtt_offset, gtt_size;
1147
1148        size = agp_bridge->current_size;
1149        page_order = size->page_order;
1150        num_entries = size->num_entries;
1151        agp_bridge->gatt_table_real = NULL;
1152
1153        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1154
1155        temp &= 0xfff00000;
1156
1157        if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1158                gtt_offset = gtt_size = MB(2);
1159        else
1160                gtt_offset = gtt_size = KB(512);
1161
1162        intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1163
1164        if (!intel_private.gtt)
1165                return -ENOMEM;
1166
1167        intel_private.registers = ioremap(temp, 128 * 4096);
1168        if (!intel_private.registers) {
1169                 iounmap(intel_private.gtt);
1170                 return -ENOMEM;
1171         }
1172
1173        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1174        global_cache_flush();   /* FIXME: ? */
1175
1176        /* we have to call this as early as possible after the MMIO base address is known */
1177        intel_i830_init_gtt_entries();
1178
1179        agp_bridge->gatt_table = NULL;
1180
1181        agp_bridge->gatt_bus_addr = temp;
1182
1183        return 0;
1184 }
1185
1186
1187 static int intel_fetch_size(void)
1188 {
1189         int i;
1190         u16 temp;
1191         struct aper_size_info_16 *values;
1192
1193         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1194         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1195
1196         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1197                 if (temp == values[i].size_value) {
1198                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1199                         agp_bridge->aperture_size_idx = i;
1200                         return values[i].size;
1201                 }
1202         }
1203
1204         return 0;
1205 }
1206
1207 static int __intel_8xx_fetch_size(u8 temp)
1208 {
1209         int i;
1210         struct aper_size_info_8 *values;
1211
1212         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1213
1214         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1215                 if (temp == values[i].size_value) {
1216                         agp_bridge->previous_size =
1217                                 agp_bridge->current_size = (void *) (values + i);
1218                         agp_bridge->aperture_size_idx = i;
1219                         return values[i].size;
1220                 }
1221         }
1222         return 0;
1223 }
1224
1225 static int intel_8xx_fetch_size(void)
1226 {
1227         u8 temp;
1228
1229         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1230         return __intel_8xx_fetch_size(temp);
1231 }
1232
1233 static int intel_815_fetch_size(void)
1234 {
1235         u8 temp;
1236
1237         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1238          * one non-reserved bit, so mask the others out ... */
1239         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1240         temp &= (1 << 3);
1241
1242         return __intel_8xx_fetch_size(temp);
1243 }
1244
1245 static void intel_tlbflush(struct agp_memory *mem)
1246 {
1247         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1248         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1249 }
1250
1251
1252 static void intel_8xx_tlbflush(struct agp_memory *mem)
1253 {
1254         u32 temp;
1255         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1256         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1257         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1258         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1259 }
1260
1261
1262 static void intel_cleanup(void)
1263 {
1264         u16 temp;
1265         struct aper_size_info_16 *previous_size;
1266
1267         previous_size = A_SIZE_16(agp_bridge->previous_size);
1268         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1269         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1270         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1271 }
1272
1273
1274 static void intel_8xx_cleanup(void)
1275 {
1276         u16 temp;
1277         struct aper_size_info_8 *previous_size;
1278
1279         previous_size = A_SIZE_8(agp_bridge->previous_size);
1280         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1281         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1282         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1283 }
1284
1285
1286 static int intel_configure(void)
1287 {
1288         u32 temp;
1289         u16 temp2;
1290         struct aper_size_info_16 *current_size;
1291
1292         current_size = A_SIZE_16(agp_bridge->current_size);
1293
1294         /* aperture size */
1295         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1296
1297         /* address to map to */
1298         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1299         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1300
1301         /* attbase - aperture base */
1302         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1303
1304         /* agpctrl */
1305         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1306
1307         /* paccfg/nbxcfg */
1308         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1309         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1310                         (temp2 & ~(1 << 10)) | (1 << 9));
1311         /* clear any possible error conditions */
1312         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1313         return 0;
1314 }
1315
1316 static int intel_815_configure(void)
1317 {
1318         u32 temp, addr;
1319         u8 temp2;
1320         struct aper_size_info_8 *current_size;
1321
1322         /* attbase - aperture base */
1323         /* the Intel 815 chipset spec. says that bits 29-31 in the
1324         * ATTBASE register are reserved -> try not to write them */
1325         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1326                 printk(KERN_EMERG PFX "gatt bus addr too high");
1327                 return -EINVAL;
1328         }
1329
1330         current_size = A_SIZE_8(agp_bridge->current_size);
1331
1332         /* aperture size */
1333         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1334                         current_size->size_value);
1335
1336         /* address to map to */
1337         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1338         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1339
1340         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1341         addr &= INTEL_815_ATTBASE_MASK;
1342         addr |= agp_bridge->gatt_bus_addr;
1343         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1344
1345         /* agpctrl */
1346         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1347
1348         /* apcont */
1349         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1350         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1351
1352         /* clear any possible error conditions */
1353         /* Oddness : this chipset seems to have no ERRSTS register ! */
1354         return 0;
1355 }
1356
1357 static void intel_820_tlbflush(struct agp_memory *mem)
1358 {
1359         return;
1360 }
1361
1362 static void intel_820_cleanup(void)
1363 {
1364         u8 temp;
1365         struct aper_size_info_8 *previous_size;
1366
1367         previous_size = A_SIZE_8(agp_bridge->previous_size);
1368         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1369         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1370                         temp & ~(1 << 1));
1371         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1372                         previous_size->size_value);
1373 }
1374
1375
1376 static int intel_820_configure(void)
1377 {
1378         u32 temp;
1379         u8 temp2;
1380         struct aper_size_info_8 *current_size;
1381
1382         current_size = A_SIZE_8(agp_bridge->current_size);
1383
1384         /* aperture size */
1385         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1386
1387         /* address to map to */
1388         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1389         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1390
1391         /* attbase - aperture base */
1392         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1393
1394         /* agpctrl */
1395         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1396
1397         /* global enable aperture access */
1398         /* This flag is not accessed through MCHCFG register as in */
1399         /* i850 chipset. */
1400         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1401         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1402         /* clear any possible AGP-related error conditions */
1403         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1404         return 0;
1405 }
1406
1407 static int intel_840_configure(void)
1408 {
1409         u32 temp;
1410         u16 temp2;
1411         struct aper_size_info_8 *current_size;
1412
1413         current_size = A_SIZE_8(agp_bridge->current_size);
1414
1415         /* aperture size */
1416         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1417
1418         /* address to map to */
1419         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1420         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1421
1422         /* attbase - aperture base */
1423         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1424
1425         /* agpctrl */
1426         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1427
1428         /* mcgcfg */
1429         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1430         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1431         /* clear any possible error conditions */
1432         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1433         return 0;
1434 }
1435
1436 static int intel_845_configure(void)
1437 {
1438         u32 temp;
1439         u8 temp2;
1440         struct aper_size_info_8 *current_size;
1441
1442         current_size = A_SIZE_8(agp_bridge->current_size);
1443
1444         /* aperture size */
1445         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1446
1447         if (agp_bridge->apbase_config != 0) {
1448                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1449                                        agp_bridge->apbase_config);
1450         } else {
1451                 /* address to map to */
1452                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1453                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1454                 agp_bridge->apbase_config = temp;
1455         }
1456
1457         /* attbase - aperture base */
1458         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1459
1460         /* agpctrl */
1461         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1462
1463         /* agpm */
1464         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1465         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1466         /* clear any possible error conditions */
1467         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1468
1469         intel_i830_setup_flush();
1470         return 0;
1471 }
1472
1473 static int intel_850_configure(void)
1474 {
1475         u32 temp;
1476         u16 temp2;
1477         struct aper_size_info_8 *current_size;
1478
1479         current_size = A_SIZE_8(agp_bridge->current_size);
1480
1481         /* aperture size */
1482         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1483
1484         /* address to map to */
1485         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1486         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1487
1488         /* attbase - aperture base */
1489         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1490
1491         /* agpctrl */
1492         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1493
1494         /* mcgcfg */
1495         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1496         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1497         /* clear any possible AGP-related error conditions */
1498         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1499         return 0;
1500 }
1501
1502 static int intel_860_configure(void)
1503 {
1504         u32 temp;
1505         u16 temp2;
1506         struct aper_size_info_8 *current_size;
1507
1508         current_size = A_SIZE_8(agp_bridge->current_size);
1509
1510         /* aperture size */
1511         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1512
1513         /* address to map to */
1514         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1515         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1516
1517         /* attbase - aperture base */
1518         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1519
1520         /* agpctrl */
1521         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1522
1523         /* mcgcfg */
1524         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1525         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1526         /* clear any possible AGP-related error conditions */
1527         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1528         return 0;
1529 }
1530
1531 static int intel_830mp_configure(void)
1532 {
1533         u32 temp;
1534         u16 temp2;
1535         struct aper_size_info_8 *current_size;
1536
1537         current_size = A_SIZE_8(agp_bridge->current_size);
1538
1539         /* aperture size */
1540         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1541
1542         /* address to map to */
1543         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1544         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1545
1546         /* attbase - aperture base */
1547         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1548
1549         /* agpctrl */
1550         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1551
1552         /* gmch */
1553         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1554         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1555         /* clear any possible AGP-related error conditions */
1556         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1557         return 0;
1558 }
1559
1560 static int intel_7505_configure(void)
1561 {
1562         u32 temp;
1563         u16 temp2;
1564         struct aper_size_info_8 *current_size;
1565
1566         current_size = A_SIZE_8(agp_bridge->current_size);
1567
1568         /* aperture size */
1569         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1570
1571         /* address to map to */
1572         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1573         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1574
1575         /* attbase - aperture base */
1576         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1577
1578         /* agpctrl */
1579         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1580
1581         /* mchcfg */
1582         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1583         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1584
1585         return 0;
1586 }
1587
1588 /* Setup function */
1589 static const struct gatt_mask intel_generic_masks[] =
1590 {
1591         {.mask = 0x00000017, .type = 0}
1592 };
1593
1594 static const struct aper_size_info_8 intel_815_sizes[2] =
1595 {
1596         {64, 16384, 4, 0},
1597         {32, 8192, 3, 8},
1598 };
1599
1600 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1601 {
1602         {256, 65536, 6, 0},
1603         {128, 32768, 5, 32},
1604         {64, 16384, 4, 48},
1605         {32, 8192, 3, 56},
1606         {16, 4096, 2, 60},
1607         {8, 2048, 1, 62},
1608         {4, 1024, 0, 63}
1609 };
1610
1611 static const struct aper_size_info_16 intel_generic_sizes[7] =
1612 {
1613         {256, 65536, 6, 0},
1614         {128, 32768, 5, 32},
1615         {64, 16384, 4, 48},
1616         {32, 8192, 3, 56},
1617         {16, 4096, 2, 60},
1618         {8, 2048, 1, 62},
1619         {4, 1024, 0, 63}
1620 };
1621
1622 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1623 {
1624         {256, 65536, 6, 0},
1625         {128, 32768, 5, 32},
1626         {64, 16384, 4, 48},
1627         {32, 8192, 3, 56}
1628 };
1629
1630 static const struct agp_bridge_driver intel_generic_driver = {
1631         .owner                  = THIS_MODULE,
1632         .aperture_sizes         = intel_generic_sizes,
1633         .size_type              = U16_APER_SIZE,
1634         .num_aperture_sizes     = 7,
1635         .configure              = intel_configure,
1636         .fetch_size             = intel_fetch_size,
1637         .cleanup                = intel_cleanup,
1638         .tlb_flush              = intel_tlbflush,
1639         .mask_memory            = agp_generic_mask_memory,
1640         .masks                  = intel_generic_masks,
1641         .agp_enable             = agp_generic_enable,
1642         .cache_flush            = global_cache_flush,
1643         .create_gatt_table      = agp_generic_create_gatt_table,
1644         .free_gatt_table        = agp_generic_free_gatt_table,
1645         .insert_memory          = agp_generic_insert_memory,
1646         .remove_memory          = agp_generic_remove_memory,
1647         .alloc_by_type          = agp_generic_alloc_by_type,
1648         .free_by_type           = agp_generic_free_by_type,
1649         .agp_alloc_page         = agp_generic_alloc_page,
1650         .agp_destroy_page       = agp_generic_destroy_page,
1651         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1652 };
1653
1654 static const struct agp_bridge_driver intel_810_driver = {
1655         .owner                  = THIS_MODULE,
1656         .aperture_sizes         = intel_i810_sizes,
1657         .size_type              = FIXED_APER_SIZE,
1658         .num_aperture_sizes     = 2,
1659         .needs_scratch_page     = TRUE,
1660         .configure              = intel_i810_configure,
1661         .fetch_size             = intel_i810_fetch_size,
1662         .cleanup                = intel_i810_cleanup,
1663         .tlb_flush              = intel_i810_tlbflush,
1664         .mask_memory            = intel_i810_mask_memory,
1665         .masks                  = intel_i810_masks,
1666         .agp_enable             = intel_i810_agp_enable,
1667         .cache_flush            = global_cache_flush,
1668         .create_gatt_table      = agp_generic_create_gatt_table,
1669         .free_gatt_table        = agp_generic_free_gatt_table,
1670         .insert_memory          = intel_i810_insert_entries,
1671         .remove_memory          = intel_i810_remove_entries,
1672         .alloc_by_type          = intel_i810_alloc_by_type,
1673         .free_by_type           = intel_i810_free_by_type,
1674         .agp_alloc_page         = agp_generic_alloc_page,
1675         .agp_destroy_page       = agp_generic_destroy_page,
1676         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1677 };
1678
1679 static const struct agp_bridge_driver intel_815_driver = {
1680         .owner                  = THIS_MODULE,
1681         .aperture_sizes         = intel_815_sizes,
1682         .size_type              = U8_APER_SIZE,
1683         .num_aperture_sizes     = 2,
1684         .configure              = intel_815_configure,
1685         .fetch_size             = intel_815_fetch_size,
1686         .cleanup                = intel_8xx_cleanup,
1687         .tlb_flush              = intel_8xx_tlbflush,
1688         .mask_memory            = agp_generic_mask_memory,
1689         .masks                  = intel_generic_masks,
1690         .agp_enable             = agp_generic_enable,
1691         .cache_flush            = global_cache_flush,
1692         .create_gatt_table      = agp_generic_create_gatt_table,
1693         .free_gatt_table        = agp_generic_free_gatt_table,
1694         .insert_memory          = agp_generic_insert_memory,
1695         .remove_memory          = agp_generic_remove_memory,
1696         .alloc_by_type          = agp_generic_alloc_by_type,
1697         .free_by_type           = agp_generic_free_by_type,
1698         .agp_alloc_page         = agp_generic_alloc_page,
1699         .agp_destroy_page       = agp_generic_destroy_page,
1700         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1701 };
1702
1703 static const struct agp_bridge_driver intel_830_driver = {
1704         .owner                  = THIS_MODULE,
1705         .aperture_sizes         = intel_i830_sizes,
1706         .size_type              = FIXED_APER_SIZE,
1707         .num_aperture_sizes     = 4,
1708         .needs_scratch_page     = TRUE,
1709         .configure              = intel_i830_configure,
1710         .fetch_size             = intel_i830_fetch_size,
1711         .cleanup                = intel_i830_cleanup,
1712         .tlb_flush              = intel_i810_tlbflush,
1713         .mask_memory            = intel_i810_mask_memory,
1714         .masks                  = intel_i810_masks,
1715         .agp_enable             = intel_i810_agp_enable,
1716         .cache_flush            = global_cache_flush,
1717         .create_gatt_table      = intel_i830_create_gatt_table,
1718         .free_gatt_table        = intel_i830_free_gatt_table,
1719         .insert_memory          = intel_i830_insert_entries,
1720         .remove_memory          = intel_i830_remove_entries,
1721         .alloc_by_type          = intel_i830_alloc_by_type,
1722         .free_by_type           = intel_i810_free_by_type,
1723         .agp_alloc_page         = agp_generic_alloc_page,
1724         .agp_destroy_page       = agp_generic_destroy_page,
1725         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1726         .chipset_flush          = intel_i830_chipset_flush,
1727 };
1728
1729 static const struct agp_bridge_driver intel_820_driver = {
1730         .owner                  = THIS_MODULE,
1731         .aperture_sizes         = intel_8xx_sizes,
1732         .size_type              = U8_APER_SIZE,
1733         .num_aperture_sizes     = 7,
1734         .configure              = intel_820_configure,
1735         .fetch_size             = intel_8xx_fetch_size,
1736         .cleanup                = intel_820_cleanup,
1737         .tlb_flush              = intel_820_tlbflush,
1738         .mask_memory            = agp_generic_mask_memory,
1739         .masks                  = intel_generic_masks,
1740         .agp_enable             = agp_generic_enable,
1741         .cache_flush            = global_cache_flush,
1742         .create_gatt_table      = agp_generic_create_gatt_table,
1743         .free_gatt_table        = agp_generic_free_gatt_table,
1744         .insert_memory          = agp_generic_insert_memory,
1745         .remove_memory          = agp_generic_remove_memory,
1746         .alloc_by_type          = agp_generic_alloc_by_type,
1747         .free_by_type           = agp_generic_free_by_type,
1748         .agp_alloc_page         = agp_generic_alloc_page,
1749         .agp_destroy_page       = agp_generic_destroy_page,
1750         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1751 };
1752
1753 static const struct agp_bridge_driver intel_830mp_driver = {
1754         .owner                  = THIS_MODULE,
1755         .aperture_sizes         = intel_830mp_sizes,
1756         .size_type              = U8_APER_SIZE,
1757         .num_aperture_sizes     = 4,
1758         .configure              = intel_830mp_configure,
1759         .fetch_size             = intel_8xx_fetch_size,
1760         .cleanup                = intel_8xx_cleanup,
1761         .tlb_flush              = intel_8xx_tlbflush,
1762         .mask_memory            = agp_generic_mask_memory,
1763         .masks                  = intel_generic_masks,
1764         .agp_enable             = agp_generic_enable,
1765         .cache_flush            = global_cache_flush,
1766         .create_gatt_table      = agp_generic_create_gatt_table,
1767         .free_gatt_table        = agp_generic_free_gatt_table,
1768         .insert_memory          = agp_generic_insert_memory,
1769         .remove_memory          = agp_generic_remove_memory,
1770         .alloc_by_type          = agp_generic_alloc_by_type,
1771         .free_by_type           = agp_generic_free_by_type,
1772         .agp_alloc_page         = agp_generic_alloc_page,
1773         .agp_destroy_page       = agp_generic_destroy_page,
1774         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1775 };
1776
1777 static const struct agp_bridge_driver intel_840_driver = {
1778         .owner                  = THIS_MODULE,
1779         .aperture_sizes         = intel_8xx_sizes,
1780         .size_type              = U8_APER_SIZE,
1781         .num_aperture_sizes     = 7,
1782         .configure              = intel_840_configure,
1783         .fetch_size             = intel_8xx_fetch_size,
1784         .cleanup                = intel_8xx_cleanup,
1785         .tlb_flush              = intel_8xx_tlbflush,
1786         .mask_memory            = agp_generic_mask_memory,
1787         .masks                  = intel_generic_masks,
1788         .agp_enable             = agp_generic_enable,
1789         .cache_flush            = global_cache_flush,
1790         .create_gatt_table      = agp_generic_create_gatt_table,
1791         .free_gatt_table        = agp_generic_free_gatt_table,
1792         .insert_memory          = agp_generic_insert_memory,
1793         .remove_memory          = agp_generic_remove_memory,
1794         .alloc_by_type          = agp_generic_alloc_by_type,
1795         .free_by_type           = agp_generic_free_by_type,
1796         .agp_alloc_page         = agp_generic_alloc_page,
1797         .agp_destroy_page       = agp_generic_destroy_page,
1798         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1799 };
1800
1801 static const struct agp_bridge_driver intel_845_driver = {
1802         .owner                  = THIS_MODULE,
1803         .aperture_sizes         = intel_8xx_sizes,
1804         .size_type              = U8_APER_SIZE,
1805         .num_aperture_sizes     = 7,
1806         .configure              = intel_845_configure,
1807         .fetch_size             = intel_8xx_fetch_size,
1808         .cleanup                = intel_8xx_cleanup,
1809         .tlb_flush              = intel_8xx_tlbflush,
1810         .mask_memory            = agp_generic_mask_memory,
1811         .masks                  = intel_generic_masks,
1812         .agp_enable             = agp_generic_enable,
1813         .cache_flush            = global_cache_flush,
1814         .create_gatt_table      = agp_generic_create_gatt_table,
1815         .free_gatt_table        = agp_generic_free_gatt_table,
1816         .insert_memory          = agp_generic_insert_memory,
1817         .remove_memory          = agp_generic_remove_memory,
1818         .alloc_by_type          = agp_generic_alloc_by_type,
1819         .free_by_type           = agp_generic_free_by_type,
1820         .agp_alloc_page         = agp_generic_alloc_page,
1821         .agp_destroy_page       = agp_generic_destroy_page,
1822         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1823         .chipset_flush          = intel_i830_chipset_flush,
1824 };
1825
1826 static const struct agp_bridge_driver intel_850_driver = {
1827         .owner                  = THIS_MODULE,
1828         .aperture_sizes         = intel_8xx_sizes,
1829         .size_type              = U8_APER_SIZE,
1830         .num_aperture_sizes     = 7,
1831         .configure              = intel_850_configure,
1832         .fetch_size             = intel_8xx_fetch_size,
1833         .cleanup                = intel_8xx_cleanup,
1834         .tlb_flush              = intel_8xx_tlbflush,
1835         .mask_memory            = agp_generic_mask_memory,
1836         .masks                  = intel_generic_masks,
1837         .agp_enable             = agp_generic_enable,
1838         .cache_flush            = global_cache_flush,
1839         .create_gatt_table      = agp_generic_create_gatt_table,
1840         .free_gatt_table        = agp_generic_free_gatt_table,
1841         .insert_memory          = agp_generic_insert_memory,
1842         .remove_memory          = agp_generic_remove_memory,
1843         .alloc_by_type          = agp_generic_alloc_by_type,
1844         .free_by_type           = agp_generic_free_by_type,
1845         .agp_alloc_page         = agp_generic_alloc_page,
1846         .agp_destroy_page       = agp_generic_destroy_page,
1847         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1848 };
1849
1850 static const struct agp_bridge_driver intel_860_driver = {
1851         .owner                  = THIS_MODULE,
1852         .aperture_sizes         = intel_8xx_sizes,
1853         .size_type              = U8_APER_SIZE,
1854         .num_aperture_sizes     = 7,
1855         .configure              = intel_860_configure,
1856         .fetch_size             = intel_8xx_fetch_size,
1857         .cleanup                = intel_8xx_cleanup,
1858         .tlb_flush              = intel_8xx_tlbflush,
1859         .mask_memory            = agp_generic_mask_memory,
1860         .masks                  = intel_generic_masks,
1861         .agp_enable             = agp_generic_enable,
1862         .cache_flush            = global_cache_flush,
1863         .create_gatt_table      = agp_generic_create_gatt_table,
1864         .free_gatt_table        = agp_generic_free_gatt_table,
1865         .insert_memory          = agp_generic_insert_memory,
1866         .remove_memory          = agp_generic_remove_memory,
1867         .alloc_by_type          = agp_generic_alloc_by_type,
1868         .free_by_type           = agp_generic_free_by_type,
1869         .agp_alloc_page         = agp_generic_alloc_page,
1870         .agp_destroy_page       = agp_generic_destroy_page,
1871         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1872 };
1873
1874 static const struct agp_bridge_driver intel_915_driver = {
1875         .owner                  = THIS_MODULE,
1876         .aperture_sizes         = intel_i830_sizes,
1877         .size_type              = FIXED_APER_SIZE,
1878         .num_aperture_sizes     = 4,
1879         .needs_scratch_page     = TRUE,
1880         .configure              = intel_i915_configure,
1881         .fetch_size             = intel_i9xx_fetch_size,
1882         .cleanup                = intel_i915_cleanup,
1883         .tlb_flush              = intel_i810_tlbflush,
1884         .mask_memory            = intel_i810_mask_memory,
1885         .masks                  = intel_i810_masks,
1886         .agp_enable             = intel_i810_agp_enable,
1887         .cache_flush            = global_cache_flush,
1888         .create_gatt_table      = intel_i915_create_gatt_table,
1889         .free_gatt_table        = intel_i830_free_gatt_table,
1890         .insert_memory          = intel_i915_insert_entries,
1891         .remove_memory          = intel_i915_remove_entries,
1892         .alloc_by_type          = intel_i830_alloc_by_type,
1893         .free_by_type           = intel_i810_free_by_type,
1894         .agp_alloc_page         = agp_generic_alloc_page,
1895         .agp_destroy_page       = agp_generic_destroy_page,
1896         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1897         .chipset_flush          = intel_i915_chipset_flush,
1898 };
1899
1900 static const struct agp_bridge_driver intel_i965_driver = {
1901        .owner                  = THIS_MODULE,
1902        .aperture_sizes         = intel_i830_sizes,
1903        .size_type              = FIXED_APER_SIZE,
1904        .num_aperture_sizes     = 4,
1905        .needs_scratch_page     = TRUE,
1906        .configure              = intel_i915_configure,
1907        .fetch_size             = intel_i9xx_fetch_size,
1908        .cleanup                = intel_i915_cleanup,
1909        .tlb_flush              = intel_i810_tlbflush,
1910        .mask_memory            = intel_i965_mask_memory,
1911        .masks                  = intel_i810_masks,
1912        .agp_enable             = intel_i810_agp_enable,
1913        .cache_flush            = global_cache_flush,
1914        .create_gatt_table      = intel_i965_create_gatt_table,
1915        .free_gatt_table        = intel_i830_free_gatt_table,
1916        .insert_memory          = intel_i915_insert_entries,
1917        .remove_memory          = intel_i915_remove_entries,
1918        .alloc_by_type          = intel_i830_alloc_by_type,
1919        .free_by_type           = intel_i810_free_by_type,
1920        .agp_alloc_page         = agp_generic_alloc_page,
1921        .agp_destroy_page       = agp_generic_destroy_page,
1922        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1923         .chipset_flush          = intel_i915_chipset_flush,
1924 };
1925
1926 static const struct agp_bridge_driver intel_7505_driver = {
1927         .owner                  = THIS_MODULE,
1928         .aperture_sizes         = intel_8xx_sizes,
1929         .size_type              = U8_APER_SIZE,
1930         .num_aperture_sizes     = 7,
1931         .configure              = intel_7505_configure,
1932         .fetch_size             = intel_8xx_fetch_size,
1933         .cleanup                = intel_8xx_cleanup,
1934         .tlb_flush              = intel_8xx_tlbflush,
1935         .mask_memory            = agp_generic_mask_memory,
1936         .masks                  = intel_generic_masks,
1937         .agp_enable             = agp_generic_enable,
1938         .cache_flush            = global_cache_flush,
1939         .create_gatt_table      = agp_generic_create_gatt_table,
1940         .free_gatt_table        = agp_generic_free_gatt_table,
1941         .insert_memory          = agp_generic_insert_memory,
1942         .remove_memory          = agp_generic_remove_memory,
1943         .alloc_by_type          = agp_generic_alloc_by_type,
1944         .free_by_type           = agp_generic_free_by_type,
1945         .agp_alloc_page         = agp_generic_alloc_page,
1946         .agp_destroy_page       = agp_generic_destroy_page,
1947         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1948 };
1949
1950 static const struct agp_bridge_driver intel_g33_driver = {
1951         .owner                  = THIS_MODULE,
1952         .aperture_sizes         = intel_i830_sizes,
1953         .size_type              = FIXED_APER_SIZE,
1954         .num_aperture_sizes     = 4,
1955         .needs_scratch_page     = TRUE,
1956         .configure              = intel_i915_configure,
1957         .fetch_size             = intel_i9xx_fetch_size,
1958         .cleanup                = intel_i915_cleanup,
1959         .tlb_flush              = intel_i810_tlbflush,
1960         .mask_memory            = intel_i965_mask_memory,
1961         .masks                  = intel_i810_masks,
1962         .agp_enable             = intel_i810_agp_enable,
1963         .cache_flush            = global_cache_flush,
1964         .create_gatt_table      = intel_i915_create_gatt_table,
1965         .free_gatt_table        = intel_i830_free_gatt_table,
1966         .insert_memory          = intel_i915_insert_entries,
1967         .remove_memory          = intel_i915_remove_entries,
1968         .alloc_by_type          = intel_i830_alloc_by_type,
1969         .free_by_type           = intel_i810_free_by_type,
1970         .agp_alloc_page         = agp_generic_alloc_page,
1971         .agp_destroy_page       = agp_generic_destroy_page,
1972         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1973         .chipset_flush          = intel_i915_chipset_flush,
1974 };
1975
1976 static int find_gmch(u16 device)
1977 {
1978         struct pci_dev *gmch_device;
1979
1980         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1981         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1982                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1983                                              device, gmch_device);
1984         }
1985
1986         if (!gmch_device)
1987                 return 0;
1988
1989         intel_private.pcidev = gmch_device;
1990         return 1;
1991 }
1992
1993 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1994  * driver and gmch_driver must be non-null, and find_gmch will determine
1995  * which one should be used if a gmch_chip_id is present.
1996  */
1997 static const struct intel_driver_description {
1998         unsigned int chip_id;
1999         unsigned int gmch_chip_id;
2000         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2001         char *name;
2002         const struct agp_bridge_driver *driver;
2003         const struct agp_bridge_driver *gmch_driver;
2004 } intel_agp_chipsets[] = {
2005         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2006         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2007         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2008         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2009                 NULL, &intel_810_driver },
2010         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2011                 NULL, &intel_810_driver },
2012         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2013                 NULL, &intel_810_driver },
2014         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2015                 &intel_815_driver, &intel_810_driver },
2016         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2017         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2018         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2019                 &intel_830mp_driver, &intel_830_driver },
2020         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2021         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2022         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2023                 &intel_845_driver, &intel_830_driver },
2024         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2025         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2026         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2027                 &intel_845_driver, &intel_830_driver },
2028         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2029         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2030                 &intel_845_driver, &intel_830_driver },
2031         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2032         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2033                 NULL, &intel_915_driver },
2034         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2035                 NULL, &intel_915_driver },
2036         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2037                 NULL, &intel_915_driver },
2038         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2039                 NULL, &intel_915_driver },
2040         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2041                 NULL, &intel_915_driver },
2042         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2043                 NULL, &intel_915_driver },
2044         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2045                 NULL, &intel_i965_driver },
2046         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2047                 NULL, &intel_i965_driver },
2048         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2049                 NULL, &intel_i965_driver },
2050         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2051                 NULL, &intel_i965_driver },
2052         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2053                 NULL, &intel_i965_driver },
2054         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2055                 NULL, &intel_i965_driver },
2056         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2057         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2058         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2059                 NULL, &intel_g33_driver },
2060         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2061                 NULL, &intel_g33_driver },
2062         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2063                 NULL, &intel_g33_driver },
2064         { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2065             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2066         { 0, 0, 0, NULL, NULL, NULL }
2067 };
2068
2069 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2070                                      const struct pci_device_id *ent)
2071 {
2072         struct agp_bridge_data *bridge;
2073         u8 cap_ptr = 0;
2074         struct resource *r;
2075         int i;
2076
2077         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2078
2079         bridge = agp_alloc_bridge();
2080         if (!bridge)
2081                 return -ENOMEM;
2082
2083         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2084                 /* In case that multiple models of gfx chip may
2085                    stand on same host bridge type, this can be
2086                    sure we detect the right IGD. */
2087                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2088                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2089                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2090                                 bridge->driver =
2091                                         intel_agp_chipsets[i].gmch_driver;
2092                                 break;
2093                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2094                                 continue;
2095                         } else {
2096                                 bridge->driver = intel_agp_chipsets[i].driver;
2097                                 break;
2098                         }
2099                 }
2100         }
2101
2102         if (intel_agp_chipsets[i].name == NULL) {
2103                 if (cap_ptr)
2104                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
2105                                "(device id: %04x)\n", pdev->device);
2106                 agp_put_bridge(bridge);
2107                 return -ENODEV;
2108         }
2109
2110         if (bridge->driver == NULL) {
2111                 /* bridge has no AGP and no IGD detected */
2112                 if (cap_ptr)
2113                         printk(KERN_WARNING PFX "Failed to find bridge device "
2114                                 "(chip_id: %04x)\n",
2115                                 intel_agp_chipsets[i].gmch_chip_id);
2116                 agp_put_bridge(bridge);
2117                 return -ENODEV;
2118         }
2119
2120         bridge->dev = pdev;
2121         bridge->capndx = cap_ptr;
2122         bridge->dev_private_data = &intel_private;
2123
2124         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2125                 intel_agp_chipsets[i].name);
2126
2127         /*
2128         * The following fixes the case where the BIOS has "forgotten" to
2129         * provide an address range for the GART.
2130         * 20030610 - hamish@zot.org
2131         */
2132         r = &pdev->resource[0];
2133         if (!r->start && r->end) {
2134                 if (pci_assign_resource(pdev, 0)) {
2135                         printk(KERN_ERR PFX "could not assign resource 0\n");
2136                         agp_put_bridge(bridge);
2137                         return -ENODEV;
2138                 }
2139         }
2140
2141         /*
2142         * If the device has not been properly setup, the following will catch
2143         * the problem and should stop the system from crashing.
2144         * 20030610 - hamish@zot.org
2145         */
2146         if (pci_enable_device(pdev)) {
2147                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2148                 agp_put_bridge(bridge);
2149                 return -ENODEV;
2150         }
2151
2152         /* Fill in the mode register */
2153         if (cap_ptr) {
2154                 pci_read_config_dword(pdev,
2155                                 bridge->capndx+PCI_AGP_STATUS,
2156                                 &bridge->mode);
2157         }
2158
2159         pci_set_drvdata(pdev, bridge);
2160         return agp_add_bridge(bridge);
2161 }
2162
2163 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2164 {
2165         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2166
2167         agp_remove_bridge(bridge);
2168
2169         if (intel_private.pcidev)
2170                 pci_dev_put(intel_private.pcidev);
2171
2172         agp_put_bridge(bridge);
2173 }
2174
2175 #ifdef CONFIG_PM
2176 static int agp_intel_resume(struct pci_dev *pdev)
2177 {
2178         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2179
2180         pci_restore_state(pdev);
2181
2182         /* We should restore our graphics device's config space,
2183          * as host bridge (00:00) resumes before graphics device (02:00),
2184          * then our access to its pci space can work right.
2185          */
2186         if (intel_private.pcidev)
2187                 pci_restore_state(intel_private.pcidev);
2188
2189         if (bridge->driver == &intel_generic_driver)
2190                 intel_configure();
2191         else if (bridge->driver == &intel_850_driver)
2192                 intel_850_configure();
2193         else if (bridge->driver == &intel_845_driver)
2194                 intel_845_configure();
2195         else if (bridge->driver == &intel_830mp_driver)
2196                 intel_830mp_configure();
2197         else if (bridge->driver == &intel_915_driver)
2198                 intel_i915_configure();
2199         else if (bridge->driver == &intel_830_driver)
2200                 intel_i830_configure();
2201         else if (bridge->driver == &intel_810_driver)
2202                 intel_i810_configure();
2203         else if (bridge->driver == &intel_i965_driver)
2204                 intel_i915_configure();
2205
2206         return 0;
2207 }
2208 #endif
2209
2210 static struct pci_device_id agp_intel_pci_table[] = {
2211 #define ID(x)                                           \
2212         {                                               \
2213         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2214         .class_mask     = ~0,                           \
2215         .vendor         = PCI_VENDOR_ID_INTEL,          \
2216         .device         = x,                            \
2217         .subvendor      = PCI_ANY_ID,                   \
2218         .subdevice      = PCI_ANY_ID,                   \
2219         }
2220         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2221         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2222         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2223         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2224         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2225         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2226         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2227         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2228         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2229         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2230         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2231         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2232         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2233         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2234         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2235         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2236         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2237         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2238         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2239         ID(PCI_DEVICE_ID_INTEL_7505_0),
2240         ID(PCI_DEVICE_ID_INTEL_7205_0),
2241         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2242         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2243         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2244         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2245         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2246         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2247         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2248         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2249         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2250         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2251         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2252         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2253         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2254         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2255         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2256         ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2257         { }
2258 };
2259
2260 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2261
2262 static struct pci_driver agp_intel_pci_driver = {
2263         .name           = "agpgart-intel",
2264         .id_table       = agp_intel_pci_table,
2265         .probe          = agp_intel_probe,
2266         .remove         = __devexit_p(agp_intel_remove),
2267 #ifdef CONFIG_PM
2268         .resume         = agp_intel_resume,
2269 #endif
2270 };
2271
2272 static int __init agp_intel_init(void)
2273 {
2274         if (agp_off)
2275                 return -EINVAL;
2276         return pci_register_driver(&agp_intel_pci_driver);
2277 }
2278
2279 static void __exit agp_intel_cleanup(void)
2280 {
2281         pci_unregister_driver(&agp_intel_pci_driver);
2282 }
2283
2284 module_init(agp_intel_init);
2285 module_exit(agp_intel_cleanup);
2286
2287 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2288 MODULE_LICENSE("GPL and additional rights");