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   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *
   6  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   7  *  compiled into the kernel if you have more than one card installed.
   8  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
   9  *  safe chipset tuning, including this support is harmless
  10  *
  11  *  Promise Ultra66 cards with BIOS v1.11 this
  12  *  compiled into the kernel if you have more than one card installed.
  13  *
  14  *  Promise Ultra100 cards.
  15  *
  16  *  The latest chipset code will support the following ::
  17  *  Three Ultra33 controllers and 12 drives.
  18  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  19  *  The 8/4 ratio is a BIOS code limit by promise.
  20  *
  21  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  22  *
  23  */
  24
  25 /*
  26  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  27  *  Author: Frank Tiernan (frankt@promise.com)
  28  *  Released under terms of General Public License
  29  */
  30
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/delay.h>
  35 #include <linux/timer.h>
  36 #include <linux/mm.h>
  37 #include <linux/ioport.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/hdreg.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/pci.h>
  42 #include <linux/init.h>
  43 #include <linux/ide.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47
  48 #define PDC202_DEBUG_CABLE              0
  49 #define PDC202XX_DEBUG_DRIVE_INFO       0
  50
  51 static const char *pdc_quirk_drives[] = {
  52         "QUANTUM FIREBALLlct08 08",
  53         "QUANTUM FIREBALLP KA6.4",
  54         "QUANTUM FIREBALLP KA9.1",
  55         "QUANTUM FIREBALLP LM20.4",
  56         "QUANTUM FIREBALLP KX13.6",
  57         "QUANTUM FIREBALLP KX20.5",
  58         "QUANTUM FIREBALLP KX27.3",
  59         "QUANTUM FIREBALLP LM20.5",
  60         NULL
  61 };
  62
  63 /* A Register */
  64 #define SYNC_ERRDY_EN   0xC0
  65
  66 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  67 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  68 #define IORDY_EN        0x20    /* PIO: IOREADY */
  69 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  70
  71 #define PA3             0x08    /* PIO"A" timing */
  72 #define PA2             0x04    /* PIO"A" timing */
  73 #define PA1             0x02    /* PIO"A" timing */
  74 #define PA0             0x01    /* PIO"A" timing */
  75
  76 /* B Register */
  77
  78 #define MB2             0x80    /* DMA"B" timing */
  79 #define MB1             0x40    /* DMA"B" timing */
  80 #define MB0             0x20    /* DMA"B" timing */
  81
  82 #define PB4             0x10    /* PIO_FORCE 1:0 */
  83
  84 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  85 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  86 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  87 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  88
  89 /* C Register */
  90 #define IORDYp_NO_SPEED 0x4F
  91 #define SPEED_DIS       0x0F
  92
  93 #define DMARQp          0x80
  94 #define IORDYp          0x40
  95 #define DMAR_EN         0x20
  96 #define DMAW_EN         0x10
  97
  98 #define MC3             0x08    /* DMA"C" timing */
  99 #define MC2             0x04    /* DMA"C" timing */
 100 #define MC1             0x02    /* DMA"C" timing */
 101 #define MC0             0x01    /* DMA"C" timing */
 102
 103 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 104 {
 105         u8 mode;
 106
 107         switch(HWIF(drive)->pci_dev->device) {
 108                 case PCI_DEVICE_ID_PROMISE_20267:
 109                 case PCI_DEVICE_ID_PROMISE_20265:
 110                         mode = 3;
 111                         break;
 112                 case PCI_DEVICE_ID_PROMISE_20263:
 113                 case PCI_DEVICE_ID_PROMISE_20262:
 114                         mode = 2;
 115                         break;
 116                 case PCI_DEVICE_ID_PROMISE_20246:
 117                         return 1;
 118                 default:
 119                         return 0;
 120         }
 121         if (!eighty_ninty_three(drive))
 122                 mode = min(mode, (u8)1);
 123         return mode;
 124 }
 125
 126 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 127 {
 128         struct hd_driveid *id = drive->id;
 129
 130         if (pdc_quirk_drives == list) {
 131                 while (*list) {
 132                         if (strstr(id->model, *list++)) {
 133                                 return 2;
 134                         }
 135                 }
 136         } else {
 137                 while (*list) {
 138                         if (!strcmp(*list++,id->model)) {
 139                                 return 1;
 140                         }
 141                 }
 142         }
 143         return 0;
 144 }
 145
 146 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 147 {
 148         ide_hwif_t *hwif        = HWIF(drive);
 149         struct pci_dev *dev     = hwif->pci_dev;
 150         u8 drive_pci            = 0x60 + (drive->dn << 2);
 151         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 152
 153         u32                     drive_conf;
 154         u8                      AP, BP, CP, DP;
 155         u8                      TA = 0, TB = 0, TC = 0;
 156
 157         if (drive->media != ide_disk &&
 158                 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
 159                 return -1;
 160
 161         pci_read_config_dword(dev, drive_pci, &drive_conf);
 162         pci_read_config_byte(dev, (drive_pci), &AP);
 163         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 164         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 165         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 166
 167         if (speed < XFER_SW_DMA_0) {
 168                 if ((AP & 0x0F) || (BP & 0x07)) {
 169                         /* clear PIO modes of lower 8421 bits of A Register */
 170                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 171                         pci_read_config_byte(dev, (drive_pci), &AP);
 172
 173                         /* clear PIO modes of lower 421 bits of B Register */
 174                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 175                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 176
 177                         pci_read_config_byte(dev, (drive_pci), &AP);
 178                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 179                 }
 180         } else {
 181                 if ((BP & 0xF0) && (CP & 0x0F)) {
 182                         /* clear DMA modes of upper 842 bits of B Register */
 183                         /* clear PIO forced mode upper 1 bit of B Register */
 184                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 185                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 186
 187                         /* clear DMA modes of lower 8421 bits of C Register */
 188                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 189                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 190                 }
 191         }
 192
 193         pci_read_config_byte(dev, (drive_pci), &AP);
 194         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 195         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 196
 197         switch(speed) {
 198                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 199                 case XFER_UDMA_5:
 200                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 201                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 202                 case XFER_UDMA_3:
 203                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 204                 case XFER_UDMA_0:
 205                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 206                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 207                 case XFER_MW_DMA_0:
 208                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 209                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 210                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 211                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 212                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 213                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 214                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 215                 case XFER_PIO_0:
 216                 default:                TA = 0x09; TB = 0x13; break;
 217         }
 218
 219         if (speed < XFER_SW_DMA_0) {
 220                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 221                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 222         } else {
 223                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 224                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 225         }
 226
 227 #if PDC202XX_DEBUG_DRIVE_INFO
 228         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 229                 drive->name, ide_xfer_verbose(speed),
 230                 drive->dn, drive_conf);
 231                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 232         printk("0x%08x\n", drive_conf);
 233 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 234
 235         return (ide_config_drive_speed(drive, speed));
 236 }
 237
 238
 239 /*   0    1    2    3    4    5    6   7   8
 240  * 960, 480, 390, 300, 240, 180, 120, 90, 60
 241  *           180, 150, 120,  90,  60
 242  * DMA_Speed
 243  * 180, 120,  90,  90,  90,  60,  30
 244  *  11,   5,   4,   3,   2,   1,   0
 245  */
 246 static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 247 {
 248         u8 speed = 0;
 249
 250         if (pio == 5) pio = 4;
 251         speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
 252
 253         pdc202xx_tune_chipset(drive, speed);
 254 }
 255
 256 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 257 {
 258         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 259         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 260         return (CIS & mask) ? 1 : 0;
 261 }
 262
 263 /*
 264  * Set the control register to use the 66MHz system
 265  * clock for UDMA 3/4/5 mode operation when necessary.
 266  *
 267  * It may also be possible to leave the 66MHz clock on
 268  * and readjust the timing parameters.
 269  */
 270 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 271 {
 272         unsigned long clock_reg = hwif->dma_master + 0x11;
 273         u8 clock = hwif->INB(clock_reg);
 274
 275         hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 276 }
 277
 278 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 279 {
 280         unsigned long clock_reg = hwif->dma_master + 0x11;
 281         u8 clock = hwif->INB(clock_reg);
 282
 283         hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 284 }
 285
 286 static int config_chipset_for_dma (ide_drive_t *drive)
 287 {
 288         struct hd_driveid *id   = drive->id;
 289         ide_hwif_t *hwif        = HWIF(drive);
 290         struct pci_dev *dev     = hwif->pci_dev;
 291         u32 drive_conf          = 0;
 292         u8 drive_pci            = 0x60 + (drive->dn << 2);
 293         u8 test1 = 0, test2 = 0, speed = -1;
 294         u8 AP = 0, cable = 0;
 295
 296         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 297                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 298
 299         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 300                 cable = pdc202xx_old_cable_detect(hwif);
 301         else
 302                 ultra_66 = 0;
 303
 304         if (ultra_66 && cable) {
 305                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 306                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 307         }
 308
 309         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 310                 pdc_old_disable_66MHz_clock(drive->hwif);
 311
 312         drive_pci = 0x60 + (drive->dn << 2);
 313         pci_read_config_dword(dev, drive_pci, &drive_conf);
 314         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 315                 goto chipset_is_set;
 316
 317         pci_read_config_byte(dev, drive_pci, &test1);
 318         if (!(test1 & SYNC_ERRDY_EN)) {
 319                 if (drive->select.b.unit & 0x01) {
 320                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 321                         if ((test2 & SYNC_ERRDY_EN) &&
 322                             !(test1 & SYNC_ERRDY_EN)) {
 323                                 pci_write_config_byte(dev, drive_pci,
 324                                         test1|SYNC_ERRDY_EN);
 325                         }
 326                 } else {
 327                         pci_write_config_byte(dev, drive_pci,
 328                                 test1|SYNC_ERRDY_EN);
 329                 }
 330         }
 331
 332 chipset_is_set:
 333
 334         pci_read_config_byte(dev, (drive_pci), &AP);
 335         if (id->capability & 4) /* IORDY_EN */
 336                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 337         pci_read_config_byte(dev, (drive_pci), &AP);
 338         if (drive->media == ide_disk)   /* PREFETCH_EN */
 339                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 340
 341         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 342
 343         if (!(speed)) {
 344                 /* restore original pci-config space */
 345                 pci_write_config_dword(dev, drive_pci, drive_conf);
 346                 return 0;
 347         }
 348
 349         (void) hwif->speedproc(drive, speed);
 350         return ide_dma_enable(drive);
 351 }
 352
 353 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 354 {
 355         ide_hwif_t *hwif        = HWIF(drive);
 356         struct hd_driveid *id   = drive->id;
 357
 358         drive->init_speed = 0;
 359
 360         if (id && (id->capability & 1) && drive->autodma) {
 361
 362                 if (ide_use_dma(drive)) {
 363                         if (config_chipset_for_dma(drive))
 364                                 return hwif->ide_dma_on(drive);
 365                 }
 366
 367                 goto fast_ata_pio;
 368
 369         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 370 fast_ata_pio:
 371                 hwif->tuneproc(drive, 5);
 372                 return hwif->ide_dma_off_quietly(drive);
 373         }
 374         /* IORDY not supported */
 375         return 0;
 376 }
 377
 378 static int pdc202xx_quirkproc (ide_drive_t *drive)
 379 {
 380         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
 381 }
 382
 383 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 384 {
 385         if (drive->current_speed > XFER_UDMA_2)
 386                 pdc_old_enable_66MHz_clock(drive->hwif);
 387         if (drive->media != ide_disk || drive->addressing == 1) {
 388                 struct request *rq      = HWGROUP(drive)->rq;
 389                 ide_hwif_t *hwif        = HWIF(drive);
 390                 unsigned long high_16   = hwif->dma_master;
 391                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 392                 u32 word_count  = 0;
 393                 u8 clock = hwif->INB(high_16 + 0x11);
 394
 395                 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
 396                 word_count = (rq->nr_sectors << 8);
 397                 word_count = (rq_data_dir(rq) == READ) ?
 398                                         word_count | 0x05000000 :
 399                                         word_count | 0x06000000;
 400                 hwif->OUTL(word_count, atapi_reg);
 401         }
 402         ide_dma_start(drive);
 403 }
 404
 405 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 406 {
 407         if (drive->media != ide_disk || drive->addressing == 1) {
 408                 ide_hwif_t *hwif        = HWIF(drive);
 409                 unsigned long high_16   = hwif->dma_master;
 410                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 411                 u8 clock                = 0;
 412
 413                 hwif->OUTL(0, atapi_reg); /* zero out extra */
 414                 clock = hwif->INB(high_16 + 0x11);
 415                 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
 416         }
 417         if (drive->current_speed > XFER_UDMA_2)
 418                 pdc_old_disable_66MHz_clock(drive->hwif);
 419         return __ide_dma_end(drive);
 420 }
 421
 422 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 423 {
 424         ide_hwif_t *hwif        = HWIF(drive);
 425         unsigned long high_16   = hwif->dma_master;
 426         u8 dma_stat             = hwif->INB(hwif->dma_status);
 427         u8 sc1d                 = hwif->INB((high_16 + 0x001d));
 428
 429         if (hwif->channel) {
 430                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 431                 if ((sc1d & 0x50) == 0x50)
 432                         goto somebody_else;
 433                 else if ((sc1d & 0x40) == 0x40)
 434                         return (dma_stat & 4) == 4;
 435         } else {
 436                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 437                 if ((sc1d & 0x05) == 0x05)
 438                         goto somebody_else;
 439                 else if ((sc1d & 0x04) == 0x04)
 440                         return (dma_stat & 4) == 4;
 441         }
 442 somebody_else:
 443         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 444 }
 445
 446 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 447 {
 448         if (HWIF(drive)->resetproc != NULL)
 449                 HWIF(drive)->resetproc(drive);
 450         return __ide_dma_lostirq(drive);
 451 }
 452
 453 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 454 {
 455         if (HWIF(drive)->resetproc != NULL)
 456                 HWIF(drive)->resetproc(drive);
 457         return __ide_dma_timeout(drive);
 458 }
 459
 460 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 461 {
 462         unsigned long high_16   = hwif->dma_master;
 463         u8 udma_speed_flag      = hwif->INB(high_16|0x001f);
 464
 465         hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
 466         mdelay(100);
 467         hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
 468         mdelay(2000);   /* 2 seconds ?! */
 469
 470         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 471                 hwif->channel ? "Secondary" : "Primary");
 472 }
 473
 474 static void pdc202xx_reset (ide_drive_t *drive)
 475 {
 476         ide_hwif_t *hwif        = HWIF(drive);
 477         ide_hwif_t *mate        = hwif->mate;
 478
 479         pdc202xx_reset_host(hwif);
 480         pdc202xx_reset_host(mate);
 481         hwif->tuneproc(drive, 5);
 482 }
 483
 484 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 485                                                         const char *name)
 486 {
 487         /* This doesn't appear needed */
 488         if (dev->resource[PCI_ROM_RESOURCE].start) {
 489                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 490                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 491                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 492                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 493         }
 494
 495         return dev->irq;
 496 }
 497
 498 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 499 {
 500         struct pci_dev *dev = hwif->pci_dev;
 501
 502         /* PDC20265 has problems with large LBA48 requests */
 503         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 504             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 505                 hwif->rqsize = 256;
 506
 507         hwif->autodma = 0;
 508         hwif->tuneproc  = &config_chipset_for_pio;
 509         hwif->quirkproc = &pdc202xx_quirkproc;
 510
 511         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 512                 hwif->resetproc = &pdc202xx_reset;
 513
 514         hwif->speedproc = &pdc202xx_tune_chipset;
 515
 516         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 517
 518         hwif->ultra_mask = 0x3f;
 519         hwif->mwdma_mask = 0x07;
 520         hwif->swdma_mask = 0x07;
 521         hwif->atapi_dma = 1;
 522
 523         hwif->err_stops_fifo = 1;
 524
 525         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 526         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 527         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 528
 529         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 530                 if (!(hwif->udma_four))
 531                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 532                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 533                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 534         }
 535         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 536
 537         if (!noautodma)
 538                 hwif->autodma = 1;
 539         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 540 #if PDC202_DEBUG_CABLE
 541         printk(KERN_DEBUG "%s: %s-pin cable\n",
 542                 hwif->name, hwif->udma_four ? "80" : "40");
 543 #endif /* PDC202_DEBUG_CABLE */
 544 }
 545
 546 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 547 {
 548         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 549
 550         if (hwif->channel) {
 551                 ide_setup_dma(hwif, dmabase, 8);
 552                 return;
 553         }
 554
 555         udma_speed_flag = hwif->INB((dmabase|0x1f));
 556         primary_mode    = hwif->INB((dmabase|0x1a));
 557         secondary_mode  = hwif->INB((dmabase|0x1b));
 558         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 559                 "Primary %s Mode " \
 560                 "Secondary %s Mode.\n", hwif->cds->name,
 561                 (udma_speed_flag & 1) ? "EN" : "DIS",
 562                 (primary_mode & 1) ? "MASTER" : "PCI",
 563                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 564
 565 #ifdef CONFIG_PDC202XX_BURST
 566         if (!(udma_speed_flag & 1)) {
 567                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 568                         hwif->cds->name, udma_speed_flag,
 569                         (udma_speed_flag|1));
 570                 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
 571                 printk("%sACTIVE\n",
 572                         (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
 573         }
 574 #endif /* CONFIG_PDC202XX_BURST */
 575 #ifdef CONFIG_PDC202XX_MASTER
 576         if (!(primary_mode & 1)) {
 577                 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
 578                         "0x%02x -> 0x%02x ", hwif->cds->name,
 579                         primary_mode, (primary_mode|1));
 580                 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
 581                 printk("%s\n",
 582                         (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
 583         }
 584
 585         if (!(secondary_mode & 1)) {
 586                 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
 587                         "0x%02x -> 0x%02x ", hwif->cds->name,
 588                         secondary_mode, (secondary_mode|1));
 589                 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
 590                 printk("%s\n",
 591                         (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
 592         }
 593 #endif /* CONFIG_PDC202XX_MASTER */
 594
 595         ide_setup_dma(hwif, dmabase, 8);
 596 }
 597
 598 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 599                                            ide_pci_device_t *d)
 600 {
 601         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 602                 u8 irq = 0, irq2 = 0;
 603                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 604                 /* 0xbc */
 605                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 606                 if (irq != irq2) {
 607                         pci_write_config_byte(dev,
 608                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 609                         printk(KERN_INFO "%s: pci-config space interrupt "
 610                                 "mirror fixed.\n", d->name);
 611                 }
 612         }
 613         return ide_setup_pci_device(dev, d);
 614 }
 615
 616 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 617                                          ide_pci_device_t *d)
 618 {
 619         if ((dev->bus->self) &&
 620             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 621             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 622              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 623                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 624                         "attached to I2O RAID controller.\n");
 625                 return -ENODEV;
 626         }
 627         return ide_setup_pci_device(dev, d);
 628 }
 629
 630 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 631                                          ide_pci_device_t *d)
 632 {
 633         return ide_setup_pci_device(dev, d);
 634 }
 635
 636 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 637         {       /* 0 */
 638                 .name           = "PDC20246",
 639                 .init_setup     = init_setup_pdc202ata4,
 640                 .init_chipset   = init_chipset_pdc202xx,
 641                 .init_hwif      = init_hwif_pdc202xx,
 642                 .init_dma       = init_dma_pdc202xx,
 643                 .channels       = 2,
 644                 .autodma        = AUTODMA,
 645                 .bootable       = OFF_BOARD,
 646                 .extra          = 16,
 647         },{     /* 1 */
 648                 .name           = "PDC20262",
 649                 .init_setup     = init_setup_pdc202ata4,
 650                 .init_chipset   = init_chipset_pdc202xx,
 651                 .init_hwif      = init_hwif_pdc202xx,
 652                 .init_dma       = init_dma_pdc202xx,
 653                 .channels       = 2,
 654                 .autodma        = AUTODMA,
 655                 .bootable       = OFF_BOARD,
 656                 .extra          = 48,
 657         },{     /* 2 */
 658                 .name           = "PDC20263",
 659                 .init_setup     = init_setup_pdc202ata4,
 660                 .init_chipset   = init_chipset_pdc202xx,
 661                 .init_hwif      = init_hwif_pdc202xx,
 662                 .init_dma       = init_dma_pdc202xx,
 663                 .channels       = 2,
 664                 .autodma        = AUTODMA,
 665                 .bootable       = OFF_BOARD,
 666                 .extra          = 48,
 667         },{     /* 3 */
 668                 .name           = "PDC20265",
 669                 .init_setup     = init_setup_pdc20265,
 670                 .init_chipset   = init_chipset_pdc202xx,
 671                 .init_hwif      = init_hwif_pdc202xx,
 672                 .init_dma       = init_dma_pdc202xx,
 673                 .channels       = 2,
 674                 .autodma        = AUTODMA,
 675                 .bootable       = OFF_BOARD,
 676                 .extra          = 48,
 677         },{     /* 4 */
 678                 .name           = "PDC20267",
 679                 .init_setup     = init_setup_pdc202xx,
 680                 .init_chipset   = init_chipset_pdc202xx,
 681                 .init_hwif      = init_hwif_pdc202xx,
 682                 .init_dma       = init_dma_pdc202xx,
 683                 .channels       = 2,
 684                 .autodma        = AUTODMA,
 685                 .bootable       = OFF_BOARD,
 686                 .extra          = 48,
 687         }
 688 };
 689
 690 /**
 691  *      pdc202xx_init_one       -       called when a PDC202xx is found
 692  *      @dev: the pdc202xx device
 693  *      @id: the matching pci id
 694  *
 695  *      Called when the PCI registration layer (or the IDE initialization)
 696  *      finds a device matching our IDE device tables.
 697  */
 698
 699 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 700 {
 701         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 702
 703         return d->init_setup(dev, d);
 704 }
 705
 706 static struct pci_device_id pdc202xx_pci_tbl[] = {
 707         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 708         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 709         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 710         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 711         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 712         { 0, },
 713 };
 714 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 715
 716 static struct pci_driver driver = {
 717         .name           = "Promise_Old_IDE",
 718         .id_table       = pdc202xx_pci_tbl,
 719         .probe          = pdc202xx_init_one,
 720 };
 721
 722 static int __init pdc202xx_ide_init(void)
 723 {
 724         return ide_pci_register_driver(&driver);
 725 }
 726
 727 module_init(pdc202xx_ide_init);
 728
 729 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 730 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 731 MODULE_LICENSE("GPL");