Char: cyclades, remove volatiles
[linux-2.6] / include / asm-ppc / immap_cpm2.h
1 /*
2  * CPM2 Internal Memory Map
3  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
4  *
5  * The Internal Memory Map for devices with CPM2 on them.  This
6  * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
7  * 8560). 
8  */
9 #ifdef __KERNEL__
10 #ifndef __IMMAP_CPM2__
11 #define __IMMAP_CPM2__
12
13 /* System configuration registers.
14 */
15 typedef struct sys_82xx_conf {
16         u32     sc_siumcr;
17         u32     sc_sypcr;
18         u8      res1[6];
19         u16     sc_swsr;
20         u8      res2[20];
21         u32     sc_bcr;
22         u8      sc_ppc_acr;
23         u8      res3[3];
24         u32     sc_ppc_alrh;
25         u32     sc_ppc_alrl;
26         u8      sc_lcl_acr;
27         u8      res4[3];
28         u32     sc_lcl_alrh;
29         u32     sc_lcl_alrl;
30         u32     sc_tescr1;
31         u32     sc_tescr2;
32         u32     sc_ltescr1;
33         u32     sc_ltescr2;
34         u32     sc_pdtea;
35         u8      sc_pdtem;
36         u8      res5[3];
37         u32     sc_ldtea;
38         u8      sc_ldtem;
39         u8      res6[163];
40 } sysconf_82xx_cpm2_t;
41
42 typedef struct sys_85xx_conf {
43         u32     sc_cear;
44         u16     sc_ceer;
45         u16     sc_cemr;
46         u8      res1[70];
47         u32     sc_smaer;
48         u8      res2[4];
49         u32     sc_smevr;
50         u32     sc_smctr;
51         u32     sc_lmaer;
52         u8      res3[4];
53         u32     sc_lmevr;
54         u32     sc_lmctr;
55         u8      res4[144];
56 } sysconf_85xx_cpm2_t;
57
58 typedef union sys_conf {
59         sysconf_82xx_cpm2_t     siu_82xx;
60         sysconf_85xx_cpm2_t     siu_85xx;
61 } sysconf_cpm2_t;
62
63
64
65 /* Memory controller registers.
66 */
67 typedef struct  mem_ctlr {
68         u32     memc_br0;
69         u32     memc_or0;
70         u32     memc_br1;
71         u32     memc_or1;
72         u32     memc_br2;
73         u32     memc_or2;
74         u32     memc_br3;
75         u32     memc_or3;
76         u32     memc_br4;
77         u32     memc_or4;
78         u32     memc_br5;
79         u32     memc_or5;
80         u32     memc_br6;
81         u32     memc_or6;
82         u32     memc_br7;
83         u32     memc_or7;
84         u32     memc_br8;
85         u32     memc_or8;
86         u32     memc_br9;
87         u32     memc_or9;
88         u32     memc_br10;
89         u32     memc_or10;
90         u32     memc_br11;
91         u32     memc_or11;
92         u8      res1[8];
93         u32     memc_mar;
94         u8      res2[4];
95         u32     memc_mamr;
96         u32     memc_mbmr;
97         u32     memc_mcmr;
98         u8      res3[8];
99         u16     memc_mptpr;
100         u8      res4[2];
101         u32     memc_mdr;
102         u8      res5[4];
103         u32     memc_psdmr;
104         u32     memc_lsdmr;
105         u8      memc_purt;
106         u8      res6[3];
107         u8      memc_psrt;
108         u8      res7[3];
109         u8      memc_lurt;
110         u8      res8[3];
111         u8      memc_lsrt;
112         u8      res9[3];
113         u32     memc_immr;
114         u32     memc_pcibr0;
115         u32     memc_pcibr1;
116         u8      res10[16];
117         u32     memc_pcimsk0;
118         u32     memc_pcimsk1;
119         u8      res11[52];
120 } memctl_cpm2_t;
121
122 /* System Integration Timers.
123 */
124 typedef struct  sys_int_timers {
125         u8      res1[32];
126         u16     sit_tmcntsc;
127         u8      res2[2];
128         u32     sit_tmcnt;
129         u8      res3[4];
130         u32     sit_tmcntal;
131         u8      res4[16];
132         u16     sit_piscr;
133         u8      res5[2];
134         u32     sit_pitc;
135         u32     sit_pitr;
136         u8      res6[94];
137         u8      res7[390];
138 } sit_cpm2_t;
139
140 #define PISCR_PIRQ_MASK         ((u16)0xff00)
141 #define PISCR_PS                ((u16)0x0080)
142 #define PISCR_PIE               ((u16)0x0004)
143 #define PISCR_PTF               ((u16)0x0002)
144 #define PISCR_PTE               ((u16)0x0001)
145
146 /* PCI Controller.
147 */
148 typedef struct pci_ctlr {
149         u32     pci_omisr;
150         u32     pci_omimr;
151         u8      res1[8];
152         u32     pci_ifqpr;
153         u32     pci_ofqpr;
154         u8      res2[8];
155         u32     pci_imr0;
156         u32     pci_imr1;
157         u32     pci_omr0;
158         u32     pci_omr1;
159         u32     pci_odr;
160         u8      res3[4];
161         u32     pci_idr;
162         u8      res4[20];
163         u32     pci_imisr;
164         u32     pci_imimr;
165         u8      res5[24];
166         u32     pci_ifhpr;
167         u8      res6[4];
168         u32     pci_iftpr;
169         u8      res7[4];
170         u32     pci_iphpr;
171         u8      res8[4];
172         u32     pci_iptpr;
173         u8      res9[4];
174         u32     pci_ofhpr;
175         u8      res10[4];
176         u32     pci_oftpr;
177         u8      res11[4];
178         u32     pci_ophpr;
179         u8      res12[4];
180         u32     pci_optpr;
181         u8      res13[8];
182         u32     pci_mucr;
183         u8      res14[8];
184         u32     pci_qbar;
185         u8      res15[12];
186         u32     pci_dmamr0;
187         u32     pci_dmasr0;
188         u32     pci_dmacdar0;
189         u8      res16[4];
190         u32     pci_dmasar0;
191         u8      res17[4];
192         u32     pci_dmadar0;
193         u8      res18[4];
194         u32     pci_dmabcr0;
195         u32     pci_dmandar0;
196         u8      res19[86];
197         u32     pci_dmamr1;
198         u32     pci_dmasr1;
199         u32     pci_dmacdar1;
200         u8      res20[4];
201         u32     pci_dmasar1;
202         u8      res21[4];
203         u32     pci_dmadar1;
204         u8      res22[4];
205         u32     pci_dmabcr1;
206         u32     pci_dmandar1;
207         u8      res23[88];
208         u32     pci_dmamr2;
209         u32     pci_dmasr2;
210         u32     pci_dmacdar2;
211         u8      res24[4];
212         u32     pci_dmasar2;
213         u8      res25[4];
214         u32     pci_dmadar2;
215         u8      res26[4];
216         u32     pci_dmabcr2;
217         u32     pci_dmandar2;
218         u8      res27[88];
219         u32     pci_dmamr3;
220         u32     pci_dmasr3;
221         u32     pci_dmacdar3;
222         u8      res28[4];
223         u32     pci_dmasar3;
224         u8      res29[4];
225         u32     pci_dmadar3;
226         u8      res30[4];
227         u32     pci_dmabcr3;
228         u32     pci_dmandar3;
229         u8      res31[344];
230         u32     pci_potar0;
231         u8      res32[4];
232         u32     pci_pobar0;
233         u8      res33[4];
234         u32     pci_pocmr0;
235         u8      res34[4];
236         u32     pci_potar1;
237         u8      res35[4];
238         u32     pci_pobar1;
239         u8      res36[4];
240         u32     pci_pocmr1;
241         u8      res37[4];
242         u32     pci_potar2;
243         u8      res38[4];
244         u32     pci_pobar2;
245         u8      res39[4];
246         u32     pci_pocmr2;
247         u8      res40[50];
248         u32     pci_ptcr;
249         u32     pci_gpcr;
250         u32     pci_gcr;
251         u32     pci_esr;
252         u32     pci_emr;
253         u32     pci_ecr;
254         u32     pci_eacr;
255         u8      res41[4];
256         u32     pci_edcr;
257         u8      res42[4];
258         u32     pci_eccr;
259         u8      res43[44];
260         u32     pci_pitar1;
261         u8      res44[4];
262         u32     pci_pibar1;
263         u8      res45[4];
264         u32     pci_picmr1;
265         u8      res46[4];
266         u32     pci_pitar0;
267         u8      res47[4];
268         u32     pci_pibar0;
269         u8      res48[4];
270         u32     pci_picmr0;
271         u8      res49[4];
272         u32     pci_cfg_addr;
273         u32     pci_cfg_data;
274         u32     pci_int_ack;
275         u8      res50[756];
276 } pci_cpm2_t;
277
278 /* Interrupt Controller.
279 */
280 typedef struct interrupt_controller {
281         u16     ic_sicr;
282         u8      res1[2];
283         u32     ic_sivec;
284         u32     ic_sipnrh;
285         u32     ic_sipnrl;
286         u32     ic_siprr;
287         u32     ic_scprrh;
288         u32     ic_scprrl;
289         u32     ic_simrh;
290         u32     ic_simrl;
291         u32     ic_siexr;
292         u8      res2[88];
293 } intctl_cpm2_t;
294
295 /* Clocks and Reset.
296 */
297 typedef struct clk_and_reset {
298         u32     car_sccr;
299         u8      res1[4];
300         u32     car_scmr;
301         u8      res2[4];
302         u32     car_rsr;
303         u32     car_rmr;
304         u8      res[104];
305 } car_cpm2_t;
306
307 /* Input/Output Port control/status registers.
308  * Names consistent with processor manual, although they are different
309  * from the original 8xx names.......
310  */
311 typedef struct io_port {
312         u32     iop_pdira;
313         u32     iop_ppara;
314         u32     iop_psora;
315         u32     iop_podra;
316         u32     iop_pdata;
317         u8      res1[12];
318         u32     iop_pdirb;
319         u32     iop_pparb;
320         u32     iop_psorb;
321         u32     iop_podrb;
322         u32     iop_pdatb;
323         u8      res2[12];
324         u32     iop_pdirc;
325         u32     iop_pparc;
326         u32     iop_psorc;
327         u32     iop_podrc;
328         u32     iop_pdatc;
329         u8      res3[12];
330         u32     iop_pdird;
331         u32     iop_ppard;
332         u32     iop_psord;
333         u32     iop_podrd;
334         u32     iop_pdatd;
335         u8      res4[12];
336 } iop_cpm2_t;
337
338 /* Communication Processor Module Timers
339 */
340 typedef struct cpm_timers {
341         u8      cpmt_tgcr1;
342         u8      res1[3];
343         u8      cpmt_tgcr2;
344         u8      res2[11];
345         u16     cpmt_tmr1;
346         u16     cpmt_tmr2;
347         u16     cpmt_trr1;
348         u16     cpmt_trr2;
349         u16     cpmt_tcr1;
350         u16     cpmt_tcr2;
351         u16     cpmt_tcn1;
352         u16     cpmt_tcn2;
353         u16     cpmt_tmr3;
354         u16     cpmt_tmr4;
355         u16     cpmt_trr3;
356         u16     cpmt_trr4;
357         u16     cpmt_tcr3;
358         u16     cpmt_tcr4;
359         u16     cpmt_tcn3;
360         u16     cpmt_tcn4;
361         u16     cpmt_ter1;
362         u16     cpmt_ter2;
363         u16     cpmt_ter3;
364         u16     cpmt_ter4;
365         u8      res3[584];
366 } cpmtimer_cpm2_t;
367
368 /* DMA control/status registers.
369 */
370 typedef struct sdma_csr {
371         u8      res0[24];
372         u8      sdma_sdsr;
373         u8      res1[3];
374         u8      sdma_sdmr;
375         u8      res2[3];
376         u8      sdma_idsr1;
377         u8      res3[3];
378         u8      sdma_idmr1;
379         u8      res4[3];
380         u8      sdma_idsr2;
381         u8      res5[3];
382         u8      sdma_idmr2;
383         u8      res6[3];
384         u8      sdma_idsr3;
385         u8      res7[3];
386         u8      sdma_idmr3;
387         u8      res8[3];
388         u8      sdma_idsr4;
389         u8      res9[3];
390         u8      sdma_idmr4;
391         u8      res10[707];
392 } sdma_cpm2_t;
393
394 /* Fast controllers
395 */
396 typedef struct fcc {
397         u32     fcc_gfmr;
398         u32     fcc_fpsmr;
399         u16     fcc_ftodr;
400         u8      res1[2];
401         u16     fcc_fdsr;
402         u8      res2[2];
403         u16     fcc_fcce;
404         u8      res3[2];
405         u16     fcc_fccm;
406         u8      res4[2];
407         u8      fcc_fccs;
408         u8      res5[3];
409         u8      fcc_ftirr_phy[4];
410 } fcc_t;
411
412 /* Fast controllers continued
413  */
414 typedef struct fcc_c {
415         u32     fcc_firper;
416         u32     fcc_firer;
417         u32     fcc_firsr_hi;
418         u32     fcc_firsr_lo;
419         u8      fcc_gfemr;
420         u8      res1[15];
421 } fcc_c_t;
422
423 /* TC Layer
424  */
425 typedef struct tclayer {
426         u16     tc_tcmode;
427         u16     tc_cdsmr;
428         u16     tc_tcer;
429         u16     tc_rcc;
430         u16     tc_tcmr;
431         u16     tc_fcc;
432         u16     tc_ccc;
433         u16     tc_icc;
434         u16     tc_tcc;
435         u16     tc_ecc;
436         u8      res1[12];
437 } tclayer_t;
438
439
440 /* I2C
441 */
442 typedef struct i2c {
443         u8      i2c_i2mod;
444         u8      res1[3];
445         u8      i2c_i2add;
446         u8      res2[3];
447         u8      i2c_i2brg;
448         u8      res3[3];
449         u8      i2c_i2com;
450         u8      res4[3];
451         u8      i2c_i2cer;
452         u8      res5[3];
453         u8      i2c_i2cmr;
454         u8      res6[331];
455 } i2c_cpm2_t;
456
457 typedef struct scc {            /* Serial communication channels */
458         u32     scc_gsmrl;
459         u32     scc_gsmrh;
460         u16     scc_psmr;
461         u8      res1[2];
462         u16     scc_todr;
463         u16     scc_dsr;
464         u16     scc_scce;
465         u8      res2[2];
466         u16     scc_sccm;
467         u8      res3;
468         u8      scc_sccs;
469         u8      res4[8];
470 } scc_t;
471
472 typedef struct smc {            /* Serial management channels */
473         u8      res1[2];
474         u16     smc_smcmr;
475         u8      res2[2];
476         u8      smc_smce;
477         u8      res3[3];
478         u8      smc_smcm;
479         u8      res4[5];
480 } smc_t;
481
482 /* Serial Peripheral Interface.
483 */
484 typedef struct spi_ctrl {
485         u16     spi_spmode;
486         u8      res1[4];
487         u8      spi_spie;
488         u8      res2[3];
489         u8      spi_spim;
490         u8      res3[2];
491         u8      spi_spcom;
492         u8      res4[82];
493 } spictl_cpm2_t;
494
495 /* CPM Mux.
496 */
497 typedef struct cpmux {
498         u8      cmx_si1cr;
499         u8      res1;
500         u8      cmx_si2cr;
501         u8      res2;
502         u32     cmx_fcr;
503         u32     cmx_scr;
504         u8      cmx_smr;
505         u8      res3;
506         u16     cmx_uar;
507         u8      res4[16];
508 } cpmux_t;
509
510 /* SIRAM control
511 */
512 typedef struct siram {
513         u16     si_amr;
514         u16     si_bmr;
515         u16     si_cmr;
516         u16     si_dmr;
517         u8      si_gmr;
518         u8      res1;
519         u8      si_cmdr;
520         u8      res2;
521         u8      si_str;
522         u8      res3;
523         u16     si_rsr;
524 } siramctl_t;
525
526 typedef struct mcc {
527         u16     mcc_mcce;
528         u8      res1[2];
529         u16     mcc_mccm;
530         u8      res2[2];
531         u8      mcc_mccf;
532         u8      res3[7];
533 } mcc_t;
534
535 typedef struct comm_proc {
536         u32     cp_cpcr;
537         u32     cp_rccr;
538         u8      res1[14];
539         u16     cp_rter;
540         u8      res2[2];
541         u16     cp_rtmr;
542         u16     cp_rtscr;
543         u8      res3[2];
544         u32     cp_rtsr;
545         u8      res4[12];
546 } cpm_cpm2_t;
547
548 /* USB Controller.
549 */
550 typedef struct usb_ctlr {
551         u8      usb_usmod;
552         u8      usb_usadr;
553         u8      usb_uscom;
554         u8      res1[1];
555         u16     usb_usep1;
556         u16     usb_usep2;
557         u16     usb_usep3;
558         u16     usb_usep4;
559         u8      res2[4];
560         u16     usb_usber;
561         u8      res3[2];
562         u16     usb_usbmr;
563         u8      usb_usbs;
564         u8      res4[7];
565 } usb_cpm2_t;
566
567 /* ...and the whole thing wrapped up....
568 */
569
570 typedef struct immap {
571         /* Some references are into the unique and known dpram spaces,
572          * others are from the generic base.
573          */
574 #define im_dprambase    im_dpram1
575         u8              im_dpram1[16*1024];
576         u8              res1[16*1024];
577         u8              im_dpram2[4*1024];
578         u8              res2[8*1024];
579         u8              im_dpram3[4*1024];
580         u8              res3[16*1024];
581
582         sysconf_cpm2_t  im_siu_conf;    /* SIU Configuration */
583         memctl_cpm2_t   im_memctl;      /* Memory Controller */
584         sit_cpm2_t      im_sit;         /* System Integration Timers */
585         pci_cpm2_t      im_pci;         /* PCI Controller */
586         intctl_cpm2_t   im_intctl;      /* Interrupt Controller */
587         car_cpm2_t      im_clkrst;      /* Clocks and reset */
588         iop_cpm2_t      im_ioport;      /* IO Port control/status */
589         cpmtimer_cpm2_t im_cpmtimer;    /* CPM timers */
590         sdma_cpm2_t     im_sdma;        /* SDMA control/status */
591
592         fcc_t           im_fcc[3];      /* Three FCCs */
593         u8              res4z[32];
594         fcc_c_t         im_fcc_c[3];    /* Continued FCCs */
595
596         u8              res4[32];
597
598         tclayer_t       im_tclayer[8];  /* Eight TCLayers */
599         u16             tc_tcgsr;
600         u16             tc_tcger;
601         
602         /* First set of baud rate generators.
603         */
604         u8              res[236];
605         u32             im_brgc5;
606         u32             im_brgc6;
607         u32             im_brgc7;
608         u32             im_brgc8;
609
610         u8              res5[608];
611
612         i2c_cpm2_t      im_i2c;         /* I2C control/status */
613         cpm_cpm2_t      im_cpm;         /* Communication processor */
614
615         /* Second set of baud rate generators.
616         */
617         u32             im_brgc1;
618         u32             im_brgc2;
619         u32             im_brgc3;
620         u32             im_brgc4;
621
622         scc_t           im_scc[4];      /* Four SCCs */
623         smc_t           im_smc[2];      /* Couple of SMCs */
624         spictl_cpm2_t   im_spi;         /* A SPI */
625         cpmux_t         im_cpmux;       /* CPM clock route mux */
626         siramctl_t      im_siramctl1;   /* First SI RAM Control */
627         mcc_t           im_mcc1;        /* First MCC */
628         siramctl_t      im_siramctl2;   /* Second SI RAM Control */
629         mcc_t           im_mcc2;        /* Second MCC */
630         usb_cpm2_t      im_usb;         /* USB Controller */
631
632         u8              res6[1153];
633
634         u16             im_si1txram[256];
635         u8              res7[512];
636         u16             im_si1rxram[256];
637         u8              res8[512];
638         u16             im_si2txram[256];
639         u8              res9[512];
640         u16             im_si2rxram[256];
641         u8              res10[512];
642         u8              res11[4096];
643 } cpm2_map_t;
644
645 extern cpm2_map_t       *cpm2_immr;
646
647 #endif /* __IMMAP_CPM2__ */
648 #endif /* __KERNEL__ */