Char: cyclades, remove volatiles
[linux-2.6] / include / asm-ppc / mpc52xx_psc.h
1 /*
2  * include/asm-ppc/mpc52xx_psc.h
3  * 
4  * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5  * PSCs. Theses are shared between multiple drivers since a PSC can be
6  * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7  *
8  *
9  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10  *
11  * Based/Extracted from some header of the 2.4 originally written by 
12  * Dale Farnsworth <dfarnsworth@mvista.com> 
13  *
14  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15  * Copyright (C) 2003 MontaVista, Software, Inc.
16  *
17  * This file is licensed under the terms of the GNU General Public License
18  * version 2. This program is licensed "as is" without any warranty of any
19  * kind, whether express or implied.
20  */
21
22 #ifndef __ASM_MPC52xx_PSC_H__
23 #define __ASM_MPC52xx_PSC_H__
24
25 #include <asm/types.h>
26
27 /* Max number of PSCs */
28 #define MPC52xx_PSC_MAXNUM      6
29
30 /* Programmable Serial Controller (PSC) status register bits */
31 #define MPC52xx_PSC_SR_CDE      0x0080
32 #define MPC52xx_PSC_SR_RXRDY    0x0100
33 #define MPC52xx_PSC_SR_RXFULL   0x0200
34 #define MPC52xx_PSC_SR_TXRDY    0x0400
35 #define MPC52xx_PSC_SR_TXEMP    0x0800
36 #define MPC52xx_PSC_SR_OE       0x1000
37 #define MPC52xx_PSC_SR_PE       0x2000
38 #define MPC52xx_PSC_SR_FE       0x4000
39 #define MPC52xx_PSC_SR_RB       0x8000
40
41 /* PSC Command values */
42 #define MPC52xx_PSC_RX_ENABLE           0x0001
43 #define MPC52xx_PSC_RX_DISABLE          0x0002
44 #define MPC52xx_PSC_TX_ENABLE           0x0004
45 #define MPC52xx_PSC_TX_DISABLE          0x0008
46 #define MPC52xx_PSC_SEL_MODE_REG_1      0x0010
47 #define MPC52xx_PSC_RST_RX              0x0020
48 #define MPC52xx_PSC_RST_TX              0x0030
49 #define MPC52xx_PSC_RST_ERR_STAT        0x0040
50 #define MPC52xx_PSC_RST_BRK_CHG_INT     0x0050
51 #define MPC52xx_PSC_START_BRK           0x0060
52 #define MPC52xx_PSC_STOP_BRK            0x0070
53
54 /* PSC TxRx FIFO status bits */
55 #define MPC52xx_PSC_RXTX_FIFO_ERR       0x0040
56 #define MPC52xx_PSC_RXTX_FIFO_UF        0x0020
57 #define MPC52xx_PSC_RXTX_FIFO_OF        0x0010
58 #define MPC52xx_PSC_RXTX_FIFO_FR        0x0008
59 #define MPC52xx_PSC_RXTX_FIFO_FULL      0x0004
60 #define MPC52xx_PSC_RXTX_FIFO_ALARM     0x0002
61 #define MPC52xx_PSC_RXTX_FIFO_EMPTY     0x0001
62
63 /* PSC interrupt mask bits */
64 #define MPC52xx_PSC_IMR_TXRDY           0x0100
65 #define MPC52xx_PSC_IMR_RXRDY           0x0200
66 #define MPC52xx_PSC_IMR_DB              0x0400
67 #define MPC52xx_PSC_IMR_IPC             0x8000
68
69 /* PSC input port change bit */
70 #define MPC52xx_PSC_CTS                 0x01
71 #define MPC52xx_PSC_DCD                 0x02
72 #define MPC52xx_PSC_D_CTS               0x10
73 #define MPC52xx_PSC_D_DCD               0x20
74
75 /* PSC mode fields */
76 #define MPC52xx_PSC_MODE_5_BITS                 0x00
77 #define MPC52xx_PSC_MODE_6_BITS                 0x01
78 #define MPC52xx_PSC_MODE_7_BITS                 0x02
79 #define MPC52xx_PSC_MODE_8_BITS                 0x03
80 #define MPC52xx_PSC_MODE_BITS_MASK              0x03
81 #define MPC52xx_PSC_MODE_PAREVEN                0x00
82 #define MPC52xx_PSC_MODE_PARODD                 0x04
83 #define MPC52xx_PSC_MODE_PARFORCE               0x08
84 #define MPC52xx_PSC_MODE_PARNONE                0x10
85 #define MPC52xx_PSC_MODE_ERR                    0x20
86 #define MPC52xx_PSC_MODE_FFULL                  0x40
87 #define MPC52xx_PSC_MODE_RXRTS                  0x80
88
89 #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS        0x00
90 #define MPC52xx_PSC_MODE_ONE_STOP               0x07
91 #define MPC52xx_PSC_MODE_TWO_STOP               0x0f
92
93 #define MPC52xx_PSC_RFNUM_MASK  0x01ff
94
95
96 /* Structure of the hardware registers */
97 struct mpc52xx_psc {
98         u8              mode;           /* PSC + 0x00 */
99         u8              reserved0[3];
100         union {                         /* PSC + 0x04 */
101                 u16     status;
102                 u16     clock_select;
103         } sr_csr;
104 #define mpc52xx_psc_status      sr_csr.status
105 #define mpc52xx_psc_clock_select sr_csr.clock_select
106         u16             reserved1;
107         u8              command;        /* PSC + 0x08 */
108         u8              reserved2[3];
109         union {                         /* PSC + 0x0c */
110                 u8      buffer_8;
111                 u16     buffer_16;
112                 u32     buffer_32;
113         } buffer;
114 #define mpc52xx_psc_buffer_8    buffer.buffer_8
115 #define mpc52xx_psc_buffer_16   buffer.buffer_16
116 #define mpc52xx_psc_buffer_32   buffer.buffer_32
117         union {                         /* PSC + 0x10 */
118                 u8      ipcr;
119                 u8      acr;
120         } ipcr_acr;
121 #define mpc52xx_psc_ipcr        ipcr_acr.ipcr
122 #define mpc52xx_psc_acr         ipcr_acr.acr
123         u8              reserved3[3];
124         union {                         /* PSC + 0x14 */
125                 u16     isr;
126                 u16     imr;
127         } isr_imr;
128 #define mpc52xx_psc_isr         isr_imr.isr
129 #define mpc52xx_psc_imr         isr_imr.imr
130         u16             reserved4;
131         u8              ctur;           /* PSC + 0x18 */
132         u8              reserved5[3];
133         u8              ctlr;           /* PSC + 0x1c */
134         u8              reserved6[3];
135         u16             ccr;            /* PSC + 0x20 */
136         u8              reserved7[14];
137         u8              ivr;            /* PSC + 0x30 */
138         u8              reserved8[3];
139         u8              ip;             /* PSC + 0x34 */
140         u8              reserved9[3];
141         u8              op1;            /* PSC + 0x38 */
142         u8              reserved10[3];
143         u8              op0;            /* PSC + 0x3c */
144         u8              reserved11[3];
145         u32             sicr;           /* PSC + 0x40 */
146         u8              ircr1;          /* PSC + 0x44 */
147         u8              reserved13[3];
148         u8              ircr2;          /* PSC + 0x44 */
149         u8              reserved14[3];
150         u8              irsdr;          /* PSC + 0x4c */
151         u8              reserved15[3];
152         u8              irmdr;          /* PSC + 0x50 */
153         u8              reserved16[3];
154         u8              irfdr;          /* PSC + 0x54 */
155         u8              reserved17[3];
156         u16             rfnum;          /* PSC + 0x58 */
157         u16             reserved18;
158         u16             tfnum;          /* PSC + 0x5c */
159         u16             reserved19;
160         u32             rfdata;         /* PSC + 0x60 */
161         u16             rfstat;         /* PSC + 0x64 */
162         u16             reserved20;
163         u8              rfcntl;         /* PSC + 0x68 */
164         u8              reserved21[5];
165         u16             rfalarm;        /* PSC + 0x6e */
166         u16             reserved22;
167         u16             rfrptr;         /* PSC + 0x72 */
168         u16             reserved23;
169         u16             rfwptr;         /* PSC + 0x76 */
170         u16             reserved24;
171         u16             rflrfptr;       /* PSC + 0x7a */
172         u16             reserved25;
173         u16             rflwfptr;       /* PSC + 0x7e */
174         u32             tfdata;         /* PSC + 0x80 */
175         u16             tfstat;         /* PSC + 0x84 */
176         u16             reserved26;
177         u8              tfcntl;         /* PSC + 0x88 */
178         u8              reserved27[5];
179         u16             tfalarm;        /* PSC + 0x8e */
180         u16             reserved28;
181         u16             tfrptr;         /* PSC + 0x92 */
182         u16             reserved29;
183         u16             tfwptr;         /* PSC + 0x96 */
184         u16             reserved30;
185         u16             tflrfptr;       /* PSC + 0x9a */
186         u16             reserved31;
187         u16             tflwfptr;       /* PSC + 0x9e */
188 };
189
190
191 #endif  /* __ASM_MPC52xx_PSC_H__ */