Char: cyclades, remove volatiles
[linux-2.6] / include / asm-ppc / mv64x60_defs.h
1 /*
2  * include/asm-ppc/mv64x60_defs.h
3  *
4  * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
5  * host bridges.
6  *
7  * Author: Mark A. Greer <mgreer@mvista.com>
8  *
9  * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
10  * the terms of the GNU General Public License version 2.  This program
11  * is licensed "as is" without any warranty of any kind, whether express
12  * or implied.
13  */
14 #ifndef __ASMPPC_MV64x60_DEFS_H
15 #define __ASMPPC_MV64x60_DEFS_H
16
17 /*
18  * Define the Marvell bridges that are supported
19  */
20 #define MV64x60_TYPE_INVALID                    0
21 #define MV64x60_TYPE_GT64260A                   1
22 #define MV64x60_TYPE_GT64260B                   2
23 #define MV64x60_TYPE_MV64360                    3
24 #define MV64x60_TYPE_MV64361                    4
25 #define MV64x60_TYPE_MV64362                    5
26 #define MV64x60_TYPE_MV64460                    6
27
28
29 /* Revisions of each supported chip */
30 #define GT64260_REV_A                           0x10
31 #define GT64260_REV_B                           0x20
32 #define MV64360                                 0x01
33 #define MV64460                                 0x01
34
35 /* Minimum window size supported by 64260 is 1MB */
36 #define GT64260_WINDOW_SIZE_MIN                 0x00100000
37 #define MV64360_WINDOW_SIZE_MIN                 0x00010000
38
39 #define MV64x60_TCLK_FREQ_MAX                   133333333U
40
41 /* IRQ's for embedded controllers */
42 #define MV64x60_IRQ_DEV                         1
43 #define MV64x60_IRQ_CPU_ERR                     3
44 #define MV64x60_IRQ_TIMER_0_1                   8
45 #define MV64x60_IRQ_TIMER_2_3                   9
46 #define MV64x60_IRQ_TIMER_4_5                   10
47 #define MV64x60_IRQ_TIMER_6_7                   11
48 #define MV64x60_IRQ_P1_GPP_0_7                  24
49 #define MV64x60_IRQ_P1_GPP_8_15                 25
50 #define MV64x60_IRQ_P1_GPP_16_23                26
51 #define MV64x60_IRQ_P1_GPP_24_31                27
52 #define MV64x60_IRQ_DOORBELL                    28
53 #define MV64x60_IRQ_ETH_0                       32
54 #define MV64x60_IRQ_ETH_1                       33
55 #define MV64x60_IRQ_ETH_2                       34
56 #define MV64x60_IRQ_SDMA_0                      36
57 #define MV64x60_IRQ_I2C                         37
58 #define MV64x60_IRQ_BRG                         39
59 #define MV64x60_IRQ_MPSC_0                      40
60 #define MV64x60_IRQ_MPSC_1                      42
61 #define MV64x60_IRQ_COMM                        43
62 #define MV64x60_IRQ_P0_GPP_0_7                  56
63 #define MV64x60_IRQ_P0_GPP_8_15                 57
64 #define MV64x60_IRQ_P0_GPP_16_23                58
65 #define MV64x60_IRQ_P0_GPP_24_31                59
66
67 #define MV64360_IRQ_PCI0                        12
68 #define MV64360_IRQ_SRAM_PAR_ERR                13
69 #define MV64360_IRQ_PCI1                        16
70 #define MV64360_IRQ_SDMA_1                      38
71
72 #define MV64x60_IRQ_GPP0                        64
73 #define MV64x60_IRQ_GPP1                        65
74 #define MV64x60_IRQ_GPP2                        66
75 #define MV64x60_IRQ_GPP3                        67
76 #define MV64x60_IRQ_GPP4                        68
77 #define MV64x60_IRQ_GPP5                        69
78 #define MV64x60_IRQ_GPP6                        70
79 #define MV64x60_IRQ_GPP7                        71
80 #define MV64x60_IRQ_GPP8                        72
81 #define MV64x60_IRQ_GPP9                        73
82 #define MV64x60_IRQ_GPP10                       74
83 #define MV64x60_IRQ_GPP11                       75
84 #define MV64x60_IRQ_GPP12                       76
85 #define MV64x60_IRQ_GPP13                       77
86 #define MV64x60_IRQ_GPP14                       78
87 #define MV64x60_IRQ_GPP15                       79
88 #define MV64x60_IRQ_GPP16                       80
89 #define MV64x60_IRQ_GPP17                       81
90 #define MV64x60_IRQ_GPP18                       82
91 #define MV64x60_IRQ_GPP19                       83
92 #define MV64x60_IRQ_GPP20                       84
93 #define MV64x60_IRQ_GPP21                       85
94 #define MV64x60_IRQ_GPP22                       86
95 #define MV64x60_IRQ_GPP23                       87
96 #define MV64x60_IRQ_GPP24                       88
97 #define MV64x60_IRQ_GPP25                       89
98 #define MV64x60_IRQ_GPP26                       90
99 #define MV64x60_IRQ_GPP27                       91
100 #define MV64x60_IRQ_GPP28                       92
101 #define MV64x60_IRQ_GPP29                       93
102 #define MV64x60_IRQ_GPP30                       94
103 #define MV64x60_IRQ_GPP31                       95
104
105 /* Offsets for register blocks */
106 #define GT64260_ENET_PHY_ADDR                   0x2000
107 #define GT64260_ENET_ESMIR                      0x2010
108 #define GT64260_ENET_0_OFFSET                   0x2400
109 #define GT64260_ENET_1_OFFSET                   0x2800
110 #define GT64260_ENET_2_OFFSET                   0x2c00
111 #define MV64x60_SDMA_0_OFFSET                   0x4000
112 #define MV64x60_SDMA_1_OFFSET                   0x6000
113 #define MV64x60_MPSC_0_OFFSET                   0x8000
114 #define MV64x60_MPSC_1_OFFSET                   0x9000
115 #define MV64x60_MPSC_ROUTING_OFFSET             0xb400
116 #define MV64x60_SDMA_INTR_OFFSET                0xb800
117 #define MV64x60_BRG_0_OFFSET                    0xb200
118 #define MV64x60_BRG_1_OFFSET                    0xb208
119
120 /*
121  *****************************************************************************
122  *
123  *      CPU Interface Registers
124  *
125  *****************************************************************************
126  */
127
128 /* CPU physical address of bridge's registers */
129 #define MV64x60_INTERNAL_SPACE_DECODE           0x0068
130 #define MV64x60_INTERNAL_SPACE_SIZE             0x10000
131 #define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR     0x14000000
132
133 #define MV64360_CPU_BAR_ENABLE                  0x0278
134
135 /* CPU Memory Controller Window Registers (4 windows) */
136 #define MV64x60_CPU2MEM_WINDOWS                 4
137
138 #define MV64x60_CPU2MEM_0_BASE                  0x0008
139 #define MV64x60_CPU2MEM_0_SIZE                  0x0010
140 #define MV64x60_CPU2MEM_1_BASE                  0x0208
141 #define MV64x60_CPU2MEM_1_SIZE                  0x0210
142 #define MV64x60_CPU2MEM_2_BASE                  0x0018
143 #define MV64x60_CPU2MEM_2_SIZE                  0x0020
144 #define MV64x60_CPU2MEM_3_BASE                  0x0218
145 #define MV64x60_CPU2MEM_3_SIZE                  0x0220
146
147 /* CPU Device Controller Window Registers (4 windows) */
148 #define MV64x60_CPU2DEV_WINDOWS                 4
149
150 #define MV64x60_CPU2DEV_0_BASE                  0x0028
151 #define MV64x60_CPU2DEV_0_SIZE                  0x0030
152 #define MV64x60_CPU2DEV_1_BASE                  0x0228
153 #define MV64x60_CPU2DEV_1_SIZE                  0x0230
154 #define MV64x60_CPU2DEV_2_BASE                  0x0248
155 #define MV64x60_CPU2DEV_2_SIZE                  0x0250
156 #define MV64x60_CPU2DEV_3_BASE                  0x0038
157 #define MV64x60_CPU2DEV_3_SIZE                  0x0040
158
159 #define MV64x60_CPU2BOOT_0_BASE                 0x0238
160 #define MV64x60_CPU2BOOT_0_SIZE                 0x0240
161
162 #define MV64360_CPU2SRAM_BASE                   0x0268
163
164 /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
165 #define MV64x60_PCI_BUSES                       2
166 #define MV64x60_PCI_IO_WINDOWS_PER_BUS          1
167 #define MV64x60_PCI_MEM_WINDOWS_PER_BUS         4
168
169 #define MV64x60_CPU2PCI_SWAP_BYTE               0x00000000
170 #define MV64x60_CPU2PCI_SWAP_NONE               0x01000000
171 #define MV64x60_CPU2PCI_SWAP_BYTE_WORD          0x02000000
172 #define MV64x60_CPU2PCI_SWAP_WORD               0x03000000
173
174 #define MV64x60_CPU2PCI_MEM_REQ64               (1<<27)
175
176 #define MV64x60_CPU2PCI0_IO_BASE                0x0048
177 #define MV64x60_CPU2PCI0_IO_SIZE                0x0050
178 #define MV64x60_CPU2PCI0_MEM_0_BASE             0x0058
179 #define MV64x60_CPU2PCI0_MEM_0_SIZE             0x0060
180 #define MV64x60_CPU2PCI0_MEM_1_BASE             0x0080
181 #define MV64x60_CPU2PCI0_MEM_1_SIZE             0x0088
182 #define MV64x60_CPU2PCI0_MEM_2_BASE             0x0258
183 #define MV64x60_CPU2PCI0_MEM_2_SIZE             0x0260
184 #define MV64x60_CPU2PCI0_MEM_3_BASE             0x0280
185 #define MV64x60_CPU2PCI0_MEM_3_SIZE             0x0288
186
187 #define MV64x60_CPU2PCI0_IO_REMAP               0x00f0
188 #define MV64x60_CPU2PCI0_MEM_0_REMAP_LO         0x00f8
189 #define MV64x60_CPU2PCI0_MEM_0_REMAP_HI         0x0320
190 #define MV64x60_CPU2PCI0_MEM_1_REMAP_LO         0x0100
191 #define MV64x60_CPU2PCI0_MEM_1_REMAP_HI         0x0328
192 #define MV64x60_CPU2PCI0_MEM_2_REMAP_LO         0x02f8
193 #define MV64x60_CPU2PCI0_MEM_2_REMAP_HI         0x0330
194 #define MV64x60_CPU2PCI0_MEM_3_REMAP_LO         0x0300
195 #define MV64x60_CPU2PCI0_MEM_3_REMAP_HI         0x0338
196
197 #define MV64x60_CPU2PCI1_IO_BASE                0x0090
198 #define MV64x60_CPU2PCI1_IO_SIZE                0x0098
199 #define MV64x60_CPU2PCI1_MEM_0_BASE             0x00a0
200 #define MV64x60_CPU2PCI1_MEM_0_SIZE             0x00a8
201 #define MV64x60_CPU2PCI1_MEM_1_BASE             0x00b0
202 #define MV64x60_CPU2PCI1_MEM_1_SIZE             0x00b8
203 #define MV64x60_CPU2PCI1_MEM_2_BASE             0x02a0
204 #define MV64x60_CPU2PCI1_MEM_2_SIZE             0x02a8
205 #define MV64x60_CPU2PCI1_MEM_3_BASE             0x02b0
206 #define MV64x60_CPU2PCI1_MEM_3_SIZE             0x02b8
207
208 #define MV64x60_CPU2PCI1_IO_REMAP               0x0108
209 #define MV64x60_CPU2PCI1_MEM_0_REMAP_LO         0x0110
210 #define MV64x60_CPU2PCI1_MEM_0_REMAP_HI         0x0340
211 #define MV64x60_CPU2PCI1_MEM_1_REMAP_LO         0x0118
212 #define MV64x60_CPU2PCI1_MEM_1_REMAP_HI         0x0348
213 #define MV64x60_CPU2PCI1_MEM_2_REMAP_LO         0x0310
214 #define MV64x60_CPU2PCI1_MEM_2_REMAP_HI         0x0350
215 #define MV64x60_CPU2PCI1_MEM_3_REMAP_LO         0x0318
216 #define MV64x60_CPU2PCI1_MEM_3_REMAP_HI         0x0358
217
218 /* CPU Control Registers */
219 #define MV64x60_CPU_CONFIG                      0x0000
220 #define MV64x60_CPU_MODE                        0x0120
221 #define MV64x60_CPU_MASTER_CNTL                 0x0160
222 #define MV64x60_CPU_XBAR_CNTL_LO                0x0150
223 #define MV64x60_CPU_XBAR_CNTL_HI                0x0158
224 #define MV64x60_CPU_XBAR_TO                     0x0168
225
226 #define GT64260_CPU_RR_XBAR_CNTL_LO             0x0170
227 #define GT64260_CPU_RR_XBAR_CNTL_HI             0x0178
228
229 #define MV64360_CPU_PADS_CALIBRATION            0x03b4
230 #define MV64360_CPU_RESET_SAMPLE_LO             0x03c4
231 #define MV64360_CPU_RESET_SAMPLE_HI             0x03d4
232
233 /* SMP Register Map */
234 #define MV64360_WHO_AM_I                        0x0200
235 #define MV64360_CPU0_DOORBELL                   0x0214
236 #define MV64360_CPU0_DOORBELL_CLR               0x021c
237 #define MV64360_CPU0_DOORBELL_MASK              0x0234
238 #define MV64360_CPU1_DOORBELL                   0x0224
239 #define MV64360_CPU1_DOORBELL_CLR               0x022c
240 #define MV64360_CPU1_DOORBELL_MASK              0x023c
241 #define MV64360_CPUx_DOORBELL(x)                (0x0214 + ((x)*0x10))
242 #define MV64360_CPUx_DOORBELL_CLR(x)            (0x021c + ((x)*0x10))
243 #define MV64360_CPUx_DOORBELL_MASK(x)           (0x0234 + ((x)*0x08))
244 #define MV64360_SEMAPHORE_0                     0x0244
245 #define MV64360_SEMAPHORE_1                     0x024c
246 #define MV64360_SEMAPHORE_2                     0x0254
247 #define MV64360_SEMAPHORE_3                     0x025c
248 #define MV64360_SEMAPHORE_4                     0x0264
249 #define MV64360_SEMAPHORE_5                     0x026c
250 #define MV64360_SEMAPHORE_6                     0x0274
251 #define MV64360_SEMAPHORE_7                     0x027c
252
253 /* CPU Sync Barrier Registers */
254 #define GT64260_CPU_SYNC_BARRIER_PCI0           0x00c0
255 #define GT64260_CPU_SYNC_BARRIER_PCI1           0x00c8
256
257 #define MV64360_CPU0_SYNC_BARRIER_TRIG          0x00c0
258 #define MV64360_CPU0_SYNC_BARRIER_VIRT          0x00c8
259 #define MV64360_CPU1_SYNC_BARRIER_TRIG          0x00d0
260 #define MV64360_CPU1_SYNC_BARRIER_VIRT          0x00d8
261
262 /* CPU Deadlock and Ordering registers (Rev B part only) */
263 #define GT64260_CPU_DEADLOCK_ORDERING                   0x02d0
264 #define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH            0x02d8
265 #define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE     0x02e0
266
267 /* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
268 #define MV64x260_CPU_PROT_WINDOWS               4
269
270 #define GT64260_CPU_PROT_ACCPROTECT             (1<<16)
271 #define GT64260_CPU_PROT_WRPROTECT              (1<<17)
272 #define GT64260_CPU_PROT_CACHEPROTECT           (1<<18)
273
274 #define MV64360_CPU_PROT_ACCPROTECT             (1<<20)
275 #define MV64360_CPU_PROT_WRPROTECT              (1<<21)
276 #define MV64360_CPU_PROT_CACHEPROTECT           (1<<22)
277 #define MV64360_CPU_PROT_WIN_ENABLE             (1<<31)
278
279 #define MV64x60_CPU_PROT_BASE_0                 0x0180
280 #define MV64x60_CPU_PROT_SIZE_0                 0x0188
281 #define MV64x60_CPU_PROT_BASE_1                 0x0190
282 #define MV64x60_CPU_PROT_SIZE_1                 0x0198
283 #define MV64x60_CPU_PROT_BASE_2                 0x01a0
284 #define MV64x60_CPU_PROT_SIZE_2                 0x01a8
285 #define MV64x60_CPU_PROT_BASE_3                 0x01b0
286 #define MV64x60_CPU_PROT_SIZE_3                 0x01b8
287
288 #define GT64260_CPU_PROT_BASE_4                 0x01c0
289 #define GT64260_CPU_PROT_SIZE_4                 0x01c8
290 #define GT64260_CPU_PROT_BASE_5                 0x01d0
291 #define GT64260_CPU_PROT_SIZE_5                 0x01d8
292 #define GT64260_CPU_PROT_BASE_6                 0x01e0
293 #define GT64260_CPU_PROT_SIZE_6                 0x01e8
294 #define GT64260_CPU_PROT_BASE_7                 0x01f0
295 #define GT64260_CPU_PROT_SIZE_7                 0x01f8
296
297 /* CPU Snoop Control Registers (64260 only) */
298 #define GT64260_CPU_SNOOP_WINDOWS               4
299
300 #define GT64260_CPU_SNOOP_NONE                  0x00000000
301 #define GT64260_CPU_SNOOP_WT                    0x00010000
302 #define GT64260_CPU_SNOOP_WB                    0x00020000
303 #define GT64260_CPU_SNOOP_MASK                  0x00030000
304 #define GT64260_CPU_SNOOP_ALL_BITS              GT64260_CPU_SNOOP_MASK
305
306 #define GT64260_CPU_SNOOP_BASE_0                0x0380
307 #define GT64260_CPU_SNOOP_SIZE_0                0x0388
308 #define GT64260_CPU_SNOOP_BASE_1                0x0390
309 #define GT64260_CPU_SNOOP_SIZE_1                0x0398
310 #define GT64260_CPU_SNOOP_BASE_2                0x03a0
311 #define GT64260_CPU_SNOOP_SIZE_2                0x03a8
312 #define GT64260_CPU_SNOOP_BASE_3                0x03b0
313 #define GT64260_CPU_SNOOP_SIZE_3                0x03b8
314
315 /* CPU Snoop Control Registers (64360 only) */
316 #define MV64360_CPU_SNOOP_WINDOWS               4
317 #define MV64360_CPU_SNOOP_NONE                  0x00000000
318 #define MV64360_CPU_SNOOP_WT                    0x00010000
319 #define MV64360_CPU_SNOOP_WB                    0x00020000
320 #define MV64360_CPU_SNOOP_MASK                  0x00030000
321 #define MV64360_CPU_SNOOP_ALL_BITS              MV64360_CPU_SNOOP_MASK
322
323
324 /* CPU Error Report Registers */
325 #define MV64x60_CPU_ERR_ADDR_LO                 0x0070
326 #define MV64x60_CPU_ERR_ADDR_HI                 0x0078
327 #define MV64x60_CPU_ERR_DATA_LO                 0x0128
328 #define MV64x60_CPU_ERR_DATA_HI                 0x0130
329 #define MV64x60_CPU_ERR_PARITY                  0x0138
330 #define MV64x60_CPU_ERR_CAUSE                   0x0140
331 #define MV64x60_CPU_ERR_MASK                    0x0148
332
333 /*
334  *****************************************************************************
335  *
336  *      SRAM Controller Registers
337  *
338  *****************************************************************************
339  */
340
341 #define MV64360_SRAM_CONFIG                     0x0380
342 #define MV64360_SRAM_TEST_MODE                  0x03f4
343 #define MV64360_SRAM_ERR_CAUSE                  0x0388
344 #define MV64360_SRAM_ERR_ADDR_LO                0x0390
345 #define MV64360_SRAM_ERR_ADDR_HI                0x03f8
346 #define MV64360_SRAM_ERR_DATA_LO                0x0398
347 #define MV64360_SRAM_ERR_DATA_HI                0x03a0
348 #define MV64360_SRAM_ERR_PARITY                 0x03a8
349
350 #define MV64360_SRAM_SIZE                       0x00040000 /* 2Mb/256KB SRAM */
351
352 /*
353  *****************************************************************************
354  *
355  *      SDRAM/MEM Controller Registers
356  *
357  *****************************************************************************
358  */
359
360 /* SDRAM Config Registers (64260) */
361 #define GT64260_SDRAM_CONFIG                    0x0448
362
363 /* SDRAM Error Report Registers (64260) */
364 #define GT64260_SDRAM_ERR_DATA_LO               0x0484
365 #define GT64260_SDRAM_ERR_DATA_HI               0x0480
366 #define GT64260_SDRAM_ERR_ADDR                  0x0490
367 #define GT64260_SDRAM_ERR_ECC_RCVD              0x0488
368 #define GT64260_SDRAM_ERR_ECC_CALC              0x048c
369 #define GT64260_SDRAM_ERR_ECC_CNTL              0x0494
370 #define GT64260_SDRAM_ERR_ECC_ERR_CNT           0x0498
371
372 /* SDRAM Config Registers (64360) */
373 #define MV64360_SDRAM_CONFIG                    0x1400
374
375 /* SDRAM Control Registers */
376 #define MV64360_D_UNIT_CONTROL_LOW              0x1404
377 #define MV64360_D_UNIT_CONTROL_HIGH             0x1424
378 #define MV64460_D_UNIT_MMASK                    0x14b0
379
380 /* SDRAM Error Report Registers (64360) */
381 #define MV64360_SDRAM_ERR_DATA_LO               0x1444
382 #define MV64360_SDRAM_ERR_DATA_HI               0x1440
383 #define MV64360_SDRAM_ERR_ADDR                  0x1450
384 #define MV64360_SDRAM_ERR_ECC_RCVD              0x1448
385 #define MV64360_SDRAM_ERR_ECC_CALC              0x144c
386 #define MV64360_SDRAM_ERR_ECC_CNTL              0x1454
387 #define MV64360_SDRAM_ERR_ECC_ERR_CNT           0x1458
388
389 /*
390  *****************************************************************************
391  *
392  *      Device/BOOT Controller Registers
393  *
394  *****************************************************************************
395  */
396
397 /* Device Control Registers */
398 #define MV64x60_DEV_BANK_PARAMS_0               0x045c
399 #define MV64x60_DEV_BANK_PARAMS_1               0x0460
400 #define MV64x60_DEV_BANK_PARAMS_2               0x0464
401 #define MV64x60_DEV_BANK_PARAMS_3               0x0468
402 #define MV64x60_DEV_BOOT_PARAMS                 0x046c
403 #define MV64x60_DEV_IF_CNTL                     0x04c0
404 #define MV64x60_DEV_IF_XBAR_CNTL_LO             0x04c8
405 #define MV64x60_DEV_IF_XBAR_CNTL_HI             0x04cc
406 #define MV64x60_DEV_IF_XBAR_CNTL_TO             0x04c4
407
408 /* Device Interrupt Registers */
409 #define MV64x60_DEV_INTR_CAUSE                  0x04d0
410 #define MV64x60_DEV_INTR_MASK                   0x04d4
411 #define MV64x60_DEV_INTR_ERR_ADDR               0x04d8
412
413 #define MV64360_DEV_INTR_ERR_DATA               0x04dc
414 #define MV64360_DEV_INTR_ERR_PAR                0x04e0
415
416 /*
417  *****************************************************************************
418  *
419  *      PCI Bridge Interface Registers
420  *
421  *****************************************************************************
422  */
423
424 /* PCI Configuration Access Registers */
425 #define MV64x60_PCI0_CONFIG_ADDR                0x0cf8
426 #define MV64x60_PCI0_CONFIG_DATA                0x0cfc
427 #define MV64x60_PCI0_IACK                       0x0c34
428
429 #define MV64x60_PCI1_CONFIG_ADDR                0x0c78
430 #define MV64x60_PCI1_CONFIG_DATA                0x0c7c
431 #define MV64x60_PCI1_IACK                       0x0cb4
432
433 /* PCI Control Registers */
434 #define MV64x60_PCI0_CMD                        0x0c00
435 #define MV64x60_PCI0_MODE                       0x0d00
436 #define MV64x60_PCI0_TO_RETRY                   0x0c04
437 #define MV64x60_PCI0_RD_BUF_DISCARD_TIMER       0x0d04
438 #define MV64x60_PCI0_MSI_TRIGGER_TIMER          0x0c38
439 #define MV64x60_PCI0_ARBITER_CNTL               0x1d00
440 #define MV64x60_PCI0_XBAR_CNTL_LO               0x1d08
441 #define MV64x60_PCI0_XBAR_CNTL_HI               0x1d0c
442 #define MV64x60_PCI0_XBAR_CNTL_TO               0x1d04
443 #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO       0x1d18
444 #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI       0x1d1c
445 #define MV64x60_PCI0_SYNC_BARRIER               0x1d10
446 #define MV64x60_PCI0_P2P_CONFIG                 0x1d14
447 #define MV64x60_PCI0_INTR_MASK
448
449 #define GT64260_PCI0_P2P_SWAP_CNTL              0x1d54
450
451 #define MV64x60_PCI1_CMD                        0x0c80
452 #define MV64x60_PCI1_MODE                       0x0d80
453 #define MV64x60_PCI1_TO_RETRY                   0x0c84
454 #define MV64x60_PCI1_RD_BUF_DISCARD_TIMER       0x0d84
455 #define MV64x60_PCI1_MSI_TRIGGER_TIMER          0x0cb8
456 #define MV64x60_PCI1_ARBITER_CNTL               0x1d80
457 #define MV64x60_PCI1_XBAR_CNTL_LO               0x1d88
458 #define MV64x60_PCI1_XBAR_CNTL_HI               0x1d8c
459 #define MV64x60_PCI1_XBAR_CNTL_TO               0x1d84
460 #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO       0x1d98
461 #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI       0x1d9c
462 #define MV64x60_PCI1_SYNC_BARRIER               0x1d90
463 #define MV64x60_PCI1_P2P_CONFIG                 0x1d94
464
465 #define GT64260_PCI1_P2P_SWAP_CNTL              0x1dd4
466
467 /* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
468 #define MV64x60_PCIMODE_CONVENTIONAL            0
469 #define MV64x60_PCIMODE_PCIX_66                 (1 << 4)
470 #define MV64x60_PCIMODE_PCIX_100                (2 << 4)
471 #define MV64x60_PCIMODE_PCIX_133                (3 << 4)
472 #define MV64x60_PCIMODE_MASK                    (0x3 << 4)
473
474 /* PCI Access Control Regions Registers */
475 #define GT64260_PCI_ACC_CNTL_PREFETCHEN         (1<<12)
476 #define GT64260_PCI_ACC_CNTL_DREADEN            (1<<13)
477 #define GT64260_PCI_ACC_CNTL_RDPREFETCH         (1<<16)
478 #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH     (1<<17)
479 #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH      (1<<18)
480 #define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES    0x00000000
481 #define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES    0x00100000
482 #define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES   0x00200000
483 #define GT64260_PCI_ACC_CNTL_MBURST_MASK        0x00300000
484 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
485 #define GT64260_PCI_ACC_CNTL_SWAP_NONE          0x01000000
486 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x02000000
487 #define GT64260_PCI_ACC_CNTL_SWAP_WORD          0x03000000
488 #define GT64260_PCI_ACC_CNTL_SWAP_MASK          0x03000000
489 #define GT64260_PCI_ACC_CNTL_ACCPROT            (1<<28)
490 #define GT64260_PCI_ACC_CNTL_WRPROT             (1<<29)
491
492 #define GT64260_PCI_ACC_CNTL_ALL_BITS   (GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
493                                          GT64260_PCI_ACC_CNTL_DREADEN |       \
494                                          GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
495                                          GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
496                                          GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
497                                          GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
498                                          GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
499                                          GT64260_PCI_ACC_CNTL_ACCPROT|        \
500                                          GT64260_PCI_ACC_CNTL_WRPROT)
501
502 #define MV64360_PCI_ACC_CNTL_ENABLE             (1<<0)
503 #define MV64360_PCI_ACC_CNTL_REQ64              (1<<1)
504 #define MV64360_PCI_ACC_CNTL_SNOOP_NONE         0x00000000
505 #define MV64360_PCI_ACC_CNTL_SNOOP_WT           0x00000004
506 #define MV64360_PCI_ACC_CNTL_SNOOP_WB           0x00000008
507 #define MV64360_PCI_ACC_CNTL_SNOOP_MASK         0x0000000c
508 #define MV64360_PCI_ACC_CNTL_ACCPROT            (1<<4)
509 #define MV64360_PCI_ACC_CNTL_WRPROT             (1<<5)
510 #define MV64360_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
511 #define MV64360_PCI_ACC_CNTL_SWAP_NONE          0x00000040
512 #define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x00000080
513 #define MV64360_PCI_ACC_CNTL_SWAP_WORD          0x000000c0
514 #define MV64360_PCI_ACC_CNTL_SWAP_MASK          0x000000c0
515 #define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES    0x00000000
516 #define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES    0x00000100
517 #define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES   0x00000200
518 #define MV64360_PCI_ACC_CNTL_MBURST_MASK        0x00000300
519 #define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES    0x00000000
520 #define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES    0x00000400
521 #define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES   0x00000800
522 #define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES   0x00000c00
523 #define MV64360_PCI_ACC_CNTL_RDSIZE_MASK        0x00000c00
524
525 #define MV64360_PCI_ACC_CNTL_ALL_BITS   (MV64360_PCI_ACC_CNTL_ENABLE |      \
526                                          MV64360_PCI_ACC_CNTL_REQ64 |       \
527                                          MV64360_PCI_ACC_CNTL_SNOOP_MASK |  \
528                                          MV64360_PCI_ACC_CNTL_ACCPROT |     \
529                                          MV64360_PCI_ACC_CNTL_WRPROT |      \
530                                          MV64360_PCI_ACC_CNTL_SWAP_MASK |   \
531                                          MV64360_PCI_ACC_CNTL_MBURST_MASK | \
532                                          MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
533
534 #define MV64x60_PCI0_ACC_CNTL_0_BASE_LO         0x1e00
535 #define MV64x60_PCI0_ACC_CNTL_0_BASE_HI         0x1e04
536 #define MV64x60_PCI0_ACC_CNTL_0_SIZE            0x1e08
537 #define MV64x60_PCI0_ACC_CNTL_1_BASE_LO         0x1e10
538 #define MV64x60_PCI0_ACC_CNTL_1_BASE_HI         0x1e14
539 #define MV64x60_PCI0_ACC_CNTL_1_SIZE            0x1e18
540 #define MV64x60_PCI0_ACC_CNTL_2_BASE_LO         0x1e20
541 #define MV64x60_PCI0_ACC_CNTL_2_BASE_HI         0x1e24
542 #define MV64x60_PCI0_ACC_CNTL_2_SIZE            0x1e28
543 #define MV64x60_PCI0_ACC_CNTL_3_BASE_LO         0x1e30
544 #define MV64x60_PCI0_ACC_CNTL_3_BASE_HI         0x1e34
545 #define MV64x60_PCI0_ACC_CNTL_3_SIZE            0x1e38
546 #define MV64x60_PCI0_ACC_CNTL_4_BASE_LO         0x1e40
547 #define MV64x60_PCI0_ACC_CNTL_4_BASE_HI         0x1e44
548 #define MV64x60_PCI0_ACC_CNTL_4_SIZE            0x1e48
549 #define MV64x60_PCI0_ACC_CNTL_5_BASE_LO         0x1e50
550 #define MV64x60_PCI0_ACC_CNTL_5_BASE_HI         0x1e54
551 #define MV64x60_PCI0_ACC_CNTL_5_SIZE            0x1e58
552
553 #define GT64260_PCI0_ACC_CNTL_6_BASE_LO         0x1e60
554 #define GT64260_PCI0_ACC_CNTL_6_BASE_HI         0x1e64
555 #define GT64260_PCI0_ACC_CNTL_6_SIZE            0x1e68
556 #define GT64260_PCI0_ACC_CNTL_7_BASE_LO         0x1e70
557 #define GT64260_PCI0_ACC_CNTL_7_BASE_HI         0x1e74
558 #define GT64260_PCI0_ACC_CNTL_7_SIZE            0x1e78
559
560 #define MV64x60_PCI1_ACC_CNTL_0_BASE_LO         0x1e80
561 #define MV64x60_PCI1_ACC_CNTL_0_BASE_HI         0x1e84
562 #define MV64x60_PCI1_ACC_CNTL_0_SIZE            0x1e88
563 #define MV64x60_PCI1_ACC_CNTL_1_BASE_LO         0x1e90
564 #define MV64x60_PCI1_ACC_CNTL_1_BASE_HI         0x1e94
565 #define MV64x60_PCI1_ACC_CNTL_1_SIZE            0x1e98
566 #define MV64x60_PCI1_ACC_CNTL_2_BASE_LO         0x1ea0
567 #define MV64x60_PCI1_ACC_CNTL_2_BASE_HI         0x1ea4
568 #define MV64x60_PCI1_ACC_CNTL_2_SIZE            0x1ea8
569 #define MV64x60_PCI1_ACC_CNTL_3_BASE_LO         0x1eb0
570 #define MV64x60_PCI1_ACC_CNTL_3_BASE_HI         0x1eb4
571 #define MV64x60_PCI1_ACC_CNTL_3_SIZE            0x1eb8
572 #define MV64x60_PCI1_ACC_CNTL_4_BASE_LO         0x1ec0
573 #define MV64x60_PCI1_ACC_CNTL_4_BASE_HI         0x1ec4
574 #define MV64x60_PCI1_ACC_CNTL_4_SIZE            0x1ec8
575 #define MV64x60_PCI1_ACC_CNTL_5_BASE_LO         0x1ed0
576 #define MV64x60_PCI1_ACC_CNTL_5_BASE_HI         0x1ed4
577 #define MV64x60_PCI1_ACC_CNTL_5_SIZE            0x1ed8
578
579 #define GT64260_PCI1_ACC_CNTL_6_BASE_LO         0x1ee0
580 #define GT64260_PCI1_ACC_CNTL_6_BASE_HI         0x1ee4
581 #define GT64260_PCI1_ACC_CNTL_6_SIZE            0x1ee8
582 #define GT64260_PCI1_ACC_CNTL_7_BASE_LO         0x1ef0
583 #define GT64260_PCI1_ACC_CNTL_7_BASE_HI         0x1ef4
584 #define GT64260_PCI1_ACC_CNTL_7_SIZE            0x1ef8
585
586 /* PCI Snoop Control Registers (64260 only) */
587 #define GT64260_PCI_SNOOP_NONE                  0x00000000
588 #define GT64260_PCI_SNOOP_WT                    0x00001000
589 #define GT64260_PCI_SNOOP_WB                    0x00002000
590
591 #define GT64260_PCI0_SNOOP_0_BASE_LO            0x1f00
592 #define GT64260_PCI0_SNOOP_0_BASE_HI            0x1f04
593 #define GT64260_PCI0_SNOOP_0_SIZE               0x1f08
594 #define GT64260_PCI0_SNOOP_1_BASE_LO            0x1f10
595 #define GT64260_PCI0_SNOOP_1_BASE_HI            0x1f14
596 #define GT64260_PCI0_SNOOP_1_SIZE               0x1f18
597 #define GT64260_PCI0_SNOOP_2_BASE_LO            0x1f20
598 #define GT64260_PCI0_SNOOP_2_BASE_HI            0x1f24
599 #define GT64260_PCI0_SNOOP_2_SIZE               0x1f28
600 #define GT64260_PCI0_SNOOP_3_BASE_LO            0x1f30
601 #define GT64260_PCI0_SNOOP_3_BASE_HI            0x1f34
602 #define GT64260_PCI0_SNOOP_3_SIZE               0x1f38
603
604 #define GT64260_PCI1_SNOOP_0_BASE_LO            0x1f80
605 #define GT64260_PCI1_SNOOP_0_BASE_HI            0x1f84
606 #define GT64260_PCI1_SNOOP_0_SIZE               0x1f88
607 #define GT64260_PCI1_SNOOP_1_BASE_LO            0x1f90
608 #define GT64260_PCI1_SNOOP_1_BASE_HI            0x1f94
609 #define GT64260_PCI1_SNOOP_1_SIZE               0x1f98
610 #define GT64260_PCI1_SNOOP_2_BASE_LO            0x1fa0
611 #define GT64260_PCI1_SNOOP_2_BASE_HI            0x1fa4
612 #define GT64260_PCI1_SNOOP_2_SIZE               0x1fa8
613 #define GT64260_PCI1_SNOOP_3_BASE_LO            0x1fb0
614 #define GT64260_PCI1_SNOOP_3_BASE_HI            0x1fb4
615 #define GT64260_PCI1_SNOOP_3_SIZE               0x1fb8
616
617 /* PCI Error Report Registers */
618 #define MV64x60_PCI0_ERR_SERR_MASK              0x0c28
619 #define MV64x60_PCI0_ERR_ADDR_LO                0x1d40
620 #define MV64x60_PCI0_ERR_ADDR_HI                0x1d44
621 #define MV64x60_PCI0_ERR_DATA_LO                0x1d48
622 #define MV64x60_PCI0_ERR_DATA_HI                0x1d4c
623 #define MV64x60_PCI0_ERR_CMD                    0x1d50
624 #define MV64x60_PCI0_ERR_CAUSE                  0x1d58
625 #define MV64x60_PCI0_ERR_MASK                   0x1d5c
626
627 #define MV64x60_PCI1_ERR_SERR_MASK              0x0ca8
628 #define MV64x60_PCI1_ERR_ADDR_LO                0x1dc0
629 #define MV64x60_PCI1_ERR_ADDR_HI                0x1dc4
630 #define MV64x60_PCI1_ERR_DATA_LO                0x1dc8
631 #define MV64x60_PCI1_ERR_DATA_HI                0x1dcc
632 #define MV64x60_PCI1_ERR_CMD                    0x1dd0
633 #define MV64x60_PCI1_ERR_CAUSE                  0x1dd8
634 #define MV64x60_PCI1_ERR_MASK                   0x1ddc
635
636 /* PCI Slave Address Decoding Registers */
637 #define MV64x60_PCI0_MEM_0_SIZE                 0x0c08
638 #define MV64x60_PCI0_MEM_1_SIZE                 0x0d08
639 #define MV64x60_PCI0_MEM_2_SIZE                 0x0c0c
640 #define MV64x60_PCI0_MEM_3_SIZE                 0x0d0c
641 #define MV64x60_PCI1_MEM_0_SIZE                 0x0c88
642 #define MV64x60_PCI1_MEM_1_SIZE                 0x0d88
643 #define MV64x60_PCI1_MEM_2_SIZE                 0x0c8c
644 #define MV64x60_PCI1_MEM_3_SIZE                 0x0d8c
645
646 #define MV64x60_PCI0_BAR_ENABLE                 0x0c3c
647 #define MV64x60_PCI1_BAR_ENABLE                 0x0cbc
648
649 #define MV64x60_PCI0_PCI_DECODE_CNTL            0x0d3c
650 #define MV64x60_PCI1_PCI_DECODE_CNTL            0x0dbc
651
652 #define MV64x60_PCI0_SLAVE_MEM_0_REMAP          0x0c48
653 #define MV64x60_PCI0_SLAVE_MEM_1_REMAP          0x0d48
654 #define MV64x60_PCI0_SLAVE_MEM_2_REMAP          0x0c4c
655 #define MV64x60_PCI0_SLAVE_MEM_3_REMAP          0x0d4c
656 #define MV64x60_PCI0_SLAVE_DEV_0_REMAP          0x0c50
657 #define MV64x60_PCI0_SLAVE_DEV_1_REMAP          0x0d50
658 #define MV64x60_PCI0_SLAVE_DEV_2_REMAP          0x0d58
659 #define MV64x60_PCI0_SLAVE_DEV_3_REMAP          0x0c54
660 #define MV64x60_PCI0_SLAVE_BOOT_REMAP           0x0d54
661 #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO   0x0d5c
662 #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI   0x0d60
663 #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO   0x0d64
664 #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI   0x0d68
665 #define MV64x60_PCI0_SLAVE_P2P_IO_REMAP         0x0d6c
666 #define MV64x60_PCI0_SLAVE_CPU_REMAP            0x0d70
667
668 #define MV64x60_PCI1_SLAVE_MEM_0_REMAP          0x0cc8
669 #define MV64x60_PCI1_SLAVE_MEM_1_REMAP          0x0dc8
670 #define MV64x60_PCI1_SLAVE_MEM_2_REMAP          0x0ccc
671 #define MV64x60_PCI1_SLAVE_MEM_3_REMAP          0x0dcc
672 #define MV64x60_PCI1_SLAVE_DEV_0_REMAP          0x0cd0
673 #define MV64x60_PCI1_SLAVE_DEV_1_REMAP          0x0dd0
674 #define MV64x60_PCI1_SLAVE_DEV_2_REMAP          0x0dd8
675 #define MV64x60_PCI1_SLAVE_DEV_3_REMAP          0x0cd4
676 #define MV64x60_PCI1_SLAVE_BOOT_REMAP           0x0dd4
677 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO   0x0ddc
678 #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI   0x0de0
679 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO   0x0de4
680 #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI   0x0de8
681 #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP         0x0dec
682 #define MV64x60_PCI1_SLAVE_CPU_REMAP            0x0df0
683
684 #define MV64360_PCICFG_CPCI_HOTSWAP             0x68
685
686 /*
687  *****************************************************************************
688  *
689  *      ENET Controller Interface Registers
690  *
691  *****************************************************************************
692  */
693
694 /* ENET Controller Window Registers (6 windows) */
695 #define MV64360_ENET2MEM_WINDOWS                6
696
697 #define MV64360_ENET2MEM_0_BASE                 0x2200
698 #define MV64360_ENET2MEM_0_SIZE                 0x2204
699 #define MV64360_ENET2MEM_1_BASE                 0x2208
700 #define MV64360_ENET2MEM_1_SIZE                 0x220c
701 #define MV64360_ENET2MEM_2_BASE                 0x2210
702 #define MV64360_ENET2MEM_2_SIZE                 0x2214
703 #define MV64360_ENET2MEM_3_BASE                 0x2218
704 #define MV64360_ENET2MEM_3_SIZE                 0x221c
705 #define MV64360_ENET2MEM_4_BASE                 0x2220
706 #define MV64360_ENET2MEM_4_SIZE                 0x2224
707 #define MV64360_ENET2MEM_5_BASE                 0x2228
708 #define MV64360_ENET2MEM_5_SIZE                 0x222c
709
710 #define MV64360_ENET2MEM_SNOOP_NONE             0x00000000
711 #define MV64360_ENET2MEM_SNOOP_WT               0x00001000
712 #define MV64360_ENET2MEM_SNOOP_WB               0x00002000
713
714 #define MV64360_ENET2MEM_BAR_ENABLE             0x2290
715
716 #define MV64360_ENET2MEM_ACC_PROT_0             0x2294
717 #define MV64360_ENET2MEM_ACC_PROT_1             0x2298
718 #define MV64360_ENET2MEM_ACC_PROT_2             0x229c
719
720 /*
721  *****************************************************************************
722  *
723  *      MPSC Controller Interface Registers
724  *
725  *****************************************************************************
726  */
727
728 /* MPSC Controller Window Registers (4 windows) */
729 #define MV64360_MPSC2MEM_WINDOWS                4
730
731 #define MV64360_MPSC2MEM_0_BASE                 0xf200
732 #define MV64360_MPSC2MEM_0_SIZE                 0xf204
733 #define MV64360_MPSC2MEM_1_BASE                 0xf208
734 #define MV64360_MPSC2MEM_1_SIZE                 0xf20c
735 #define MV64360_MPSC2MEM_2_BASE                 0xf210
736 #define MV64360_MPSC2MEM_2_SIZE                 0xf214
737 #define MV64360_MPSC2MEM_3_BASE                 0xf218
738 #define MV64360_MPSC2MEM_3_SIZE                 0xf21c
739
740 #define MV64360_MPSC_0_REMAP                    0xf240
741 #define MV64360_MPSC_1_REMAP                    0xf244
742
743 #define MV64360_MPSC2MEM_SNOOP_NONE             0x00000000
744 #define MV64360_MPSC2MEM_SNOOP_WT               0x00001000
745 #define MV64360_MPSC2MEM_SNOOP_WB               0x00002000
746
747 #define MV64360_MPSC2MEM_BAR_ENABLE             0xf250
748
749 #define MV64360_MPSC2MEM_ACC_PROT_0             0xf254
750 #define MV64360_MPSC2MEM_ACC_PROT_1             0xf258
751
752 #define MV64360_MPSC2REGS_BASE                  0xf25c
753
754 /*
755  *****************************************************************************
756  *
757  *      Timer/Counter Interface Registers
758  *
759  *****************************************************************************
760  */
761
762 #define MV64x60_TIMR_CNTR_0                     0x0850
763 #define MV64x60_TIMR_CNTR_1                     0x0854
764 #define MV64x60_TIMR_CNTR_2                     0x0858
765 #define MV64x60_TIMR_CNTR_3                     0x085c
766 #define MV64x60_TIMR_CNTR_0_3_CNTL              0x0864
767 #define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE        0x0868
768 #define MV64x60_TIMR_CNTR_0_3_INTR_MASK         0x086c
769
770 #define GT64260_TIMR_CNTR_4                     0x0950
771 #define GT64260_TIMR_CNTR_5                     0x0954
772 #define GT64260_TIMR_CNTR_6                     0x0958
773 #define GT64260_TIMR_CNTR_7                     0x095c
774 #define GT64260_TIMR_CNTR_4_7_CNTL              0x0964
775 #define GT64260_TIMR_CNTR_4_7_INTR_CAUSE        0x0968
776 #define GT64260_TIMR_CNTR_4_7_INTR_MASK         0x096c
777
778 /*
779  *****************************************************************************
780  *
781  *      Communications Controller
782  *
783  *****************************************************************************
784  */
785
786 #define GT64260_SER_INIT_PCI_ADDR_HI            0xf320
787 #define GT64260_SER_INIT_LAST_DATA              0xf324
788 #define GT64260_SER_INIT_CONTROL                0xf328
789 #define GT64260_SER_INIT_STATUS                 0xf32c
790
791 #define MV64x60_COMM_ARBITER_CNTL               0xf300
792 #define MV64x60_COMM_CONFIG                     0xb40c
793 #define MV64x60_COMM_XBAR_TO                    0xf304
794 #define MV64x60_COMM_INTR_CAUSE                 0xf310
795 #define MV64x60_COMM_INTR_MASK                  0xf314
796 #define MV64x60_COMM_ERR_ADDR                   0xf318
797
798 #define MV64360_COMM_ARBITER_CNTL               0xf300
799
800 /*
801  *****************************************************************************
802  *
803  *      IDMA Controller Interface Registers
804  *
805  *****************************************************************************
806  */
807
808 /* IDMA Controller Window Registers (8 windows) */
809 #define MV64360_IDMA2MEM_WINDOWS                8
810
811 #define MV64360_IDMA2MEM_0_BASE                 0x0a00
812 #define MV64360_IDMA2MEM_0_SIZE                 0x0a04
813 #define MV64360_IDMA2MEM_1_BASE                 0x0a08
814 #define MV64360_IDMA2MEM_1_SIZE                 0x0a0c
815 #define MV64360_IDMA2MEM_2_BASE                 0x0a10
816 #define MV64360_IDMA2MEM_2_SIZE                 0x0a14
817 #define MV64360_IDMA2MEM_3_BASE                 0x0a18
818 #define MV64360_IDMA2MEM_3_SIZE                 0x0a1c
819 #define MV64360_IDMA2MEM_4_BASE                 0x0a20
820 #define MV64360_IDMA2MEM_4_SIZE                 0x0a24
821 #define MV64360_IDMA2MEM_5_BASE                 0x0a28
822 #define MV64360_IDMA2MEM_5_SIZE                 0x0a2c
823 #define MV64360_IDMA2MEM_6_BASE                 0x0a30
824 #define MV64360_IDMA2MEM_6_SIZE                 0x0a34
825 #define MV64360_IDMA2MEM_7_BASE                 0x0a38
826 #define MV64360_IDMA2MEM_7_SIZE                 0x0a3c
827
828 #define MV64360_IDMA2MEM_SNOOP_NONE             0x00000000
829 #define MV64360_IDMA2MEM_SNOOP_WT               0x00001000
830 #define MV64360_IDMA2MEM_SNOOP_WB               0x00002000
831
832 #define MV64360_IDMA2MEM_BAR_ENABLE             0x0a80
833
834 #define MV64360_IDMA2MEM_ACC_PROT_0             0x0a70
835 #define MV64360_IDMA2MEM_ACC_PROT_1             0x0a74
836 #define MV64360_IDMA2MEM_ACC_PROT_2             0x0a78
837 #define MV64360_IDMA2MEM_ACC_PROT_3             0x0a7c
838
839 #define MV64x60_IDMA_0_OFFSET                   0x0800
840 #define MV64x60_IDMA_1_OFFSET                   0x0804
841 #define MV64x60_IDMA_2_OFFSET                   0x0808
842 #define MV64x60_IDMA_3_OFFSET                   0x080c
843 #define MV64x60_IDMA_4_OFFSET                   0x0900
844 #define MV64x60_IDMA_5_OFFSET                   0x0904
845 #define MV64x60_IDMA_6_OFFSET                   0x0908
846 #define MV64x60_IDMA_7_OFFSET                   0x090c
847
848 #define MV64x60_IDMA_BYTE_COUNT                 (0x0800 - MV64x60_IDMA_0_OFFSET)
849 #define MV64x60_IDMA_SRC_ADDR                   (0x0810 - MV64x60_IDMA_0_OFFSET)
850 #define MV64x60_IDMA_DST_ADDR                   (0x0820 - MV64x60_IDMA_0_OFFSET)
851 #define MV64x60_IDMA_NEXT_DESC                  (0x0830 - MV64x60_IDMA_0_OFFSET)
852 #define MV64x60_IDMA_CUR_DESC                   (0x0870 - MV64x60_IDMA_0_OFFSET)
853 #define MV64x60_IDMA_SRC_PCI_ADDR_HI            (0x0890 - MV64x60_IDMA_0_OFFSET)
854 #define MV64x60_IDMA_DST_PCI_ADDR_HI            (0x08a0 - MV64x60_IDMA_0_OFFSET)
855 #define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI      (0x08b0 - MV64x60_IDMA_0_OFFSET)
856 #define MV64x60_IDMA_CONTROL_LO                 (0x0840 - MV64x60_IDMA_0_OFFSET)
857 #define MV64x60_IDMA_CONTROL_HI                 (0x0880 - MV64x60_IDMA_0_OFFSET)
858
859 #define MV64x60_IDMA_0_3_ARBITER_CNTL           0x0860
860 #define MV64x60_IDMA_4_7_ARBITER_CNTL           0x0960
861
862 #define MV64x60_IDMA_0_3_XBAR_TO                0x08d0
863 #define MV64x60_IDMA_4_7_XBAR_TO                0x09d0
864
865 #define MV64x60_IDMA_0_3_INTR_CAUSE             0x08c0
866 #define MV64x60_IDMA_0_3_INTR_MASK              0x08c4
867 #define MV64x60_IDMA_0_3_ERROR_ADDR             0x08c8
868 #define MV64x60_IDMA_0_3_ERROR_SELECT           0x08cc
869 #define MV64x60_IDMA_4_7_INTR_CAUSE             0x09c0
870 #define MV64x60_IDMA_4_7_INTR_MASK              0x09c4
871 #define MV64x60_IDMA_4_7_ERROR_ADDR             0x09c8
872 #define MV64x60_IDMA_4_7_ERROR_SELECT           0x09cc
873
874 /*
875  *****************************************************************************
876  *
877  *      Watchdog Timer Interface Registers
878  *
879  *****************************************************************************
880  */
881
882 #define MV64x60_WDT_WDC                         0xb410
883 #define MV64x60_WDT_WDV                         0xb414
884
885
886 /*
887  *****************************************************************************
888  *
889  *       General Purpose Pins Controller Interface Registers
890  *
891  *****************************************************************************
892  */
893
894 #define MV64x60_GPP_IO_CNTL                     0xf100
895 #define MV64x60_GPP_LEVEL_CNTL                  0xf110
896 #define MV64x60_GPP_VALUE                       0xf104
897 #define MV64x60_GPP_INTR_CAUSE                  0xf108
898 #define MV64x60_GPP_INTR_MASK                   0xf10c
899 #define MV64x60_GPP_VALUE_SET                   0xf118
900 #define MV64x60_GPP_VALUE_CLR                   0xf11c
901
902
903 /*
904  *****************************************************************************
905  *
906  *      Multi-Purpose Pins Controller Interface Registers
907  *
908  *****************************************************************************
909  */
910
911 #define MV64x60_MPP_CNTL_0                      0xf000
912 #define MV64x60_MPP_CNTL_1                      0xf004
913 #define MV64x60_MPP_CNTL_2                      0xf008
914 #define MV64x60_MPP_CNTL_3                      0xf00c
915 #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX      0xf010
916
917 #define MV64x60_ETH_BAR_GAP                     0x8
918 #define MV64x60_ETH_SIZE_REG_GAP                0x8
919 #define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP     0x4
920 #define MV64x60_ETH_PORT_ACCESS_CTRL_GAP        0x4
921
922 #define MV64x60_EBAR_ATTR_DRAM_CS0              0x00000E00
923 #define MV64x60_EBAR_ATTR_DRAM_CS1              0x00000D00
924 #define MV64x60_EBAR_ATTR_DRAM_CS2              0x00000B00
925 #define MV64x60_EBAR_ATTR_DRAM_CS3              0x00000700
926
927 #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0       0x00000000
928 #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1       0x00000100
929 #define MV64x60_EBAR_ATTR_CBS_SRAM              0x00000000
930 #define MV64x60_EBAR_ATTR_CBS_CPU_BUS           0x00000800
931
932
933 /*
934  *****************************************************************************
935  *
936  *      Interrupt Controller Interface Registers
937  *
938  *****************************************************************************
939  */
940
941 #define GT64260_IC_OFFSET                       0x0c18
942
943 #define GT64260_IC_MAIN_CAUSE_LO                0x0c18
944 #define GT64260_IC_MAIN_CAUSE_HI                0x0c68
945 #define GT64260_IC_CPU_INTR_MASK_LO             0x0c1c
946 #define GT64260_IC_CPU_INTR_MASK_HI             0x0c6c
947 #define GT64260_IC_CPU_SELECT_CAUSE             0x0c70
948 #define GT64260_IC_PCI0_INTR_MASK_LO            0x0c24
949 #define GT64260_IC_PCI0_INTR_MASK_HI            0x0c64
950 #define GT64260_IC_PCI0_SELECT_CAUSE            0x0c74
951 #define GT64260_IC_PCI1_INTR_MASK_LO            0x0ca4
952 #define GT64260_IC_PCI1_INTR_MASK_HI            0x0ce4
953 #define GT64260_IC_PCI1_SELECT_CAUSE            0x0cf4
954 #define GT64260_IC_CPU_INT_0_MASK               0x0e60
955 #define GT64260_IC_CPU_INT_1_MASK               0x0e64
956 #define GT64260_IC_CPU_INT_2_MASK               0x0e68
957 #define GT64260_IC_CPU_INT_3_MASK               0x0e6c
958
959 #define MV64360_IC_OFFSET                       0x0000
960
961 #define MV64360_IC_MAIN_CAUSE_LO                0x0004
962 #define MV64360_IC_MAIN_CAUSE_HI                0x000c
963 #define MV64360_IC_CPU0_INTR_MASK_LO            0x0014
964 #define MV64360_IC_CPU0_INTR_MASK_HI            0x001c
965 #define MV64360_IC_CPU0_SELECT_CAUSE            0x0024
966 #define MV64360_IC_CPU1_INTR_MASK_LO            0x0034
967 #define MV64360_IC_CPU1_INTR_MASK_HI            0x003c
968 #define MV64360_IC_CPU1_SELECT_CAUSE            0x0044
969 #define MV64360_IC_INT0_MASK_LO                 0x0054
970 #define MV64360_IC_INT0_MASK_HI                 0x005c
971 #define MV64360_IC_INT0_SELECT_CAUSE            0x0064
972 #define MV64360_IC_INT1_MASK_LO                 0x0074
973 #define MV64360_IC_INT1_MASK_HI                 0x007c
974 #define MV64360_IC_INT1_SELECT_CAUSE            0x0084
975
976 #endif /* __ASMPPC_MV64x60_DEFS_H */