git.oblomov.eu Git - linux-2.6/blob - drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Fiber)
  32  * 82571EB Dual Port Gigabit Mezzanine Adapter
  33  * 82571EB Quad Port Gigabit Mezzanine Adapter
  34  * 82571PT Gigabit PT Quad Port Server ExpressModule
  35  * 82572EI Gigabit Ethernet Controller (Copper)
  36  * 82572EI Gigabit Ethernet Controller (Fiber)
  37  * 82572EI Gigabit Ethernet Controller
  38  * 82573V Gigabit Ethernet Controller (Copper)
  39  * 82573E Gigabit Ethernet Controller (Copper)
  40  * 82573L Gigabit Ethernet Controller
  41  */
  42
  43 #include <linux/netdevice.h>
  44 #include <linux/delay.h>
  45 #include <linux/pci.h>
  46
  47 #include "e1000.h"
  48
  49 #define ID_LED_RESERVED_F746 0xF746
  50 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  51                               (ID_LED_OFF1_ON2  <<  8) | \
  52                               (ID_LED_DEF1_DEF2 <<  4) | \
  53                               (ID_LED_DEF1_DEF2))
  54
  55 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  56
  57 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  58 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  59 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  60 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  61                                       u16 words, u16 *data);
  62 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  63 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  64 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  65 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  66
  67 /**
  68  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  69  *  @hw: pointer to the HW structure
  70  *
  71  *  This is a function pointer entry point called by the api module.
  72  **/
  73 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  74 {
  75         struct e1000_phy_info *phy = &hw->phy;
  76         s32 ret_val;
  77
  78         if (hw->media_type != e1000_media_type_copper) {
  79                 phy->type = e1000_phy_none;
  80                 return 0;
  81         }
  82
  83         phy->addr                        = 1;
  84         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  85         phy->reset_delay_us              = 100;
  86
  87         switch (hw->mac.type) {
  88         case e1000_82571:
  89         case e1000_82572:
  90                 phy->type                = e1000_phy_igp_2;
  91                 break;
  92         case e1000_82573:
  93                 phy->type                = e1000_phy_m88;
  94                 break;
  95         default:
  96                 return -E1000_ERR_PHY;
  97                 break;
  98         }
  99
 100         /* This can only be done after all function pointers are setup. */
 101         ret_val = e1000_get_phy_id_82571(hw);
 102
 103         /* Verify phy id */
 104         switch (hw->mac.type) {
 105         case e1000_82571:
 106         case e1000_82572:
 107                 if (phy->id != IGP01E1000_I_PHY_ID)
 108                         return -E1000_ERR_PHY;
 109                 break;
 110         case e1000_82573:
 111                 if (phy->id != M88E1111_I_PHY_ID)
 112                         return -E1000_ERR_PHY;
 113                 break;
 114         default:
 115                 return -E1000_ERR_PHY;
 116                 break;
 117         }
 118
 119         return 0;
 120 }
 121
 122 /**
 123  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 124  *  @hw: pointer to the HW structure
 125  *
 126  *  This is a function pointer entry point called by the api module.
 127  **/
 128 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 129 {
 130         struct e1000_nvm_info *nvm = &hw->nvm;
 131         u32 eecd = er32(EECD);
 132         u16 size;
 133
 134         nvm->opcode_bits = 8;
 135         nvm->delay_usec = 1;
 136         switch (nvm->override) {
 137         case e1000_nvm_override_spi_large:
 138                 nvm->page_size = 32;
 139                 nvm->address_bits = 16;
 140                 break;
 141         case e1000_nvm_override_spi_small:
 142                 nvm->page_size = 8;
 143                 nvm->address_bits = 8;
 144                 break;
 145         default:
 146                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 147                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 148                 break;
 149         }
 150
 151         switch (hw->mac.type) {
 152         case e1000_82573:
 153                 if (((eecd >> 15) & 0x3) == 0x3) {
 154                         nvm->type = e1000_nvm_flash_hw;
 155                         nvm->word_size = 2048;
 156                         /*
 157                          * Autonomous Flash update bit must be cleared due
 158                          * to Flash update issue.
 159                          */
 160                         eecd &= ~E1000_EECD_AUPDEN;
 161                         ew32(EECD, eecd);
 162                         break;
 163                 }
 164                 /* Fall Through */
 165         default:
 166                 nvm->type = e1000_nvm_eeprom_spi;
 167                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 168                                   E1000_EECD_SIZE_EX_SHIFT);
 169                 /*
 170                  * Added to a constant, "size" becomes the left-shift value
 171                  * for setting word_size.
 172                  */
 173                 size += NVM_WORD_SIZE_BASE_SHIFT;
 174                 nvm->word_size  = 1 << size;
 175                 break;
 176         }
 177
 178         return 0;
 179 }
 180
 181 /**
 182  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 183  *  @hw: pointer to the HW structure
 184  *
 185  *  This is a function pointer entry point called by the api module.
 186  **/
 187 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 188 {
 189         struct e1000_hw *hw = &adapter->hw;
 190         struct e1000_mac_info *mac = &hw->mac;
 191         struct e1000_mac_operations *func = &mac->ops;
 192
 193         /* Set media type */
 194         switch (adapter->pdev->device) {
 195         case E1000_DEV_ID_82571EB_FIBER:
 196         case E1000_DEV_ID_82572EI_FIBER:
 197         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 198                 hw->media_type = e1000_media_type_fiber;
 199                 break;
 200         case E1000_DEV_ID_82571EB_SERDES:
 201         case E1000_DEV_ID_82572EI_SERDES:
 202         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 203         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 204                 hw->media_type = e1000_media_type_internal_serdes;
 205                 break;
 206         default:
 207                 hw->media_type = e1000_media_type_copper;
 208                 break;
 209         }
 210
 211         /* Set mta register count */
 212         mac->mta_reg_count = 128;
 213         /* Set rar entry count */
 214         mac->rar_entry_count = E1000_RAR_ENTRIES;
 215         /* Set if manageability features are enabled. */
 216         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 217
 218         /* check for link */
 219         switch (hw->media_type) {
 220         case e1000_media_type_copper:
 221                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 222                 func->check_for_link = e1000e_check_for_copper_link;
 223                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 224                 break;
 225         case e1000_media_type_fiber:
 226                 func->setup_physical_interface =
 227                         e1000_setup_fiber_serdes_link_82571;
 228                 func->check_for_link = e1000e_check_for_fiber_link;
 229                 func->get_link_up_info =
 230                         e1000e_get_speed_and_duplex_fiber_serdes;
 231                 break;
 232         case e1000_media_type_internal_serdes:
 233                 func->setup_physical_interface =
 234                         e1000_setup_fiber_serdes_link_82571;
 235                 func->check_for_link = e1000e_check_for_serdes_link;
 236                 func->get_link_up_info =
 237                         e1000e_get_speed_and_duplex_fiber_serdes;
 238                 break;
 239         default:
 240                 return -E1000_ERR_CONFIG;
 241                 break;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter)
 248 {
 249         struct e1000_hw *hw = &adapter->hw;
 250         static int global_quad_port_a; /* global port a indication */
 251         struct pci_dev *pdev = adapter->pdev;
 252         u16 eeprom_data = 0;
 253         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 254         s32 rc;
 255
 256         rc = e1000_init_mac_params_82571(adapter);
 257         if (rc)
 258                 return rc;
 259
 260         rc = e1000_init_nvm_params_82571(hw);
 261         if (rc)
 262                 return rc;
 263
 264         rc = e1000_init_phy_params_82571(hw);
 265         if (rc)
 266                 return rc;
 267
 268         /* tag quad port adapters first, it's used below */
 269         switch (pdev->device) {
 270         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 271         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 272         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 273         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 274                 adapter->flags |= FLAG_IS_QUAD_PORT;
 275                 /* mark the first port */
 276                 if (global_quad_port_a == 0)
 277                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 278                 /* Reset for multiple quad port adapters */
 279                 global_quad_port_a++;
 280                 if (global_quad_port_a == 4)
 281                         global_quad_port_a = 0;
 282                 break;
 283         default:
 284                 break;
 285         }
 286
 287         switch (adapter->hw.mac.type) {
 288         case e1000_82571:
 289                 /* these dual ports don't have WoL on port B at all */
 290                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 291                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 292                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 293                     (is_port_b))
 294                         adapter->flags &= ~FLAG_HAS_WOL;
 295                 /* quad ports only support WoL on port A */
 296                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 297                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 298                         adapter->flags &= ~FLAG_HAS_WOL;
 299                 /* Does not support WoL on any port */
 300                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 301                         adapter->flags &= ~FLAG_HAS_WOL;
 302                 break;
 303
 304         case e1000_82573:
 305                 if (pdev->device == E1000_DEV_ID_82573L) {
 306                         e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
 307                                        &eeprom_data);
 308                         if (eeprom_data & NVM_WORD1A_ASPM_MASK)
 309                                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 310                 }
 311                 break;
 312         default:
 313                 break;
 314         }
 315
 316         return 0;
 317 }
 318
 319 /**
 320  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 321  *  @hw: pointer to the HW structure
 322  *
 323  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 324  *  revision in the hardware structure.
 325  **/
 326 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 327 {
 328         struct e1000_phy_info *phy = &hw->phy;
 329
 330         switch (hw->mac.type) {
 331         case e1000_82571:
 332         case e1000_82572:
 333                 /*
 334                  * The 82571 firmware may still be configuring the PHY.
 335                  * In this case, we cannot access the PHY until the
 336                  * configuration is done.  So we explicitly set the
 337                  * PHY ID.
 338                  */
 339                 phy->id = IGP01E1000_I_PHY_ID;
 340                 break;
 341         case e1000_82573:
 342                 return e1000e_get_phy_id(hw);
 343                 break;
 344         default:
 345                 return -E1000_ERR_PHY;
 346                 break;
 347         }
 348
 349         return 0;
 350 }
 351
 352 /**
 353  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 354  *  @hw: pointer to the HW structure
 355  *
 356  *  Acquire the HW semaphore to access the PHY or NVM
 357  **/
 358 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 359 {
 360         u32 swsm;
 361         s32 timeout = hw->nvm.word_size + 1;
 362         s32 i = 0;
 363
 364         /* Get the FW semaphore. */
 365         for (i = 0; i < timeout; i++) {
 366                 swsm = er32(SWSM);
 367                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 368
 369                 /* Semaphore acquired if bit latched */
 370                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 371                         break;
 372
 373                 udelay(50);
 374         }
 375
 376         if (i == timeout) {
 377                 /* Release semaphores */
 378                 e1000e_put_hw_semaphore(hw);
 379                 hw_dbg(hw, "Driver can't access the NVM\n");
 380                 return -E1000_ERR_NVM;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /**
 387  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 388  *  @hw: pointer to the HW structure
 389  *
 390  *  Release hardware semaphore used to access the PHY or NVM
 391  **/
 392 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 393 {
 394         u32 swsm;
 395
 396         swsm = er32(SWSM);
 397
 398         swsm &= ~E1000_SWSM_SWESMBI;
 399
 400         ew32(SWSM, swsm);
 401 }
 402
 403 /**
 404  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 405  *  @hw: pointer to the HW structure
 406  *
 407  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 408  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 409  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 410  *  hardware semaphore.
 411  **/
 412 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 413 {
 414         s32 ret_val;
 415
 416         ret_val = e1000_get_hw_semaphore_82571(hw);
 417         if (ret_val)
 418                 return ret_val;
 419
 420         if (hw->mac.type != e1000_82573)
 421                 ret_val = e1000e_acquire_nvm(hw);
 422
 423         if (ret_val)
 424                 e1000_put_hw_semaphore_82571(hw);
 425
 426         return ret_val;
 427 }
 428
 429 /**
 430  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 431  *  @hw: pointer to the HW structure
 432  *
 433  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 434  **/
 435 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 436 {
 437         e1000e_release_nvm(hw);
 438         e1000_put_hw_semaphore_82571(hw);
 439 }
 440
 441 /**
 442  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 443  *  @hw: pointer to the HW structure
 444  *  @offset: offset within the EEPROM to be written to
 445  *  @words: number of words to write
 446  *  @data: 16 bit word(s) to be written to the EEPROM
 447  *
 448  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 449  *
 450  *  If e1000e_update_nvm_checksum is not called after this function, the
 451  *  EEPROM will most likely contain an invalid checksum.
 452  **/
 453 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 454                                  u16 *data)
 455 {
 456         s32 ret_val;
 457
 458         switch (hw->mac.type) {
 459         case e1000_82573:
 460                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 461                 break;
 462         case e1000_82571:
 463         case e1000_82572:
 464                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 465                 break;
 466         default:
 467                 ret_val = -E1000_ERR_NVM;
 468                 break;
 469         }
 470
 471         return ret_val;
 472 }
 473
 474 /**
 475  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 476  *  @hw: pointer to the HW structure
 477  *
 478  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 479  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 480  *  value to the EEPROM.
 481  **/
 482 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 483 {
 484         u32 eecd;
 485         s32 ret_val;
 486         u16 i;
 487
 488         ret_val = e1000e_update_nvm_checksum_generic(hw);
 489         if (ret_val)
 490                 return ret_val;
 491
 492         /*
 493          * If our nvm is an EEPROM, then we're done
 494          * otherwise, commit the checksum to the flash NVM.
 495          */
 496         if (hw->nvm.type != e1000_nvm_flash_hw)
 497                 return ret_val;
 498
 499         /* Check for pending operations. */
 500         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 501                 msleep(1);
 502                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 503                         break;
 504         }
 505
 506         if (i == E1000_FLASH_UPDATES)
 507                 return -E1000_ERR_NVM;
 508
 509         /* Reset the firmware if using STM opcode. */
 510         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 511                 /*
 512                  * The enabling of and the actual reset must be done
 513                  * in two write cycles.
 514                  */
 515                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 516                 e1e_flush();
 517                 ew32(HICR, E1000_HICR_FW_RESET);
 518         }
 519
 520         /* Commit the write to flash */
 521         eecd = er32(EECD) | E1000_EECD_FLUPD;
 522         ew32(EECD, eecd);
 523
 524         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 525                 msleep(1);
 526                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 527                         break;
 528         }
 529
 530         if (i == E1000_FLASH_UPDATES)
 531                 return -E1000_ERR_NVM;
 532
 533         return 0;
 534 }
 535
 536 /**
 537  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 538  *  @hw: pointer to the HW structure
 539  *
 540  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 541  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 542  **/
 543 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 544 {
 545         if (hw->nvm.type == e1000_nvm_flash_hw)
 546                 e1000_fix_nvm_checksum_82571(hw);
 547
 548         return e1000e_validate_nvm_checksum_generic(hw);
 549 }
 550
 551 /**
 552  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 553  *  @hw: pointer to the HW structure
 554  *  @offset: offset within the EEPROM to be written to
 555  *  @words: number of words to write
 556  *  @data: 16 bit word(s) to be written to the EEPROM
 557  *
 558  *  After checking for invalid values, poll the EEPROM to ensure the previous
 559  *  command has completed before trying to write the next word.  After write
 560  *  poll for completion.
 561  *
 562  *  If e1000e_update_nvm_checksum is not called after this function, the
 563  *  EEPROM will most likely contain an invalid checksum.
 564  **/
 565 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 566                                       u16 words, u16 *data)
 567 {
 568         struct e1000_nvm_info *nvm = &hw->nvm;
 569         u32 i;
 570         u32 eewr = 0;
 571         s32 ret_val = 0;
 572
 573         /*
 574          * A check for invalid values:  offset too large, too many words,
 575          * and not enough words.
 576          */
 577         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 578             (words == 0)) {
 579                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 580                 return -E1000_ERR_NVM;
 581         }
 582
 583         for (i = 0; i < words; i++) {
 584                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 585                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 586                        E1000_NVM_RW_REG_START;
 587
 588                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 589                 if (ret_val)
 590                         break;
 591
 592                 ew32(EEWR, eewr);
 593
 594                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 595                 if (ret_val)
 596                         break;
 597         }
 598
 599         return ret_val;
 600 }
 601
 602 /**
 603  *  e1000_get_cfg_done_82571 - Poll for configuration done
 604  *  @hw: pointer to the HW structure
 605  *
 606  *  Reads the management control register for the config done bit to be set.
 607  **/
 608 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 609 {
 610         s32 timeout = PHY_CFG_TIMEOUT;
 611
 612         while (timeout) {
 613                 if (er32(EEMNGCTL) &
 614                     E1000_NVM_CFG_DONE_PORT_0)
 615                         break;
 616                 msleep(1);
 617                 timeout--;
 618         }
 619         if (!timeout) {
 620                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 621                 return -E1000_ERR_RESET;
 622         }
 623
 624         return 0;
 625 }
 626
 627 /**
 628  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 629  *  @hw: pointer to the HW structure
 630  *  @active: TRUE to enable LPLU, FALSE to disable
 631  *
 632  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 633  *  this function also disables smart speed and vice versa.  LPLU will not be
 634  *  activated unless the device autonegotiation advertisement meets standards
 635  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 636  *  pointer entry point only called by PHY setup routines.
 637  **/
 638 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 639 {
 640         struct e1000_phy_info *phy = &hw->phy;
 641         s32 ret_val;
 642         u16 data;
 643
 644         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 645         if (ret_val)
 646                 return ret_val;
 647
 648         if (active) {
 649                 data |= IGP02E1000_PM_D0_LPLU;
 650                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 651                 if (ret_val)
 652                         return ret_val;
 653
 654                 /* When LPLU is enabled, we should disable SmartSpeed */
 655                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 656                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 657                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 658                 if (ret_val)
 659                         return ret_val;
 660         } else {
 661                 data &= ~IGP02E1000_PM_D0_LPLU;
 662                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 663                 /*
 664                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 665                  * during Dx states where the power conservation is most
 666                  * important.  During driver activity we should enable
 667                  * SmartSpeed, so performance is maintained.
 668                  */
 669                 if (phy->smart_speed == e1000_smart_speed_on) {
 670                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 671                                            &data);
 672                         if (ret_val)
 673                                 return ret_val;
 674
 675                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 676                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 677                                            data);
 678                         if (ret_val)
 679                                 return ret_val;
 680                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 681                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 682                                            &data);
 683                         if (ret_val)
 684                                 return ret_val;
 685
 686                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 687                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 688                                            data);
 689                         if (ret_val)
 690                                 return ret_val;
 691                 }
 692         }
 693
 694         return 0;
 695 }
 696
 697 /**
 698  *  e1000_reset_hw_82571 - Reset hardware
 699  *  @hw: pointer to the HW structure
 700  *
 701  *  This resets the hardware into a known state.  This is a
 702  *  function pointer entry point called by the api module.
 703  **/
 704 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 705 {
 706         u32 ctrl;
 707         u32 extcnf_ctrl;
 708         u32 ctrl_ext;
 709         u32 icr;
 710         s32 ret_val;
 711         u16 i = 0;
 712
 713         /*
 714          * Prevent the PCI-E bus from sticking if there is no TLP connection
 715          * on the last TLP read/write transaction when MAC is reset.
 716          */
 717         ret_val = e1000e_disable_pcie_master(hw);
 718         if (ret_val)
 719                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 720
 721         hw_dbg(hw, "Masking off all interrupts\n");
 722         ew32(IMC, 0xffffffff);
 723
 724         ew32(RCTL, 0);
 725         ew32(TCTL, E1000_TCTL_PSP);
 726         e1e_flush();
 727
 728         msleep(10);
 729
 730         /*
 731          * Must acquire the MDIO ownership before MAC reset.
 732          * Ownership defaults to firmware after a reset.
 733          */
 734         if (hw->mac.type == e1000_82573) {
 735                 extcnf_ctrl = er32(EXTCNF_CTRL);
 736                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 737
 738                 do {
 739                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 740                         extcnf_ctrl = er32(EXTCNF_CTRL);
 741
 742                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 743                                 break;
 744
 745                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 746
 747                         msleep(2);
 748                         i++;
 749                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 750         }
 751
 752         ctrl = er32(CTRL);
 753
 754         hw_dbg(hw, "Issuing a global reset to MAC\n");
 755         ew32(CTRL, ctrl | E1000_CTRL_RST);
 756
 757         if (hw->nvm.type == e1000_nvm_flash_hw) {
 758                 udelay(10);
 759                 ctrl_ext = er32(CTRL_EXT);
 760                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 761                 ew32(CTRL_EXT, ctrl_ext);
 762                 e1e_flush();
 763         }
 764
 765         ret_val = e1000e_get_auto_rd_done(hw);
 766         if (ret_val)
 767                 /* We don't want to continue accessing MAC registers. */
 768                 return ret_val;
 769
 770         /*
 771          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 772          * Need to wait for Phy configuration completion before accessing
 773          * NVM and Phy.
 774          */
 775         if (hw->mac.type == e1000_82573)
 776                 msleep(25);
 777
 778         /* Clear any pending interrupt events. */
 779         ew32(IMC, 0xffffffff);
 780         icr = er32(ICR);
 781
 782         if (hw->mac.type == e1000_82571 &&
 783                 hw->dev_spec.e82571.alt_mac_addr_is_present)
 784                         e1000e_set_laa_state_82571(hw, true);
 785
 786         return 0;
 787 }
 788
 789 /**
 790  *  e1000_init_hw_82571 - Initialize hardware
 791  *  @hw: pointer to the HW structure
 792  *
 793  *  This inits the hardware readying it for operation.
 794  **/
 795 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 796 {
 797         struct e1000_mac_info *mac = &hw->mac;
 798         u32 reg_data;
 799         s32 ret_val;
 800         u16 i;
 801         u16 rar_count = mac->rar_entry_count;
 802
 803         e1000_initialize_hw_bits_82571(hw);
 804
 805         /* Initialize identification LED */
 806         ret_val = e1000e_id_led_init(hw);
 807         if (ret_val) {
 808                 hw_dbg(hw, "Error initializing identification LED\n");
 809                 return ret_val;
 810         }
 811
 812         /* Disabling VLAN filtering */
 813         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 814         e1000e_clear_vfta(hw);
 815
 816         /* Setup the receive address. */
 817         /*
 818          * If, however, a locally administered address was assigned to the
 819          * 82571, we must reserve a RAR for it to work around an issue where
 820          * resetting one port will reload the MAC on the other port.
 821          */
 822         if (e1000e_get_laa_state_82571(hw))
 823                 rar_count--;
 824         e1000e_init_rx_addrs(hw, rar_count);
 825
 826         /* Zero out the Multicast HASH table */
 827         hw_dbg(hw, "Zeroing the MTA\n");
 828         for (i = 0; i < mac->mta_reg_count; i++)
 829                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 830
 831         /* Setup link and flow control */
 832         ret_val = e1000_setup_link_82571(hw);
 833
 834         /* Set the transmit descriptor write-back policy */
 835         reg_data = er32(TXDCTL);
 836         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 837                    E1000_TXDCTL_FULL_TX_DESC_WB |
 838                    E1000_TXDCTL_COUNT_DESC;
 839         ew32(TXDCTL, reg_data);
 840
 841         /* ...for both queues. */
 842         if (mac->type != e1000_82573) {
 843                 reg_data = er32(TXDCTL1);
 844                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 845                            E1000_TXDCTL_FULL_TX_DESC_WB |
 846                            E1000_TXDCTL_COUNT_DESC;
 847                 ew32(TXDCTL1, reg_data);
 848         } else {
 849                 e1000e_enable_tx_pkt_filtering(hw);
 850                 reg_data = er32(GCR);
 851                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
 852                 ew32(GCR, reg_data);
 853         }
 854
 855         /*
 856          * Clear all of the statistics registers (clear on read).  It is
 857          * important that we do this after we have tried to establish link
 858          * because the symbol error count will increment wildly if there
 859          * is no link.
 860          */
 861         e1000_clear_hw_cntrs_82571(hw);
 862
 863         return ret_val;
 864 }
 865
 866 /**
 867  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
 868  *  @hw: pointer to the HW structure
 869  *
 870  *  Initializes required hardware-dependent bits needed for normal operation.
 871  **/
 872 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
 873 {
 874         u32 reg;
 875
 876         /* Transmit Descriptor Control 0 */
 877         reg = er32(TXDCTL);
 878         reg |= (1 << 22);
 879         ew32(TXDCTL, reg);
 880
 881         /* Transmit Descriptor Control 1 */
 882         reg = er32(TXDCTL1);
 883         reg |= (1 << 22);
 884         ew32(TXDCTL1, reg);
 885
 886         /* Transmit Arbitration Control 0 */
 887         reg = er32(TARC0);
 888         reg &= ~(0xF << 27); /* 30:27 */
 889         switch (hw->mac.type) {
 890         case e1000_82571:
 891         case e1000_82572:
 892                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
 893                 break;
 894         default:
 895                 break;
 896         }
 897         ew32(TARC0, reg);
 898
 899         /* Transmit Arbitration Control 1 */
 900         reg = er32(TARC1);
 901         switch (hw->mac.type) {
 902         case e1000_82571:
 903         case e1000_82572:
 904                 reg &= ~((1 << 29) | (1 << 30));
 905                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
 906                 if (er32(TCTL) & E1000_TCTL_MULR)
 907                         reg &= ~(1 << 28);
 908                 else
 909                         reg |= (1 << 28);
 910                 ew32(TARC1, reg);
 911                 break;
 912         default:
 913                 break;
 914         }
 915
 916         /* Device Control */
 917         if (hw->mac.type == e1000_82573) {
 918                 reg = er32(CTRL);
 919                 reg &= ~(1 << 29);
 920                 ew32(CTRL, reg);
 921         }
 922
 923         /* Extended Device Control */
 924         if (hw->mac.type == e1000_82573) {
 925                 reg = er32(CTRL_EXT);
 926                 reg &= ~(1 << 23);
 927                 reg |= (1 << 22);
 928                 ew32(CTRL_EXT, reg);
 929         }
 930 }
 931
 932 /**
 933  *  e1000e_clear_vfta - Clear VLAN filter table
 934  *  @hw: pointer to the HW structure
 935  *
 936  *  Clears the register array which contains the VLAN filter table by
 937  *  setting all the values to 0.
 938  **/
 939 void e1000e_clear_vfta(struct e1000_hw *hw)
 940 {
 941         u32 offset;
 942         u32 vfta_value = 0;
 943         u32 vfta_offset = 0;
 944         u32 vfta_bit_in_reg = 0;
 945
 946         if (hw->mac.type == e1000_82573) {
 947                 if (hw->mng_cookie.vlan_id != 0) {
 948                         /*
 949                          * The VFTA is a 4096b bit-field, each identifying
 950                          * a single VLAN ID.  The following operations
 951                          * determine which 32b entry (i.e. offset) into the
 952                          * array we want to set the VLAN ID (i.e. bit) of
 953                          * the manageability unit.
 954                          */
 955                         vfta_offset = (hw->mng_cookie.vlan_id >>
 956                                        E1000_VFTA_ENTRY_SHIFT) &
 957                                       E1000_VFTA_ENTRY_MASK;
 958                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
 959                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
 960                 }
 961         }
 962         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
 963                 /*
 964                  * If the offset we want to clear is the same offset of the
 965                  * manageability VLAN ID, then clear all bits except that of
 966                  * the manageability unit.
 967                  */
 968                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
 969                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
 970                 e1e_flush();
 971         }
 972 }
 973
 974 /**
 975  *  e1000_mc_addr_list_update_82571 - Update Multicast addresses
 976  *  @hw: pointer to the HW structure
 977  *  @mc_addr_list: array of multicast addresses to program
 978  *  @mc_addr_count: number of multicast addresses to program
 979  *  @rar_used_count: the first RAR register free to program
 980  *  @rar_count: total number of supported Receive Address Registers
 981  *
 982  *  Updates the Receive Address Registers and Multicast Table Array.
 983  *  The caller must have a packed mc_addr_list of multicast addresses.
 984  *  The parameter rar_count will usually be hw->mac.rar_entry_count
 985  *  unless there are workarounds that change this.
 986  **/
 987 static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw,
 988                                             u8 *mc_addr_list,
 989                                             u32 mc_addr_count,
 990                                             u32 rar_used_count,
 991                                             u32 rar_count)
 992 {
 993         if (e1000e_get_laa_state_82571(hw))
 994                 rar_count--;
 995
 996         e1000e_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count,
 997                                           rar_used_count, rar_count);
 998 }
 999
1000 /**
1001  *  e1000_setup_link_82571 - Setup flow control and link settings
1002  *  @hw: pointer to the HW structure
1003  *
1004  *  Determines which flow control settings to use, then configures flow
1005  *  control.  Calls the appropriate media-specific link configuration
1006  *  function.  Assuming the adapter has a valid link partner, a valid link
1007  *  should be established.  Assumes the hardware has previously been reset
1008  *  and the transmitter and receiver are not enabled.
1009  **/
1010 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1011 {
1012         /*
1013          * 82573 does not have a word in the NVM to determine
1014          * the default flow control setting, so we explicitly
1015          * set it to full.
1016          */
1017         if (hw->mac.type == e1000_82573)
1018                 hw->mac.fc = e1000_fc_full;
1019
1020         return e1000e_setup_link(hw);
1021 }
1022
1023 /**
1024  *  e1000_setup_copper_link_82571 - Configure copper link settings
1025  *  @hw: pointer to the HW structure
1026  *
1027  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1028  *  for link, once link is established calls to configure collision distance
1029  *  and flow control are called.
1030  **/
1031 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1032 {
1033         u32 ctrl;
1034         u32 led_ctrl;
1035         s32 ret_val;
1036
1037         ctrl = er32(CTRL);
1038         ctrl |= E1000_CTRL_SLU;
1039         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1040         ew32(CTRL, ctrl);
1041
1042         switch (hw->phy.type) {
1043         case e1000_phy_m88:
1044                 ret_val = e1000e_copper_link_setup_m88(hw);
1045                 break;
1046         case e1000_phy_igp_2:
1047                 ret_val = e1000e_copper_link_setup_igp(hw);
1048                 /* Setup activity LED */
1049                 led_ctrl = er32(LEDCTL);
1050                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1051                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1052                 ew32(LEDCTL, led_ctrl);
1053                 break;
1054         default:
1055                 return -E1000_ERR_PHY;
1056                 break;
1057         }
1058
1059         if (ret_val)
1060                 return ret_val;
1061
1062         ret_val = e1000e_setup_copper_link(hw);
1063
1064         return ret_val;
1065 }
1066
1067 /**
1068  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1069  *  @hw: pointer to the HW structure
1070  *
1071  *  Configures collision distance and flow control for fiber and serdes links.
1072  *  Upon successful setup, poll for link.
1073  **/
1074 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1075 {
1076         switch (hw->mac.type) {
1077         case e1000_82571:
1078         case e1000_82572:
1079                 /*
1080                  * If SerDes loopback mode is entered, there is no form
1081                  * of reset to take the adapter out of that mode.  So we
1082                  * have to explicitly take the adapter out of loopback
1083                  * mode.  This prevents drivers from twiddling their thumbs
1084                  * if another tool failed to take it out of loopback mode.
1085                  */
1086                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1087                 break;
1088         default:
1089                 break;
1090         }
1091
1092         return e1000e_setup_fiber_serdes_link(hw);
1093 }
1094
1095 /**
1096  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1097  *  @hw: pointer to the HW structure
1098  *  @data: pointer to the NVM (EEPROM)
1099  *
1100  *  Read the EEPROM for the current default LED configuration.  If the
1101  *  LED configuration is not valid, set to a valid LED configuration.
1102  **/
1103 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1104 {
1105         s32 ret_val;
1106
1107         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1108         if (ret_val) {
1109                 hw_dbg(hw, "NVM Read Error\n");
1110                 return ret_val;
1111         }
1112
1113         if (hw->mac.type == e1000_82573 &&
1114             *data == ID_LED_RESERVED_F746)
1115                 *data = ID_LED_DEFAULT_82573;
1116         else if (*data == ID_LED_RESERVED_0000 ||
1117                  *data == ID_LED_RESERVED_FFFF)
1118                 *data = ID_LED_DEFAULT;
1119
1120         return 0;
1121 }
1122
1123 /**
1124  *  e1000e_get_laa_state_82571 - Get locally administered address state
1125  *  @hw: pointer to the HW structure
1126  *
1127  *  Retrieve and return the current locally administered address state.
1128  **/
1129 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1130 {
1131         if (hw->mac.type != e1000_82571)
1132                 return 0;
1133
1134         return hw->dev_spec.e82571.laa_is_present;
1135 }
1136
1137 /**
1138  *  e1000e_set_laa_state_82571 - Set locally administered address state
1139  *  @hw: pointer to the HW structure
1140  *  @state: enable/disable locally administered address
1141  *
1142  *  Enable/Disable the current locally administers address state.
1143  **/
1144 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1145 {
1146         if (hw->mac.type != e1000_82571)
1147                 return;
1148
1149         hw->dev_spec.e82571.laa_is_present = state;
1150
1151         /* If workaround is activated... */
1152         if (state)
1153                 /*
1154                  * Hold a copy of the LAA in RAR[14] This is done so that
1155                  * between the time RAR[0] gets clobbered and the time it
1156                  * gets fixed, the actual LAA is in one of the RARs and no
1157                  * incoming packets directed to this port are dropped.
1158                  * Eventually the LAA will be in RAR[0] and RAR[14].
1159                  */
1160                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1161 }
1162
1163 /**
1164  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1165  *  @hw: pointer to the HW structure
1166  *
1167  *  Verifies that the EEPROM has completed the update.  After updating the
1168  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1169  *  the checksum fix is not implemented, we need to set the bit and update
1170  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1171  *  we need to return bad checksum.
1172  **/
1173 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1174 {
1175         struct e1000_nvm_info *nvm = &hw->nvm;
1176         s32 ret_val;
1177         u16 data;
1178
1179         if (nvm->type != e1000_nvm_flash_hw)
1180                 return 0;
1181
1182         /*
1183          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1184          * 10h-12h.  Checksum may need to be fixed.
1185          */
1186         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1187         if (ret_val)
1188                 return ret_val;
1189
1190         if (!(data & 0x10)) {
1191                 /*
1192                  * Read 0x23 and check bit 15.  This bit is a 1
1193                  * when the checksum has already been fixed.  If
1194                  * the checksum is still wrong and this bit is a
1195                  * 1, we need to return bad checksum.  Otherwise,
1196                  * we need to set this bit to a 1 and update the
1197                  * checksum.
1198                  */
1199                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1200                 if (ret_val)
1201                         return ret_val;
1202
1203                 if (!(data & 0x8000)) {
1204                         data |= 0x8000;
1205                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1206                         if (ret_val)
1207                                 return ret_val;
1208                         ret_val = e1000e_update_nvm_checksum(hw);
1209                 }
1210         }
1211
1212         return 0;
1213 }
1214
1215 /**
1216  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1217  *  @hw: pointer to the HW structure
1218  *
1219  *  Clears the hardware counters by reading the counter registers.
1220  **/
1221 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1222 {
1223         u32 temp;
1224
1225         e1000e_clear_hw_cntrs_base(hw);
1226
1227         temp = er32(PRC64);
1228         temp = er32(PRC127);
1229         temp = er32(PRC255);
1230         temp = er32(PRC511);
1231         temp = er32(PRC1023);
1232         temp = er32(PRC1522);
1233         temp = er32(PTC64);
1234         temp = er32(PTC127);
1235         temp = er32(PTC255);
1236         temp = er32(PTC511);
1237         temp = er32(PTC1023);
1238         temp = er32(PTC1522);
1239
1240         temp = er32(ALGNERRC);
1241         temp = er32(RXERRC);
1242         temp = er32(TNCRS);
1243         temp = er32(CEXTERR);
1244         temp = er32(TSCTC);
1245         temp = er32(TSCTFC);
1246
1247         temp = er32(MGTPRC);
1248         temp = er32(MGTPDC);
1249         temp = er32(MGTPTC);
1250
1251         temp = er32(IAC);
1252         temp = er32(ICRXOC);
1253
1254         temp = er32(ICRXPTC);
1255         temp = er32(ICRXATC);
1256         temp = er32(ICTXPTC);
1257         temp = er32(ICTXATC);
1258         temp = er32(ICTXQEC);
1259         temp = er32(ICTXQMTC);
1260         temp = er32(ICRXDMTC);
1261 }
1262
1263 static struct e1000_mac_operations e82571_mac_ops = {
1264         .mng_mode_enab          = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1265         /* .check_for_link: media type dependent */
1266         .cleanup_led            = e1000e_cleanup_led_generic,
1267         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1268         .get_bus_info           = e1000e_get_bus_info_pcie,
1269         /* .get_link_up_info: media type dependent */
1270         .led_on                 = e1000e_led_on_generic,
1271         .led_off                = e1000e_led_off_generic,
1272         .mc_addr_list_update    = e1000_mc_addr_list_update_82571,
1273         .reset_hw               = e1000_reset_hw_82571,
1274         .init_hw                = e1000_init_hw_82571,
1275         .setup_link             = e1000_setup_link_82571,
1276         /* .setup_physical_interface: media type dependent */
1277 };
1278
1279 static struct e1000_phy_operations e82_phy_ops_igp = {
1280         .acquire_phy            = e1000_get_hw_semaphore_82571,
1281         .check_reset_block      = e1000e_check_reset_block_generic,
1282         .commit_phy             = NULL,
1283         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1284         .get_cfg_done           = e1000_get_cfg_done_82571,
1285         .get_cable_length       = e1000e_get_cable_length_igp_2,
1286         .get_phy_info           = e1000e_get_phy_info_igp,
1287         .read_phy_reg           = e1000e_read_phy_reg_igp,
1288         .release_phy            = e1000_put_hw_semaphore_82571,
1289         .reset_phy              = e1000e_phy_hw_reset_generic,
1290         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1291         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1292         .write_phy_reg          = e1000e_write_phy_reg_igp,
1293 };
1294
1295 static struct e1000_phy_operations e82_phy_ops_m88 = {
1296         .acquire_phy            = e1000_get_hw_semaphore_82571,
1297         .check_reset_block      = e1000e_check_reset_block_generic,
1298         .commit_phy             = e1000e_phy_sw_reset,
1299         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1300         .get_cfg_done           = e1000e_get_cfg_done,
1301         .get_cable_length       = e1000e_get_cable_length_m88,
1302         .get_phy_info           = e1000e_get_phy_info_m88,
1303         .read_phy_reg           = e1000e_read_phy_reg_m88,
1304         .release_phy            = e1000_put_hw_semaphore_82571,
1305         .reset_phy              = e1000e_phy_hw_reset_generic,
1306         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1307         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1308         .write_phy_reg          = e1000e_write_phy_reg_m88,
1309 };
1310
1311 static struct e1000_nvm_operations e82571_nvm_ops = {
1312         .acquire_nvm            = e1000_acquire_nvm_82571,
1313         .read_nvm               = e1000e_read_nvm_eerd,
1314         .release_nvm            = e1000_release_nvm_82571,
1315         .update_nvm             = e1000_update_nvm_checksum_82571,
1316         .valid_led_default      = e1000_valid_led_default_82571,
1317         .validate_nvm           = e1000_validate_nvm_checksum_82571,
1318         .write_nvm              = e1000_write_nvm_82571,
1319 };
1320
1321 struct e1000_info e1000_82571_info = {
1322         .mac                    = e1000_82571,
1323         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1324                                   | FLAG_HAS_JUMBO_FRAMES
1325                                   | FLAG_HAS_STATS_PTC_PRC
1326                                   | FLAG_HAS_WOL
1327                                   | FLAG_APME_IN_CTRL3
1328                                   | FLAG_RX_CSUM_ENABLED
1329                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1330                                   | FLAG_HAS_STATS_ICR_ICT
1331                                   | FLAG_HAS_SMART_POWER_DOWN
1332                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1333                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1334                                   | FLAG_APME_CHECK_PORT_B,
1335         .pba                    = 38,
1336         .get_invariants         = e1000_get_invariants_82571,
1337         .mac_ops                = &e82571_mac_ops,
1338         .phy_ops                = &e82_phy_ops_igp,
1339         .nvm_ops                = &e82571_nvm_ops,
1340 };
1341
1342 struct e1000_info e1000_82572_info = {
1343         .mac                    = e1000_82572,
1344         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1345                                   | FLAG_HAS_JUMBO_FRAMES
1346                                   | FLAG_HAS_STATS_PTC_PRC
1347                                   | FLAG_HAS_WOL
1348                                   | FLAG_APME_IN_CTRL3
1349                                   | FLAG_RX_CSUM_ENABLED
1350                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1351                                   | FLAG_HAS_STATS_ICR_ICT
1352                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1353         .pba                    = 38,
1354         .get_invariants         = e1000_get_invariants_82571,
1355         .mac_ops                = &e82571_mac_ops,
1356         .phy_ops                = &e82_phy_ops_igp,
1357         .nvm_ops                = &e82571_nvm_ops,
1358 };
1359
1360 struct e1000_info e1000_82573_info = {
1361         .mac                    = e1000_82573,
1362         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1363                                   | FLAG_HAS_JUMBO_FRAMES
1364                                   | FLAG_HAS_STATS_PTC_PRC
1365                                   | FLAG_HAS_WOL
1366                                   | FLAG_APME_IN_CTRL3
1367                                   | FLAG_RX_CSUM_ENABLED
1368                                   | FLAG_HAS_STATS_ICR_ICT
1369                                   | FLAG_HAS_SMART_POWER_DOWN
1370                                   | FLAG_HAS_AMT
1371                                   | FLAG_HAS_ERT
1372                                   | FLAG_HAS_SWSM_ON_LOAD,
1373         .pba                    = 20,
1374         .get_invariants         = e1000_get_invariants_82571,
1375         .mac_ops                = &e82571_mac_ops,
1376         .phy_ops                = &e82_phy_ops_m88,
1377         .nvm_ops                = &e82571_nvm_ops,
1378 };
1379