2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
3 * Provides Bus interface for MIIM regs
5 * Author: Andy Fleming <afleming@freescale.com>
7 * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
9 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/spinlock.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/crc32.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
37 #include <linux/of_platform.h>
41 #include <asm/uaccess.h>
45 #include "fsl_pq_mdio.h"
48 * Write value to the PHY at mii_id at register regnum,
49 * on the bus attached to the local interface, which may be different from the
50 * generic mdio bus (tied to a single interface), waiting until the write is
51 * done before returning. This is helpful in programming interfaces like
52 * the TBI which control interfaces like onchip SERDES and are always tied to
53 * the local mdio pins, which may not be the same as system mdio bus, used for
54 * controlling the external PHYs, for example.
56 int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
57 int regnum, u16 value)
59 /* Set the PHY address and the register address we want to write */
60 out_be32(®s->miimadd, (mii_id << 8) | regnum);
62 /* Write out the value we want */
63 out_be32(®s->miimcon, value);
65 /* Wait for the transaction to finish */
66 while (in_be32(®s->miimind) & MIIMIND_BUSY)
73 * Read the bus for PHY at addr mii_id, register regnum, and
74 * return the value. Clears miimcom first. All PHY operation
75 * done on the bus attached to the local interface,
76 * which may be different from the generic mdio bus
77 * This is helpful in programming interfaces like
78 * the TBI which, in turn, control interfaces like onchip SERDES
79 * and are always tied to the local mdio pins, which may not be the
80 * same as system mdio bus, used for controlling the external PHYs, for eg.
82 int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
83 int mii_id, int regnum)
87 /* Set the PHY address and the register address we want to read */
88 out_be32(®s->miimadd, (mii_id << 8) | regnum);
90 /* Clear miimcom, and then initiate a read */
91 out_be32(®s->miimcom, 0);
92 out_be32(®s->miimcom, MII_READ_COMMAND);
94 /* Wait for the transaction to finish */
95 while (in_be32(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
98 /* Grab the value of the register from miimstat */
99 value = in_be32(®s->miimstat);
105 * Write value to the PHY at mii_id at register regnum,
106 * on the bus, waiting until the write is done before returning.
108 int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
110 struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
112 /* Write to the local MII regs */
113 return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value));
117 * Read the bus for PHY at addr mii_id, register regnum, and
118 * return the value. Clears miimcom first.
120 int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
122 struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
124 /* Read the local MII regs */
125 return(fsl_pq_local_mdio_read(regs, mii_id, regnum));
128 /* Reset the MIIM registers, and wait for the bus to free */
129 static int fsl_pq_mdio_reset(struct mii_bus *bus)
131 struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv;
132 unsigned int timeout = PHY_INIT_TIMEOUT;
134 mutex_lock(&bus->mdio_lock);
136 /* Reset the management interface */
137 out_be32(®s->miimcfg, MIIMCFG_RESET);
139 /* Setup the MII Mgmt clock speed */
140 out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
142 /* Wait until the bus is free */
143 while ((in_be32(®s->miimind) & MIIMIND_BUSY) && timeout--)
146 mutex_unlock(&bus->mdio_lock);
149 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
157 /* Allocate an array which provides irq #s for each PHY on the given bus */
158 static int *create_irq_map(struct device_node *np)
162 struct device_node *child = NULL;
164 irqs = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
169 for (i = 0; i < PHY_MAX_ADDR; i++)
172 while ((child = of_get_next_child(np, child)) != NULL) {
173 int irq = irq_of_parse_and_map(child, 0);
179 id = of_get_property(child, "reg", NULL);
184 if (*id < PHY_MAX_ADDR && *id >= 0)
187 printk(KERN_WARNING "%s: "
188 "%d is not a valid PHY address\n",
195 void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
199 reg = of_get_property(np, "reg", NULL);
201 snprintf(name, MII_BUS_ID_SIZE, "%s@%x", np->name, reg ? *reg : 0);
204 /* Scan the bus in reverse, looking for an empty spot */
205 static int fsl_pq_mdio_find_free(struct mii_bus *new_bus)
209 for (i = PHY_MAX_ADDR; i > 0; i--) {
212 if (get_phy_id(new_bus, i, &phy_id))
215 if (phy_id == 0xffffffff)
223 #ifdef CONFIG_GIANFAR
224 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs)
226 struct gfar __iomem *enet_regs;
229 * This is mildly evil, but so is our hardware for doing this.
230 * Also, we have to cast back to struct gfar because of
231 * definition weirdness done in gianfar.h.
233 enet_regs = (struct gfar __iomem *)
234 ((char __iomem *)regs - offsetof(struct gfar, gfar_mii_regs));
236 return &enet_regs->tbipa;
241 #ifdef CONFIG_UCC_GETH
242 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
244 struct device_node *np = NULL;
247 for_each_compatible_node(np, NULL, "ucc_geth") {
248 struct resource tempres;
250 err = of_address_to_resource(np, 0, &tempres);
254 /* if our mdio regs fall within this UCC regs range */
255 if ((start >= tempres.start) && (end <= tempres.end)) {
256 /* Find the id of the UCC */
259 id = of_get_property(np, "cell-index", NULL);
261 id = of_get_property(np, "device-id", NULL);
280 static int fsl_pq_mdio_probe(struct of_device *ofdev,
281 const struct of_device_id *match)
283 struct device_node *np = ofdev->node;
284 struct device_node *tbi;
285 struct fsl_pq_mdio __iomem *regs;
287 struct mii_bus *new_bus;
292 new_bus = mdiobus_alloc();
296 new_bus->name = "Freescale PowerQUICC MII Bus",
297 new_bus->read = &fsl_pq_mdio_read,
298 new_bus->write = &fsl_pq_mdio_write,
299 new_bus->reset = &fsl_pq_mdio_reset,
300 fsl_pq_mdio_bus_name(new_bus->id, np);
302 /* Set the PHY base address */
303 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
304 regs = ioremap(addr, size);
311 new_bus->priv = (void __force *)regs;
313 new_bus->irq = create_irq_map(np);
315 if (NULL == new_bus->irq) {
320 new_bus->parent = &ofdev->dev;
321 dev_set_drvdata(&ofdev->dev, new_bus);
323 if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
324 of_device_is_compatible(np, "gianfar")) {
325 #ifdef CONFIG_GIANFAR
326 tbipa = get_gfar_tbipa(regs);
331 } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
332 of_device_is_compatible(np, "ucc_geth_phy")) {
333 #ifdef CONFIG_UCC_GETH
336 tbipa = ®s->utbipar;
338 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
341 ucc_set_qe_mux_mii_mng(id - 1);
351 for_each_child_of_node(np, tbi) {
352 if (!strncmp(tbi->type, "tbi-phy", 8))
357 const u32 *prop = of_get_property(tbi, "reg", NULL);
366 tbiaddr = fsl_pq_mdio_find_free(new_bus);
370 * We define TBIPA at 0 to be illegal, opting to fail for boards that
371 * have PHYs at 1-31, rather than change tbipa and rescan.
379 out_be32(tbipa, tbiaddr);
382 * The TBIPHY-only buses will find PHYs at every address,
383 * so we mask them all but the TBI
385 if (!of_device_is_compatible(np, "fsl,gianfar-mdio"))
386 new_bus->phy_mask = ~(1 << tbiaddr);
388 err = mdiobus_register(new_bus);
391 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
409 static int fsl_pq_mdio_remove(struct of_device *ofdev)
411 struct device *device = &ofdev->dev;
412 struct mii_bus *bus = dev_get_drvdata(device);
414 mdiobus_unregister(bus);
416 dev_set_drvdata(device, NULL);
418 iounmap((void __iomem *)bus->priv);
425 static struct of_device_id fsl_pq_mdio_match[] = {
428 .compatible = "ucc_geth_phy",
432 .compatible = "gianfar",
435 .compatible = "fsl,ucc-mdio",
438 .compatible = "fsl,gianfar-tbi",
441 .compatible = "fsl,gianfar-mdio",
446 static struct of_platform_driver fsl_pq_mdio_driver = {
447 .name = "fsl-pq_mdio",
448 .probe = fsl_pq_mdio_probe,
449 .remove = fsl_pq_mdio_remove,
450 .match_table = fsl_pq_mdio_match,
453 int __init fsl_pq_mdio_init(void)
455 return of_register_platform_driver(&fsl_pq_mdio_driver);
458 void fsl_pq_mdio_exit(void)
460 of_unregister_platform_driver(&fsl_pq_mdio_driver);
462 subsys_initcall_sync(fsl_pq_mdio_init);
463 module_exit(fsl_pq_mdio_exit);