2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
4 National Semiconductor SCx200 ACCESS.bus support
5 Also supports the AMD CS5535 and AMD CS5536
7 Based on i2c-keywest.c which is:
8 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
11 This program is free software; you can redistribute it and/or
12 modify it under the terms of the GNU General Public License as
13 published by the Free Software Foundation; either version 2 of the
14 License, or (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/i2c.h>
31 #include <linux/smp_lock.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/mutex.h>
37 #include <linux/scx200.h>
39 #define NAME "scx200_acb"
41 MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
42 MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
43 MODULE_LICENSE("GPL");
46 static int base[MAX_DEVICES] = { 0x820, 0x840 };
47 module_param_array(base, int, NULL, 0);
48 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
50 #define POLL_TIMEOUT (HZ/5)
52 enum scx200_acb_state {
62 static const char *scx200_acb_state_name[] = {
72 /* Physical interface */
73 struct scx200_acb_iface {
74 struct scx200_acb_iface *next;
75 struct i2c_adapter adapter;
79 /* State machine data */
80 enum scx200_acb_state state;
93 /* Register Definitions */
94 #define ACBSDA (iface->base + 0)
95 #define ACBST (iface->base + 1)
96 #define ACBST_SDAST 0x40 /* SDA Status */
97 #define ACBST_BER 0x20
98 #define ACBST_NEGACK 0x10 /* Negative Acknowledge */
99 #define ACBST_STASTR 0x08 /* Stall After Start */
100 #define ACBST_MASTER 0x02
101 #define ACBCST (iface->base + 2)
102 #define ACBCST_BB 0x02
103 #define ACBCTL1 (iface->base + 3)
104 #define ACBCTL1_STASTRE 0x80
105 #define ACBCTL1_NMINTE 0x40
106 #define ACBCTL1_ACK 0x10
107 #define ACBCTL1_STOP 0x02
108 #define ACBCTL1_START 0x01
109 #define ACBADDR (iface->base + 4)
110 #define ACBCTL2 (iface->base + 5)
111 #define ACBCTL2_ENABLE 0x01
113 /************************************************************************/
115 static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
119 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
120 scx200_acb_state_name[iface->state], status);
122 if (status & ACBST_BER) {
123 errmsg = "bus error";
126 if (!(status & ACBST_MASTER)) {
127 errmsg = "not master";
130 if (status & ACBST_NEGACK) {
131 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
132 scx200_acb_state_name[iface->state]);
134 iface->state = state_idle;
135 iface->result = -ENXIO;
137 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
138 outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
140 /* Reset the status register */
145 switch (iface->state) {
147 dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
151 /* Do a pointer write first */
152 outb(iface->address_byte & ~1, ACBSDA);
154 iface->state = state_command;
158 outb(iface->command, ACBSDA);
160 if (iface->address_byte & 1)
161 iface->state = state_repeat_start;
163 iface->state = state_write;
166 case state_repeat_start:
167 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
171 if (iface->address_byte & 1) {
173 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
175 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
176 outb(iface->address_byte, ACBSDA);
178 iface->state = state_read;
180 outb(iface->address_byte, ACBSDA);
182 iface->state = state_write;
187 /* Set ACK if _next_ byte will be the last one */
189 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
191 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
193 if (iface->len == 1) {
195 iface->state = state_idle;
196 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
199 *iface->ptr++ = inb(ACBSDA);
205 if (iface->len == 0) {
207 iface->state = state_idle;
208 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
212 outb(*iface->ptr++, ACBSDA);
221 dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
222 scx200_acb_state_name[iface->state]);
224 iface->state = state_idle;
225 iface->result = -EIO;
226 iface->needs_reset = 1;
229 static void scx200_acb_poll(struct scx200_acb_iface *iface)
232 unsigned long timeout;
234 timeout = jiffies + POLL_TIMEOUT;
238 /* Reset the status register to avoid the hang */
241 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
242 scx200_acb_machine(iface, status);
245 if (time_after(jiffies, timeout))
251 dev_err(&iface->adapter.dev, "timeout in state %s\n",
252 scx200_acb_state_name[iface->state]);
254 iface->state = state_idle;
255 iface->result = -EIO;
256 iface->needs_reset = 1;
259 static void scx200_acb_reset(struct scx200_acb_iface *iface)
261 /* Disable the ACCESS.bus device and Configure the SCL
262 frequency: 16 clock cycles */
266 /* Disable slave address */
268 /* Enable the ACCESS.bus device */
269 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
270 /* Free STALL after START */
271 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
273 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
274 /* Clear BER, NEGACK and STASTR bits */
275 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
277 outb(inb(ACBCST) | ACBCST_BB, ACBCST);
280 static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
281 u16 address, unsigned short flags,
282 char rw, u8 command, int size,
283 union i2c_smbus_data *data)
285 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
292 case I2C_SMBUS_QUICK:
299 buffer = rw ? &data->byte : &command;
302 case I2C_SMBUS_BYTE_DATA:
304 buffer = &data->byte;
307 case I2C_SMBUS_WORD_DATA:
309 cur_word = cpu_to_le16(data->word);
310 buffer = (u8 *)&cur_word;
313 case I2C_SMBUS_I2C_BLOCK_DATA:
314 if (rw == I2C_SMBUS_READ)
315 data->block[0] = I2C_SMBUS_BLOCK_MAX; /* For now */
316 len = data->block[0];
317 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
319 buffer = &data->block[1];
326 dev_dbg(&adapter->dev,
327 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
328 size, address, command, len, rw);
330 if (!len && rw == I2C_SMBUS_READ) {
331 dev_dbg(&adapter->dev, "zero length read\n");
335 mutex_lock(&iface->mutex);
337 iface->address_byte = (address << 1) | rw;
338 iface->command = command;
341 iface->result = -EINVAL;
342 iface->needs_reset = 0;
344 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
346 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
347 iface->state = state_quick;
349 iface->state = state_address;
351 while (iface->state != state_idle)
352 scx200_acb_poll(iface);
354 if (iface->needs_reset)
355 scx200_acb_reset(iface);
359 mutex_unlock(&iface->mutex);
361 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
362 data->word = le16_to_cpu(cur_word);
365 dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
369 for (i = 0; i < len; ++i)
370 printk(" %02x", buffer[i]);
378 static u32 scx200_acb_func(struct i2c_adapter *adapter)
380 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
381 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
382 I2C_FUNC_SMBUS_I2C_BLOCK;
385 /* For now, we only handle combined mode (smbus) */
386 static const struct i2c_algorithm scx200_acb_algorithm = {
387 .smbus_xfer = scx200_acb_smbus_xfer,
388 .functionality = scx200_acb_func,
391 static struct scx200_acb_iface *scx200_acb_list;
392 static DECLARE_MUTEX(scx200_acb_list_mutex);
394 static __init int scx200_acb_probe(struct scx200_acb_iface *iface)
398 /* Disable the ACCESS.bus device and Configure the SCL
399 frequency: 16 clock cycles */
402 if (inb(ACBCTL2) != 0x70) {
403 pr_debug(NAME ": ACBCTL2 readback failed\n");
407 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
411 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
416 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
418 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
421 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
422 pr_debug(NAME ": enabled, but NMINTE won't be set, "
423 "ACBCTL1=0x%02x\n", val);
430 static __init struct scx200_acb_iface *scx200_create_iface(const char *text,
433 struct scx200_acb_iface *iface;
434 struct i2c_adapter *adapter;
436 iface = kzalloc(sizeof(*iface), GFP_KERNEL);
438 printk(KERN_ERR NAME ": can't allocate memory\n");
442 adapter = &iface->adapter;
443 i2c_set_adapdata(adapter, iface);
444 snprintf(adapter->name, I2C_NAME_SIZE, "%s ACB%d", text, index);
445 adapter->owner = THIS_MODULE;
446 adapter->id = I2C_HW_SMBUS_SCX200;
447 adapter->algo = &scx200_acb_algorithm;
448 adapter->class = I2C_CLASS_HWMON;
450 mutex_init(&iface->mutex);
455 static int __init scx200_acb_create(struct scx200_acb_iface *iface)
457 struct i2c_adapter *adapter;
460 adapter = &iface->adapter;
462 rc = scx200_acb_probe(iface);
464 printk(KERN_WARNING NAME ": probe failed\n");
468 scx200_acb_reset(iface);
470 if (i2c_add_adapter(adapter) < 0) {
471 printk(KERN_ERR NAME ": failed to register\n");
475 down(&scx200_acb_list_mutex);
476 iface->next = scx200_acb_list;
477 scx200_acb_list = iface;
478 up(&scx200_acb_list_mutex);
483 static __init int scx200_create_pci(const char *text, struct pci_dev *pdev,
486 struct scx200_acb_iface *iface;
489 iface = scx200_create_iface(text, 0);
497 rc = pci_enable_device_bars(iface->pdev, 1 << iface->bar);
501 rc = pci_request_region(iface->pdev, iface->bar, iface->adapter.name);
503 printk(KERN_ERR NAME ": can't allocate PCI BAR %d\n",
508 iface->base = pci_resource_start(iface->pdev, iface->bar);
509 rc = scx200_acb_create(iface);
514 pci_release_region(iface->pdev, iface->bar);
515 pci_dev_put(iface->pdev);
521 static int __init scx200_create_isa(const char *text, unsigned long base,
524 struct scx200_acb_iface *iface;
527 iface = scx200_create_iface(text, index);
532 if (request_region(base, 8, iface->adapter.name) == 0) {
533 printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n",
540 rc = scx200_acb_create(iface);
545 release_region(base, 8);
551 /* Driver data is an index into the scx200_data array that indicates
552 * the name and the BAR where the I/O address resource is located. ISA
553 * devices are flagged with a bar value of -1 */
555 static struct pci_device_id scx200_pci[] = {
556 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE),
558 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE),
560 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA),
562 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA),
575 static __init int scx200_scan_pci(void)
579 struct pci_dev *pdev;
581 for(dev = 0; dev < ARRAY_SIZE(scx200_pci); dev++) {
582 pdev = pci_get_device(scx200_pci[dev].vendor,
583 scx200_pci[dev].device, NULL);
588 data = scx200_pci[dev].driver_data;
590 /* if .bar is greater or equal to zero, this is a
591 * PCI device - otherwise, we assume
592 that the ports are ISA based
595 if (scx200_data[data].bar >= 0)
596 rc = scx200_create_pci(scx200_data[data].name, pdev,
597 scx200_data[data].bar);
601 for (i = 0; i < MAX_DEVICES; ++i) {
605 rc = scx200_create_isa(scx200_data[data].name,
617 static int __init scx200_acb_init(void)
621 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
623 rc = scx200_scan_pci();
625 /* If at least one bus was created, init must succeed */
631 static void __exit scx200_acb_cleanup(void)
633 struct scx200_acb_iface *iface;
635 down(&scx200_acb_list_mutex);
636 while ((iface = scx200_acb_list) != NULL) {
637 scx200_acb_list = iface->next;
638 up(&scx200_acb_list_mutex);
640 i2c_del_adapter(&iface->adapter);
643 pci_release_region(iface->pdev, iface->bar);
644 pci_dev_put(iface->pdev);
647 release_region(iface->base, 8);
650 down(&scx200_acb_list_mutex);
652 up(&scx200_acb_list_mutex);
655 module_init(scx200_acb_init);
656 module_exit(scx200_acb_cleanup);