1 /*******************************************************************
3 * Copyright (c) 2000 ATecoM GmbH
5 * The author may be reached at ecd@atecom.com.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *******************************************************************/
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/poison.h>
32 #include <linux/skbuff.h>
33 #include <linux/kernel.h>
34 #include <linux/vmalloc.h>
35 #include <linux/netdevice.h>
36 #include <linux/atmdev.h>
37 #include <linux/atm.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/bitops.h>
41 #include <linux/wait.h>
42 #include <linux/jiffies.h>
43 #include <linux/mutex.h>
46 #include <asm/uaccess.h>
47 #include <asm/atomic.h>
48 #include <asm/byteorder.h>
50 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
52 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
56 #include "idt77252_tables.h"
58 static unsigned int vpibits = 1;
61 #define ATM_IDT77252_SEND_IDLE 1
67 #define DEBUG_MODULE 1
68 #undef HAVE_EEPROM /* does not work, yet. */
70 #ifdef CONFIG_ATM_IDT77252_DEBUG
71 static unsigned long debug = DBG_GENERAL;
75 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
81 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
82 static void free_scq(struct idt77252_dev *, struct scq_info *);
83 static int queue_skb(struct idt77252_dev *, struct vc_map *,
84 struct sk_buff *, int oam);
85 static void drain_scq(struct idt77252_dev *, struct vc_map *);
86 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
87 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
92 static int push_rx_skb(struct idt77252_dev *,
93 struct sk_buff *, int queue);
94 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
95 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
96 static void recycle_rx_pool_skb(struct idt77252_dev *,
98 static void add_rx_skb(struct idt77252_dev *, int queue,
99 unsigned int size, unsigned int count);
104 static int init_rsq(struct idt77252_dev *);
105 static void deinit_rsq(struct idt77252_dev *);
106 static void idt77252_rx(struct idt77252_dev *);
111 static int init_tsq(struct idt77252_dev *);
112 static void deinit_tsq(struct idt77252_dev *);
113 static void idt77252_tx(struct idt77252_dev *);
119 static void idt77252_dev_close(struct atm_dev *dev);
120 static int idt77252_open(struct atm_vcc *vcc);
121 static void idt77252_close(struct atm_vcc *vcc);
122 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
123 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
125 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
127 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
128 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
130 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
132 static void idt77252_softint(struct work_struct *work);
135 static struct atmdev_ops idt77252_ops =
137 .dev_close = idt77252_dev_close,
138 .open = idt77252_open,
139 .close = idt77252_close,
140 .send = idt77252_send,
141 .send_oam = idt77252_send_oam,
142 .phy_put = idt77252_phy_put,
143 .phy_get = idt77252_phy_get,
144 .change_qos = idt77252_change_qos,
145 .proc_read = idt77252_proc_read,
149 static struct idt77252_dev *idt77252_chain = NULL;
150 static unsigned int idt77252_sram_write_errors = 0;
152 /*****************************************************************************/
154 /* I/O and Utility Bus */
156 /*****************************************************************************/
159 waitfor_idle(struct idt77252_dev *card)
163 stat = readl(SAR_REG_STAT);
164 while (stat & SAR_STAT_CMDBZ)
165 stat = readl(SAR_REG_STAT);
169 read_sram(struct idt77252_dev *card, unsigned long addr)
174 spin_lock_irqsave(&card->cmd_lock, flags);
175 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
177 value = readl(SAR_REG_DR0);
178 spin_unlock_irqrestore(&card->cmd_lock, flags);
183 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
187 if ((idt77252_sram_write_errors == 0) &&
188 (((addr > card->tst[0] + card->tst_size - 2) &&
189 (addr < card->tst[0] + card->tst_size)) ||
190 ((addr > card->tst[1] + card->tst_size - 2) &&
191 (addr < card->tst[1] + card->tst_size)))) {
192 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
193 card->name, addr, value);
196 spin_lock_irqsave(&card->cmd_lock, flags);
197 writel(value, SAR_REG_DR0);
198 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
200 spin_unlock_irqrestore(&card->cmd_lock, flags);
204 read_utility(void *dev, unsigned long ubus_addr)
206 struct idt77252_dev *card = dev;
211 printk("Error: No such device.\n");
215 spin_lock_irqsave(&card->cmd_lock, flags);
216 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
218 value = readl(SAR_REG_DR0);
219 spin_unlock_irqrestore(&card->cmd_lock, flags);
224 write_utility(void *dev, unsigned long ubus_addr, u8 value)
226 struct idt77252_dev *card = dev;
230 printk("Error: No such device.\n");
234 spin_lock_irqsave(&card->cmd_lock, flags);
235 writel((u32) value, SAR_REG_DR0);
236 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
238 spin_unlock_irqrestore(&card->cmd_lock, flags);
242 static u32 rdsrtab[] =
244 SAR_GP_EECS | SAR_GP_EESCLK,
246 SAR_GP_EESCLK, /* 0 */
248 SAR_GP_EESCLK, /* 0 */
250 SAR_GP_EESCLK, /* 0 */
252 SAR_GP_EESCLK, /* 0 */
254 SAR_GP_EESCLK, /* 0 */
256 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
258 SAR_GP_EESCLK, /* 0 */
260 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
263 static u32 wrentab[] =
265 SAR_GP_EECS | SAR_GP_EESCLK,
267 SAR_GP_EESCLK, /* 0 */
269 SAR_GP_EESCLK, /* 0 */
271 SAR_GP_EESCLK, /* 0 */
273 SAR_GP_EESCLK, /* 0 */
275 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
277 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
279 SAR_GP_EESCLK, /* 0 */
281 SAR_GP_EESCLK /* 0 */
286 SAR_GP_EECS | SAR_GP_EESCLK,
288 SAR_GP_EESCLK, /* 0 */
290 SAR_GP_EESCLK, /* 0 */
292 SAR_GP_EESCLK, /* 0 */
294 SAR_GP_EESCLK, /* 0 */
296 SAR_GP_EESCLK, /* 0 */
298 SAR_GP_EESCLK, /* 0 */
300 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
302 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
307 SAR_GP_EECS | SAR_GP_EESCLK,
309 SAR_GP_EESCLK, /* 0 */
311 SAR_GP_EESCLK, /* 0 */
313 SAR_GP_EESCLK, /* 0 */
315 SAR_GP_EESCLK, /* 0 */
317 SAR_GP_EESCLK, /* 0 */
319 SAR_GP_EESCLK, /* 0 */
321 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
323 SAR_GP_EESCLK /* 0 */
326 static u32 clktab[] =
348 idt77252_read_gp(struct idt77252_dev *card)
352 gp = readl(SAR_REG_GP);
354 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
360 idt77252_write_gp(struct idt77252_dev *card, u32 value)
365 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
366 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
367 value & SAR_GP_EEDO ? "1" : "0");
370 spin_lock_irqsave(&card->cmd_lock, flags);
372 writel(value, SAR_REG_GP);
373 spin_unlock_irqrestore(&card->cmd_lock, flags);
377 idt77252_eeprom_read_status(struct idt77252_dev *card)
383 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
385 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
386 idt77252_write_gp(card, gp | rdsrtab[i]);
389 idt77252_write_gp(card, gp | SAR_GP_EECS);
393 for (i = 0, j = 0; i < 8; i++) {
396 idt77252_write_gp(card, gp | clktab[j++]);
399 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
401 idt77252_write_gp(card, gp | clktab[j++]);
404 idt77252_write_gp(card, gp | SAR_GP_EECS);
411 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
417 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
419 for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
420 idt77252_write_gp(card, gp | rdtab[i]);
423 idt77252_write_gp(card, gp | SAR_GP_EECS);
426 for (i = 0, j = 0; i < 8; i++) {
427 idt77252_write_gp(card, gp | clktab[j++] |
428 (offset & 1 ? SAR_GP_EEDO : 0));
431 idt77252_write_gp(card, gp | clktab[j++] |
432 (offset & 1 ? SAR_GP_EEDO : 0));
437 idt77252_write_gp(card, gp | SAR_GP_EECS);
441 for (i = 0, j = 0; i < 8; i++) {
444 idt77252_write_gp(card, gp | clktab[j++]);
447 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
449 idt77252_write_gp(card, gp | clktab[j++]);
452 idt77252_write_gp(card, gp | SAR_GP_EECS);
459 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
464 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
466 for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
467 idt77252_write_gp(card, gp | wrentab[i]);
470 idt77252_write_gp(card, gp | SAR_GP_EECS);
473 for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
474 idt77252_write_gp(card, gp | wrtab[i]);
477 idt77252_write_gp(card, gp | SAR_GP_EECS);
480 for (i = 0, j = 0; i < 8; i++) {
481 idt77252_write_gp(card, gp | clktab[j++] |
482 (offset & 1 ? SAR_GP_EEDO : 0));
485 idt77252_write_gp(card, gp | clktab[j++] |
486 (offset & 1 ? SAR_GP_EEDO : 0));
491 idt77252_write_gp(card, gp | SAR_GP_EECS);
494 for (i = 0, j = 0; i < 8; i++) {
495 idt77252_write_gp(card, gp | clktab[j++] |
496 (data & 1 ? SAR_GP_EEDO : 0));
499 idt77252_write_gp(card, gp | clktab[j++] |
500 (data & 1 ? SAR_GP_EEDO : 0));
505 idt77252_write_gp(card, gp | SAR_GP_EECS);
510 idt77252_eeprom_init(struct idt77252_dev *card)
514 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
516 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
518 idt77252_write_gp(card, gp | SAR_GP_EECS);
520 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
522 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 #endif /* HAVE_EEPROM */
528 #ifdef CONFIG_ATM_IDT77252_DEBUG
530 dump_tct(struct idt77252_dev *card, int index)
535 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
537 printk("%s: TCT %x:", card->name, index);
538 for (i = 0; i < 8; i++) {
539 printk(" %08x", read_sram(card, tct + i));
545 idt77252_tx_dump(struct idt77252_dev *card)
551 printk("%s\n", __func__);
552 for (i = 0; i < card->tct_size; i++) {
566 printk("%s: Connection %d:\n", card->name, vc->index);
567 dump_tct(card, vc->index);
573 /*****************************************************************************/
577 /*****************************************************************************/
580 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
582 struct sb_pool *pool = &card->sbpool[queue];
586 while (pool->skb[index]) {
587 index = (index + 1) & FBQ_MASK;
588 if (index == pool->index)
592 pool->skb[index] = skb;
593 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
595 pool->index = (index + 1) & FBQ_MASK;
600 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
602 unsigned int queue, index;
605 handle = IDT77252_PRV_POOL(skb);
607 queue = POOL_QUEUE(handle);
611 index = POOL_INDEX(handle);
612 if (index > FBQ_SIZE - 1)
615 card->sbpool[queue].skb[index] = NULL;
618 static struct sk_buff *
619 sb_pool_skb(struct idt77252_dev *card, u32 handle)
621 unsigned int queue, index;
623 queue = POOL_QUEUE(handle);
627 index = POOL_INDEX(handle);
628 if (index > FBQ_SIZE - 1)
631 return card->sbpool[queue].skb[index];
634 static struct scq_info *
635 alloc_scq(struct idt77252_dev *card, int class)
637 struct scq_info *scq;
639 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
642 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
644 if (scq->base == NULL) {
648 memset(scq->base, 0, SCQ_SIZE);
650 scq->next = scq->base;
651 scq->last = scq->base + (SCQ_ENTRIES - 1);
652 atomic_set(&scq->used, 0);
654 spin_lock_init(&scq->lock);
655 spin_lock_init(&scq->skblock);
657 skb_queue_head_init(&scq->transmit);
658 skb_queue_head_init(&scq->pending);
660 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
661 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
667 free_scq(struct idt77252_dev *card, struct scq_info *scq)
672 pci_free_consistent(card->pcidev, SCQ_SIZE,
673 scq->base, scq->paddr);
675 while ((skb = skb_dequeue(&scq->transmit))) {
676 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
677 skb->len, PCI_DMA_TODEVICE);
679 vcc = ATM_SKB(skb)->vcc;
686 while ((skb = skb_dequeue(&scq->pending))) {
687 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
688 skb->len, PCI_DMA_TODEVICE);
690 vcc = ATM_SKB(skb)->vcc;
702 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
704 struct scq_info *scq = vc->scq;
709 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
711 atomic_inc(&scq->used);
712 entries = atomic_read(&scq->used);
713 if (entries > (SCQ_ENTRIES - 1)) {
714 atomic_dec(&scq->used);
718 skb_queue_tail(&scq->transmit, skb);
720 spin_lock_irqsave(&vc->lock, flags);
722 struct atm_vcc *vcc = vc->tx_vcc;
723 struct sock *sk = sk_atm(vcc);
725 vc->estimator->cells += (skb->len + 47) / 48;
726 if (atomic_read(&sk->sk_wmem_alloc) >
727 (sk->sk_sndbuf >> 1)) {
728 u32 cps = vc->estimator->maxcps;
730 vc->estimator->cps = cps;
731 vc->estimator->avcps = cps << 5;
732 if (vc->lacr < vc->init_er) {
733 vc->lacr = vc->init_er;
734 writel(TCMDQ_LACR | (vc->lacr << 16) |
735 vc->index, SAR_REG_TCMDQ);
739 spin_unlock_irqrestore(&vc->lock, flags);
741 tbd = &IDT77252_PRV_TBD(skb);
743 spin_lock_irqsave(&scq->lock, flags);
744 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
745 SAR_TBD_TSIF | SAR_TBD_GTSI);
746 scq->next->word_2 = cpu_to_le32(tbd->word_2);
747 scq->next->word_3 = cpu_to_le32(tbd->word_3);
748 scq->next->word_4 = cpu_to_le32(tbd->word_4);
750 if (scq->next == scq->last)
751 scq->next = scq->base;
755 write_sram(card, scq->scd,
757 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
758 spin_unlock_irqrestore(&scq->lock, flags);
760 scq->trans_start = jiffies;
762 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
763 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
767 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
769 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
770 card->name, atomic_read(&scq->used),
771 read_sram(card, scq->scd + 1), scq->next);
776 if (time_after(jiffies, scq->trans_start + HZ)) {
777 printk("%s: Error pushing TBD for %d.%d\n",
778 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
779 #ifdef CONFIG_ATM_IDT77252_DEBUG
780 idt77252_tx_dump(card);
782 scq->trans_start = jiffies;
790 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
792 struct scq_info *scq = vc->scq;
796 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
797 card->name, atomic_read(&scq->used), scq->next);
799 skb = skb_dequeue(&scq->transmit);
801 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
803 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
804 skb->len, PCI_DMA_TODEVICE);
806 vcc = ATM_SKB(skb)->vcc;
813 atomic_inc(&vcc->stats->tx);
816 atomic_dec(&scq->used);
818 spin_lock(&scq->skblock);
819 while ((skb = skb_dequeue(&scq->pending))) {
820 if (push_on_scq(card, vc, skb)) {
821 skb_queue_head(&vc->scq->pending, skb);
825 spin_unlock(&scq->skblock);
829 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
830 struct sk_buff *skb, int oam)
839 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
843 TXPRINTK("%s: Sending %d bytes of data.\n",
844 card->name, skb->len);
846 tbd = &IDT77252_PRV_TBD(skb);
847 vcc = ATM_SKB(skb)->vcc;
849 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
850 skb->len, PCI_DMA_TODEVICE);
858 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
859 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
860 tbd->word_3 = 0x00000000;
861 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
862 (skb->data[2] << 8) | (skb->data[3] << 0);
864 if (test_bit(VCF_RSV, &vc->flags))
870 if (test_bit(VCF_RSV, &vc->flags)) {
871 printk("%s: Trying to transmit on reserved VC\n", card->name);
884 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
887 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
890 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
891 tbd->word_3 = 0x00000000;
892 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
893 (skb->data[2] << 8) | (skb->data[3] << 0);
897 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
898 tbd->word_2 = IDT77252_PRV_PADDR(skb);
899 tbd->word_3 = skb->len;
900 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
901 (vcc->vci << SAR_TBD_VCI_SHIFT);
907 printk("%s: Traffic type not supported.\n", card->name);
908 error = -EPROTONOSUPPORT;
913 spin_lock_irqsave(&vc->scq->skblock, flags);
914 skb_queue_tail(&vc->scq->pending, skb);
916 while ((skb = skb_dequeue(&vc->scq->pending))) {
917 if (push_on_scq(card, vc, skb)) {
918 skb_queue_head(&vc->scq->pending, skb);
922 spin_unlock_irqrestore(&vc->scq->skblock, flags);
927 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
928 skb->len, PCI_DMA_TODEVICE);
933 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
937 for (i = 0; i < card->scd_size; i++) {
938 if (!card->scd2vc[i]) {
939 card->scd2vc[i] = vc;
941 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
948 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
950 write_sram(card, scq->scd, scq->paddr);
951 write_sram(card, scq->scd + 1, 0x00000000);
952 write_sram(card, scq->scd + 2, 0xffffffff);
953 write_sram(card, scq->scd + 3, 0x00000000);
957 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
962 /*****************************************************************************/
966 /*****************************************************************************/
969 init_rsq(struct idt77252_dev *card)
971 struct rsq_entry *rsqe;
973 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
975 if (card->rsq.base == NULL) {
976 printk("%s: can't allocate RSQ.\n", card->name);
979 memset(card->rsq.base, 0, RSQSIZE);
981 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
982 card->rsq.next = card->rsq.last;
983 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
986 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
988 writel(card->rsq.paddr, SAR_REG_RSQB);
990 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
991 (unsigned long) card->rsq.base,
992 readl(SAR_REG_RSQB));
993 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
997 readl(SAR_REG_RSQT));
1003 deinit_rsq(struct idt77252_dev *card)
1005 pci_free_consistent(card->pcidev, RSQSIZE,
1006 card->rsq.base, card->rsq.paddr);
1010 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1012 struct atm_vcc *vcc;
1013 struct sk_buff *skb;
1014 struct rx_pool *rpp;
1016 u32 header, vpi, vci;
1020 stat = le32_to_cpu(rsqe->word_4);
1022 if (stat & SAR_RSQE_IDLE) {
1023 RXPRINTK("%s: message about inactive connection.\n",
1028 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1030 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1031 card->name, __func__,
1032 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1033 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1037 header = le32_to_cpu(rsqe->word_1);
1038 vpi = (header >> 16) & 0x00ff;
1039 vci = (header >> 0) & 0xffff;
1041 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1042 card->name, vpi, vci, skb, skb->data);
1044 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1045 printk("%s: SDU received for out-of-range vc %u.%u\n",
1046 card->name, vpi, vci);
1047 recycle_rx_skb(card, skb);
1051 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1052 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1053 printk("%s: SDU received on non RX vc %u.%u\n",
1054 card->name, vpi, vci);
1055 recycle_rx_skb(card, skb);
1061 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1062 skb_end_pointer(skb) - skb->data,
1063 PCI_DMA_FROMDEVICE);
1065 if ((vcc->qos.aal == ATM_AAL0) ||
1066 (vcc->qos.aal == ATM_AAL34)) {
1068 unsigned char *cell;
1072 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1073 if ((sb = dev_alloc_skb(64)) == NULL) {
1074 printk("%s: Can't allocate buffers for aal0.\n",
1076 atomic_add(i, &vcc->stats->rx_drop);
1079 if (!atm_charge(vcc, sb->truesize)) {
1080 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1082 atomic_add(i - 1, &vcc->stats->rx_drop);
1086 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1087 (vci << ATM_HDR_VCI_SHIFT);
1088 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1089 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1091 *((u32 *) sb->data) = aal0;
1092 skb_put(sb, sizeof(u32));
1093 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1094 cell, ATM_CELL_PAYLOAD);
1096 ATM_SKB(sb)->vcc = vcc;
1097 __net_timestamp(sb);
1099 atomic_inc(&vcc->stats->rx);
1101 cell += ATM_CELL_PAYLOAD;
1104 recycle_rx_skb(card, skb);
1107 if (vcc->qos.aal != ATM_AAL5) {
1108 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1109 card->name, vcc->qos.aal);
1110 recycle_rx_skb(card, skb);
1113 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1115 rpp = &vc->rcv.rx_pool;
1117 rpp->len += skb->len;
1121 rpp->last = &skb->next;
1123 if (stat & SAR_RSQE_EPDU) {
1124 unsigned char *l1l2;
1127 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1129 len = (l1l2[0] << 8) | l1l2[1];
1130 len = len ? len : 0x10000;
1132 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1134 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1135 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1137 card->name, len, rpp->len, readl(SAR_REG_CDC));
1138 recycle_rx_pool_skb(card, rpp);
1139 atomic_inc(&vcc->stats->rx_err);
1142 if (stat & SAR_RSQE_CRC) {
1143 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1144 recycle_rx_pool_skb(card, rpp);
1145 atomic_inc(&vcc->stats->rx_err);
1148 if (rpp->count > 1) {
1151 skb = dev_alloc_skb(rpp->len);
1153 RXPRINTK("%s: Can't alloc RX skb.\n",
1155 recycle_rx_pool_skb(card, rpp);
1156 atomic_inc(&vcc->stats->rx_err);
1159 if (!atm_charge(vcc, skb->truesize)) {
1160 recycle_rx_pool_skb(card, rpp);
1165 for (i = 0; i < rpp->count; i++) {
1166 memcpy(skb_put(skb, sb->len),
1171 recycle_rx_pool_skb(card, rpp);
1174 ATM_SKB(skb)->vcc = vcc;
1175 __net_timestamp(skb);
1177 vcc->push(vcc, skb);
1178 atomic_inc(&vcc->stats->rx);
1184 flush_rx_pool(card, rpp);
1186 if (!atm_charge(vcc, skb->truesize)) {
1187 recycle_rx_skb(card, skb);
1191 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1192 skb_end_pointer(skb) - skb->data,
1193 PCI_DMA_FROMDEVICE);
1194 sb_pool_remove(card, skb);
1197 ATM_SKB(skb)->vcc = vcc;
1198 __net_timestamp(skb);
1200 vcc->push(vcc, skb);
1201 atomic_inc(&vcc->stats->rx);
1203 if (skb->truesize > SAR_FB_SIZE_3)
1204 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1205 else if (skb->truesize > SAR_FB_SIZE_2)
1206 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1207 else if (skb->truesize > SAR_FB_SIZE_1)
1208 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1210 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1216 idt77252_rx(struct idt77252_dev *card)
1218 struct rsq_entry *rsqe;
1220 if (card->rsq.next == card->rsq.last)
1221 rsqe = card->rsq.base;
1223 rsqe = card->rsq.next + 1;
1225 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1226 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1231 dequeue_rx(card, rsqe);
1233 card->rsq.next = rsqe;
1234 if (card->rsq.next == card->rsq.last)
1235 rsqe = card->rsq.base;
1237 rsqe = card->rsq.next + 1;
1238 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1240 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1245 idt77252_rx_raw(struct idt77252_dev *card)
1247 struct sk_buff *queue;
1249 struct atm_vcc *vcc;
1253 if (card->raw_cell_head == NULL) {
1254 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1255 card->raw_cell_head = sb_pool_skb(card, handle);
1258 queue = card->raw_cell_head;
1262 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1263 tail = readl(SAR_REG_RAWCT);
1265 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1266 skb_end_pointer(queue) - queue->head - 16,
1267 PCI_DMA_FROMDEVICE);
1269 while (head != tail) {
1270 unsigned int vpi, vci, pti;
1273 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1275 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1276 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1277 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1279 #ifdef CONFIG_ATM_IDT77252_DEBUG
1280 if (debug & DBG_RAW_CELL) {
1283 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1284 card->name, (header >> 28) & 0x000f,
1285 (header >> 20) & 0x00ff,
1286 (header >> 4) & 0xffff,
1287 (header >> 1) & 0x0007,
1288 (header >> 0) & 0x0001);
1289 for (i = 16; i < 64; i++)
1290 printk(" %02x", queue->data[i]);
1295 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1296 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1297 card->name, vpi, vci);
1301 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1302 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1303 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1304 card->name, vpi, vci);
1310 if (vcc->qos.aal != ATM_AAL0) {
1311 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1312 card->name, vpi, vci);
1313 atomic_inc(&vcc->stats->rx_drop);
1317 if ((sb = dev_alloc_skb(64)) == NULL) {
1318 printk("%s: Can't allocate buffers for AAL0.\n",
1320 atomic_inc(&vcc->stats->rx_err);
1324 if (!atm_charge(vcc, sb->truesize)) {
1325 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1331 *((u32 *) sb->data) = header;
1332 skb_put(sb, sizeof(u32));
1333 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1336 ATM_SKB(sb)->vcc = vcc;
1337 __net_timestamp(sb);
1339 atomic_inc(&vcc->stats->rx);
1342 skb_pull(queue, 64);
1344 head = IDT77252_PRV_PADDR(queue)
1345 + (queue->data - queue->head - 16);
1347 if (queue->len < 128) {
1348 struct sk_buff *next;
1351 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1352 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1354 next = sb_pool_skb(card, handle);
1355 recycle_rx_skb(card, queue);
1358 card->raw_cell_head = next;
1359 queue = card->raw_cell_head;
1360 pci_dma_sync_single_for_cpu(card->pcidev,
1361 IDT77252_PRV_PADDR(queue),
1362 (skb_end_pointer(queue) -
1364 PCI_DMA_FROMDEVICE);
1366 card->raw_cell_head = NULL;
1367 printk("%s: raw cell queue overrun\n",
1376 /*****************************************************************************/
1380 /*****************************************************************************/
1383 init_tsq(struct idt77252_dev *card)
1385 struct tsq_entry *tsqe;
1387 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1389 if (card->tsq.base == NULL) {
1390 printk("%s: can't allocate TSQ.\n", card->name);
1393 memset(card->tsq.base, 0, TSQSIZE);
1395 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1396 card->tsq.next = card->tsq.last;
1397 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1398 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1400 writel(card->tsq.paddr, SAR_REG_TSQB);
1401 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1408 deinit_tsq(struct idt77252_dev *card)
1410 pci_free_consistent(card->pcidev, TSQSIZE,
1411 card->tsq.base, card->tsq.paddr);
1415 idt77252_tx(struct idt77252_dev *card)
1417 struct tsq_entry *tsqe;
1418 unsigned int vpi, vci;
1422 if (card->tsq.next == card->tsq.last)
1423 tsqe = card->tsq.base;
1425 tsqe = card->tsq.next + 1;
1427 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1428 card->tsq.base, card->tsq.next, card->tsq.last);
1429 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1430 readl(SAR_REG_TSQB),
1431 readl(SAR_REG_TSQT),
1432 readl(SAR_REG_TSQH));
1434 stat = le32_to_cpu(tsqe->word_2);
1436 if (stat & SAR_TSQE_INVALID)
1440 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1441 le32_to_cpu(tsqe->word_1),
1442 le32_to_cpu(tsqe->word_2));
1444 switch (stat & SAR_TSQE_TYPE) {
1445 case SAR_TSQE_TYPE_TIMER:
1446 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1449 case SAR_TSQE_TYPE_IDLE:
1451 conn = le32_to_cpu(tsqe->word_1);
1453 if (SAR_TSQE_TAG(stat) == 0x10) {
1455 printk("%s: Connection %d halted.\n",
1457 le32_to_cpu(tsqe->word_1) & 0x1fff);
1462 vc = card->vcs[conn & 0x1fff];
1464 printk("%s: could not find VC from conn %d\n",
1465 card->name, conn & 0x1fff);
1469 printk("%s: Connection %d IDLE.\n",
1470 card->name, vc->index);
1472 set_bit(VCF_IDLE, &vc->flags);
1475 case SAR_TSQE_TYPE_TSR:
1477 conn = le32_to_cpu(tsqe->word_1);
1479 vc = card->vcs[conn & 0x1fff];
1481 printk("%s: no VC at index %d\n",
1483 le32_to_cpu(tsqe->word_1) & 0x1fff);
1487 drain_scq(card, vc);
1490 case SAR_TSQE_TYPE_TBD_COMP:
1492 conn = le32_to_cpu(tsqe->word_1);
1494 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1495 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1497 if (vpi >= (1 << card->vpibits) ||
1498 vci >= (1 << card->vcibits)) {
1499 printk("%s: TBD complete: "
1500 "out of range VPI.VCI %u.%u\n",
1501 card->name, vpi, vci);
1505 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1507 printk("%s: TBD complete: "
1508 "no VC at VPI.VCI %u.%u\n",
1509 card->name, vpi, vci);
1513 drain_scq(card, vc);
1517 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1519 card->tsq.next = tsqe;
1520 if (card->tsq.next == card->tsq.last)
1521 tsqe = card->tsq.base;
1523 tsqe = card->tsq.next + 1;
1525 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1526 card->tsq.base, card->tsq.next, card->tsq.last);
1528 stat = le32_to_cpu(tsqe->word_2);
1530 } while (!(stat & SAR_TSQE_INVALID));
1532 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1535 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1536 card->index, readl(SAR_REG_TSQH),
1537 readl(SAR_REG_TSQT), card->tsq.next);
1542 tst_timer(unsigned long data)
1544 struct idt77252_dev *card = (struct idt77252_dev *)data;
1545 unsigned long base, idle, jump;
1546 unsigned long flags;
1550 spin_lock_irqsave(&card->tst_lock, flags);
1552 base = card->tst[card->tst_index];
1553 idle = card->tst[card->tst_index ^ 1];
1555 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1556 jump = base + card->tst_size - 2;
1558 pc = readl(SAR_REG_NOW) >> 2;
1559 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1560 mod_timer(&card->tst_timer, jiffies + 1);
1564 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1566 card->tst_index ^= 1;
1567 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1569 base = card->tst[card->tst_index];
1570 idle = card->tst[card->tst_index ^ 1];
1572 for (e = 0; e < card->tst_size - 2; e++) {
1573 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1574 write_sram(card, idle + e,
1575 card->soft_tst[e].tste & TSTE_MASK);
1576 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1581 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1583 for (e = 0; e < card->tst_size - 2; e++) {
1584 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1585 write_sram(card, idle + e,
1586 card->soft_tst[e].tste & TSTE_MASK);
1587 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1588 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1592 jump = base + card->tst_size - 2;
1594 write_sram(card, jump, TSTE_OPC_NULL);
1595 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1597 mod_timer(&card->tst_timer, jiffies + 1);
1601 spin_unlock_irqrestore(&card->tst_lock, flags);
1605 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1606 int n, unsigned int opc)
1608 unsigned long cl, avail;
1613 avail = card->tst_size - 2;
1614 for (e = 0; e < avail; e++) {
1615 if (card->soft_tst[e].vc == NULL)
1619 printk("%s: No free TST entries found\n", card->name);
1623 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1624 card->name, vc ? vc->index : -1, e);
1628 data = opc & TSTE_OPC_MASK;
1629 if (vc && (opc != TSTE_OPC_NULL))
1630 data = opc | vc->index;
1632 idle = card->tst[card->tst_index ^ 1];
1638 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1640 card->soft_tst[e].vc = vc;
1642 card->soft_tst[e].vc = (void *)-1;
1644 card->soft_tst[e].tste = data;
1645 if (timer_pending(&card->tst_timer))
1646 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1648 write_sram(card, idle + e, data);
1649 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1652 cl -= card->tst_size;
1665 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1667 unsigned long flags;
1670 spin_lock_irqsave(&card->tst_lock, flags);
1672 res = __fill_tst(card, vc, n, opc);
1674 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1675 if (!timer_pending(&card->tst_timer))
1676 mod_timer(&card->tst_timer, jiffies + 1);
1678 spin_unlock_irqrestore(&card->tst_lock, flags);
1683 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1688 idle = card->tst[card->tst_index ^ 1];
1690 for (e = 0; e < card->tst_size - 2; e++) {
1691 if (card->soft_tst[e].vc == vc) {
1692 card->soft_tst[e].vc = NULL;
1694 card->soft_tst[e].tste = TSTE_OPC_VAR;
1695 if (timer_pending(&card->tst_timer))
1696 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1698 write_sram(card, idle + e, TSTE_OPC_VAR);
1699 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1708 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1710 unsigned long flags;
1713 spin_lock_irqsave(&card->tst_lock, flags);
1715 res = __clear_tst(card, vc);
1717 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1718 if (!timer_pending(&card->tst_timer))
1719 mod_timer(&card->tst_timer, jiffies + 1);
1721 spin_unlock_irqrestore(&card->tst_lock, flags);
1726 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1727 int n, unsigned int opc)
1729 unsigned long flags;
1732 spin_lock_irqsave(&card->tst_lock, flags);
1734 __clear_tst(card, vc);
1735 res = __fill_tst(card, vc, n, opc);
1737 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1738 if (!timer_pending(&card->tst_timer))
1739 mod_timer(&card->tst_timer, jiffies + 1);
1741 spin_unlock_irqrestore(&card->tst_lock, flags);
1747 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1751 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1753 switch (vc->class) {
1755 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1756 card->name, tct, vc->scq->scd);
1758 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1759 write_sram(card, tct + 1, 0);
1760 write_sram(card, tct + 2, 0);
1761 write_sram(card, tct + 3, 0);
1762 write_sram(card, tct + 4, 0);
1763 write_sram(card, tct + 5, 0);
1764 write_sram(card, tct + 6, 0);
1765 write_sram(card, tct + 7, 0);
1769 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1770 card->name, tct, vc->scq->scd);
1772 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1773 write_sram(card, tct + 1, 0);
1774 write_sram(card, tct + 2, TCT_TSIF);
1775 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1776 write_sram(card, tct + 4, 0);
1777 write_sram(card, tct + 5, vc->init_er);
1778 write_sram(card, tct + 6, 0);
1779 write_sram(card, tct + 7, TCT_FLAG_UBR);
1791 /*****************************************************************************/
1795 /*****************************************************************************/
1797 static __inline__ int
1798 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1800 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1803 static __inline__ int
1804 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1806 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1810 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1812 unsigned long flags;
1816 skb->data = skb->head;
1817 skb_reset_tail_pointer(skb);
1820 skb_reserve(skb, 16);
1824 skb_put(skb, SAR_FB_SIZE_0);
1827 skb_put(skb, SAR_FB_SIZE_1);
1830 skb_put(skb, SAR_FB_SIZE_2);
1833 skb_put(skb, SAR_FB_SIZE_3);
1839 if (idt77252_fbq_full(card, queue))
1842 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1844 handle = IDT77252_PRV_POOL(skb);
1845 addr = IDT77252_PRV_PADDR(skb);
1847 spin_lock_irqsave(&card->cmd_lock, flags);
1848 writel(handle, card->fbq[queue]);
1849 writel(addr, card->fbq[queue]);
1850 spin_unlock_irqrestore(&card->cmd_lock, flags);
1856 add_rx_skb(struct idt77252_dev *card, int queue,
1857 unsigned int size, unsigned int count)
1859 struct sk_buff *skb;
1864 skb = dev_alloc_skb(size);
1868 if (sb_pool_add(card, skb, queue)) {
1869 printk("%s: SB POOL full\n", __func__);
1873 paddr = pci_map_single(card->pcidev, skb->data,
1874 skb_end_pointer(skb) - skb->data,
1875 PCI_DMA_FROMDEVICE);
1876 IDT77252_PRV_PADDR(skb) = paddr;
1878 if (push_rx_skb(card, skb, queue)) {
1879 printk("%s: FB QUEUE full\n", __func__);
1887 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1888 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE);
1890 handle = IDT77252_PRV_POOL(skb);
1891 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1899 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1901 u32 handle = IDT77252_PRV_POOL(skb);
1904 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1905 skb_end_pointer(skb) - skb->data,
1906 PCI_DMA_FROMDEVICE);
1908 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1910 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1911 skb_end_pointer(skb) - skb->data,
1912 PCI_DMA_FROMDEVICE);
1913 sb_pool_remove(card, skb);
1919 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1924 rpp->last = &rpp->first;
1928 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1930 struct sk_buff *skb, *next;
1934 for (i = 0; i < rpp->count; i++) {
1937 recycle_rx_skb(card, skb);
1940 flush_rx_pool(card, rpp);
1943 /*****************************************************************************/
1947 /*****************************************************************************/
1950 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1952 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1955 static unsigned char
1956 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1958 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1962 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1964 struct atm_dev *dev = vcc->dev;
1965 struct idt77252_dev *card = dev->dev_data;
1966 struct vc_map *vc = vcc->dev_data;
1970 printk("%s: NULL connection in send().\n", card->name);
1971 atomic_inc(&vcc->stats->tx_err);
1975 if (!test_bit(VCF_TX, &vc->flags)) {
1976 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1977 atomic_inc(&vcc->stats->tx_err);
1982 switch (vcc->qos.aal) {
1988 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1989 atomic_inc(&vcc->stats->tx_err);
1994 if (skb_shinfo(skb)->nr_frags != 0) {
1995 printk("%s: No scatter-gather yet.\n", card->name);
1996 atomic_inc(&vcc->stats->tx_err);
2000 ATM_SKB(skb)->vcc = vcc;
2002 err = queue_skb(card, vc, skb, oam);
2004 atomic_inc(&vcc->stats->tx_err);
2012 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2014 return idt77252_send_skb(vcc, skb, 0);
2018 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2020 struct atm_dev *dev = vcc->dev;
2021 struct idt77252_dev *card = dev->dev_data;
2022 struct sk_buff *skb;
2024 skb = dev_alloc_skb(64);
2026 printk("%s: Out of memory in send_oam().\n", card->name);
2027 atomic_inc(&vcc->stats->tx_err);
2030 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2032 memcpy(skb_put(skb, 52), cell, 52);
2034 return idt77252_send_skb(vcc, skb, 1);
2037 static __inline__ unsigned int
2038 idt77252_fls(unsigned int x)
2044 if (x & 0xffff0000) {
2066 idt77252_int_to_atmfp(unsigned int rate)
2072 e = idt77252_fls(rate) - 1;
2074 m = (rate - (1 << e)) << (9 - e);
2076 m = (rate - (1 << e));
2078 m = (rate - (1 << e)) >> (e - 9);
2079 return 0x4000 | (e << 9) | m;
2083 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2087 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2089 return rate_to_log[(afp >> 5) & 0x1ff];
2090 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2094 idt77252_est_timer(unsigned long data)
2096 struct vc_map *vc = (struct vc_map *)data;
2097 struct idt77252_dev *card = vc->card;
2098 struct rate_estimator *est;
2099 unsigned long flags;
2104 spin_lock_irqsave(&vc->lock, flags);
2105 est = vc->estimator;
2109 ncells = est->cells;
2111 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2112 est->last_cells = ncells;
2113 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2114 est->cps = (est->avcps + 0x1f) >> 5;
2117 if (cps < (est->maxcps >> 4))
2118 cps = est->maxcps >> 4;
2120 lacr = idt77252_rate_logindex(card, cps);
2121 if (lacr > vc->max_er)
2124 if (lacr != vc->lacr) {
2126 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2129 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2130 add_timer(&est->timer);
2133 spin_unlock_irqrestore(&vc->lock, flags);
2136 static struct rate_estimator *
2137 idt77252_init_est(struct vc_map *vc, int pcr)
2139 struct rate_estimator *est;
2141 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2144 est->maxcps = pcr < 0 ? -pcr : pcr;
2145 est->cps = est->maxcps;
2146 est->avcps = est->cps << 5;
2148 est->interval = 2; /* XXX: make this configurable */
2149 est->ewma_log = 2; /* XXX: make this configurable */
2150 init_timer(&est->timer);
2151 est->timer.data = (unsigned long)vc;
2152 est->timer.function = idt77252_est_timer;
2154 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2155 add_timer(&est->timer);
2161 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2162 struct atm_vcc *vcc, struct atm_qos *qos)
2164 int tst_free, tst_used, tst_entries;
2165 unsigned long tmpl, modl;
2168 if ((qos->txtp.max_pcr == 0) &&
2169 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2170 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2176 tst_free = card->tst_free;
2177 if (test_bit(VCF_TX, &vc->flags))
2178 tst_used = vc->ntste;
2179 tst_free += tst_used;
2181 tcr = atm_pcr_goal(&qos->txtp);
2182 tcra = tcr >= 0 ? tcr : -tcr;
2184 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2186 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2187 modl = tmpl % (unsigned long)card->utopia_pcr;
2189 tst_entries = (int) (tmpl / card->utopia_pcr);
2193 } else if (tcr == 0) {
2194 tst_entries = tst_free - SAR_TST_RESERVED;
2195 if (tst_entries <= 0) {
2196 printk("%s: no CBR bandwidth free.\n", card->name);
2201 if (tst_entries == 0) {
2202 printk("%s: selected CBR bandwidth < granularity.\n",
2207 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2208 printk("%s: not enough CBR bandwidth free.\n", card->name);
2212 vc->ntste = tst_entries;
2214 card->tst_free = tst_free - tst_entries;
2215 if (test_bit(VCF_TX, &vc->flags)) {
2216 if (tst_used == tst_entries)
2219 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2220 card->name, tst_used, tst_entries);
2221 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2225 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2226 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2231 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2232 struct atm_vcc *vcc, struct atm_qos *qos)
2234 unsigned long flags;
2237 spin_lock_irqsave(&vc->lock, flags);
2238 if (vc->estimator) {
2239 del_timer(&vc->estimator->timer);
2240 kfree(vc->estimator);
2241 vc->estimator = NULL;
2243 spin_unlock_irqrestore(&vc->lock, flags);
2245 tcr = atm_pcr_goal(&qos->txtp);
2247 tcr = card->link_pcr;
2249 vc->estimator = idt77252_init_est(vc, tcr);
2251 vc->class = SCHED_UBR;
2252 vc->init_er = idt77252_rate_logindex(card, tcr);
2253 vc->lacr = vc->init_er;
2255 vc->max_er = vc->init_er;
2263 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2264 struct atm_vcc *vcc, struct atm_qos *qos)
2268 if (test_bit(VCF_TX, &vc->flags))
2271 switch (qos->txtp.traffic_class) {
2273 vc->class = SCHED_CBR;
2277 vc->class = SCHED_UBR;
2283 return -EPROTONOSUPPORT;
2286 vc->scq = alloc_scq(card, vc->class);
2288 printk("%s: can't get SCQ.\n", card->name);
2292 vc->scq->scd = get_free_scd(card, vc);
2293 if (vc->scq->scd == 0) {
2294 printk("%s: no SCD available.\n", card->name);
2295 free_scq(card, vc->scq);
2299 fill_scd(card, vc->scq, vc->class);
2301 if (set_tct(card, vc)) {
2302 printk("%s: class %d not supported.\n",
2303 card->name, qos->txtp.traffic_class);
2305 card->scd2vc[vc->scd_index] = NULL;
2306 free_scq(card, vc->scq);
2307 return -EPROTONOSUPPORT;
2310 switch (vc->class) {
2312 error = idt77252_init_cbr(card, vc, vcc, qos);
2314 card->scd2vc[vc->scd_index] = NULL;
2315 free_scq(card, vc->scq);
2319 clear_bit(VCF_IDLE, &vc->flags);
2320 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2324 error = idt77252_init_ubr(card, vc, vcc, qos);
2326 card->scd2vc[vc->scd_index] = NULL;
2327 free_scq(card, vc->scq);
2331 set_bit(VCF_IDLE, &vc->flags);
2336 set_bit(VCF_TX, &vc->flags);
2341 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2342 struct atm_vcc *vcc, struct atm_qos *qos)
2344 unsigned long flags;
2348 if (test_bit(VCF_RX, &vc->flags))
2352 set_bit(VCF_RX, &vc->flags);
2354 if ((vcc->vci == 3) || (vcc->vci == 4))
2357 flush_rx_pool(card, &vc->rcv.rx_pool);
2359 rcte |= SAR_RCTE_CONNECTOPEN;
2360 rcte |= SAR_RCTE_RAWCELLINTEN;
2364 rcte |= SAR_RCTE_RCQ;
2367 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2370 rcte |= SAR_RCTE_AAL34;
2373 rcte |= SAR_RCTE_AAL5;
2376 rcte |= SAR_RCTE_RCQ;
2380 if (qos->aal != ATM_AAL5)
2381 rcte |= SAR_RCTE_FBP_1;
2382 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2383 rcte |= SAR_RCTE_FBP_3;
2384 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2385 rcte |= SAR_RCTE_FBP_2;
2386 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2387 rcte |= SAR_RCTE_FBP_1;
2389 rcte |= SAR_RCTE_FBP_01;
2391 addr = card->rct_base + (vc->index << 2);
2393 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2394 write_sram(card, addr, rcte);
2396 spin_lock_irqsave(&card->cmd_lock, flags);
2397 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2399 spin_unlock_irqrestore(&card->cmd_lock, flags);
2405 idt77252_open(struct atm_vcc *vcc)
2407 struct atm_dev *dev = vcc->dev;
2408 struct idt77252_dev *card = dev->dev_data;
2414 short vpi = vcc->vpi;
2416 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2419 if (vpi >= (1 << card->vpibits)) {
2420 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2424 if (vci >= (1 << card->vcibits)) {
2425 printk("%s: unsupported VCI: %d\n", card->name, vci);
2429 set_bit(ATM_VF_ADDR, &vcc->flags);
2431 mutex_lock(&card->mutex);
2433 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2435 switch (vcc->qos.aal) {
2441 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2442 mutex_unlock(&card->mutex);
2443 return -EPROTONOSUPPORT;
2446 index = VPCI2VC(card, vpi, vci);
2447 if (!card->vcs[index]) {
2448 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2449 if (!card->vcs[index]) {
2450 printk("%s: can't alloc vc in open()\n", card->name);
2451 mutex_unlock(&card->mutex);
2454 card->vcs[index]->card = card;
2455 card->vcs[index]->index = index;
2457 spin_lock_init(&card->vcs[index]->lock);
2459 vc = card->vcs[index];
2463 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2464 card->name, vc->index, vcc->vpi, vcc->vci,
2465 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2466 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2467 vcc->qos.rxtp.max_sdu);
2470 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2471 test_bit(VCF_TX, &vc->flags))
2473 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2474 test_bit(VCF_RX, &vc->flags))
2478 printk("%s: %s vci already in use.\n", card->name,
2479 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2480 mutex_unlock(&card->mutex);
2484 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2485 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2487 mutex_unlock(&card->mutex);
2492 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2493 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2495 mutex_unlock(&card->mutex);
2500 set_bit(ATM_VF_READY, &vcc->flags);
2502 mutex_unlock(&card->mutex);
2507 idt77252_close(struct atm_vcc *vcc)
2509 struct atm_dev *dev = vcc->dev;
2510 struct idt77252_dev *card = dev->dev_data;
2511 struct vc_map *vc = vcc->dev_data;
2512 unsigned long flags;
2514 unsigned long timeout;
2516 mutex_lock(&card->mutex);
2518 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2519 card->name, vc->index, vcc->vpi, vcc->vci);
2521 clear_bit(ATM_VF_READY, &vcc->flags);
2523 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2525 spin_lock_irqsave(&vc->lock, flags);
2526 clear_bit(VCF_RX, &vc->flags);
2528 spin_unlock_irqrestore(&vc->lock, flags);
2530 if ((vcc->vci == 3) || (vcc->vci == 4))
2533 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2535 spin_lock_irqsave(&card->cmd_lock, flags);
2536 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2538 spin_unlock_irqrestore(&card->cmd_lock, flags);
2540 if (vc->rcv.rx_pool.count) {
2541 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2544 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2549 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2551 spin_lock_irqsave(&vc->lock, flags);
2552 clear_bit(VCF_TX, &vc->flags);
2553 clear_bit(VCF_IDLE, &vc->flags);
2554 clear_bit(VCF_RSV, &vc->flags);
2557 if (vc->estimator) {
2558 del_timer(&vc->estimator->timer);
2559 kfree(vc->estimator);
2560 vc->estimator = NULL;
2562 spin_unlock_irqrestore(&vc->lock, flags);
2565 while (atomic_read(&vc->scq->used) > 0) {
2566 timeout = msleep_interruptible(timeout);
2571 printk("%s: SCQ drain timeout: %u used\n",
2572 card->name, atomic_read(&vc->scq->used));
2574 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2575 clear_scd(card, vc->scq, vc->class);
2577 if (vc->class == SCHED_CBR) {
2578 clear_tst(card, vc);
2579 card->tst_free += vc->ntste;
2583 card->scd2vc[vc->scd_index] = NULL;
2584 free_scq(card, vc->scq);
2587 mutex_unlock(&card->mutex);
2591 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2593 struct atm_dev *dev = vcc->dev;
2594 struct idt77252_dev *card = dev->dev_data;
2595 struct vc_map *vc = vcc->dev_data;
2598 mutex_lock(&card->mutex);
2600 if (qos->txtp.traffic_class != ATM_NONE) {
2601 if (!test_bit(VCF_TX, &vc->flags)) {
2602 error = idt77252_init_tx(card, vc, vcc, qos);
2606 switch (qos->txtp.traffic_class) {
2608 error = idt77252_init_cbr(card, vc, vcc, qos);
2614 error = idt77252_init_ubr(card, vc, vcc, qos);
2618 if (!test_bit(VCF_IDLE, &vc->flags)) {
2619 writel(TCMDQ_LACR | (vc->lacr << 16) |
2620 vc->index, SAR_REG_TCMDQ);
2626 error = -EOPNOTSUPP;
2632 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2633 !test_bit(VCF_RX, &vc->flags)) {
2634 error = idt77252_init_rx(card, vc, vcc, qos);
2639 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2641 set_bit(ATM_VF_HASQOS, &vcc->flags);
2644 mutex_unlock(&card->mutex);
2649 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2651 struct idt77252_dev *card = dev->dev_data;
2656 return sprintf(page, "IDT77252 Interrupts:\n");
2658 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2660 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2662 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2664 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2666 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2668 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2670 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2672 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2674 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2676 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2678 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2680 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2682 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2684 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2686 for (i = 0; i < card->tct_size; i++) {
2688 struct atm_vcc *vcc;
2705 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2706 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2708 for (i = 0; i < 8; i++)
2709 p += sprintf(p, " %08x", read_sram(card, tct + i));
2710 p += sprintf(p, "\n");
2716 /*****************************************************************************/
2718 /* Interrupt handler */
2720 /*****************************************************************************/
2723 idt77252_collect_stat(struct idt77252_dev *card)
2727 cdc = readl(SAR_REG_CDC);
2728 vpec = readl(SAR_REG_VPEC);
2729 icc = readl(SAR_REG_ICC);
2732 printk("%s:", card->name);
2734 if (cdc & 0x7f0000) {
2738 if (cdc & (1 << 22)) {
2739 printk("%sRM ID", s);
2742 if (cdc & (1 << 21)) {
2743 printk("%sCON TAB", s);
2746 if (cdc & (1 << 20)) {
2747 printk("%sNO FB", s);
2750 if (cdc & (1 << 19)) {
2751 printk("%sOAM CRC", s);
2754 if (cdc & (1 << 18)) {
2755 printk("%sRM CRC", s);
2758 if (cdc & (1 << 17)) {
2759 printk("%sRM FIFO", s);
2762 if (cdc & (1 << 16)) {
2763 printk("%sRX FIFO", s);
2769 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2770 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2775 idt77252_interrupt(int irq, void *dev_id)
2777 struct idt77252_dev *card = dev_id;
2780 stat = readl(SAR_REG_STAT) & 0xffff;
2781 if (!stat) /* no interrupt for us */
2784 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2785 printk("%s: Re-entering irq_handler()\n", card->name);
2789 writel(stat, SAR_REG_STAT); /* reset interrupt */
2791 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2792 INTPRINTK("%s: TSIF\n", card->name);
2793 card->irqstat[15]++;
2796 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2797 INTPRINTK("%s: TXICP\n", card->name);
2798 card->irqstat[14]++;
2799 #ifdef CONFIG_ATM_IDT77252_DEBUG
2800 idt77252_tx_dump(card);
2803 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2804 INTPRINTK("%s: TSQF\n", card->name);
2805 card->irqstat[12]++;
2808 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2809 INTPRINTK("%s: TMROF\n", card->name);
2810 card->irqstat[11]++;
2811 idt77252_collect_stat(card);
2814 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2815 INTPRINTK("%s: EPDU\n", card->name);
2819 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2820 INTPRINTK("%s: RSQAF\n", card->name);
2824 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2825 INTPRINTK("%s: RSQF\n", card->name);
2829 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2830 INTPRINTK("%s: RAWCF\n", card->name);
2832 idt77252_rx_raw(card);
2835 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2836 INTPRINTK("%s: PHYI", card->name);
2837 card->irqstat[10]++;
2838 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2839 card->atmdev->phy->interrupt(card->atmdev);
2842 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2843 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2845 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2847 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2849 if (stat & SAR_STAT_FBQ0A)
2851 if (stat & SAR_STAT_FBQ1A)
2853 if (stat & SAR_STAT_FBQ2A)
2855 if (stat & SAR_STAT_FBQ3A)
2858 schedule_work(&card->tqueue);
2862 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2867 idt77252_softint(struct work_struct *work)
2869 struct idt77252_dev *card =
2870 container_of(work, struct idt77252_dev, tqueue);
2874 for (done = 1; ; done = 1) {
2875 stat = readl(SAR_REG_STAT) >> 16;
2877 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2878 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2883 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2884 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2889 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2890 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2895 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2896 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2904 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2909 open_card_oam(struct idt77252_dev *card)
2911 unsigned long flags;
2918 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2919 for (vci = 3; vci < 5; vci++) {
2920 index = VPCI2VC(card, vpi, vci);
2922 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2924 printk("%s: can't alloc vc\n", card->name);
2928 card->vcs[index] = vc;
2930 flush_rx_pool(card, &vc->rcv.rx_pool);
2932 rcte = SAR_RCTE_CONNECTOPEN |
2933 SAR_RCTE_RAWCELLINTEN |
2937 addr = card->rct_base + (vc->index << 2);
2938 write_sram(card, addr, rcte);
2940 spin_lock_irqsave(&card->cmd_lock, flags);
2941 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2944 spin_unlock_irqrestore(&card->cmd_lock, flags);
2952 close_card_oam(struct idt77252_dev *card)
2954 unsigned long flags;
2960 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2961 for (vci = 3; vci < 5; vci++) {
2962 index = VPCI2VC(card, vpi, vci);
2963 vc = card->vcs[index];
2965 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2967 spin_lock_irqsave(&card->cmd_lock, flags);
2968 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2971 spin_unlock_irqrestore(&card->cmd_lock, flags);
2973 if (vc->rcv.rx_pool.count) {
2974 DPRINTK("%s: closing a VC "
2975 "with pending rx buffers.\n",
2978 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2985 open_card_ubr0(struct idt77252_dev *card)
2989 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2991 printk("%s: can't alloc vc\n", card->name);
2995 vc->class = SCHED_UBR0;
2997 vc->scq = alloc_scq(card, vc->class);
2999 printk("%s: can't get SCQ.\n", card->name);
3003 card->scd2vc[0] = vc;
3005 vc->scq->scd = card->scd_base;
3007 fill_scd(card, vc->scq, vc->class);
3009 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3010 write_sram(card, card->tct_base + 1, 0);
3011 write_sram(card, card->tct_base + 2, 0);
3012 write_sram(card, card->tct_base + 3, 0);
3013 write_sram(card, card->tct_base + 4, 0);
3014 write_sram(card, card->tct_base + 5, 0);
3015 write_sram(card, card->tct_base + 6, 0);
3016 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3018 clear_bit(VCF_IDLE, &vc->flags);
3019 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3024 idt77252_dev_open(struct idt77252_dev *card)
3028 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3029 printk("%s: SAR not yet initialized.\n", card->name);
3033 conf = SAR_CFG_RXPTH| /* enable receive path */
3034 SAR_RX_DELAY | /* interrupt on complete PDU */
3035 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3036 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3037 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3038 SAR_CFG_FBIE | /* interrupt on low free buffers */
3039 SAR_CFG_TXEN | /* transmit operation enable */
3040 SAR_CFG_TXINT | /* interrupt on transmit status */
3041 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3042 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3043 SAR_CFG_PHYIE /* enable PHY interrupts */
3046 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3047 /* Test RAW cell receive. */
3048 conf |= SAR_CFG_VPECA;
3051 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3053 if (open_card_oam(card)) {
3054 printk("%s: Error initializing OAM.\n", card->name);
3058 if (open_card_ubr0(card)) {
3059 printk("%s: Error initializing UBR0.\n", card->name);
3063 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3067 static void idt77252_dev_close(struct atm_dev *dev)
3069 struct idt77252_dev *card = dev->dev_data;
3072 close_card_oam(card);
3074 conf = SAR_CFG_RXPTH | /* enable receive path */
3075 SAR_RX_DELAY | /* interrupt on complete PDU */
3076 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3077 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3078 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3079 SAR_CFG_FBIE | /* interrupt on low free buffers */
3080 SAR_CFG_TXEN | /* transmit operation enable */
3081 SAR_CFG_TXINT | /* interrupt on transmit status */
3082 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3083 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3086 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3088 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3092 /*****************************************************************************/
3094 /* Initialisation and Deinitialization of IDT77252 */
3096 /*****************************************************************************/
3100 deinit_card(struct idt77252_dev *card)
3102 struct sk_buff *skb;
3105 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3106 printk("%s: SAR not yet initialized.\n", card->name);
3109 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3111 writel(0, SAR_REG_CFG);
3114 atm_dev_deregister(card->atmdev);
3116 for (i = 0; i < 4; i++) {
3117 for (j = 0; j < FBQ_SIZE; j++) {
3118 skb = card->sbpool[i].skb[j];
3120 pci_unmap_single(card->pcidev,
3121 IDT77252_PRV_PADDR(skb),
3122 (skb_end_pointer(skb) -
3124 PCI_DMA_FROMDEVICE);
3125 card->sbpool[i].skb[j] = NULL;
3131 vfree(card->soft_tst);
3133 vfree(card->scd2vc);
3137 if (card->raw_cell_hnd) {
3138 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3139 card->raw_cell_hnd, card->raw_cell_paddr);
3142 if (card->rsq.base) {
3143 DIPRINTK("%s: Release RSQ ...\n", card->name);
3147 if (card->tsq.base) {
3148 DIPRINTK("%s: Release TSQ ...\n", card->name);
3152 DIPRINTK("idt77252: Release IRQ.\n");
3153 free_irq(card->pcidev->irq, card);
3155 for (i = 0; i < 4; i++) {
3157 iounmap(card->fbq[i]);
3161 iounmap(card->membase);
3163 clear_bit(IDT77252_BIT_INIT, &card->flags);
3164 DIPRINTK("%s: Card deinitialized.\n", card->name);
3168 static int __devinit
3169 init_sram(struct idt77252_dev *card)
3173 for (i = 0; i < card->sramsize; i += 4)
3174 write_sram(card, (i >> 2), 0);
3176 /* set SRAM layout for THIS card */
3177 if (card->sramsize == (512 * 1024)) {
3178 card->tct_base = SAR_SRAM_TCT_128_BASE;
3179 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3180 / SAR_SRAM_TCT_SIZE;
3181 card->rct_base = SAR_SRAM_RCT_128_BASE;
3182 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3183 / SAR_SRAM_RCT_SIZE;
3184 card->rt_base = SAR_SRAM_RT_128_BASE;
3185 card->scd_base = SAR_SRAM_SCD_128_BASE;
3186 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3187 / SAR_SRAM_SCD_SIZE;
3188 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3189 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3190 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3191 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3192 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3193 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3194 card->fifo_size = SAR_RXFD_SIZE_32K;
3196 card->tct_base = SAR_SRAM_TCT_32_BASE;
3197 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3198 / SAR_SRAM_TCT_SIZE;
3199 card->rct_base = SAR_SRAM_RCT_32_BASE;
3200 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3201 / SAR_SRAM_RCT_SIZE;
3202 card->rt_base = SAR_SRAM_RT_32_BASE;
3203 card->scd_base = SAR_SRAM_SCD_32_BASE;
3204 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3205 / SAR_SRAM_SCD_SIZE;
3206 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3207 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3208 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3209 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3210 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3211 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3212 card->fifo_size = SAR_RXFD_SIZE_4K;
3215 /* Initialize TCT */
3216 for (i = 0; i < card->tct_size; i++) {
3217 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3218 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3219 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3220 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3221 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3222 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3223 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3224 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3227 /* Initialize RCT */
3228 for (i = 0; i < card->rct_size; i++) {
3229 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3230 (u32) SAR_RCTE_RAWCELLINTEN);
3231 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3233 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3235 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3239 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3240 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3241 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3242 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3243 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3244 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3245 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3246 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3248 /* Initialize rate table */
3249 for (i = 0; i < 256; i++) {
3250 write_sram(card, card->rt_base + i, log_to_rate[i]);
3253 for (i = 0; i < 128; i++) {
3256 tmp = rate_to_log[(i << 2) + 0] << 0;
3257 tmp |= rate_to_log[(i << 2) + 1] << 8;
3258 tmp |= rate_to_log[(i << 2) + 2] << 16;
3259 tmp |= rate_to_log[(i << 2) + 3] << 24;
3260 write_sram(card, card->rt_base + 256 + i, tmp);
3263 #if 0 /* Fill RDF and AIR tables. */
3264 for (i = 0; i < 128; i++) {
3267 tmp = RDF[0][(i << 1) + 0] << 16;
3268 tmp |= RDF[0][(i << 1) + 1] << 0;
3269 write_sram(card, card->rt_base + 512 + i, tmp);
3272 for (i = 0; i < 128; i++) {
3275 tmp = AIR[0][(i << 1) + 0] << 16;
3276 tmp |= AIR[0][(i << 1) + 1] << 0;
3277 write_sram(card, card->rt_base + 640 + i, tmp);
3281 IPRINTK("%s: initialize rate table ...\n", card->name);
3282 writel(card->rt_base << 2, SAR_REG_RTBL);
3284 /* Initialize TSTs */
3285 IPRINTK("%s: initialize TST ...\n", card->name);
3286 card->tst_free = card->tst_size - 2; /* last two are jumps */
3288 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3289 write_sram(card, i, TSTE_OPC_VAR);
3290 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3291 idt77252_sram_write_errors = 1;
3292 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3293 idt77252_sram_write_errors = 0;
3294 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3295 write_sram(card, i, TSTE_OPC_VAR);
3296 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3297 idt77252_sram_write_errors = 1;
3298 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3299 idt77252_sram_write_errors = 0;
3301 card->tst_index = 0;
3302 writel(card->tst[0] << 2, SAR_REG_TSTB);
3304 /* Initialize ABRSTD and Receive FIFO */
3305 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3306 writel(card->abrst_size | (card->abrst_base << 2),
3309 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3310 writel(card->fifo_size | (card->fifo_base << 2),
3313 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3317 static int __devinit
3318 init_card(struct atm_dev *dev)
3320 struct idt77252_dev *card = dev->dev_data;
3321 struct pci_dev *pcidev = card->pcidev;
3322 unsigned long tmpl, modl;
3323 unsigned int linkrate, rsvdcr;
3324 unsigned int tst_entries;
3325 struct net_device *tmp;
3333 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3334 printk("Error: SAR already initialized.\n");
3338 /*****************************************************************/
3339 /* P C I C O N F I G U R A T I O N */
3340 /*****************************************************************/
3342 /* Set PCI Retry-Timeout and TRDY timeout */
3343 IPRINTK("%s: Checking PCI retries.\n", card->name);
3344 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3345 printk("%s: can't read PCI retry timeout.\n", card->name);
3349 if (pci_byte != 0) {
3350 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3351 card->name, pci_byte);
3352 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3353 printk("%s: can't set PCI retry timeout.\n",
3359 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3360 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3361 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3365 if (pci_byte != 0) {
3366 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3367 card->name, pci_byte);
3368 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3369 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3374 /* Reset Timer register */
3375 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3376 printk("%s: resetting timer overflow.\n", card->name);
3377 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3379 IPRINTK("%s: Request IRQ ... ", card->name);
3380 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED,
3381 card->name, card) != 0) {
3382 printk("%s: can't allocate IRQ.\n", card->name);
3386 IPRINTK("got %d.\n", pcidev->irq);
3388 /*****************************************************************/
3389 /* C H E C K A N D I N I T S R A M */
3390 /*****************************************************************/
3392 IPRINTK("%s: Initializing SRAM\n", card->name);
3394 /* preset size of connecton table, so that init_sram() knows about it */
3395 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3396 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3397 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3398 #ifndef ATM_IDT77252_SEND_IDLE
3399 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3403 if (card->sramsize == (512 * 1024))
3404 conf |= SAR_CFG_CNTBL_1k;
3406 conf |= SAR_CFG_CNTBL_512;
3410 conf |= SAR_CFG_VPVCS_0;
3414 conf |= SAR_CFG_VPVCS_1;
3417 conf |= SAR_CFG_VPVCS_2;
3420 conf |= SAR_CFG_VPVCS_8;
3424 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3426 if (init_sram(card) < 0)
3429 /********************************************************************/
3430 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3431 /********************************************************************/
3432 /* Initialize TSQ */
3433 if (0 != init_tsq(card)) {
3437 /* Initialize RSQ */
3438 if (0 != init_rsq(card)) {
3443 card->vpibits = vpibits;
3444 if (card->sramsize == (512 * 1024)) {
3445 card->vcibits = 10 - card->vpibits;
3447 card->vcibits = 9 - card->vpibits;
3451 for (k = 0, i = 1; k < card->vcibits; k++) {
3456 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3457 writel(0, SAR_REG_VPM);
3459 /* Little Endian Order */
3460 writel(0, SAR_REG_GP);
3462 /* Initialize RAW Cell Handle Register */
3463 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3464 &card->raw_cell_paddr);
3465 if (!card->raw_cell_hnd) {
3466 printk("%s: memory allocation failure.\n", card->name);
3470 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3471 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3472 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3473 card->raw_cell_hnd);
3475 size = sizeof(struct vc_map *) * card->tct_size;
3476 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3477 if (NULL == (card->vcs = vmalloc(size))) {
3478 printk("%s: memory allocation failure.\n", card->name);
3482 memset(card->vcs, 0, size);
3484 size = sizeof(struct vc_map *) * card->scd_size;
3485 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3487 if (NULL == (card->scd2vc = vmalloc(size))) {
3488 printk("%s: memory allocation failure.\n", card->name);
3492 memset(card->scd2vc, 0, size);
3494 size = sizeof(struct tst_info) * (card->tst_size - 2);
3495 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3497 if (NULL == (card->soft_tst = vmalloc(size))) {
3498 printk("%s: memory allocation failure.\n", card->name);
3502 for (i = 0; i < card->tst_size - 2; i++) {
3503 card->soft_tst[i].tste = TSTE_OPC_VAR;
3504 card->soft_tst[i].vc = NULL;
3507 if (dev->phy == NULL) {
3508 printk("%s: No LT device defined.\n", card->name);
3512 if (dev->phy->ioctl == NULL) {
3513 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3518 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3520 * this is a jhs hack to get around special functionality in the
3521 * phy driver for the atecom hardware; the functionality doesn't
3522 * exist in the linux atm suni driver
3524 * it isn't the right way to do things, but as the guy from NIST
3525 * said, talking about their measurement of the fine structure
3526 * constant, "it's good enough for government work."
3528 linkrate = 149760000;
3531 card->link_pcr = (linkrate / 8 / 53);
3532 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3533 card->name, linkrate, card->link_pcr);
3535 #ifdef ATM_IDT77252_SEND_IDLE
3536 card->utopia_pcr = card->link_pcr;
3538 card->utopia_pcr = (160000000 / 8 / 54);
3542 if (card->utopia_pcr > card->link_pcr)
3543 rsvdcr = card->utopia_pcr - card->link_pcr;
3545 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3546 modl = tmpl % (unsigned long)card->utopia_pcr;
3547 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3550 card->tst_free -= tst_entries;
3551 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3554 idt77252_eeprom_init(card);
3555 printk("%s: EEPROM: %02x:", card->name,
3556 idt77252_eeprom_read_status(card));
3558 for (i = 0; i < 0x80; i++) {
3560 idt77252_eeprom_read_byte(card, i)
3564 #endif /* HAVE_EEPROM */
3569 sprintf(tname, "eth%d", card->index);
3570 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */
3572 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3574 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3575 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3576 card->atmdev->esi[2], card->atmdev->esi[3],
3577 card->atmdev->esi[4], card->atmdev->esi[5]);
3583 /* Set Maximum Deficit Count for now. */
3584 writel(0xffff, SAR_REG_MDFCT);
3586 set_bit(IDT77252_BIT_INIT, &card->flags);
3588 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3593 /*****************************************************************************/
3595 /* Probing of IDT77252 ABR SAR */
3597 /*****************************************************************************/
3600 static int __devinit
3601 idt77252_preset(struct idt77252_dev *card)
3605 /*****************************************************************/
3606 /* P C I C O N F I G U R A T I O N */
3607 /*****************************************************************/
3609 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3611 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3612 printk("%s: can't read PCI_COMMAND.\n", card->name);
3616 if (!(pci_command & PCI_COMMAND_IO)) {
3617 printk("%s: PCI_COMMAND: %04x (???)\n",
3618 card->name, pci_command);
3622 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3623 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3624 printk("%s: can't write PCI_COMMAND.\n", card->name);
3628 /*****************************************************************/
3629 /* G E N E R I C R E S E T */
3630 /*****************************************************************/
3632 /* Software reset */
3633 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3635 writel(0, SAR_REG_CFG);
3637 IPRINTK("%s: Software resetted.\n", card->name);
3642 static unsigned long __devinit
3643 probe_sram(struct idt77252_dev *card)
3647 writel(0, SAR_REG_DR0);
3648 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3650 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3651 writel(ATM_POISON, SAR_REG_DR0);
3652 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3654 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3655 data = readl(SAR_REG_DR0);
3661 return addr * sizeof(u32);
3664 static int __devinit
3665 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3667 static struct idt77252_dev **last = &idt77252_chain;
3668 static int index = 0;
3670 unsigned long membase, srambase;
3671 struct idt77252_dev *card;
3672 struct atm_dev *dev;
3676 if ((err = pci_enable_device(pcidev))) {
3677 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3681 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3683 printk("idt77252-%d: can't allocate private data\n", index);
3685 goto err_out_disable_pdev;
3687 card->revision = pcidev->revision;
3688 card->index = index;
3689 card->pcidev = pcidev;
3690 sprintf(card->name, "idt77252-%d", card->index);
3692 INIT_WORK(&card->tqueue, idt77252_softint);
3694 membase = pci_resource_start(pcidev, 1);
3695 srambase = pci_resource_start(pcidev, 2);
3697 mutex_init(&card->mutex);
3698 spin_lock_init(&card->cmd_lock);
3699 spin_lock_init(&card->tst_lock);
3701 init_timer(&card->tst_timer);
3702 card->tst_timer.data = (unsigned long)card;
3703 card->tst_timer.function = tst_timer;
3705 /* Do the I/O remapping... */
3706 card->membase = ioremap(membase, 1024);
3707 if (!card->membase) {
3708 printk("%s: can't ioremap() membase\n", card->name);
3710 goto err_out_free_card;
3713 if (idt77252_preset(card)) {
3714 printk("%s: preset failed\n", card->name);
3716 goto err_out_iounmap;
3719 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3721 printk("%s: can't register atm device\n", card->name);
3723 goto err_out_iounmap;
3725 dev->dev_data = card;
3728 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3731 printk("%s: can't init SUNI\n", card->name);
3733 goto err_out_deinit_card;
3735 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3737 card->sramsize = probe_sram(card);
3739 for (i = 0; i < 4; i++) {
3740 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3741 if (!card->fbq[i]) {
3742 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3744 goto err_out_deinit_card;
3748 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3749 card->name, ((card->revision > 1) && (card->revision < 25)) ?
3750 'A' + card->revision - 1 : '?', membase, srambase,
3751 card->sramsize / 1024);
3753 if (init_card(dev)) {
3754 printk("%s: init_card failed\n", card->name);
3756 goto err_out_deinit_card;
3759 dev->ci_range.vpi_bits = card->vpibits;
3760 dev->ci_range.vci_bits = card->vcibits;
3761 dev->link_rate = card->link_pcr;
3763 if (dev->phy->start)
3764 dev->phy->start(dev);
3766 if (idt77252_dev_open(card)) {
3767 printk("%s: dev_open failed\n", card->name);
3780 dev->phy->stop(dev);
3782 err_out_deinit_card:
3786 iounmap(card->membase);
3791 err_out_disable_pdev:
3792 pci_disable_device(pcidev);
3796 static struct pci_device_id idt77252_pci_tbl[] =
3798 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3803 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3805 static struct pci_driver idt77252_driver = {
3807 .id_table = idt77252_pci_tbl,
3808 .probe = idt77252_init_one,
3811 static int __init idt77252_init(void)
3813 struct sk_buff *skb;
3815 printk("%s: at %p\n", __func__, idt77252_init);
3817 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3818 sizeof(struct idt77252_skb_prv)) {
3819 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3820 __func__, (unsigned long) sizeof(skb->cb),
3821 (unsigned long) sizeof(struct atm_skb_data) +
3822 sizeof(struct idt77252_skb_prv));
3826 return pci_register_driver(&idt77252_driver);
3829 static void __exit idt77252_exit(void)
3831 struct idt77252_dev *card;
3832 struct atm_dev *dev;
3834 pci_unregister_driver(&idt77252_driver);
3836 while (idt77252_chain) {
3837 card = idt77252_chain;
3839 idt77252_chain = card->next;
3842 dev->phy->stop(dev);
3844 pci_disable_device(card->pcidev);
3848 DIPRINTK("idt77252: finished cleanup-module().\n");
3851 module_init(idt77252_init);
3852 module_exit(idt77252_exit);
3854 MODULE_LICENSE("GPL");
3856 module_param(vpibits, uint, 0);
3857 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3858 #ifdef CONFIG_ATM_IDT77252_DEBUG
3859 module_param(debug, ulong, 0644);
3860 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3863 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3864 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");