2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt2500pci"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
41 #include "rt2x00pci.h"
42 #include "rt2500pci.h"
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
57 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
66 udelay(REGISTER_BUSY_DELAY);
72 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
78 * Wait until the BBP becomes ready.
80 reg = rt2500pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
87 * Write the data into the BBP.
90 rt2x00_set_field32(®, BBPCSR_VALUE, value);
91 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
98 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
104 * Wait until the BBP becomes ready.
106 reg = rt2500pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
113 * Write the request into the BBP.
116 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
123 * Wait until the BBP becomes ready.
125 reg = rt2500pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
135 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
148 udelay(REGISTER_BUSY_DELAY);
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
156 rt2x00_set_field32(®, RFCSR_VALUE, value);
157 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(®, RFCSR_BUSY, 1);
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
170 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
180 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
185 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
196 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
198 static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
204 static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
210 static const struct rt2x00debug rt2500pci_rt2x00debug = {
211 .owner = THIS_MODULE,
213 .read = rt2500pci_read_csr,
214 .write = rt2500pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
225 .read = rt2500pci_bbp_read,
226 .write = rt2500pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
231 .read = rt2x00_rf_read,
232 .write = rt2500pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
239 #ifdef CONFIG_RT2500PCI_RFKILL
240 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
248 #define rt2500pci_rfkill_poll NULL
249 #endif /* CONFIG_RT2500PCI_RFKILL */
252 * Configuration handlers.
254 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
257 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
258 (2 * sizeof(__le32)));
261 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
264 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
265 (2 * sizeof(__le32)));
268 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
273 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
276 * Enable beacon config
278 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
279 rt2x00_set_field32(®, BCNCSR1_PRELOAD,
280 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
281 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN,
282 rt2x00lib_get_ring(rt2x00dev,
283 IEEE80211_TX_QUEUE_BEACON)
285 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
288 * Enable synchronisation.
290 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
291 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
292 rt2x00_set_field32(®, CSR14_TBCN, 1);
293 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
294 rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync);
295 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
298 static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
299 const int short_preamble,
300 const int ack_timeout,
301 const int ack_consume_time)
307 * When short preamble is enabled, we should set bit 0x08
309 preamble_mask = short_preamble << 3;
311 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
312 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
313 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
314 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
316 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
317 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
318 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
319 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
320 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
322 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
323 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
324 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
325 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
326 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
328 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
329 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
330 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
331 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
332 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
334 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
335 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
336 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
337 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
338 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
341 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
342 const int basic_rate_mask)
344 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
347 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
348 struct rf_channel *rf, const int txpower)
355 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
358 * Switch on tuning bits.
359 * For RT2523 devices we do not need to update the R1 register.
361 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
362 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
363 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
366 * For RT2525 we should first set the channel to half band higher.
368 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
369 static const u32 vals[] = {
370 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
371 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
372 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
373 0x00080d2e, 0x00080d3a
376 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
377 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
378 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
380 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
383 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
384 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
385 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
387 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
390 * Channel 14 requires the Japan filter bit to be set.
393 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
394 rt2500pci_bbp_write(rt2x00dev, 70, r70);
399 * Switch off tuning bits.
400 * For RT2523 devices we do not need to update the R1 register.
402 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
407 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
408 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
411 * Clear false CRC during channel switch.
413 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
416 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
421 rt2x00_rf_read(rt2x00dev, 3, &rf3);
422 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
423 rt2500pci_rf_write(rt2x00dev, 3, rf3);
426 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
427 struct antenna_setup *ant)
433 rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®);
434 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
435 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
438 * Configure the TX antenna.
441 case ANTENNA_SW_DIVERSITY:
442 case ANTENNA_HW_DIVERSITY:
443 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
444 rt2x00_set_field32(®, BBPCSR1_CCK, 2);
445 rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
448 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
449 rt2x00_set_field32(®, BBPCSR1_CCK, 0);
450 rt2x00_set_field32(®, BBPCSR1_OFDM, 0);
453 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
454 rt2x00_set_field32(®, BBPCSR1_CCK, 2);
455 rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
460 * Configure the RX antenna.
463 case ANTENNA_SW_DIVERSITY:
464 case ANTENNA_HW_DIVERSITY:
465 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
468 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
471 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
476 * RT2525E and RT5222 need to flip TX I/Q
478 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
479 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
480 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
481 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1);
482 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1);
485 * RT2525E does not need RX I/Q Flip.
487 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
488 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
490 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0);
491 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0);
494 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
495 rt2500pci_bbp_write(rt2x00dev, 14, r14);
496 rt2500pci_bbp_write(rt2x00dev, 2, r2);
499 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
500 struct rt2x00lib_conf *libconf)
504 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
505 rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
506 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
508 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
509 rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
510 rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
511 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
513 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
514 rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
515 rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
516 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
518 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
519 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
520 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
521 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
523 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
524 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
525 libconf->conf->beacon_int * 16);
526 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
527 libconf->conf->beacon_int * 16);
528 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
531 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
532 const unsigned int flags,
533 struct rt2x00lib_conf *libconf)
535 if (flags & CONFIG_UPDATE_PHYMODE)
536 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
537 if (flags & CONFIG_UPDATE_CHANNEL)
538 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
539 libconf->conf->power_level);
540 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
541 rt2500pci_config_txpower(rt2x00dev,
542 libconf->conf->power_level);
543 if (flags & CONFIG_UPDATE_ANTENNA)
544 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
545 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
546 rt2500pci_config_duration(rt2x00dev, libconf);
552 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
556 rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
558 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
559 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
561 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
562 rt2x00_set_field32(®, LEDCSR_LINK, 1);
563 rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
564 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
565 rt2x00_set_field32(®, LEDCSR_LINK, 0);
566 rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
568 rt2x00_set_field32(®, LEDCSR_LINK, 1);
569 rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
572 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
575 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
579 rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
580 rt2x00_set_field32(®, LEDCSR_LINK, 0);
581 rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
582 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
588 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
589 struct link_qual *qual)
594 * Update FCS error count from register.
596 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
597 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
600 * Update False CCA count from register.
602 rt2x00pci_register_read(rt2x00dev, CNT3, ®);
603 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
606 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
608 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
609 rt2x00dev->link.vgc_level = 0x48;
612 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
614 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
618 * To prevent collisions with MAC ASIC on chipsets
619 * up to version C the link tuning should halt after 20
622 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
623 rt2x00dev->link.count > 20)
626 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
629 * Chipset versions C and lower should directly continue
630 * to the dynamic CCA tuning.
632 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
633 goto dynamic_cca_tune;
636 * A too low RSSI will cause too much false CCA which will
637 * then corrupt the R17 tuning. To remidy this the tuning should
638 * be stopped (While making sure the R17 value will not exceed limits)
640 if (rssi < -80 && rt2x00dev->link.count > 20) {
642 r17 = rt2x00dev->link.vgc_level;
643 rt2500pci_bbp_write(rt2x00dev, 17, r17);
649 * Special big-R17 for short distance
653 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
658 * Special mid-R17 for middle distance
662 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
667 * Leave short or middle distance condition, restore r17
668 * to the dynamic tuning range.
671 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
678 * R17 is inside the dynamic tuning range,
679 * start tuning the link based on the false cca counter.
681 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
682 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
683 rt2x00dev->link.vgc_level = r17;
684 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
685 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
686 rt2x00dev->link.vgc_level = r17;
691 * Initialization functions.
693 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
695 struct data_ring *ring = rt2x00dev->rx;
696 struct data_desc *rxd;
700 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
702 for (i = 0; i < ring->stats.limit; i++) {
703 rxd = ring->entry[i].priv;
705 rt2x00_desc_read(rxd, 1, &word);
706 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
707 ring->entry[i].data_dma);
708 rt2x00_desc_write(rxd, 1, word);
710 rt2x00_desc_read(rxd, 0, &word);
711 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
712 rt2x00_desc_write(rxd, 0, word);
715 rt2x00_ring_index_clear(rt2x00dev->rx);
718 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
720 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
721 struct data_desc *txd;
725 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
727 for (i = 0; i < ring->stats.limit; i++) {
728 txd = ring->entry[i].priv;
730 rt2x00_desc_read(txd, 1, &word);
731 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
732 ring->entry[i].data_dma);
733 rt2x00_desc_write(txd, 1, word);
735 rt2x00_desc_read(txd, 0, &word);
736 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
737 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
738 rt2x00_desc_write(txd, 0, word);
741 rt2x00_ring_index_clear(ring);
744 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
751 rt2500pci_init_rxring(rt2x00dev);
752 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
753 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
754 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
755 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
758 * Initialize registers.
760 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
761 rt2x00_set_field32(®, TXCSR2_TXD_SIZE,
762 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
763 rt2x00_set_field32(®, TXCSR2_NUM_TXD,
764 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
765 rt2x00_set_field32(®, TXCSR2_NUM_ATIM,
766 rt2x00dev->bcn[1].stats.limit);
767 rt2x00_set_field32(®, TXCSR2_NUM_PRIO,
768 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
769 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
771 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
772 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
773 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
774 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
776 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
777 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
778 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
779 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
781 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
782 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
783 rt2x00dev->bcn[1].data_dma);
784 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
786 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
787 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
788 rt2x00dev->bcn[0].data_dma);
789 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
791 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
792 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
793 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
794 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
796 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
797 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
798 rt2x00dev->rx->data_dma);
799 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
804 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
808 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
809 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
810 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
813 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
814 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
815 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
816 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
817 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
819 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
820 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
821 rt2x00dev->rx->data_size / 128);
822 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
825 * Always use CWmin and CWmax set in descriptor.
827 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
828 rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
829 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
831 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
833 rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
834 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
835 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
836 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
837 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1);
838 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13);
839 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
840 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
841 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
842 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
844 rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
845 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
846 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
847 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
848 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
849 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
851 rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
852 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
853 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
854 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
855 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
856 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
858 rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
859 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
860 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
861 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
862 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
863 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
865 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
866 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
867 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
868 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
869 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
870 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
871 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
872 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
873 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
874 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
876 rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
877 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
878 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
879 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
880 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
881 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
882 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
883 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
884 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
886 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
888 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
889 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
891 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
894 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
895 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
897 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
898 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
899 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
901 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
902 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
903 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
904 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1);
905 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
906 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26);
907 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1);
908 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
910 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
912 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
914 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
915 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
916 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
917 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
918 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
920 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
921 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
922 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
923 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
926 * We must clear the FCS and FIFO error count.
927 * These registers are cleared on read,
928 * so we may pass a useless variable to store the value.
930 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
931 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
936 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
943 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
944 rt2500pci_bbp_read(rt2x00dev, 0, &value);
945 if ((value != 0xff) && (value != 0x00))
946 goto continue_csr_init;
947 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
948 udelay(REGISTER_BUSY_DELAY);
951 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
955 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
956 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
957 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
958 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
959 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
960 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
961 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
962 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
963 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
964 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
965 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
966 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
967 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
968 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
969 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
970 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
971 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
972 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
973 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
974 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
975 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
976 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
977 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
978 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
979 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
980 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
981 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
982 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
983 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
984 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
986 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
987 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
988 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
990 if (eeprom != 0xffff && eeprom != 0x0000) {
991 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
992 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
993 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
995 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
998 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1004 * Device state switch handlers.
1006 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1007 enum dev_state state)
1011 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1012 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
1013 state == STATE_RADIO_RX_OFF);
1014 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1017 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1018 enum dev_state state)
1020 int mask = (state == STATE_RADIO_IRQ_OFF);
1024 * When interrupts are being enabled, the interrupt registers
1025 * should clear the register to assure a clean state.
1027 if (state == STATE_RADIO_IRQ_ON) {
1028 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1029 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1033 * Only toggle the interrupts bits we are going to use.
1034 * Non-checked interrupt bits are disabled by default.
1036 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1037 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
1038 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
1039 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
1040 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
1041 rt2x00_set_field32(®, CSR8_RXDONE, mask);
1042 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1045 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1048 * Initialize all registers.
1050 if (rt2500pci_init_rings(rt2x00dev) ||
1051 rt2500pci_init_registers(rt2x00dev) ||
1052 rt2500pci_init_bbp(rt2x00dev)) {
1053 ERROR(rt2x00dev, "Register initialization failed.\n");
1058 * Enable interrupts.
1060 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1065 rt2500pci_enable_led(rt2x00dev);
1070 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1077 rt2500pci_disable_led(rt2x00dev);
1079 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1082 * Disable synchronisation.
1084 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1089 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1090 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
1091 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1094 * Disable interrupts.
1096 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1099 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1100 enum dev_state state)
1108 put_to_sleep = (state != STATE_AWAKE);
1110 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1111 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1112 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1113 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1114 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1115 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1118 * Device is not guaranteed to be in the requested state yet.
1119 * We must wait until the register indicates that the
1120 * device has entered the correct state.
1122 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1123 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1124 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1125 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1126 if (bbp_state == state && rf_state == state)
1131 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1132 "current device state: bbp %d and rf %d.\n",
1133 state, bbp_state, rf_state);
1138 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1139 enum dev_state state)
1144 case STATE_RADIO_ON:
1145 retval = rt2500pci_enable_radio(rt2x00dev);
1147 case STATE_RADIO_OFF:
1148 rt2500pci_disable_radio(rt2x00dev);
1150 case STATE_RADIO_RX_ON:
1151 case STATE_RADIO_RX_OFF:
1152 rt2500pci_toggle_rx(rt2x00dev, state);
1154 case STATE_DEEP_SLEEP:
1158 retval = rt2500pci_set_state(rt2x00dev, state);
1169 * TX descriptor initialization
1171 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1172 struct data_desc *txd,
1173 struct txdata_entry_desc *desc,
1174 struct ieee80211_hdr *ieee80211hdr,
1175 unsigned int length,
1176 struct ieee80211_tx_control *control)
1181 * Start writing the descriptor words.
1183 rt2x00_desc_read(txd, 2, &word);
1184 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1185 rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1186 rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1187 rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1188 rt2x00_desc_write(txd, 2, word);
1190 rt2x00_desc_read(txd, 3, &word);
1191 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1192 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1193 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1194 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1195 rt2x00_desc_write(txd, 3, word);
1197 rt2x00_desc_read(txd, 10, &word);
1198 rt2x00_set_field32(&word, TXD_W10_RTS,
1199 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1200 rt2x00_desc_write(txd, 10, word);
1202 rt2x00_desc_read(txd, 0, &word);
1203 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1204 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1205 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1206 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1207 rt2x00_set_field32(&word, TXD_W0_ACK,
1208 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1209 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1210 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1211 rt2x00_set_field32(&word, TXD_W0_OFDM,
1212 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1213 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1214 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1215 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1217 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1218 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1219 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1220 rt2x00_desc_write(txd, 0, word);
1224 * TX data initialization
1226 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1231 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1232 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1233 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1234 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1235 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1240 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1241 if (queue == IEEE80211_TX_QUEUE_DATA0)
1242 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
1243 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1244 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
1245 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1246 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
1247 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1251 * RX control handlers
1253 static void rt2500pci_fill_rxdone(struct data_entry *entry,
1254 struct rxdata_entry_desc *desc)
1256 struct data_desc *rxd = entry->priv;
1260 rt2x00_desc_read(rxd, 0, &word0);
1261 rt2x00_desc_read(rxd, 2, &word2);
1264 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1265 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1266 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1267 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1269 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1270 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1271 entry->ring->rt2x00dev->rssi_offset;
1272 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1273 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1277 * Interrupt functions.
1279 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1281 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1282 struct data_entry *entry;
1283 struct data_desc *txd;
1288 while (!rt2x00_ring_empty(ring)) {
1289 entry = rt2x00_get_data_entry_done(ring);
1291 rt2x00_desc_read(txd, 0, &word);
1293 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1294 !rt2x00_get_field32(word, TXD_W0_VALID))
1298 * Obtain the status about this packet.
1300 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1301 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1303 rt2x00lib_txdone(entry, tx_status, retry);
1306 * Make this entry available for reuse.
1309 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1310 rt2x00_desc_write(txd, 0, word);
1311 rt2x00_ring_index_done_inc(ring);
1315 * If the data ring was full before the txdone handler
1316 * we must make sure the packet queue in the mac80211 stack
1317 * is reenabled when the txdone handler has finished.
1319 entry = ring->entry;
1320 if (!rt2x00_ring_full(ring))
1321 ieee80211_wake_queue(rt2x00dev->hw,
1322 entry->tx_status.control.queue);
1325 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1327 struct rt2x00_dev *rt2x00dev = dev_instance;
1331 * Get the interrupt sources & saved to local variable.
1332 * Write register value back to clear pending interrupts.
1334 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1335 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1340 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1344 * Handle interrupts, walk through all bits
1345 * and run the tasks, the bits are checked in order of
1350 * 1 - Beacon timer expired interrupt.
1352 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1353 rt2x00lib_beacondone(rt2x00dev);
1356 * 2 - Rx ring done interrupt.
1358 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1359 rt2x00pci_rxdone(rt2x00dev);
1362 * 3 - Atim ring transmit done interrupt.
1364 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1365 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1368 * 4 - Priority ring transmit done interrupt.
1370 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1371 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1374 * 5 - Tx ring transmit done interrupt.
1376 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1377 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1383 * Device probe functions.
1385 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1387 struct eeprom_93cx6 eeprom;
1392 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1394 eeprom.data = rt2x00dev;
1395 eeprom.register_read = rt2500pci_eepromregister_read;
1396 eeprom.register_write = rt2500pci_eepromregister_write;
1397 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1398 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1399 eeprom.reg_data_in = 0;
1400 eeprom.reg_data_out = 0;
1401 eeprom.reg_data_clock = 0;
1402 eeprom.reg_chip_select = 0;
1404 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1405 EEPROM_SIZE / sizeof(u16));
1408 * Start validation of the data that has been read.
1410 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1411 if (!is_valid_ether_addr(mac)) {
1412 DECLARE_MAC_BUF(macbuf);
1414 random_ether_addr(mac);
1415 EEPROM(rt2x00dev, "MAC: %s\n",
1416 print_mac(macbuf, mac));
1419 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1420 if (word == 0xffff) {
1421 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1422 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1423 ANTENNA_SW_DIVERSITY);
1424 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1425 ANTENNA_SW_DIVERSITY);
1426 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1428 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1429 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1430 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1431 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1432 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1435 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1436 if (word == 0xffff) {
1437 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1438 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1439 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1440 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1441 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1444 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1445 if (word == 0xffff) {
1446 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1447 DEFAULT_RSSI_OFFSET);
1448 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1449 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1455 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1462 * Read EEPROM word for configuration.
1464 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1467 * Identify RF chipset.
1469 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1470 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1471 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1473 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1474 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1475 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1476 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1477 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1478 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1479 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1484 * Identify default antenna configuration.
1486 rt2x00dev->default_ant.tx =
1487 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1488 rt2x00dev->default_ant.rx =
1489 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1492 * Store led mode, for correct led behaviour.
1494 rt2x00dev->led_mode =
1495 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1498 * Detect if this device has an hardware controlled radio.
1500 #ifdef CONFIG_RT2500PCI_RFKILL
1501 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1502 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1503 #endif /* CONFIG_RT2500PCI_RFKILL */
1506 * Check if the BBP tuning should be enabled.
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1510 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1511 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1514 * Read the RSSI <-> dBm offset information.
1516 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1517 rt2x00dev->rssi_offset =
1518 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1524 * RF value list for RF2522
1527 static const struct rf_channel rf_vals_bg_2522[] = {
1528 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1529 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1530 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1531 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1532 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1533 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1534 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1535 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1536 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1537 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1538 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1539 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1540 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1541 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1545 * RF value list for RF2523
1548 static const struct rf_channel rf_vals_bg_2523[] = {
1549 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1550 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1551 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1552 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1553 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1554 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1555 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1556 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1557 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1558 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1559 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1560 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1561 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1562 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1566 * RF value list for RF2524
1569 static const struct rf_channel rf_vals_bg_2524[] = {
1570 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1571 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1572 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1573 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1574 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1575 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1576 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1577 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1578 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1579 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1580 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1581 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1582 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1583 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1587 * RF value list for RF2525
1590 static const struct rf_channel rf_vals_bg_2525[] = {
1591 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1592 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1593 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1594 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1595 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1596 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1597 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1598 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1599 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1600 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1601 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1602 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1603 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1604 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1608 * RF value list for RF2525e
1611 static const struct rf_channel rf_vals_bg_2525e[] = {
1612 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1613 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1614 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1615 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1616 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1617 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1618 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1619 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1620 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1621 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1622 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1623 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1624 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1625 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1629 * RF value list for RF5222
1630 * Supports: 2.4 GHz & 5.2 GHz
1632 static const struct rf_channel rf_vals_5222[] = {
1633 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1634 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1635 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1636 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1637 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1638 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1639 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1640 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1641 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1642 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1643 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1644 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1645 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1646 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1648 /* 802.11 UNI / HyperLan 2 */
1649 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1650 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1651 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1652 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1653 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1654 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1655 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1656 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1658 /* 802.11 HyperLan 2 */
1659 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1660 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1661 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1662 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1663 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1664 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1665 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1666 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1667 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1668 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1671 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1672 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1673 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1674 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1675 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1678 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1680 struct hw_mode_spec *spec = &rt2x00dev->spec;
1685 * Initialize all hw fields.
1687 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1688 rt2x00dev->hw->extra_tx_headroom = 0;
1689 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1690 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1691 rt2x00dev->hw->queues = 2;
1693 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1694 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1695 rt2x00_eeprom_addr(rt2x00dev,
1696 EEPROM_MAC_ADDR_0));
1699 * Convert tx_power array in eeprom.
1701 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1702 for (i = 0; i < 14; i++)
1703 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1706 * Initialize hw_mode information.
1708 spec->num_modes = 2;
1709 spec->num_rates = 12;
1710 spec->tx_power_a = NULL;
1711 spec->tx_power_bg = txpower;
1712 spec->tx_power_default = DEFAULT_TXPOWER;
1714 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1715 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1716 spec->channels = rf_vals_bg_2522;
1717 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1718 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1719 spec->channels = rf_vals_bg_2523;
1720 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1721 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1722 spec->channels = rf_vals_bg_2524;
1723 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1724 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1725 spec->channels = rf_vals_bg_2525;
1726 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1727 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1728 spec->channels = rf_vals_bg_2525e;
1729 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1730 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1731 spec->channels = rf_vals_5222;
1732 spec->num_modes = 3;
1736 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1741 * Allocate eeprom data.
1743 retval = rt2500pci_validate_eeprom(rt2x00dev);
1747 retval = rt2500pci_init_eeprom(rt2x00dev);
1752 * Initialize hw specifications.
1754 rt2500pci_probe_hw_mode(rt2x00dev);
1757 * This device requires the beacon ring
1759 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1762 * Set the rssi offset.
1764 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1770 * IEEE80211 stack callback functions.
1772 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1773 unsigned int changed_flags,
1774 unsigned int *total_flags,
1776 struct dev_addr_list *mc_list)
1778 struct rt2x00_dev *rt2x00dev = hw->priv;
1779 struct interface *intf = &rt2x00dev->interface;
1783 * Mask off any flags we are going to ignore from
1784 * the total_flags field.
1795 * Apply some rules to the filters:
1796 * - Some filters imply different filters to be set.
1797 * - Some things we can't filter out at all.
1798 * - Some filters are set based on interface type.
1801 *total_flags |= FIF_ALLMULTI;
1802 if (*total_flags & FIF_OTHER_BSS ||
1803 *total_flags & FIF_PROMISC_IN_BSS)
1804 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1805 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1806 *total_flags |= FIF_PROMISC_IN_BSS;
1809 * Check if there is any work left for us.
1811 if (intf->filter == *total_flags)
1813 intf->filter = *total_flags;
1816 * Start configuration steps.
1817 * Note that the version error will always be dropped
1818 * and broadcast frames will always be accepted since
1819 * there is no filter for it at this time.
1821 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1822 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
1823 !(*total_flags & FIF_FCSFAIL));
1824 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
1825 !(*total_flags & FIF_PLCPFAIL));
1826 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
1827 !(*total_flags & FIF_CONTROL));
1828 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
1829 !(*total_flags & FIF_PROMISC_IN_BSS));
1830 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
1831 !(*total_flags & FIF_PROMISC_IN_BSS));
1832 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
1833 rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
1834 !(*total_flags & FIF_ALLMULTI));
1835 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
1836 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1839 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1840 u32 short_retry, u32 long_retry)
1842 struct rt2x00_dev *rt2x00dev = hw->priv;
1845 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
1846 rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
1847 rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
1848 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1853 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1855 struct rt2x00_dev *rt2x00dev = hw->priv;
1859 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1860 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1861 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1862 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1867 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1869 struct rt2x00_dev *rt2x00dev = hw->priv;
1871 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1872 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1875 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1877 struct rt2x00_dev *rt2x00dev = hw->priv;
1880 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1881 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1884 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1886 .start = rt2x00mac_start,
1887 .stop = rt2x00mac_stop,
1888 .add_interface = rt2x00mac_add_interface,
1889 .remove_interface = rt2x00mac_remove_interface,
1890 .config = rt2x00mac_config,
1891 .config_interface = rt2x00mac_config_interface,
1892 .configure_filter = rt2500pci_configure_filter,
1893 .get_stats = rt2x00mac_get_stats,
1894 .set_retry_limit = rt2500pci_set_retry_limit,
1895 .erp_ie_changed = rt2x00mac_erp_ie_changed,
1896 .conf_tx = rt2x00mac_conf_tx,
1897 .get_tx_stats = rt2x00mac_get_tx_stats,
1898 .get_tsf = rt2500pci_get_tsf,
1899 .reset_tsf = rt2500pci_reset_tsf,
1900 .beacon_update = rt2x00pci_beacon_update,
1901 .tx_last_beacon = rt2500pci_tx_last_beacon,
1904 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1905 .irq_handler = rt2500pci_interrupt,
1906 .probe_hw = rt2500pci_probe_hw,
1907 .initialize = rt2x00pci_initialize,
1908 .uninitialize = rt2x00pci_uninitialize,
1909 .set_device_state = rt2500pci_set_device_state,
1910 .rfkill_poll = rt2500pci_rfkill_poll,
1911 .link_stats = rt2500pci_link_stats,
1912 .reset_tuner = rt2500pci_reset_tuner,
1913 .link_tuner = rt2500pci_link_tuner,
1914 .write_tx_desc = rt2500pci_write_tx_desc,
1915 .write_tx_data = rt2x00pci_write_tx_data,
1916 .kick_tx_queue = rt2500pci_kick_tx_queue,
1917 .fill_rxdone = rt2500pci_fill_rxdone,
1918 .config_mac_addr = rt2500pci_config_mac_addr,
1919 .config_bssid = rt2500pci_config_bssid,
1920 .config_type = rt2500pci_config_type,
1921 .config_preamble = rt2500pci_config_preamble,
1922 .config = rt2500pci_config,
1925 static const struct rt2x00_ops rt2500pci_ops = {
1927 .rxd_size = RXD_DESC_SIZE,
1928 .txd_size = TXD_DESC_SIZE,
1929 .eeprom_size = EEPROM_SIZE,
1931 .lib = &rt2500pci_rt2x00_ops,
1932 .hw = &rt2500pci_mac80211_ops,
1933 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1934 .debugfs = &rt2500pci_rt2x00debug,
1935 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1939 * RT2500pci module information.
1941 static struct pci_device_id rt2500pci_device_table[] = {
1942 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1946 MODULE_AUTHOR(DRV_PROJECT);
1947 MODULE_VERSION(DRV_VERSION);
1948 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1949 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1950 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1951 MODULE_LICENSE("GPL");
1953 static struct pci_driver rt2500pci_driver = {
1955 .id_table = rt2500pci_device_table,
1956 .probe = rt2x00pci_probe,
1957 .remove = __devexit_p(rt2x00pci_remove),
1958 .suspend = rt2x00pci_suspend,
1959 .resume = rt2x00pci_resume,
1962 static int __init rt2500pci_init(void)
1964 return pci_register_driver(&rt2500pci_driver);
1967 static void __exit rt2500pci_exit(void)
1969 pci_unregister_driver(&rt2500pci_driver);
1972 module_init(rt2500pci_init);
1973 module_exit(rt2500pci_exit);