Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/hpa/linux...
[linux-2.6] / drivers / video / ffb.c
1 /* ffb.c: Creator/Elite3D frame buffer driver
2  *
3  * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
4  * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
5  *
6  * Driver layout based loosely on tgafb.c, see that file for credits.
7  */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <linux/string.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/fb.h>
17 #include <linux/mm.h>
18 #include <linux/timer.h>
19
20 #include <asm/io.h>
21 #include <asm/upa.h>
22 #include <asm/prom.h>
23 #include <asm/of_device.h>
24 #include <asm/fbio.h>
25
26 #include "sbuslib.h"
27
28 /*
29  * Local functions.
30  */
31
32 static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
33                          unsigned, struct fb_info *);
34 static int ffb_blank(int, struct fb_info *);
35 static void ffb_init_fix(struct fb_info *);
36
37 static void ffb_imageblit(struct fb_info *, const struct fb_image *);
38 static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
39 static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
40 static int ffb_sync(struct fb_info *);
41 static int ffb_mmap(struct fb_info *, struct vm_area_struct *);
42 static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long);
43 static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
44
45 /*
46  *  Frame buffer operations
47  */
48
49 static struct fb_ops ffb_ops = {
50         .owner                  = THIS_MODULE,
51         .fb_setcolreg           = ffb_setcolreg,
52         .fb_blank               = ffb_blank,
53         .fb_pan_display         = ffb_pan_display,
54         .fb_fillrect            = ffb_fillrect,
55         .fb_copyarea            = ffb_copyarea,
56         .fb_imageblit           = ffb_imageblit,
57         .fb_sync                = ffb_sync,
58         .fb_mmap                = ffb_mmap,
59         .fb_ioctl               = ffb_ioctl,
60 #ifdef CONFIG_COMPAT
61         .fb_compat_ioctl        = sbusfb_compat_ioctl,
62 #endif
63 };
64
65 /* Register layout and definitions */
66 #define FFB_SFB8R_VOFF          0x00000000
67 #define FFB_SFB8G_VOFF          0x00400000
68 #define FFB_SFB8B_VOFF          0x00800000
69 #define FFB_SFB8X_VOFF          0x00c00000
70 #define FFB_SFB32_VOFF          0x01000000
71 #define FFB_SFB64_VOFF          0x02000000
72 #define FFB_FBC_REGS_VOFF       0x04000000
73 #define FFB_BM_FBC_REGS_VOFF    0x04002000
74 #define FFB_DFB8R_VOFF          0x04004000
75 #define FFB_DFB8G_VOFF          0x04404000
76 #define FFB_DFB8B_VOFF          0x04804000
77 #define FFB_DFB8X_VOFF          0x04c04000
78 #define FFB_DFB24_VOFF          0x05004000
79 #define FFB_DFB32_VOFF          0x06004000
80 #define FFB_DFB422A_VOFF        0x07004000      /* DFB 422 mode write to A */
81 #define FFB_DFB422AD_VOFF       0x07804000      /* DFB 422 mode with line doubling */
82 #define FFB_DFB24B_VOFF         0x08004000      /* DFB 24bit mode write to B */
83 #define FFB_DFB422B_VOFF        0x09004000      /* DFB 422 mode write to B */
84 #define FFB_DFB422BD_VOFF       0x09804000      /* DFB 422 mode with line doubling */
85 #define FFB_SFB16Z_VOFF         0x0a004000      /* 16bit mode Z planes */
86 #define FFB_SFB8Z_VOFF          0x0a404000      /* 8bit mode Z planes */
87 #define FFB_SFB422_VOFF         0x0ac04000      /* SFB 422 mode write to A/B */
88 #define FFB_SFB422D_VOFF        0x0b404000      /* SFB 422 mode with line doubling */
89 #define FFB_FBC_KREGS_VOFF      0x0bc04000
90 #define FFB_DAC_VOFF            0x0bc06000
91 #define FFB_PROM_VOFF           0x0bc08000
92 #define FFB_EXP_VOFF            0x0bc18000
93
94 #define FFB_SFB8R_POFF          0x04000000UL
95 #define FFB_SFB8G_POFF          0x04400000UL
96 #define FFB_SFB8B_POFF          0x04800000UL
97 #define FFB_SFB8X_POFF          0x04c00000UL
98 #define FFB_SFB32_POFF          0x05000000UL
99 #define FFB_SFB64_POFF          0x06000000UL
100 #define FFB_FBC_REGS_POFF       0x00600000UL
101 #define FFB_BM_FBC_REGS_POFF    0x00600000UL
102 #define FFB_DFB8R_POFF          0x01000000UL
103 #define FFB_DFB8G_POFF          0x01400000UL
104 #define FFB_DFB8B_POFF          0x01800000UL
105 #define FFB_DFB8X_POFF          0x01c00000UL
106 #define FFB_DFB24_POFF          0x02000000UL
107 #define FFB_DFB32_POFF          0x03000000UL
108 #define FFB_FBC_KREGS_POFF      0x00610000UL
109 #define FFB_DAC_POFF            0x00400000UL
110 #define FFB_PROM_POFF           0x00000000UL
111 #define FFB_EXP_POFF            0x00200000UL
112 #define FFB_DFB422A_POFF        0x09000000UL
113 #define FFB_DFB422AD_POFF       0x09800000UL
114 #define FFB_DFB24B_POFF         0x0a000000UL
115 #define FFB_DFB422B_POFF        0x0b000000UL
116 #define FFB_DFB422BD_POFF       0x0b800000UL
117 #define FFB_SFB16Z_POFF         0x0c800000UL
118 #define FFB_SFB8Z_POFF          0x0c000000UL
119 #define FFB_SFB422_POFF         0x0d000000UL
120 #define FFB_SFB422D_POFF        0x0d800000UL
121
122 /* Draw operations */
123 #define FFB_DRAWOP_DOT          0x00
124 #define FFB_DRAWOP_AADOT        0x01
125 #define FFB_DRAWOP_BRLINECAP    0x02
126 #define FFB_DRAWOP_BRLINEOPEN   0x03
127 #define FFB_DRAWOP_DDLINE       0x04
128 #define FFB_DRAWOP_AALINE       0x05
129 #define FFB_DRAWOP_TRIANGLE     0x06
130 #define FFB_DRAWOP_POLYGON      0x07
131 #define FFB_DRAWOP_RECTANGLE    0x08
132 #define FFB_DRAWOP_FASTFILL     0x09
133 #define FFB_DRAWOP_BCOPY        0x0a
134 #define FFB_DRAWOP_VSCROLL      0x0b
135
136 /* Pixel processor control */
137 /* Force WID */
138 #define FFB_PPC_FW_DISABLE      0x800000
139 #define FFB_PPC_FW_ENABLE       0xc00000
140 /* Auxiliary clip */
141 #define FFB_PPC_ACE_DISABLE     0x040000
142 #define FFB_PPC_ACE_AUX_SUB     0x080000
143 #define FFB_PPC_ACE_AUX_ADD     0x0c0000
144 /* Depth cue */
145 #define FFB_PPC_DCE_DISABLE     0x020000
146 #define FFB_PPC_DCE_ENABLE      0x030000
147 /* Alpha blend */
148 #define FFB_PPC_ABE_DISABLE     0x008000
149 #define FFB_PPC_ABE_ENABLE      0x00c000
150 /* View clip */
151 #define FFB_PPC_VCE_DISABLE     0x001000
152 #define FFB_PPC_VCE_2D          0x002000
153 #define FFB_PPC_VCE_3D          0x003000
154 /* Area pattern */
155 #define FFB_PPC_APE_DISABLE     0x000800
156 #define FFB_PPC_APE_ENABLE      0x000c00
157 /* Transparent background */
158 #define FFB_PPC_TBE_OPAQUE      0x000200
159 #define FFB_PPC_TBE_TRANSPARENT 0x000300
160 /* Z source */
161 #define FFB_PPC_ZS_VAR          0x000080
162 #define FFB_PPC_ZS_CONST        0x0000c0
163 /* Y source */
164 #define FFB_PPC_YS_VAR          0x000020
165 #define FFB_PPC_YS_CONST        0x000030
166 /* X source */
167 #define FFB_PPC_XS_WID          0x000004
168 #define FFB_PPC_XS_VAR          0x000008
169 #define FFB_PPC_XS_CONST        0x00000c
170 /* Color (BGR) source */
171 #define FFB_PPC_CS_VAR          0x000002
172 #define FFB_PPC_CS_CONST        0x000003
173
174 #define FFB_ROP_NEW                  0x83
175 #define FFB_ROP_OLD                  0x85
176 #define FFB_ROP_NEW_XOR_OLD          0x86
177
178 #define FFB_UCSR_FIFO_MASK     0x00000fff
179 #define FFB_UCSR_FB_BUSY       0x01000000
180 #define FFB_UCSR_RP_BUSY       0x02000000
181 #define FFB_UCSR_ALL_BUSY      (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
182 #define FFB_UCSR_READ_ERR      0x40000000
183 #define FFB_UCSR_FIFO_OVFL     0x80000000
184 #define FFB_UCSR_ALL_ERRORS    (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
185
186 struct ffb_fbc {
187         /* Next vertex registers */
188         u32     xxx1[3];
189         u32     alpha;
190         u32     red;
191         u32     green;
192         u32     blue;
193         u32     depth;
194         u32     y;
195         u32     x;
196         u32     xxx2[2];
197         u32     ryf;
198         u32     rxf;
199         u32     xxx3[2];
200         
201         u32     dmyf;
202         u32     dmxf;
203         u32     xxx4[2];
204         u32     ebyi;
205         u32     ebxi;
206         u32     xxx5[2];
207         u32     by;
208         u32     bx;
209         u32     dy;
210         u32     dx;
211         u32     bh;
212         u32     bw;
213         u32     xxx6[2];
214         
215         u32     xxx7[32];
216         
217         /* Setup unit vertex state register */
218         u32     suvtx;
219         u32     xxx8[63];
220         
221         /* Control registers */
222         u32     ppc;
223         u32     wid;
224         u32     fg;
225         u32     bg;
226         u32     consty;
227         u32     constz;
228         u32     xclip;
229         u32     dcss;
230         u32     vclipmin;
231         u32     vclipmax;
232         u32     vclipzmin;
233         u32     vclipzmax;
234         u32     dcsf;
235         u32     dcsb;
236         u32     dczf;
237         u32     dczb;
238         
239         u32     xxx9;
240         u32     blendc;
241         u32     blendc1;
242         u32     blendc2;
243         u32     fbramitc;
244         u32     fbc;
245         u32     rop;
246         u32     cmp;
247         u32     matchab;
248         u32     matchc;
249         u32     magnab;
250         u32     magnc;
251         u32     fbcfg0;
252         u32     fbcfg1;
253         u32     fbcfg2;
254         u32     fbcfg3;
255         
256         u32     ppcfg;
257         u32     pick;
258         u32     fillmode;
259         u32     fbramwac;
260         u32     pmask;
261         u32     xpmask;
262         u32     ypmask;
263         u32     zpmask;
264         u32     clip0min;
265         u32     clip0max;
266         u32     clip1min;
267         u32     clip1max;
268         u32     clip2min;
269         u32     clip2max;
270         u32     clip3min;
271         u32     clip3max;
272         
273         /* New 3dRAM III support regs */
274         u32     rawblend2;
275         u32     rawpreblend;
276         u32     rawstencil;
277         u32     rawstencilctl;
278         u32     threedram1;
279         u32     threedram2;
280         u32     passin;
281         u32     rawclrdepth;
282         u32     rawpmask;
283         u32     rawcsrc;
284         u32     rawmatch;
285         u32     rawmagn;
286         u32     rawropblend;
287         u32     rawcmp;
288         u32     rawwac;
289         u32     fbramid;
290         
291         u32     drawop;
292         u32     xxx10[2];
293         u32     fontlpat;
294         u32     xxx11;
295         u32     fontxy;
296         u32     fontw;
297         u32     fontinc;
298         u32     font;
299         u32     xxx12[3];
300         u32     blend2;
301         u32     preblend;
302         u32     stencil;
303         u32     stencilctl;
304
305         u32     xxx13[4];       
306         u32     dcss1;
307         u32     dcss2;
308         u32     dcss3;
309         u32     widpmask;
310         u32     dcs2;
311         u32     dcs3;
312         u32     dcs4;
313         u32     xxx14;
314         u32     dcd2;
315         u32     dcd3;
316         u32     dcd4;
317         u32     xxx15;
318         
319         u32     pattern[32];
320         
321         u32     xxx16[256];
322         
323         u32     devid;
324         u32     xxx17[63];
325         
326         u32     ucsr;
327         u32     xxx18[31];
328         
329         u32     mer;
330 };
331
332 struct ffb_dac {
333         u32     type;
334         u32     value;
335         u32     type2;
336         u32     value2;
337 };
338
339 #define FFB_DAC_UCTRL   0x1001 /* User Control */
340 #define  FFB_DAC_UCTRL_MANREV   0x00000f00 /* 4-bit Manufacturing Revision */
341 #define  FFB_DAC_UCTRL_MANREV_SHIFT 8
342 #define FFB_DAC_TGEN    0x6000 /* Timing Generator */
343 #define  FFB_DAC_TGEN_VIDE      0x00000001 /* Video Enable */
344 #define FFB_DAC_DID     0x8000 /* Device Identification */
345 #define  FFB_DAC_DID_PNUM       0x0ffff000 /* Device Part Number */
346 #define  FFB_DAC_DID_PNUM_SHIFT 12
347 #define  FFB_DAC_DID_REV        0xf0000000 /* Device Revision */
348 #define  FFB_DAC_DID_REV_SHIFT 28
349
350 #define FFB_DAC_CUR_CTRL        0x100
351 #define  FFB_DAC_CUR_CTRL_P0    0x00000001
352 #define  FFB_DAC_CUR_CTRL_P1    0x00000002
353
354 struct ffb_par {
355         spinlock_t              lock;
356         struct ffb_fbc __iomem  *fbc;
357         struct ffb_dac __iomem  *dac;
358
359         u32                     flags;
360 #define FFB_FLAG_AFB            0x00000001 /* AFB m3 or m6 */
361 #define FFB_FLAG_BLANKED        0x00000002 /* screen is blanked */
362 #define FFB_FLAG_INVCURSOR      0x00000004 /* DAC has inverted cursor logic */
363
364         u32                     fg_cache __attribute__((aligned (8)));
365         u32                     bg_cache;
366         u32                     rop_cache;
367
368         int                     fifo_cache;
369
370         unsigned long           physbase;
371         unsigned long           fbsize;
372
373         int                     board_type;
374
375         u32                     pseudo_palette[16];
376 };
377
378 static void FFBFifo(struct ffb_par *par, int n)
379 {
380         struct ffb_fbc __iomem *fbc;
381         int cache = par->fifo_cache;
382
383         if (cache - n < 0) {
384                 fbc = par->fbc;
385                 do {    cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8;
386                 } while (cache - n < 0);
387         }
388         par->fifo_cache = cache - n;
389 }
390
391 static void FFBWait(struct ffb_par *par)
392 {
393         struct ffb_fbc __iomem *fbc;
394         int limit = 10000;
395
396         fbc = par->fbc;
397         do {
398                 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
399                         break;
400                 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
401                         upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
402                 }
403                 udelay(10);
404         } while(--limit > 0);
405 }
406
407 static int ffb_sync(struct fb_info *p)
408 {
409         struct ffb_par *par = (struct ffb_par *) p->par;
410
411         FFBWait(par);
412         return 0;
413 }
414
415 static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
416 {
417         if (par->rop_cache != rop) {
418                 FFBFifo(par, 1);
419                 upa_writel(rop, &par->fbc->rop);
420                 par->rop_cache = rop;
421         }
422 }
423
424 static void ffb_switch_from_graph(struct ffb_par *par)
425 {
426         struct ffb_fbc __iomem *fbc = par->fbc;
427         struct ffb_dac __iomem *dac = par->dac;
428         unsigned long flags;
429
430         spin_lock_irqsave(&par->lock, flags);
431         FFBWait(par);
432         par->fifo_cache = 0;
433         FFBFifo(par, 7);
434         upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE|
435                    FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST,
436                    &fbc->ppc);
437         upa_writel(0x2000707f, &fbc->fbc);
438         upa_writel(par->rop_cache, &fbc->rop);
439         upa_writel(0xffffffff, &fbc->pmask);
440         upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
441         upa_writel(par->fg_cache, &fbc->fg);
442         upa_writel(par->bg_cache, &fbc->bg);
443         FFBWait(par);
444
445         /* Disable cursor.  */
446         upa_writel(FFB_DAC_CUR_CTRL, &dac->type2);
447         if (par->flags & FFB_FLAG_INVCURSOR)
448                 upa_writel(0, &dac->value2);
449         else
450                 upa_writel((FFB_DAC_CUR_CTRL_P0 |
451                             FFB_DAC_CUR_CTRL_P1), &dac->value2);
452
453         spin_unlock_irqrestore(&par->lock, flags);
454 }
455
456 static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
457 {
458         struct ffb_par *par = (struct ffb_par *) info->par;
459
460         /* We just use this to catch switches out of
461          * graphics mode.
462          */
463         ffb_switch_from_graph(par);
464
465         if (var->xoffset || var->yoffset || var->vmode)
466                 return -EINVAL;
467         return 0;
468 }
469
470 /**
471  *      ffb_fillrect - REQUIRED function. Can use generic routines if 
472  *                     non acclerated hardware and packed pixel based.
473  *                     Draws a rectangle on the screen.               
474  *
475  *      @info: frame buffer structure that represents a single frame buffer
476  *      @rect: structure defining the rectagle and operation.
477  */
478 static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
479 {
480         struct ffb_par *par = (struct ffb_par *) info->par;
481         struct ffb_fbc __iomem *fbc = par->fbc;
482         unsigned long flags;
483         u32 fg;
484
485         BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR);
486
487         fg = ((u32 *)info->pseudo_palette)[rect->color];
488
489         spin_lock_irqsave(&par->lock, flags);
490
491         if (fg != par->fg_cache) {
492                 FFBFifo(par, 1);
493                 upa_writel(fg, &fbc->fg);
494                 par->fg_cache = fg;
495         }
496
497         ffb_rop(par, (rect->rop == ROP_COPY ?
498                       FFB_ROP_NEW :
499                       FFB_ROP_NEW_XOR_OLD));
500
501         FFBFifo(par, 5);
502         upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
503         upa_writel(rect->dy, &fbc->by);
504         upa_writel(rect->dx, &fbc->bx);
505         upa_writel(rect->height, &fbc->bh);
506         upa_writel(rect->width, &fbc->bw);
507
508         spin_unlock_irqrestore(&par->lock, flags);
509 }
510
511 /**
512  *      ffb_copyarea - REQUIRED function. Can use generic routines if
513  *                     non acclerated hardware and packed pixel based.
514  *                     Copies on area of the screen to another area.
515  *
516  *      @info: frame buffer structure that represents a single frame buffer
517  *      @area: structure defining the source and destination.
518  */
519
520 static void
521 ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 
522 {
523         struct ffb_par *par = (struct ffb_par *) info->par;
524         struct ffb_fbc __iomem *fbc = par->fbc;
525         unsigned long flags;
526
527         if (area->dx != area->sx ||
528             area->dy == area->sy) {
529                 cfb_copyarea(info, area);
530                 return;
531         }
532
533         spin_lock_irqsave(&par->lock, flags);
534
535         ffb_rop(par, FFB_ROP_OLD);
536
537         FFBFifo(par, 7);
538         upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
539         upa_writel(area->sy, &fbc->by);
540         upa_writel(area->sx, &fbc->bx);
541         upa_writel(area->dy, &fbc->dy);
542         upa_writel(area->dx, &fbc->dx);
543         upa_writel(area->height, &fbc->bh);
544         upa_writel(area->width, &fbc->bw);
545
546         spin_unlock_irqrestore(&par->lock, flags);
547 }
548
549 /**
550  *      ffb_imageblit - REQUIRED function. Can use generic routines if
551  *                      non acclerated hardware and packed pixel based.
552  *                      Copies a image from system memory to the screen. 
553  *
554  *      @info: frame buffer structure that represents a single frame buffer
555  *      @image: structure defining the image.
556  */
557 static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
558 {
559         struct ffb_par *par = (struct ffb_par *) info->par;
560         struct ffb_fbc __iomem *fbc = par->fbc;
561         const u8 *data = image->data;
562         unsigned long flags;
563         u32 fg, bg, xy;
564         u64 fgbg;
565         int i, width, stride;
566
567         if (image->depth > 1) {
568                 cfb_imageblit(info, image);
569                 return;
570         }
571
572         fg = ((u32 *)info->pseudo_palette)[image->fg_color];
573         bg = ((u32 *)info->pseudo_palette)[image->bg_color];
574         fgbg = ((u64) fg << 32) | (u64) bg;
575         xy = (image->dy << 16) | image->dx;
576         width = image->width;
577         stride = ((width + 7) >> 3);
578
579         spin_lock_irqsave(&par->lock, flags);
580
581         if (fgbg != *(u64 *)&par->fg_cache) {
582                 FFBFifo(par, 2);
583                 upa_writeq(fgbg, &fbc->fg);
584                 *(u64 *)&par->fg_cache = fgbg;
585         }
586
587         if (width >= 32) {
588                 FFBFifo(par, 1);
589                 upa_writel(32, &fbc->fontw);
590         }
591
592         while (width >= 32) {
593                 const u8 *next_data = data + 4;
594
595                 FFBFifo(par, 1);
596                 upa_writel(xy, &fbc->fontxy);
597                 xy += (32 << 0);
598
599                 for (i = 0; i < image->height; i++) {
600                         u32 val = (((u32)data[0] << 24) |
601                                    ((u32)data[1] << 16) |
602                                    ((u32)data[2] <<  8) |
603                                    ((u32)data[3] <<  0));
604                         FFBFifo(par, 1);
605                         upa_writel(val, &fbc->font);
606
607                         data += stride;
608                 }
609
610                 data = next_data;
611                 width -= 32;
612         }
613
614         if (width) {
615                 FFBFifo(par, 2);
616                 upa_writel(width, &fbc->fontw);
617                 upa_writel(xy, &fbc->fontxy);
618
619                 for (i = 0; i < image->height; i++) {
620                         u32 val = (((u32)data[0] << 24) |
621                                    ((u32)data[1] << 16) |
622                                    ((u32)data[2] <<  8) |
623                                    ((u32)data[3] <<  0));
624                         FFBFifo(par, 1);
625                         upa_writel(val, &fbc->font);
626
627                         data += stride;
628                 }
629         }
630
631         spin_unlock_irqrestore(&par->lock, flags);
632 }
633
634 static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
635 {
636         var->red.offset = 0;
637         var->red.length = 8;
638         var->green.offset = 8;
639         var->green.length = 8;
640         var->blue.offset = 16;
641         var->blue.length = 8;
642         var->transp.offset = 0;
643         var->transp.length = 0;
644 }
645
646 /**
647  *      ffb_setcolreg - Optional function. Sets a color register.
648  *      @regno: boolean, 0 copy local, 1 get_user() function
649  *      @red: frame buffer colormap structure
650  *      @green: The green value which can be up to 16 bits wide
651  *      @blue:  The blue value which can be up to 16 bits wide.
652  *      @transp: If supported the alpha value which can be up to 16 bits wide.
653  *      @info: frame buffer info structure
654  */
655 static int ffb_setcolreg(unsigned regno,
656                          unsigned red, unsigned green, unsigned blue,
657                          unsigned transp, struct fb_info *info)
658 {
659         u32 value;
660
661         if (regno >= 16)
662                 return 1;
663
664         red >>= 8;
665         green >>= 8;
666         blue >>= 8;
667
668         value = (blue << 16) | (green << 8) | red;
669         ((u32 *)info->pseudo_palette)[regno] = value;
670
671         return 0;
672 }
673
674 /**
675  *      ffb_blank - Optional function.  Blanks the display.
676  *      @blank_mode: the blank mode we want.
677  *      @info: frame buffer structure that represents a single frame buffer
678  */
679 static int
680 ffb_blank(int blank, struct fb_info *info)
681 {
682         struct ffb_par *par = (struct ffb_par *) info->par;
683         struct ffb_dac __iomem *dac = par->dac;
684         unsigned long flags;
685         u32 val;
686         int i;
687
688         spin_lock_irqsave(&par->lock, flags);
689
690         FFBWait(par);
691
692         upa_writel(FFB_DAC_TGEN, &dac->type);
693         val = upa_readl(&dac->value);
694         switch (blank) {
695         case FB_BLANK_UNBLANK: /* Unblanking */
696                 val |= FFB_DAC_TGEN_VIDE;
697                 par->flags &= ~FFB_FLAG_BLANKED;
698                 break;
699
700         case FB_BLANK_NORMAL: /* Normal blanking */
701         case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
702         case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
703         case FB_BLANK_POWERDOWN: /* Poweroff */
704                 val &= ~FFB_DAC_TGEN_VIDE;
705                 par->flags |= FFB_FLAG_BLANKED;
706                 break;
707         }
708         upa_writel(FFB_DAC_TGEN, &dac->type);
709         upa_writel(val, &dac->value);
710         for (i = 0; i < 10; i++) {
711                 upa_writel(FFB_DAC_TGEN, &dac->type);
712                 upa_readl(&dac->value);
713         }
714
715         spin_unlock_irqrestore(&par->lock, flags);
716
717         return 0;
718 }
719
720 static struct sbus_mmap_map ffb_mmap_map[] = {
721         {
722                 .voff   = FFB_SFB8R_VOFF,
723                 .poff   = FFB_SFB8R_POFF,
724                 .size   = 0x0400000
725         },
726         {
727                 .voff   = FFB_SFB8G_VOFF,
728                 .poff   = FFB_SFB8G_POFF,
729                 .size   = 0x0400000
730         },
731         {
732                 .voff   = FFB_SFB8B_VOFF,
733                 .poff   = FFB_SFB8B_POFF,
734                 .size   = 0x0400000
735         },
736         {
737                 .voff   = FFB_SFB8X_VOFF,
738                 .poff   = FFB_SFB8X_POFF,
739                 .size   = 0x0400000
740         },
741         {
742                 .voff   = FFB_SFB32_VOFF,
743                 .poff   = FFB_SFB32_POFF,
744                 .size   = 0x1000000
745         },
746         {
747                 .voff   = FFB_SFB64_VOFF,
748                 .poff   = FFB_SFB64_POFF,
749                 .size   = 0x2000000
750         },
751         {
752                 .voff   = FFB_FBC_REGS_VOFF,
753                 .poff   = FFB_FBC_REGS_POFF,
754                 .size   = 0x0002000
755         },
756         {
757                 .voff   = FFB_BM_FBC_REGS_VOFF,
758                 .poff   = FFB_BM_FBC_REGS_POFF,
759                 .size   = 0x0002000
760         },
761         {
762                 .voff   = FFB_DFB8R_VOFF,
763                 .poff   = FFB_DFB8R_POFF,
764                 .size   = 0x0400000
765         },
766         {
767                 .voff   = FFB_DFB8G_VOFF,
768                 .poff   = FFB_DFB8G_POFF,
769                 .size   = 0x0400000
770         },
771         {
772                 .voff   = FFB_DFB8B_VOFF,
773                 .poff   = FFB_DFB8B_POFF,
774                 .size   = 0x0400000
775         },
776         {
777                 .voff   = FFB_DFB8X_VOFF,
778                 .poff   = FFB_DFB8X_POFF,
779                 .size   = 0x0400000
780         },
781         {
782                 .voff   = FFB_DFB24_VOFF,
783                 .poff   = FFB_DFB24_POFF,
784                 .size   = 0x1000000
785         },
786         {
787                 .voff   = FFB_DFB32_VOFF,
788                 .poff   = FFB_DFB32_POFF,
789                 .size   = 0x1000000
790         },
791         {
792                 .voff   = FFB_FBC_KREGS_VOFF,
793                 .poff   = FFB_FBC_KREGS_POFF,
794                 .size   = 0x0002000
795         },
796         {
797                 .voff   = FFB_DAC_VOFF,
798                 .poff   = FFB_DAC_POFF,
799                 .size   = 0x0002000
800         },
801         {
802                 .voff   = FFB_PROM_VOFF,
803                 .poff   = FFB_PROM_POFF,
804                 .size   = 0x0010000
805         },
806         {
807                 .voff   = FFB_EXP_VOFF,
808                 .poff   = FFB_EXP_POFF,
809                 .size   = 0x0002000
810         },
811         {
812                 .voff   = FFB_DFB422A_VOFF,
813                 .poff   = FFB_DFB422A_POFF,
814                 .size   = 0x0800000
815         },
816         {
817                 .voff   = FFB_DFB422AD_VOFF,
818                 .poff   = FFB_DFB422AD_POFF,
819                 .size   = 0x0800000
820         },
821         {
822                 .voff   = FFB_DFB24B_VOFF,
823                 .poff   = FFB_DFB24B_POFF,
824                 .size   = 0x1000000
825         },
826         {
827                 .voff   = FFB_DFB422B_VOFF,
828                 .poff   = FFB_DFB422B_POFF,
829                 .size   = 0x0800000
830         },
831         {
832                 .voff   = FFB_DFB422BD_VOFF,
833                 .poff   = FFB_DFB422BD_POFF,
834                 .size   = 0x0800000
835         },
836         {
837                 .voff   = FFB_SFB16Z_VOFF,
838                 .poff   = FFB_SFB16Z_POFF,
839                 .size   = 0x0800000
840         },
841         {
842                 .voff   = FFB_SFB8Z_VOFF,
843                 .poff   = FFB_SFB8Z_POFF,
844                 .size   = 0x0800000
845         },
846         {
847                 .voff   = FFB_SFB422_VOFF,
848                 .poff   = FFB_SFB422_POFF,
849                 .size   = 0x0800000
850         },
851         {
852                 .voff   = FFB_SFB422D_VOFF,
853                 .poff   = FFB_SFB422D_POFF,
854                 .size   = 0x0800000
855         },
856         { .size = 0 }
857 };
858
859 static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma)
860 {
861         struct ffb_par *par = (struct ffb_par *)info->par;
862
863         return sbusfb_mmap_helper(ffb_mmap_map,
864                                   par->physbase, par->fbsize,
865                                   0, vma);
866 }
867
868 static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
869 {
870         struct ffb_par *par = (struct ffb_par *) info->par;
871
872         return sbusfb_ioctl_helper(cmd, arg, info,
873                                    FBTYPE_CREATOR, 24, par->fbsize);
874 }
875
876 /*
877  *  Initialisation
878  */
879
880 static void
881 ffb_init_fix(struct fb_info *info)
882 {
883         struct ffb_par *par = (struct ffb_par *)info->par;
884         const char *ffb_type_name;
885
886         if (!(par->flags & FFB_FLAG_AFB)) {
887                 if ((par->board_type & 0x7) == 0x3)
888                         ffb_type_name = "Creator 3D";
889                 else
890                         ffb_type_name = "Creator";
891         } else
892                 ffb_type_name = "Elite 3D";
893
894         strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
895
896         info->fix.type = FB_TYPE_PACKED_PIXELS;
897         info->fix.visual = FB_VISUAL_TRUECOLOR;
898
899         /* Framebuffer length is the same regardless of resolution. */
900         info->fix.line_length = 8192;
901
902         info->fix.accel = FB_ACCEL_SUN_CREATOR;
903 }
904
905 static int __devinit ffb_probe(struct of_device *op, const struct of_device_id *match)
906 {
907         struct device_node *dp = op->node;
908         struct ffb_fbc __iomem *fbc;
909         struct ffb_dac __iomem *dac;
910         struct fb_info *info;
911         struct ffb_par *par;
912         u32 dac_pnum, dac_rev, dac_mrev;
913         int err;
914
915         info = framebuffer_alloc(sizeof(struct ffb_par), &op->dev);
916
917         err = -ENOMEM;
918         if (!info)
919                 goto out_err;
920
921         par = info->par;
922
923         spin_lock_init(&par->lock);
924         par->fbc = of_ioremap(&op->resource[2], 0,
925                               sizeof(struct ffb_fbc), "ffb fbc");
926         if (!par->fbc)
927                 goto out_release_fb;
928
929         par->dac = of_ioremap(&op->resource[1], 0,
930                               sizeof(struct ffb_dac), "ffb dac");
931         if (!par->dac)
932                 goto out_unmap_fbc;
933
934         par->rop_cache = FFB_ROP_NEW;
935         par->physbase = op->resource[0].start;
936
937         /* Don't mention copyarea, so SCROLL_REDRAW is always
938          * used.  It is the fastest on this chip.
939          */
940         info->flags = (FBINFO_DEFAULT |
941                        /* FBINFO_HWACCEL_COPYAREA | */
942                        FBINFO_HWACCEL_FILLRECT |
943                        FBINFO_HWACCEL_IMAGEBLIT);
944
945         info->fbops = &ffb_ops;
946
947         info->screen_base = (char *) par->physbase + FFB_DFB24_POFF;
948         info->pseudo_palette = par->pseudo_palette;
949
950         sbusfb_fill_var(&info->var, dp->node, 32);
951         par->fbsize = PAGE_ALIGN(info->var.xres * info->var.yres * 4);
952         ffb_fixup_var_rgb(&info->var);
953
954         info->var.accel_flags = FB_ACCELF_TEXT;
955
956         if (!strcmp(dp->name, "SUNW,afb"))
957                 par->flags |= FFB_FLAG_AFB;
958
959         par->board_type = of_getintprop_default(dp, "board_type", 0);
960
961         fbc = par->fbc;
962         if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
963                 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
964
965         dac = par->dac;
966         upa_writel(FFB_DAC_DID, &dac->type);
967         dac_pnum = upa_readl(&dac->value);
968         dac_rev = (dac_pnum & FFB_DAC_DID_REV) >> FFB_DAC_DID_REV_SHIFT;
969         dac_pnum = (dac_pnum & FFB_DAC_DID_PNUM) >> FFB_DAC_DID_PNUM_SHIFT;
970
971         upa_writel(FFB_DAC_UCTRL, &dac->type);
972         dac_mrev = upa_readl(&dac->value);
973         dac_mrev = (dac_mrev & FFB_DAC_UCTRL_MANREV) >>
974                 FFB_DAC_UCTRL_MANREV_SHIFT;
975
976         /* Elite3D has different DAC revision numbering, and no DAC revisions
977          * have the reversed meaning of cursor enable.  Otherwise, Pacifica 1
978          * ramdacs with manufacturing revision less than 3 have inverted
979          * cursor logic.  We identify Pacifica 1 as not Pacifica 2, the
980          * latter having a part number value of 0x236e.
981          */
982         if ((par->flags & FFB_FLAG_AFB) || dac_pnum == 0x236e) {
983                 par->flags &= ~FFB_FLAG_INVCURSOR;
984         } else {
985                 if (dac_mrev < 3)
986                         par->flags |= FFB_FLAG_INVCURSOR;
987         }
988
989         ffb_switch_from_graph(par);
990
991         /* Unblank it just to be sure.  When there are multiple
992          * FFB/AFB cards in the system, or it is not the OBP
993          * chosen console, it will have video outputs off in
994          * the DAC.
995          */
996         ffb_blank(0, info);
997
998         if (fb_alloc_cmap(&info->cmap, 256, 0))
999                 goto out_unmap_dac;
1000
1001         ffb_init_fix(info);
1002
1003         err = register_framebuffer(info);
1004         if (err < 0)
1005                 goto out_dealloc_cmap;
1006
1007         dev_set_drvdata(&op->dev, info);
1008
1009         printk("%s: %s at %016lx, type %d, "
1010                "DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
1011                dp->full_name,
1012                ((par->flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
1013                par->physbase, par->board_type,
1014                dac_pnum, dac_rev, dac_mrev);
1015
1016         return 0;
1017
1018 out_dealloc_cmap:
1019         fb_dealloc_cmap(&info->cmap);
1020
1021 out_unmap_dac:
1022         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
1023
1024 out_unmap_fbc:
1025         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
1026
1027 out_release_fb:
1028         framebuffer_release(info);
1029
1030 out_err:
1031         return err;
1032 }
1033
1034 static int __devexit ffb_remove(struct of_device *op)
1035 {
1036         struct fb_info *info = dev_get_drvdata(&op->dev);
1037         struct ffb_par *par = info->par;
1038
1039         unregister_framebuffer(info);
1040         fb_dealloc_cmap(&info->cmap);
1041
1042         of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
1043         of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
1044
1045         framebuffer_release(info);
1046
1047         dev_set_drvdata(&op->dev, NULL);
1048
1049         return 0;
1050 }
1051
1052 static struct of_device_id ffb_match[] = {
1053         {
1054                 .name = "SUNW,ffb",
1055         },
1056         {
1057                 .name = "SUNW,afb",
1058         },
1059         {},
1060 };
1061 MODULE_DEVICE_TABLE(of, ffb_match);
1062
1063 static struct of_platform_driver ffb_driver = {
1064         .name           = "ffb",
1065         .match_table    = ffb_match,
1066         .probe          = ffb_probe,
1067         .remove         = __devexit_p(ffb_remove),
1068 };
1069
1070 int __init ffb_init(void)
1071 {
1072         if (fb_get_options("ffb", NULL))
1073                 return -ENODEV;
1074
1075         return of_register_driver(&ffb_driver, &of_bus_type);
1076 }
1077
1078 void __exit ffb_exit(void)
1079 {
1080         of_unregister_driver(&ffb_driver);
1081 }
1082
1083 module_init(ffb_init);
1084 module_exit(ffb_exit);
1085
1086 MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
1087 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
1088 MODULE_VERSION("2.0");
1089 MODULE_LICENSE("GPL");