2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
15 * it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
22 #include <asm/thread_notify.h>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 1: get_irqnr_and_base r0, r6, r5, lr
33 @ routine called with r0 = irq number, r1 = struct pt_regs *
42 * this macro assumes that irqstat (r6) and base (r5) are
43 * preserved from get_irqnr_and_base above
45 test_for_ipi r0, r6, r5, lr
50 #ifdef CONFIG_LOCAL_TIMERS
51 test_for_ltirq r0, r6, r5, lr
61 * Invalid mode handlers
63 .macro inv_entry, reason
64 sub sp, sp, #S_FRAME_SIZE
70 inv_entry BAD_PREFETCH
82 inv_entry BAD_UNDEFINSTR
85 @ XXX fall through to common_invalid
89 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
95 add r0, sp, #S_PC @ here for interlock avoidance
96 mov r7, #-1 @ "" "" "" ""
97 str r4, [sp] @ save preserved r0
98 stmia r0, {r5 - r7} @ lr_<exception>,
99 @ cpsr_<exception>, "old_r0"
108 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
109 #define SPFIX(code...) code
111 #define SPFIX(code...)
115 sub sp, sp, #S_FRAME_SIZE
117 SPFIX( bicne sp, sp, #4 )
121 add r5, sp, #S_SP @ here for interlock avoidance
122 mov r4, #-1 @ "" "" "" ""
123 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
124 SPFIX( addne r0, r0, #4 )
125 str r1, [sp] @ save the "real" r0 copied
126 @ from the exception stack
131 @ We are now ready to fill in the remaining blanks on the stack:
135 @ r2 - lr_<exception>, already fixed up for correct return/restart
136 @ r3 - spsr_<exception>
137 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
147 @ get ready to re-enable interrupts if appropriate
151 biceq r9, r9, #PSR_I_BIT
154 @ Call the processor-specific abort handler:
156 @ r2 - aborted context pc
157 @ r3 - aborted context cpsr
159 @ The abort handler must return the aborted address in r0, and
160 @ the fault status register in r1. r9 must be preserved.
171 @ set desired IRQ state, then call main handler
178 @ IRQs off again before pulling preserved data off the stack
183 @ restore SPSR and restart the instruction
187 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
193 #ifdef CONFIG_TRACE_IRQFLAGS
194 bl trace_hardirqs_off
196 #ifdef CONFIG_PREEMPT
198 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
199 add r7, r8, #1 @ increment it
200 str r7, [tsk, #TI_PREEMPT]
204 #ifdef CONFIG_PREEMPT
205 ldr r0, [tsk, #TI_FLAGS] @ get flags
206 tst r0, #_TIF_NEED_RESCHED
209 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
210 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
212 strne r0, [r0, -r0] @ bug()
214 ldr r0, [sp, #S_PSR] @ irqs are already disabled
216 #ifdef CONFIG_TRACE_IRQFLAGS
218 bleq trace_hardirqs_on
220 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
224 #ifdef CONFIG_PREEMPT
226 teq r8, #0 @ was preempt count = 0
227 ldreq r6, .LCirq_stat
229 ldr r0, [r6, #4] @ local_irq_count
230 ldr r1, [r6, #8] @ local_bh_count
233 mov r7, #0 @ preempt_schedule_irq
234 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
235 1: bl preempt_schedule_irq @ irq en/disable is done inside
236 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
237 tst r0, #_TIF_NEED_RESCHED
238 beq preempt_return @ go again
247 @ call emulation code, which returns using r9 if it has emulated
248 @ the instruction, or the more conventional lr if we are to treat
249 @ this as a real undefined instruction
257 mov r0, sp @ struct pt_regs *regs
261 @ IRQs off again before pulling preserved data off the stack
266 @ restore SPSR and restart the instruction
268 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
270 ldmia sp, {r0 - pc}^ @ Restore SVC registers
277 @ re-enable interrupts if appropriate
281 biceq r9, r9, #PSR_I_BIT
285 @ set args, then call main handler
287 @ r0 - address of faulting instruction
288 @ r1 - pointer to registers on stack
290 mov r0, r2 @ address (pc)
292 bl do_PrefetchAbort @ call abort handler
295 @ IRQs off again before pulling preserved data off the stack
300 @ restore SPSR and restart the instruction
304 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
315 #ifdef CONFIG_PREEMPT
323 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
326 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
327 #error "sizeof(struct pt_regs) must be a multiple of 8"
331 sub sp, sp, #S_FRAME_SIZE
335 add r0, sp, #S_PC @ here for interlock avoidance
336 mov r4, #-1 @ "" "" "" ""
338 str r1, [sp] @ save the "real" r0 copied
339 @ from the exception stack
341 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
343 #warning "NPTL on non MMU needs fixing"
345 @ make sure our user space atomic helper is aborted
347 bichs r3, r3, #PSR_Z_BIT
352 @ We are now ready to fill in the remaining blanks on the stack:
354 @ r2 - lr_<exception>, already fixed up for correct return/restart
355 @ r3 - spsr_<exception>
356 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
358 @ Also, separately save sp_usr and lr_usr
364 @ Enable the alignment trap while in kernel mode
369 @ Clear FP to mark the first stack frame
379 @ Call the processor-specific abort handler:
381 @ r2 - aborted context pc
382 @ r3 - aborted context cpsr
384 @ The abort handler must return the aborted address in r0, and
385 @ the fault status register in r1.
396 @ IRQs on, then call the main handler
400 adr lr, ret_from_exception
407 #ifdef CONFIG_TRACE_IRQFLAGS
408 bl trace_hardirqs_off
411 #ifdef CONFIG_PREEMPT
412 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
413 add r7, r8, #1 @ increment it
414 str r7, [tsk, #TI_PREEMPT]
418 #ifdef CONFIG_PREEMPT
419 ldr r0, [tsk, #TI_PREEMPT]
420 str r8, [tsk, #TI_PREEMPT]
424 #ifdef CONFIG_TRACE_IRQFLAGS
437 tst r3, #PSR_T_BIT @ Thumb mode?
438 bne __und_usr_unknown @ ignore FP
442 @ fall through to the emulation code, which returns using r9 if
443 @ it has emulated the instruction, or the more conventional lr
444 @ if we are to treat this as a real undefined instruction
449 adr r9, ret_from_exception
450 adr lr, __und_usr_unknown
452 @ fallthrough to call_fpe
456 * The out of line fixup for the ldrt above.
458 .section .fixup, "ax"
461 .section __ex_table,"a"
466 * Check whether the instruction is a co-processor instruction.
467 * If yes, we need to call the relevant co-processor handler.
469 * Note that we don't do a full check here for the co-processor
470 * instructions; all instructions with bit 27 set are well
471 * defined. The only instructions that should fault are the
472 * co-processor instructions. However, we have to watch out
473 * for the ARM6/ARM7 SWI bug.
475 * Emulators may wish to make use of the following registers:
476 * r0 = instruction opcode.
478 * r9 = normal "successful" return address
479 * r10 = this threads thread_info structure.
480 * lr = unrecognised instruction return address
483 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
484 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
485 and r8, r0, #0x0f000000 @ mask out op-code bits
486 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
489 get_thread_info r10 @ get current thread
490 and r8, r0, #0x00000f00 @ mask out CP number
492 add r6, r10, #TI_USED_CP
493 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
495 @ Test if we need to give access to iWMMXt coprocessors
496 ldr r5, [r10, #TI_FLAGS]
497 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
498 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
499 bcs iwmmxt_task_enable
501 add pc, pc, r8, lsr #6
505 b do_fpe @ CP#1 (FPE)
506 b do_fpe @ CP#2 (FPE)
509 b crunch_task_enable @ CP#4 (MaverickCrunch)
510 b crunch_task_enable @ CP#5 (MaverickCrunch)
511 b crunch_task_enable @ CP#6 (MaverickCrunch)
521 b do_vfp @ CP#10 (VFP)
522 b do_vfp @ CP#11 (VFP)
524 mov pc, lr @ CP#10 (VFP)
525 mov pc, lr @ CP#11 (VFP)
529 mov pc, lr @ CP#14 (Debug)
530 mov pc, lr @ CP#15 (Control)
535 add r10, r10, #TI_FPSTATE @ r10 = workspace
536 ldr pc, [r4] @ Call FP module USR entry point
539 * The FP module is called with these registers set:
542 * r9 = normal "successful" return address
544 * lr = unrecognised FP instruction return address
556 adr lr, ret_from_exception
563 enable_irq @ Enable interrupts
564 mov r0, r2 @ address (pc)
566 bl do_PrefetchAbort @ call abort handler
569 * This is the return code to user mode for abort handlers
571 ENTRY(ret_from_exception)
577 * Register switch for ARMv3 and ARMv4 processors
578 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
579 * previous and next are guaranteed not to be the same.
582 add ip, r1, #TI_CPU_SAVE
583 ldr r3, [r2, #TI_TP_VALUE]
584 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
586 ldr r6, [r2, #TI_CPU_DOMAIN]
588 #if __LINUX_ARM_ARCH__ >= 6
589 #ifdef CONFIG_CPU_32v6K
592 strex r5, r4, [ip] @ Clear exclusive monitor
595 #if defined(CONFIG_HAS_TLS_REG)
596 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
597 #elif !defined(CONFIG_TLS_REG_EMUL)
599 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
602 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
605 add r4, r2, #TI_CPU_SAVE
606 ldr r0, =thread_notify_head
607 mov r1, #THREAD_NOTIFY_SWITCH
608 bl atomic_notifier_call_chain
610 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
617 * These are segment of kernel provided user code reachable from user space
618 * at a fixed address in kernel memory. This is used to provide user space
619 * with some operations which require kernel help because of unimplemented
620 * native feature and/or instructions in many ARM CPUs. The idea is for
621 * this code to be executed directly in user mode for best efficiency but
622 * which is too intimate with the kernel counter part to be left to user
623 * libraries. In fact this code might even differ from one CPU to another
624 * depending on the available instruction set and restrictions like on
625 * SMP systems. In other words, the kernel reserves the right to change
626 * this code as needed without warning. Only the entry points and their
627 * results are guaranteed to be stable.
629 * Each segment is 32-byte aligned and will be moved to the top of the high
630 * vector page. New segments (if ever needed) must be added in front of
631 * existing ones. This mechanism should be used only for things that are
632 * really small and justified, and not be abused freely.
634 * User space is expected to implement those things inline when optimizing
635 * for a processor that has the necessary native support, but only if such
636 * resulting binaries are already to be incompatible with earlier ARM
637 * processors due to the use of unsupported instructions other than what
638 * is provided here. In other words don't make binaries unable to run on
639 * earlier processors just for the sake of not using these kernel helpers
640 * if your compiled code is not going to use the new instructions for other
645 #ifdef CONFIG_ARM_THUMB
653 .globl __kuser_helper_start
654 __kuser_helper_start:
657 * Reference prototype:
659 * void __kernel_memory_barrier(void)
663 * lr = return address
671 * the Z flag might be lost
673 * Definition and user space usage example:
675 * typedef void (__kernel_dmb_t)(void);
676 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
678 * Apply any needed memory barrier to preserve consistency with data modified
679 * manually and __kuser_cmpxchg usage.
681 * This could be used as follows:
683 * #define __kernel_dmb() \
684 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
685 * : : : "r0", "lr","cc" )
688 __kuser_memory_barrier: @ 0xffff0fa0
690 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
691 mcr p15, 0, r0, c7, c10, 5 @ dmb
698 * Reference prototype:
700 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
707 * lr = return address
711 * r0 = returned value (zero or non-zero)
712 * C flag = set if r0 == 0, clear if r0 != 0
718 * Definition and user space usage example:
720 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
721 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
723 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
724 * Return zero if *ptr was changed or non-zero if no exchange happened.
725 * The C flag is also set if *ptr was changed to allow for assembly
726 * optimization in the calling code.
730 * - This routine already includes memory barriers as needed.
732 * - A failure might be transient, i.e. it is possible, although unlikely,
733 * that "failure" be returned even if *ptr == oldval.
735 * For example, a user space atomic_add implementation could look like this:
737 * #define atomic_add(ptr, val) \
738 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
739 * register unsigned int __result asm("r1"); \
741 * "1: @ atomic_add\n\t" \
742 * "ldr r0, [r2]\n\t" \
743 * "mov r3, #0xffff0fff\n\t" \
744 * "add lr, pc, #4\n\t" \
745 * "add r1, r0, %2\n\t" \
746 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
748 * : "=&r" (__result) \
749 * : "r" (__ptr), "rIL" (val) \
750 * : "r0","r3","ip","lr","cc","memory" ); \
754 __kuser_cmpxchg: @ 0xffff0fc0
756 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
759 * Poor you. No fast solution possible...
760 * The kernel itself must perform the operation.
761 * A special ghost syscall is used for that (see traps.c).
764 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
769 #elif __LINUX_ARM_ARCH__ < 6
772 * Theory of operation:
774 * We set the Z flag before loading oldval. If ever an exception
775 * occurs we can not be sure the loaded value will still be the same
776 * when the exception returns, therefore the user exception handler
777 * will clear the Z flag whenever the interrupted user code was
778 * actually from the kernel address space (see the usr_entry macro).
780 * The post-increment on the str is used to prevent a race with an
781 * exception happening just after the str instruction which would
782 * clear the Z flag although the exchange was done.
785 teq ip, ip @ set Z flag
786 ldr ip, [r2] @ load current val
787 add r3, r2, #1 @ prepare store ptr
788 teqeq ip, r0 @ compare with oldval if still allowed
789 streq r1, [r3, #-1]! @ store newval if still allowed
790 subs r0, r2, r3 @ if r2 == r3 the str occured
792 #warning "NPTL on non MMU needs fixing"
801 mcr p15, 0, r0, c7, c10, 5 @ dmb
808 mcr p15, 0, r0, c7, c10, 5 @ dmb
817 * Reference prototype:
819 * int __kernel_get_tls(void)
823 * lr = return address
831 * the Z flag might be lost
833 * Definition and user space usage example:
835 * typedef int (__kernel_get_tls_t)(void);
836 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
838 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
840 * This could be used as follows:
842 * #define __kernel_get_tls() \
843 * ({ register unsigned int __val asm("r0"); \
844 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
845 * : "=r" (__val) : : "lr","cc" ); \
849 __kuser_get_tls: @ 0xffff0fe0
851 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
852 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
854 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
859 .word 0 @ pad up to __kuser_helper_version
863 * Reference declaration:
865 * extern unsigned int __kernel_helper_version;
867 * Definition and user space usage example:
869 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
871 * User space may read this to determine the curent number of helpers
875 __kuser_helper_version: @ 0xffff0ffc
876 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
878 .globl __kuser_helper_end
885 * This code is copied to 0xffff0200 so we can use branches in the
886 * vectors, rather than ldr's. Note that this code must not
887 * exceed 0x300 bytes.
889 * Common stub entry macro:
890 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
892 * SP points to a minimal amount of processor-private memory, the address
893 * of which is copied into r0 for the mode specific abort handler.
895 .macro vector_stub, name, mode, correction=0
900 sub lr, lr, #\correction
904 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
907 stmia sp, {r0, lr} @ save r0, lr
909 str lr, [sp, #8] @ save spsr
912 @ Prepare for SVC32 mode. IRQs remain disabled.
915 eor r0, r0, #(\mode ^ SVC_MODE)
919 @ the branch table must immediately follow this code
923 ldr lr, [pc, lr, lsl #2]
924 movs pc, lr @ branch to handler in SVC mode
930 * Interrupt dispatcher
932 vector_stub irq, IRQ_MODE, 4
934 .long __irq_usr @ 0 (USR_26 / USR_32)
935 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
936 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
937 .long __irq_svc @ 3 (SVC_26 / SVC_32)
938 .long __irq_invalid @ 4
939 .long __irq_invalid @ 5
940 .long __irq_invalid @ 6
941 .long __irq_invalid @ 7
942 .long __irq_invalid @ 8
943 .long __irq_invalid @ 9
944 .long __irq_invalid @ a
945 .long __irq_invalid @ b
946 .long __irq_invalid @ c
947 .long __irq_invalid @ d
948 .long __irq_invalid @ e
949 .long __irq_invalid @ f
952 * Data abort dispatcher
953 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
955 vector_stub dabt, ABT_MODE, 8
957 .long __dabt_usr @ 0 (USR_26 / USR_32)
958 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
959 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
960 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
961 .long __dabt_invalid @ 4
962 .long __dabt_invalid @ 5
963 .long __dabt_invalid @ 6
964 .long __dabt_invalid @ 7
965 .long __dabt_invalid @ 8
966 .long __dabt_invalid @ 9
967 .long __dabt_invalid @ a
968 .long __dabt_invalid @ b
969 .long __dabt_invalid @ c
970 .long __dabt_invalid @ d
971 .long __dabt_invalid @ e
972 .long __dabt_invalid @ f
975 * Prefetch abort dispatcher
976 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
978 vector_stub pabt, ABT_MODE, 4
980 .long __pabt_usr @ 0 (USR_26 / USR_32)
981 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
982 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
983 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
984 .long __pabt_invalid @ 4
985 .long __pabt_invalid @ 5
986 .long __pabt_invalid @ 6
987 .long __pabt_invalid @ 7
988 .long __pabt_invalid @ 8
989 .long __pabt_invalid @ 9
990 .long __pabt_invalid @ a
991 .long __pabt_invalid @ b
992 .long __pabt_invalid @ c
993 .long __pabt_invalid @ d
994 .long __pabt_invalid @ e
995 .long __pabt_invalid @ f
998 * Undef instr entry dispatcher
999 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1001 vector_stub und, UND_MODE
1003 .long __und_usr @ 0 (USR_26 / USR_32)
1004 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1005 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1006 .long __und_svc @ 3 (SVC_26 / SVC_32)
1007 .long __und_invalid @ 4
1008 .long __und_invalid @ 5
1009 .long __und_invalid @ 6
1010 .long __und_invalid @ 7
1011 .long __und_invalid @ 8
1012 .long __und_invalid @ 9
1013 .long __und_invalid @ a
1014 .long __und_invalid @ b
1015 .long __und_invalid @ c
1016 .long __und_invalid @ d
1017 .long __und_invalid @ e
1018 .long __und_invalid @ f
1022 /*=============================================================================
1024 *-----------------------------------------------------------------------------
1025 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1026 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1027 * Basically to switch modes, we *HAVE* to clobber one register... brain
1028 * damage alert! I don't think that we can execute any code in here in any
1029 * other mode than FIQ... Ok you can switch to another mode, but you can't
1030 * get out of that mode without clobbering one register.
1036 /*=============================================================================
1037 * Address exception handler
1038 *-----------------------------------------------------------------------------
1039 * These aren't too critical.
1040 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1047 * We group all the following data together to optimise
1048 * for CPUs with separate I & D caches.
1058 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1060 .globl __vectors_start
1063 b vector_und + stubs_offset
1064 ldr pc, .LCvswi + stubs_offset
1065 b vector_pabt + stubs_offset
1066 b vector_dabt + stubs_offset
1067 b vector_addrexcptn + stubs_offset
1068 b vector_irq + stubs_offset
1069 b vector_fiq + stubs_offset
1071 .globl __vectors_end
1077 .globl cr_no_alignment
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