git.oblomov.eu Git - linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along with
  21  *  this program; if not, write to the Free Software Foundation, Inc., 59
  22  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23  *
  24  *  CONTACTS:
  25  *
  26  *  Matt Jared          matt.jared@intel.com
  27  *  Andy Kopp           andy.kopp@intel.com
  28  *  Dan Kogan           dan.d.kogan@intel.com
  29  *
  30  *  CHANGES:
  31  *
  32  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  33  *
  34  */
  35
  36 #include <sound/driver.h>
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/init.h>
  43 #include <linux/slab.h>
  44 #include <linux/pci.h>
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include "hda_codec.h"
  48
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  53 static char *model[SNDRV_CARDS];
  54 static int position_fix[SNDRV_CARDS];
  55
  56 module_param_array(index, int, NULL, 0444);
  57 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  58 module_param_array(id, charp, NULL, 0444);
  59 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  60 module_param_array(enable, bool, NULL, 0444);
  61 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  62 module_param_array(model, charp, NULL, 0444);
  63 MODULE_PARM_DESC(model, "Use the given board model.");
  64 module_param_array(position_fix, int, NULL, 0444);
  65 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF).");
  66
  67 MODULE_LICENSE("GPL");
  68 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  69                          "{Intel, ICH6M},"
  70                          "{Intel, ICH7},"
  71                          "{Intel, ESB2},"
  72                          "{ATI, SB450},"
  73                          "{VIA, VT8251},"
  74                          "{VIA, VT8237A},"
  75                          "{SiS, SIS966},"
  76                          "{ULI, M5461}}");
  77 MODULE_DESCRIPTION("Intel HDA driver");
  78
  79 #define SFX     "hda-intel: "
  80
  81 /*
  82  * registers
  83  */
  84 #define ICH6_REG_GCAP                   0x00
  85 #define ICH6_REG_VMIN                   0x02
  86 #define ICH6_REG_VMAJ                   0x03
  87 #define ICH6_REG_OUTPAY                 0x04
  88 #define ICH6_REG_INPAY                  0x06
  89 #define ICH6_REG_GCTL                   0x08
  90 #define ICH6_REG_WAKEEN                 0x0c
  91 #define ICH6_REG_STATESTS               0x0e
  92 #define ICH6_REG_GSTS                   0x10
  93 #define ICH6_REG_INTCTL                 0x20
  94 #define ICH6_REG_INTSTS                 0x24
  95 #define ICH6_REG_WALCLK                 0x30
  96 #define ICH6_REG_SYNC                   0x34
  97 #define ICH6_REG_CORBLBASE              0x40
  98 #define ICH6_REG_CORBUBASE              0x44
  99 #define ICH6_REG_CORBWP                 0x48
 100 #define ICH6_REG_CORBRP                 0x4A
 101 #define ICH6_REG_CORBCTL                0x4c
 102 #define ICH6_REG_CORBSTS                0x4d
 103 #define ICH6_REG_CORBSIZE               0x4e
 104
 105 #define ICH6_REG_RIRBLBASE              0x50
 106 #define ICH6_REG_RIRBUBASE              0x54
 107 #define ICH6_REG_RIRBWP                 0x58
 108 #define ICH6_REG_RINTCNT                0x5a
 109 #define ICH6_REG_RIRBCTL                0x5c
 110 #define ICH6_REG_RIRBSTS                0x5d
 111 #define ICH6_REG_RIRBSIZE               0x5e
 112
 113 #define ICH6_REG_IC                     0x60
 114 #define ICH6_REG_IR                     0x64
 115 #define ICH6_REG_IRS                    0x68
 116 #define   ICH6_IRS_VALID        (1<<1)
 117 #define   ICH6_IRS_BUSY         (1<<0)
 118
 119 #define ICH6_REG_DPLBASE                0x70
 120 #define ICH6_REG_DPUBASE                0x74
 121 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 122
 123 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 124 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 125
 126 /* stream register offsets from stream base */
 127 #define ICH6_REG_SD_CTL                 0x00
 128 #define ICH6_REG_SD_STS                 0x03
 129 #define ICH6_REG_SD_LPIB                0x04
 130 #define ICH6_REG_SD_CBL                 0x08
 131 #define ICH6_REG_SD_LVI                 0x0c
 132 #define ICH6_REG_SD_FIFOW               0x0e
 133 #define ICH6_REG_SD_FIFOSIZE            0x10
 134 #define ICH6_REG_SD_FORMAT              0x12
 135 #define ICH6_REG_SD_BDLPL               0x18
 136 #define ICH6_REG_SD_BDLPU               0x1c
 137
 138 /* PCI space */
 139 #define ICH6_PCIREG_TCSEL       0x44
 140
 141 /*
 142  * other constants
 143  */
 144
 145 /* max number of SDs */
 146 /* ICH, ATI and VIA have 4 playback and 4 capture */
 147 #define ICH6_CAPTURE_INDEX      0
 148 #define ICH6_NUM_CAPTURE        4
 149 #define ICH6_PLAYBACK_INDEX     4
 150 #define ICH6_NUM_PLAYBACK       4
 151
 152 /* ULI has 6 playback and 5 capture */
 153 #define ULI_CAPTURE_INDEX       0
 154 #define ULI_NUM_CAPTURE         5
 155 #define ULI_PLAYBACK_INDEX      5
 156 #define ULI_NUM_PLAYBACK        6
 157
 158 /* this number is statically defined for simplicity */
 159 #define MAX_AZX_DEV             16
 160
 161 /* max number of fragments - we may use more if allocating more pages for BDL */
 162 #define BDL_SIZE                PAGE_ALIGN(8192)
 163 #define AZX_MAX_FRAG            (BDL_SIZE / (MAX_AZX_DEV * 16))
 164 /* max buffer size - no h/w limit, you can increase as you like */
 165 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 166 /* max number of PCM devics per card */
 167 #define AZX_MAX_PCMS            8
 168
 169 /* RIRB int mask: overrun[2], response[0] */
 170 #define RIRB_INT_RESPONSE       0x01
 171 #define RIRB_INT_OVERRUN        0x04
 172 #define RIRB_INT_MASK           0x05
 173
 174 /* STATESTS int mask: SD2,SD1,SD0 */
 175 #define STATESTS_INT_MASK       0x07
 176 #define AZX_MAX_CODECS          4
 177
 178 /* SD_CTL bits */
 179 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 180 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 181 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 182 #define SD_CTL_STREAM_TAG_SHIFT 20
 183
 184 /* SD_CTL and SD_STS */
 185 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 186 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 187 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 188 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
 189
 190 /* SD_STS */
 191 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 192
 193 /* INTCTL and INTSTS */
 194 #define ICH6_INT_ALL_STREAM     0xff            /* all stream interrupts */
 195 #define ICH6_INT_CTRL_EN        0x40000000      /* controller interrupt enable bit */
 196 #define ICH6_INT_GLOBAL_EN      0x80000000      /* global interrupt enable bit */
 197
 198 /* GCTL unsolicited response enable bit */
 199 #define ICH6_GCTL_UREN          (1<<8)
 200
 201 /* GCTL reset bit */
 202 #define ICH6_GCTL_RESET         (1<<0)
 203
 204 /* CORB/RIRB control, read/write pointer */
 205 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 206 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 207 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 208 /* below are so far hardcoded - should read registers in future */
 209 #define ICH6_MAX_CORB_ENTRIES   256
 210 #define ICH6_MAX_RIRB_ENTRIES   256
 211
 212 /* position fix mode */
 213 enum {
 214         POS_FIX_FIFO,
 215         POS_FIX_NONE,
 216         POS_FIX_POSBUF
 217 };
 218
 219 /* Defines for ATI HD Audio support in SB450 south bridge */
 220 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 221 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 222
 223
 224 /*
 225  * Use CORB/RIRB for communication from/to codecs.
 226  * This is the way recommended by Intel (see below).
 227  */
 228 #define USE_CORB_RIRB
 229
 230 /*
 231  */
 232
 233 typedef struct snd_azx azx_t;
 234 typedef struct snd_azx_rb azx_rb_t;
 235 typedef struct snd_azx_dev azx_dev_t;
 236
 237 struct snd_azx_dev {
 238         u32 *bdl;                       /* virtual address of the BDL */
 239         dma_addr_t bdl_addr;            /* physical address of the BDL */
 240         volatile u32 *posbuf;                   /* position buffer pointer */
 241
 242         unsigned int bufsize;           /* size of the play buffer in bytes */
 243         unsigned int fragsize;          /* size of each period in bytes */
 244         unsigned int frags;             /* number for period in the play buffer */
 245         unsigned int fifo_size;         /* FIFO size */
 246
 247         void __iomem *sd_addr;          /* stream descriptor pointer */
 248
 249         u32 sd_int_sta_mask;            /* stream int status mask */
 250
 251         /* pcm support */
 252         snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
 253         unsigned int format_val;        /* format value to be set in the controller and the codec */
 254         unsigned char stream_tag;       /* assigned stream */
 255         unsigned char index;            /* stream index */
 256
 257         unsigned int opened: 1;
 258         unsigned int running: 1;
 259 };
 260
 261 /* CORB/RIRB */
 262 struct snd_azx_rb {
 263         u32 *buf;               /* CORB/RIRB buffer
 264                                  * Each CORB entry is 4byte, RIRB is 8byte
 265                                  */
 266         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 267         /* for RIRB */
 268         unsigned short rp, wp;  /* read/write pointers */
 269         int cmds;               /* number of pending requests */
 270         u32 res;                /* last read value */
 271 };
 272
 273 struct snd_azx {
 274         snd_card_t *card;
 275         struct pci_dev *pci;
 276
 277         /* chip type specific */
 278         int driver_type;
 279         int playback_streams;
 280         int playback_index_offset;
 281         int capture_streams;
 282         int capture_index_offset;
 283         int num_streams;
 284
 285         /* pci resources */
 286         unsigned long addr;
 287         void __iomem *remap_addr;
 288         int irq;
 289
 290         /* locks */
 291         spinlock_t reg_lock;
 292         struct semaphore open_mutex;
 293
 294         /* streams (x num_streams) */
 295         azx_dev_t *azx_dev;
 296
 297         /* PCM */
 298         unsigned int pcm_devs;
 299         snd_pcm_t *pcm[AZX_MAX_PCMS];
 300
 301         /* HD codec */
 302         unsigned short codec_mask;
 303         struct hda_bus *bus;
 304
 305         /* CORB/RIRB */
 306         azx_rb_t corb;
 307         azx_rb_t rirb;
 308
 309         /* BDL, CORB/RIRB and position buffers */
 310         struct snd_dma_buffer bdl;
 311         struct snd_dma_buffer rb;
 312         struct snd_dma_buffer posbuf;
 313
 314         /* flags */
 315         int position_fix;
 316         unsigned int initialized: 1;
 317 };
 318
 319 /* driver types */
 320 enum {
 321         AZX_DRIVER_ICH,
 322         AZX_DRIVER_ATI,
 323         AZX_DRIVER_VIA,
 324         AZX_DRIVER_SIS,
 325         AZX_DRIVER_ULI,
 326 };
 327
 328 static char *driver_short_names[] __devinitdata = {
 329         [AZX_DRIVER_ICH] = "HDA Intel",
 330         [AZX_DRIVER_ATI] = "HDA ATI SB",
 331         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 332         [AZX_DRIVER_SIS] = "HDA SIS966",
 333         [AZX_DRIVER_ULI] = "HDA ULI M5461"
 334 };
 335
 336 /*
 337  * macros for easy use
 338  */
 339 #define azx_writel(chip,reg,value) \
 340         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 341 #define azx_readl(chip,reg) \
 342         readl((chip)->remap_addr + ICH6_REG_##reg)
 343 #define azx_writew(chip,reg,value) \
 344         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 345 #define azx_readw(chip,reg) \
 346         readw((chip)->remap_addr + ICH6_REG_##reg)
 347 #define azx_writeb(chip,reg,value) \
 348         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 349 #define azx_readb(chip,reg) \
 350         readb((chip)->remap_addr + ICH6_REG_##reg)
 351
 352 #define azx_sd_writel(dev,reg,value) \
 353         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 354 #define azx_sd_readl(dev,reg) \
 355         readl((dev)->sd_addr + ICH6_REG_##reg)
 356 #define azx_sd_writew(dev,reg,value) \
 357         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 358 #define azx_sd_readw(dev,reg) \
 359         readw((dev)->sd_addr + ICH6_REG_##reg)
 360 #define azx_sd_writeb(dev,reg,value) \
 361         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 362 #define azx_sd_readb(dev,reg) \
 363         readb((dev)->sd_addr + ICH6_REG_##reg)
 364
 365 /* for pcm support */
 366 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
 367
 368 /* Get the upper 32bit of the given dma_addr_t
 369  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 370  */
 371 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 372
 373
 374 /*
 375  * Interface for HD codec
 376  */
 377
 378 #ifdef USE_CORB_RIRB
 379 /*
 380  * CORB / RIRB interface
 381  */
 382 static int azx_alloc_cmd_io(azx_t *chip)
 383 {
 384         int err;
 385
 386         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 387         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
 388                                   PAGE_SIZE, &chip->rb);
 389         if (err < 0) {
 390                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 391                 return err;
 392         }
 393         return 0;
 394 }
 395
 396 static void azx_init_cmd_io(azx_t *chip)
 397 {
 398         /* CORB set up */
 399         chip->corb.addr = chip->rb.addr;
 400         chip->corb.buf = (u32 *)chip->rb.area;
 401         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 402         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 403
 404         /* set the corb size to 256 entries (ULI requires explicitly) */
 405         azx_writeb(chip, CORBSIZE, 0x02);
 406         /* set the corb write pointer to 0 */
 407         azx_writew(chip, CORBWP, 0);
 408         /* reset the corb hw read pointer */
 409         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 410         /* enable corb dma */
 411         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 412
 413         /* RIRB set up */
 414         chip->rirb.addr = chip->rb.addr + 2048;
 415         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 416         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 417         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 418
 419         /* set the rirb size to 256 entries (ULI requires explicitly) */
 420         azx_writeb(chip, RIRBSIZE, 0x02);
 421         /* reset the rirb hw write pointer */
 422         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 423         /* set N=1, get RIRB response interrupt for new entry */
 424         azx_writew(chip, RINTCNT, 1);
 425         /* enable rirb dma and response irq */
 426 #ifdef USE_CORB_RIRB
 427         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 428 #else
 429         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
 430 #endif
 431         chip->rirb.rp = chip->rirb.cmds = 0;
 432 }
 433
 434 static void azx_free_cmd_io(azx_t *chip)
 435 {
 436         /* disable ringbuffer DMAs */
 437         azx_writeb(chip, RIRBCTL, 0);
 438         azx_writeb(chip, CORBCTL, 0);
 439 }
 440
 441 /* send a command */
 442 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 443                         unsigned int verb, unsigned int para)
 444 {
 445         azx_t *chip = codec->bus->private_data;
 446         unsigned int wp;
 447         u32 val;
 448
 449         val = (u32)(codec->addr & 0x0f) << 28;
 450         val |= (u32)direct << 27;
 451         val |= (u32)nid << 20;
 452         val |= verb << 8;
 453         val |= para;
 454
 455         /* add command to corb */
 456         wp = azx_readb(chip, CORBWP);
 457         wp++;
 458         wp %= ICH6_MAX_CORB_ENTRIES;
 459
 460         spin_lock_irq(&chip->reg_lock);
 461         chip->rirb.cmds++;
 462         chip->corb.buf[wp] = cpu_to_le32(val);
 463         azx_writel(chip, CORBWP, wp);
 464         spin_unlock_irq(&chip->reg_lock);
 465
 466         return 0;
 467 }
 468
 469 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 470
 471 /* retrieve RIRB entry - called from interrupt handler */
 472 static void azx_update_rirb(azx_t *chip)
 473 {
 474         unsigned int rp, wp;
 475         u32 res, res_ex;
 476
 477         wp = azx_readb(chip, RIRBWP);
 478         if (wp == chip->rirb.wp)
 479                 return;
 480         chip->rirb.wp = wp;
 481
 482         while (chip->rirb.rp != wp) {
 483                 chip->rirb.rp++;
 484                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 485
 486                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 487                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 488                 res = le32_to_cpu(chip->rirb.buf[rp]);
 489                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 490                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 491                 else if (chip->rirb.cmds) {
 492                         chip->rirb.cmds--;
 493                         chip->rirb.res = res;
 494                 }
 495         }
 496 }
 497
 498 /* receive a response */
 499 static unsigned int azx_get_response(struct hda_codec *codec)
 500 {
 501         azx_t *chip = codec->bus->private_data;
 502         int timeout = 50;
 503
 504         while (chip->rirb.cmds) {
 505                 if (! --timeout) {
 506                         snd_printk(KERN_ERR "azx_get_response timeout\n");
 507                         chip->rirb.rp = azx_readb(chip, RIRBWP);
 508                         chip->rirb.cmds = 0;
 509                         return -1;
 510                 }
 511                 msleep(1);
 512         }
 513         return chip->rirb.res; /* the last value */
 514 }
 515
 516 #else
 517 /*
 518  * Use the single immediate command instead of CORB/RIRB for simplicity
 519  *
 520  * Note: according to Intel, this is not preferred use.  The command was
 521  *       intended for the BIOS only, and may get confused with unsolicited
 522  *       responses.  So, we shouldn't use it for normal operation from the
 523  *       driver.
 524  *       I left the codes, however, for debugging/testing purposes.
 525  */
 526
 527 #define azx_alloc_cmd_io(chip)  0
 528 #define azx_init_cmd_io(chip)
 529 #define azx_free_cmd_io(chip)
 530
 531 /* send a command */
 532 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 533                         unsigned int verb, unsigned int para)
 534 {
 535         azx_t *chip = codec->bus->private_data;
 536         u32 val;
 537         int timeout = 50;
 538
 539         val = (u32)(codec->addr & 0x0f) << 28;
 540         val |= (u32)direct << 27;
 541         val |= (u32)nid << 20;
 542         val |= verb << 8;
 543         val |= para;
 544
 545         while (timeout--) {
 546                 /* check ICB busy bit */
 547                 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
 548                         /* Clear IRV valid bit */
 549                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
 550                         azx_writel(chip, IC, val);
 551                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
 552                         return 0;
 553                 }
 554                 udelay(1);
 555         }
 556         snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
 557         return -EIO;
 558 }
 559
 560 /* receive a response */
 561 static unsigned int azx_get_response(struct hda_codec *codec)
 562 {
 563         azx_t *chip = codec->bus->private_data;
 564         int timeout = 50;
 565
 566         while (timeout--) {
 567                 /* check IRV busy bit */
 568                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 569                         return azx_readl(chip, IR);
 570                 udelay(1);
 571         }
 572         snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
 573         return (unsigned int)-1;
 574 }
 575
 576 #define azx_update_rirb(chip)
 577
 578 #endif /* USE_CORB_RIRB */
 579
 580 /* reset codec link */
 581 static int azx_reset(azx_t *chip)
 582 {
 583         int count;
 584
 585         /* reset controller */
 586         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 587
 588         count = 50;
 589         while (azx_readb(chip, GCTL) && --count)
 590                 msleep(1);
 591
 592         /* delay for >= 100us for codec PLL to settle per spec
 593          * Rev 0.9 section 5.5.1
 594          */
 595         msleep(1);
 596
 597         /* Bring controller out of reset */
 598         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 599
 600         count = 50;
 601         while (! azx_readb(chip, GCTL) && --count)
 602                 msleep(1);
 603
 604         /* Brent Chartrand said to wait >= 540us for codecs to intialize */
 605         msleep(1);
 606
 607         /* check to see if controller is ready */
 608         if (! azx_readb(chip, GCTL)) {
 609                 snd_printd("azx_reset: controller not ready!\n");
 610                 return -EBUSY;
 611         }
 612
 613         /* Accept unsolicited responses */
 614         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 615
 616         /* detect codecs */
 617         if (! chip->codec_mask) {
 618                 chip->codec_mask = azx_readw(chip, STATESTS);
 619                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 620         }
 621
 622         return 0;
 623 }
 624
 625
 626 /*
 627  * Lowlevel interface
 628  */
 629
 630 /* enable interrupts */
 631 static void azx_int_enable(azx_t *chip)
 632 {
 633         /* enable controller CIE and GIE */
 634         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 635                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 636 }
 637
 638 /* disable interrupts */
 639 static void azx_int_disable(azx_t *chip)
 640 {
 641         int i;
 642
 643         /* disable interrupts in stream descriptor */
 644         for (i = 0; i < chip->num_streams; i++) {
 645                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 646                 azx_sd_writeb(azx_dev, SD_CTL,
 647                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 648         }
 649
 650         /* disable SIE for all streams */
 651         azx_writeb(chip, INTCTL, 0);
 652
 653         /* disable controller CIE and GIE */
 654         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 655                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 656 }
 657
 658 /* clear interrupts */
 659 static void azx_int_clear(azx_t *chip)
 660 {
 661         int i;
 662
 663         /* clear stream status */
 664         for (i = 0; i < chip->num_streams; i++) {
 665                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 666                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 667         }
 668
 669         /* clear STATESTS */
 670         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 671
 672         /* clear rirb status */
 673         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 674
 675         /* clear int status */
 676         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 677 }
 678
 679 /* start a stream */
 680 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
 681 {
 682         /* enable SIE */
 683         azx_writeb(chip, INTCTL,
 684                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 685         /* set DMA start and interrupt mask */
 686         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 687                       SD_CTL_DMA_START | SD_INT_MASK);
 688 }
 689
 690 /* stop a stream */
 691 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
 692 {
 693         /* stop DMA */
 694         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 695                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 696         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 697         /* disable SIE */
 698         azx_writeb(chip, INTCTL,
 699                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 700 }
 701
 702
 703 /*
 704  * initialize the chip
 705  */
 706 static void azx_init_chip(azx_t *chip)
 707 {
 708         unsigned char tcsel_reg, ati_misc_cntl2;
 709
 710         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 711          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 712          * Ensuring these bits are 0 clears playback static on some HD Audio codecs
 713          */
 714         pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
 715         pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
 716
 717         /* reset controller */
 718         azx_reset(chip);
 719
 720         /* initialize interrupts */
 721         azx_int_clear(chip);
 722         azx_int_enable(chip);
 723
 724         /* initialize the codec command I/O */
 725         azx_init_cmd_io(chip);
 726
 727         if (chip->position_fix == POS_FIX_POSBUF) {
 728                 /* program the position buffer */
 729                 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 730                 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 731         }
 732
 733         /* For ATI SB450 azalia HD audio, we need to enable snoop */
 734         if (chip->driver_type == AZX_DRIVER_ATI) {
 735                 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 736                                      &ati_misc_cntl2);
 737                 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 738                                       (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 739         }
 740 }
 741
 742
 743 /*
 744  * interrupt handler
 745  */
 746 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
 747 {
 748         azx_t *chip = dev_id;
 749         azx_dev_t *azx_dev;
 750         u32 status;
 751         int i;
 752
 753         spin_lock(&chip->reg_lock);
 754
 755         status = azx_readl(chip, INTSTS);
 756         if (status == 0) {
 757                 spin_unlock(&chip->reg_lock);
 758                 return IRQ_NONE;
 759         }
 760
 761         for (i = 0; i < chip->num_streams; i++) {
 762                 azx_dev = &chip->azx_dev[i];
 763                 if (status & azx_dev->sd_int_sta_mask) {
 764                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 765                         if (azx_dev->substream && azx_dev->running) {
 766                                 spin_unlock(&chip->reg_lock);
 767                                 snd_pcm_period_elapsed(azx_dev->substream);
 768                                 spin_lock(&chip->reg_lock);
 769                         }
 770                 }
 771         }
 772
 773         /* clear rirb int */
 774         status = azx_readb(chip, RIRBSTS);
 775         if (status & RIRB_INT_MASK) {
 776                 if (status & RIRB_INT_RESPONSE)
 777                         azx_update_rirb(chip);
 778                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 779         }
 780
 781 #if 0
 782         /* clear state status int */
 783         if (azx_readb(chip, STATESTS) & 0x04)
 784                 azx_writeb(chip, STATESTS, 0x04);
 785 #endif
 786         spin_unlock(&chip->reg_lock);
 787
 788         return IRQ_HANDLED;
 789 }
 790
 791
 792 /*
 793  * set up BDL entries
 794  */
 795 static void azx_setup_periods(azx_dev_t *azx_dev)
 796 {
 797         u32 *bdl = azx_dev->bdl;
 798         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 799         int idx;
 800
 801         /* reset BDL address */
 802         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 803         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 804
 805         /* program the initial BDL entries */
 806         for (idx = 0; idx < azx_dev->frags; idx++) {
 807                 unsigned int off = idx << 2; /* 4 dword step */
 808                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 809                 /* program the address field of the BDL entry */
 810                 bdl[off] = cpu_to_le32((u32)addr);
 811                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 812
 813                 /* program the size field of the BDL entry */
 814                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 815
 816                 /* program the IOC to enable interrupt when buffer completes */
 817                 bdl[off+3] = cpu_to_le32(0x01);
 818         }
 819 }
 820
 821 /*
 822  * set up the SD for streaming
 823  */
 824 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
 825 {
 826         unsigned char val;
 827         int timeout;
 828
 829         /* make sure the run bit is zero for SD */
 830         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 831         /* reset stream */
 832         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 833         udelay(3);
 834         timeout = 300;
 835         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 836                --timeout)
 837                 ;
 838         val &= ~SD_CTL_STREAM_RESET;
 839         azx_sd_writeb(azx_dev, SD_CTL, val);
 840         udelay(3);
 841
 842         timeout = 300;
 843         /* waiting for hardware to report that the stream is out of reset */
 844         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 845                --timeout)
 846                 ;
 847
 848         /* program the stream_tag */
 849         azx_sd_writel(azx_dev, SD_CTL,
 850                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
 851                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
 852
 853         /* program the length of samples in cyclic buffer */
 854         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 855
 856         /* program the stream format */
 857         /* this value needs to be the same as the one programmed */
 858         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 859
 860         /* program the stream LVI (last valid index) of the BDL */
 861         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 862
 863         /* program the BDL address */
 864         /* lower BDL address */
 865         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
 866         /* upper BDL address */
 867         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
 868
 869         if (chip->position_fix == POS_FIX_POSBUF) {
 870                 /* enable the position buffer */
 871                 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
 872                         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
 873         }
 874
 875         /* set the interrupt enable bits in the descriptor control register */
 876         azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
 877
 878         return 0;
 879 }
 880
 881
 882 /*
 883  * Codec initialization
 884  */
 885
 886 static int __devinit azx_codec_create(azx_t *chip, const char *model)
 887 {
 888         struct hda_bus_template bus_temp;
 889         int c, codecs, err;
 890
 891         memset(&bus_temp, 0, sizeof(bus_temp));
 892         bus_temp.private_data = chip;
 893         bus_temp.modelname = model;
 894         bus_temp.pci = chip->pci;
 895         bus_temp.ops.command = azx_send_cmd;
 896         bus_temp.ops.get_response = azx_get_response;
 897
 898         if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
 899                 return err;
 900
 901         codecs = 0;
 902         for (c = 0; c < AZX_MAX_CODECS; c++) {
 903                 if (chip->codec_mask & (1 << c)) {
 904                         err = snd_hda_codec_new(chip->bus, c, NULL);
 905                         if (err < 0)
 906                                 continue;
 907                         codecs++;
 908                 }
 909         }
 910         if (! codecs) {
 911                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
 912                 return -ENXIO;
 913         }
 914
 915         return 0;
 916 }
 917
 918
 919 /*
 920  * PCM support
 921  */
 922
 923 /* assign a stream for the PCM */
 924 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
 925 {
 926         int dev, i, nums;
 927         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 928                 dev = chip->playback_index_offset;
 929                 nums = chip->playback_streams;
 930         } else {
 931                 dev = chip->capture_index_offset;
 932                 nums = chip->capture_streams;
 933         }
 934         for (i = 0; i < nums; i++, dev++)
 935                 if (! chip->azx_dev[dev].opened) {
 936                         chip->azx_dev[dev].opened = 1;
 937                         return &chip->azx_dev[dev];
 938                 }
 939         return NULL;
 940 }
 941
 942 /* release the assigned stream */
 943 static inline void azx_release_device(azx_dev_t *azx_dev)
 944 {
 945         azx_dev->opened = 0;
 946 }
 947
 948 static snd_pcm_hardware_t azx_pcm_hw = {
 949         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 950                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 951                                  SNDRV_PCM_INFO_MMAP_VALID |
 952                                  SNDRV_PCM_INFO_PAUSE /*|*/
 953                                  /*SNDRV_PCM_INFO_RESUME*/),
 954         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 955         .rates =                SNDRV_PCM_RATE_48000,
 956         .rate_min =             48000,
 957         .rate_max =             48000,
 958         .channels_min =         2,
 959         .channels_max =         2,
 960         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 961         .period_bytes_min =     128,
 962         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 963         .periods_min =          2,
 964         .periods_max =          AZX_MAX_FRAG,
 965         .fifo_size =            0,
 966 };
 967
 968 struct azx_pcm {
 969         azx_t *chip;
 970         struct hda_codec *codec;
 971         struct hda_pcm_stream *hinfo[2];
 972 };
 973
 974 static int azx_pcm_open(snd_pcm_substream_t *substream)
 975 {
 976         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 977         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 978         azx_t *chip = apcm->chip;
 979         azx_dev_t *azx_dev;
 980         snd_pcm_runtime_t *runtime = substream->runtime;
 981         unsigned long flags;
 982         int err;
 983
 984         down(&chip->open_mutex);
 985         azx_dev = azx_assign_device(chip, substream->stream);
 986         if (azx_dev == NULL) {
 987                 up(&chip->open_mutex);
 988                 return -EBUSY;
 989         }
 990         runtime->hw = azx_pcm_hw;
 991         runtime->hw.channels_min = hinfo->channels_min;
 992         runtime->hw.channels_max = hinfo->channels_max;
 993         runtime->hw.formats = hinfo->formats;
 994         runtime->hw.rates = hinfo->rates;
 995         snd_pcm_limit_hw_rates(runtime);
 996         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 997         if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
 998                 azx_release_device(azx_dev);
 999                 up(&chip->open_mutex);
1000                 return err;
1001         }
1002         spin_lock_irqsave(&chip->reg_lock, flags);
1003         azx_dev->substream = substream;
1004         azx_dev->running = 0;
1005         spin_unlock_irqrestore(&chip->reg_lock, flags);
1006
1007         runtime->private_data = azx_dev;
1008         up(&chip->open_mutex);
1009         return 0;
1010 }
1011
1012 static int azx_pcm_close(snd_pcm_substream_t *substream)
1013 {
1014         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1015         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1016         azx_t *chip = apcm->chip;
1017         azx_dev_t *azx_dev = get_azx_dev(substream);
1018         unsigned long flags;
1019
1020         down(&chip->open_mutex);
1021         spin_lock_irqsave(&chip->reg_lock, flags);
1022         azx_dev->substream = NULL;
1023         azx_dev->running = 0;
1024         spin_unlock_irqrestore(&chip->reg_lock, flags);
1025         azx_release_device(azx_dev);
1026         hinfo->ops.close(hinfo, apcm->codec, substream);
1027         up(&chip->open_mutex);
1028         return 0;
1029 }
1030
1031 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
1032 {
1033         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1034 }
1035
1036 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
1037 {
1038         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1039         azx_dev_t *azx_dev = get_azx_dev(substream);
1040         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1041
1042         /* reset BDL address */
1043         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1044         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1045         azx_sd_writel(azx_dev, SD_CTL, 0);
1046
1047         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1048
1049         return snd_pcm_lib_free_pages(substream);
1050 }
1051
1052 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
1053 {
1054         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1055         azx_t *chip = apcm->chip;
1056         azx_dev_t *azx_dev = get_azx_dev(substream);
1057         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1058         snd_pcm_runtime_t *runtime = substream->runtime;
1059
1060         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1061         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1062         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1063         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1064                                                          runtime->channels,
1065                                                          runtime->format,
1066                                                          hinfo->maxbps);
1067         if (! azx_dev->format_val) {
1068                 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1069                            runtime->rate, runtime->channels, runtime->format);
1070                 return -EINVAL;
1071         }
1072
1073         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1074                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1075         azx_setup_periods(azx_dev);
1076         azx_setup_controller(chip, azx_dev);
1077         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1078                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1079         else
1080                 azx_dev->fifo_size = 0;
1081
1082         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1083                                   azx_dev->format_val, substream);
1084 }
1085
1086 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1087 {
1088         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1089         azx_dev_t *azx_dev = get_azx_dev(substream);
1090         azx_t *chip = apcm->chip;
1091         int err = 0;
1092
1093         spin_lock(&chip->reg_lock);
1094         switch (cmd) {
1095         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1096         case SNDRV_PCM_TRIGGER_RESUME:
1097         case SNDRV_PCM_TRIGGER_START:
1098                 azx_stream_start(chip, azx_dev);
1099                 azx_dev->running = 1;
1100                 break;
1101         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1102         case SNDRV_PCM_TRIGGER_SUSPEND:
1103         case SNDRV_PCM_TRIGGER_STOP:
1104                 azx_stream_stop(chip, azx_dev);
1105                 azx_dev->running = 0;
1106                 break;
1107         default:
1108                 err = -EINVAL;
1109         }
1110         spin_unlock(&chip->reg_lock);
1111         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1112             cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1113             cmd == SNDRV_PCM_TRIGGER_STOP) {
1114                 int timeout = 5000;
1115                 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1116                         ;
1117         }
1118         return err;
1119 }
1120
1121 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1122 {
1123         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1124         azx_t *chip = apcm->chip;
1125         azx_dev_t *azx_dev = get_azx_dev(substream);
1126         unsigned int pos;
1127
1128         if (chip->position_fix == POS_FIX_POSBUF) {
1129                 /* use the position buffer */
1130                 pos = *azx_dev->posbuf;
1131         } else {
1132                 /* read LPIB */
1133                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1134                 if (chip->position_fix == POS_FIX_FIFO)
1135                         pos += azx_dev->fifo_size;
1136         }
1137         if (pos >= azx_dev->bufsize)
1138                 pos = 0;
1139         return bytes_to_frames(substream->runtime, pos);
1140 }
1141
1142 static snd_pcm_ops_t azx_pcm_ops = {
1143         .open = azx_pcm_open,
1144         .close = azx_pcm_close,
1145         .ioctl = snd_pcm_lib_ioctl,
1146         .hw_params = azx_pcm_hw_params,
1147         .hw_free = azx_pcm_hw_free,
1148         .prepare = azx_pcm_prepare,
1149         .trigger = azx_pcm_trigger,
1150         .pointer = azx_pcm_pointer,
1151 };
1152
1153 static void azx_pcm_free(snd_pcm_t *pcm)
1154 {
1155         kfree(pcm->private_data);
1156 }
1157
1158 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1159                                       struct hda_pcm *cpcm, int pcm_dev)
1160 {
1161         int err;
1162         snd_pcm_t *pcm;
1163         struct azx_pcm *apcm;
1164
1165         snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1166         snd_assert(cpcm->name, return -EINVAL);
1167
1168         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1169                           cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1170                           &pcm);
1171         if (err < 0)
1172                 return err;
1173         strcpy(pcm->name, cpcm->name);
1174         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1175         if (apcm == NULL)
1176                 return -ENOMEM;
1177         apcm->chip = chip;
1178         apcm->codec = codec;
1179         apcm->hinfo[0] = &cpcm->stream[0];
1180         apcm->hinfo[1] = &cpcm->stream[1];
1181         pcm->private_data = apcm;
1182         pcm->private_free = azx_pcm_free;
1183         if (cpcm->stream[0].substreams)
1184                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1185         if (cpcm->stream[1].substreams)
1186                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1187         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1188                                               snd_dma_pci_data(chip->pci),
1189                                               1024 * 64, 1024 * 128);
1190         chip->pcm[pcm_dev] = pcm;
1191         chip->pcm_devs = pcm_dev + 1;
1192
1193         return 0;
1194 }
1195
1196 static int __devinit azx_pcm_create(azx_t *chip)
1197 {
1198         struct list_head *p;
1199         struct hda_codec *codec;
1200         int c, err;
1201         int pcm_dev;
1202
1203         if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1204                 return err;
1205
1206         pcm_dev = 0;
1207         list_for_each(p, &chip->bus->codec_list) {
1208                 codec = list_entry(p, struct hda_codec, list);
1209                 for (c = 0; c < codec->num_pcms; c++) {
1210                         if (pcm_dev >= AZX_MAX_PCMS) {
1211                                 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1212                                 return -EINVAL;
1213                         }
1214                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1215                         if (err < 0)
1216                                 return err;
1217                         pcm_dev++;
1218                 }
1219         }
1220         return 0;
1221 }
1222
1223 /*
1224  * mixer creation - all stuff is implemented in hda module
1225  */
1226 static int __devinit azx_mixer_create(azx_t *chip)
1227 {
1228         return snd_hda_build_controls(chip->bus);
1229 }
1230
1231
1232 /*
1233  * initialize SD streams
1234  */
1235 static int __devinit azx_init_stream(azx_t *chip)
1236 {
1237         int i;
1238
1239         /* initialize each stream (aka device)
1240          * assign the starting bdl address to each stream (device) and initialize
1241          */
1242         for (i = 0; i < chip->num_streams; i++) {
1243                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1244                 azx_dev_t *azx_dev = &chip->azx_dev[i];
1245                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1246                 azx_dev->bdl_addr = chip->bdl.addr + off;
1247                 if (chip->position_fix == POS_FIX_POSBUF)
1248                         azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1249                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1250                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1251                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1252                 azx_dev->sd_int_sta_mask = 1 << i;
1253                 /* stream tag: must be non-zero and unique */
1254                 azx_dev->index = i;
1255                 azx_dev->stream_tag = i + 1;
1256         }
1257
1258         return 0;
1259 }
1260
1261
1262 #ifdef CONFIG_PM
1263 /*
1264  * power management
1265  */
1266 static int azx_suspend(snd_card_t *card, pm_message_t state)
1267 {
1268         azx_t *chip = card->pm_private_data;
1269         int i;
1270
1271         for (i = 0; i < chip->pcm_devs; i++)
1272                 if (chip->pcm[i])
1273                         snd_pcm_suspend_all(chip->pcm[i]);
1274         snd_hda_suspend(chip->bus, state);
1275         azx_free_cmd_io(chip);
1276         pci_disable_device(chip->pci);
1277         return 0;
1278 }
1279
1280 static int azx_resume(snd_card_t *card)
1281 {
1282         azx_t *chip = card->pm_private_data;
1283
1284         pci_enable_device(chip->pci);
1285         pci_set_master(chip->pci);
1286         azx_init_chip(chip);
1287         snd_hda_resume(chip->bus);
1288         return 0;
1289 }
1290 #endif /* CONFIG_PM */
1291
1292
1293 /*
1294  * destructor
1295  */
1296 static int azx_free(azx_t *chip)
1297 {
1298         if (chip->initialized) {
1299                 int i;
1300
1301                 for (i = 0; i < chip->num_streams; i++)
1302                         azx_stream_stop(chip, &chip->azx_dev[i]);
1303
1304                 /* disable interrupts */
1305                 azx_int_disable(chip);
1306                 azx_int_clear(chip);
1307
1308                 /* disable CORB/RIRB */
1309                 azx_free_cmd_io(chip);
1310
1311                 /* disable position buffer */
1312                 azx_writel(chip, DPLBASE, 0);
1313                 azx_writel(chip, DPUBASE, 0);
1314
1315                 /* wait a little for interrupts to finish */
1316                 msleep(1);
1317         }
1318
1319         if (chip->remap_addr)
1320                 iounmap(chip->remap_addr);
1321         if (chip->irq >= 0)
1322                 free_irq(chip->irq, (void*)chip);
1323
1324         if (chip->bdl.area)
1325                 snd_dma_free_pages(&chip->bdl);
1326         if (chip->rb.area)
1327                 snd_dma_free_pages(&chip->rb);
1328         if (chip->posbuf.area)
1329                 snd_dma_free_pages(&chip->posbuf);
1330         pci_release_regions(chip->pci);
1331         pci_disable_device(chip->pci);
1332         kfree(chip->azx_dev);
1333         kfree(chip);
1334
1335         return 0;
1336 }
1337
1338 static int azx_dev_free(snd_device_t *device)
1339 {
1340         return azx_free(device->device_data);
1341 }
1342
1343 /*
1344  * constructor
1345  */
1346 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
1347                                 int posfix, int driver_type,
1348                                 azx_t **rchip)
1349 {
1350         azx_t *chip;
1351         int err = 0;
1352         static snd_device_ops_t ops = {
1353                 .dev_free = azx_dev_free,
1354         };
1355
1356         *rchip = NULL;
1357
1358         if ((err = pci_enable_device(pci)) < 0)
1359                 return err;
1360
1361         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1362
1363         if (NULL == chip) {
1364                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1365                 pci_disable_device(pci);
1366                 return -ENOMEM;
1367         }
1368
1369         spin_lock_init(&chip->reg_lock);
1370         init_MUTEX(&chip->open_mutex);
1371         chip->card = card;
1372         chip->pci = pci;
1373         chip->irq = -1;
1374         chip->driver_type = driver_type;
1375
1376         chip->position_fix = posfix;
1377
1378 #if BITS_PER_LONG != 64
1379         /* Fix up base address on ULI M5461 */
1380         if (chip->driver_type == AZX_DRIVER_ULI) {
1381                 u16 tmp3;
1382                 pci_read_config_word(pci, 0x40, &tmp3);
1383                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1384                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1385         }
1386 #endif
1387
1388         if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1389                 kfree(chip);
1390                 pci_disable_device(pci);
1391                 return err;
1392         }
1393
1394         chip->addr = pci_resource_start(pci,0);
1395         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1396         if (chip->remap_addr == NULL) {
1397                 snd_printk(KERN_ERR SFX "ioremap error\n");
1398                 err = -ENXIO;
1399                 goto errout;
1400         }
1401
1402         if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1403                         "HDA Intel", (void*)chip)) {
1404                 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1405                 err = -EBUSY;
1406                 goto errout;
1407         }
1408         chip->irq = pci->irq;
1409
1410         pci_set_master(pci);
1411         synchronize_irq(chip->irq);
1412
1413         switch (chip->driver_type) {
1414         case AZX_DRIVER_ULI:
1415                 chip->playback_streams = ULI_NUM_PLAYBACK;
1416                 chip->capture_streams = ULI_NUM_CAPTURE;
1417                 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1418                 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1419                 break;
1420         default:
1421                 chip->playback_streams = ICH6_NUM_PLAYBACK;
1422                 chip->capture_streams = ICH6_NUM_CAPTURE;
1423                 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1424                 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1425                 break;
1426         }
1427         chip->num_streams = chip->playback_streams + chip->capture_streams;
1428         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1429         if (! chip->azx_dev) {
1430                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1431                 goto errout;
1432         }
1433
1434         /* allocate memory for the BDL for each stream */
1435         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1436                                        BDL_SIZE, &chip->bdl)) < 0) {
1437                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1438                 goto errout;
1439         }
1440         if (chip->position_fix == POS_FIX_POSBUF) {
1441                 /* allocate memory for the position buffer */
1442                 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1443                                                chip->num_streams * 8, &chip->posbuf)) < 0) {
1444                         snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1445                         goto errout;
1446                 }
1447         }
1448         /* allocate CORB/RIRB */
1449         if ((err = azx_alloc_cmd_io(chip)) < 0)
1450                 goto errout;
1451
1452         /* initialize streams */
1453         azx_init_stream(chip);
1454
1455         /* initialize chip */
1456         azx_init_chip(chip);
1457
1458         chip->initialized = 1;
1459
1460         /* codec detection */
1461         if (! chip->codec_mask) {
1462                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1463                 err = -ENODEV;
1464                 goto errout;
1465         }
1466
1467         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1468                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1469                 goto errout;
1470         }
1471
1472         strcpy(card->driver, "HDA-Intel");
1473         strcpy(card->shortname, driver_short_names[chip->driver_type]);
1474         sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1475
1476         *rchip = chip;
1477         return 0;
1478
1479  errout:
1480         azx_free(chip);
1481         return err;
1482 }
1483
1484 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1485 {
1486         static int dev;
1487         snd_card_t *card;
1488         azx_t *chip;
1489         int err = 0;
1490
1491         if (dev >= SNDRV_CARDS)
1492                 return -ENODEV;
1493         if (! enable[dev]) {
1494                 dev++;
1495                 return -ENOENT;
1496         }
1497
1498         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1499         if (NULL == card) {
1500                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1501                 return -ENOMEM;
1502         }
1503
1504         if ((err = azx_create(card, pci, position_fix[dev], pci_id->driver_data,
1505                               &chip)) < 0) {
1506                 snd_card_free(card);
1507                 return err;
1508         }
1509
1510         /* create codec instances */
1511         if ((err = azx_codec_create(chip, model[dev])) < 0) {
1512                 snd_card_free(card);
1513                 return err;
1514         }
1515
1516         /* create PCM streams */
1517         if ((err = azx_pcm_create(chip)) < 0) {
1518                 snd_card_free(card);
1519                 return err;
1520         }
1521
1522         /* create mixer controls */
1523         if ((err = azx_mixer_create(chip)) < 0) {
1524                 snd_card_free(card);
1525                 return err;
1526         }
1527
1528         snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1529         snd_card_set_dev(card, &pci->dev);
1530
1531         if ((err = snd_card_register(card)) < 0) {
1532                 snd_card_free(card);
1533                 return err;
1534         }
1535
1536         pci_set_drvdata(pci, card);
1537         dev++;
1538
1539         return err;
1540 }
1541
1542 static void __devexit azx_remove(struct pci_dev *pci)
1543 {
1544         snd_card_free(pci_get_drvdata(pci));
1545         pci_set_drvdata(pci, NULL);
1546 }
1547
1548 /* PCI IDs */
1549 static struct pci_device_id azx_ids[] = {
1550         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1551         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1552         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1553         { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1554         { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1555         { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1556         { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1557         { 0, }
1558 };
1559 MODULE_DEVICE_TABLE(pci, azx_ids);
1560
1561 /* pci_driver definition */
1562 static struct pci_driver driver = {
1563         .name = "HDA Intel",
1564         .id_table = azx_ids,
1565         .probe = azx_probe,
1566         .remove = __devexit_p(azx_remove),
1567         SND_PCI_PM_CALLBACKS
1568 };
1569
1570 static int __init alsa_card_azx_init(void)
1571 {
1572         return pci_register_driver(&driver);
1573 }
1574
1575 static void __exit alsa_card_azx_exit(void)
1576 {
1577         pci_unregister_driver(&driver);
1578 }
1579
1580 module_init(alsa_card_azx_init)
1581 module_exit(alsa_card_azx_exit)