git.oblomov.eu Git - linux-2.6/blob - drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #include <linux/if_vlan.h>
  39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50 #include <linux/log2.h>
  51
  52 #include "bnx2.h"
  53 #include "bnx2_fw.h"
  54 #include "bnx2_fw2.h"
  55
  56 #define FW_BUF_SIZE             0x10000
  57
  58 #define DRV_MODULE_NAME         "bnx2"
  59 #define PFX DRV_MODULE_NAME     ": "
  60 #define DRV_MODULE_VERSION      "1.8.0"
  61 #define DRV_MODULE_RELDATE      "Aug 14, 2008"
  62
  63 #define RUN_AT(x) (jiffies + (x))
  64
  65 /* Time in jiffies before concluding the transmitter is hung. */
  66 #define TX_TIMEOUT  (5*HZ)
  67
  68 static char version[] __devinitdata =
  69         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  70
  71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 static int disable_msi = 0;
  77
  78 module_param(disable_msi, int, 0);
  79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80
  81 typedef enum {
  82         BCM5706 = 0,
  83         NC370T,
  84         NC370I,
  85         BCM5706S,
  86         NC370F,
  87         BCM5708,
  88         BCM5708S,
  89         BCM5709,
  90         BCM5709S,
  91         BCM5716,
  92 } board_t;
  93
  94 /* indexed by board_t, above */
  95 static struct {
  96         char *name;
  97 } board_info[] __devinitdata = {
  98         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  99         { "HP NC370T Multifunction Gigabit Server Adapter" },
 100         { "HP NC370i Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 102         { "HP NC370F Multifunction Gigabit Server Adapter" },
 103         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 104         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 105         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 106         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 107         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 108         };
 109
 110 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 111         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 112           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 113         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 114           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 116           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 118           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 120           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 121         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 122           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 123         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 124           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 125         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 126           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 127         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 128           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 129         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 130           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 131         { 0, }
 132 };
 133
 134 static struct flash_spec flash_table[] =
 135 {
 136 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 137 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 138         /* Slow EEPROM */
 139         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 140          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 141          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 142          "EEPROM - slow"},
 143         /* Expansion entry 0001 */
 144         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 145          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 146          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 147          "Entry 0001"},
 148         /* Saifun SA25F010 (non-buffered flash) */
 149         /* strap, cfg1, & write1 need updates */
 150         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 151          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 152          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 153          "Non-buffered flash (128kB)"},
 154         /* Saifun SA25F020 (non-buffered flash) */
 155         /* strap, cfg1, & write1 need updates */
 156         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 158          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 159          "Non-buffered flash (256kB)"},
 160         /* Expansion entry 0100 */
 161         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 162          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 163          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 164          "Entry 0100"},
 165         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 166         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 169          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 170         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 171         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 172          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 173          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 174          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 175         /* Saifun SA25F005 (non-buffered flash) */
 176         /* strap, cfg1, & write1 need updates */
 177         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 178          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 179          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 180          "Non-buffered flash (64kB)"},
 181         /* Fast EEPROM */
 182         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 183          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 184          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 185          "EEPROM - fast"},
 186         /* Expansion entry 1001 */
 187         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 190          "Entry 1001"},
 191         /* Expansion entry 1010 */
 192         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 1010"},
 196         /* ATMEL AT45DB011B (buffered flash) */
 197         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 198          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 199          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 200          "Buffered flash (128kB)"},
 201         /* Expansion entry 1100 */
 202         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1100"},
 206         /* Expansion entry 1101 */
 207         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 208          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1101"},
 211         /* Ateml Expansion entry 1110 */
 212         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 215          "Entry 1110 (Atmel)"},
 216         /* ATMEL AT45DB021B (buffered flash) */
 217         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 218          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 219          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 220          "Buffered flash (256kB)"},
 221 };
 222
 223 static struct flash_spec flash_5709 = {
 224         .flags          = BNX2_NV_BUFFERED,
 225         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 226         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 227         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 228         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 229         .name           = "5709 Buffered flash (256kB)",
 230 };
 231
 232 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 233
 234 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 235 {
 236         u32 diff;
 237
 238         smp_mb();
 239
 240         /* The ring uses 256 indices for 255 entries, one of them
 241          * needs to be skipped.
 242          */
 243         diff = txr->tx_prod - txr->tx_cons;
 244         if (unlikely(diff >= TX_DESC_CNT)) {
 245                 diff &= 0xffff;
 246                 if (diff == TX_DESC_CNT)
 247                         diff = MAX_TX_DESC_CNT;
 248         }
 249         return (bp->tx_ring_size - diff);
 250 }
 251
 252 static u32
 253 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 254 {
 255         u32 val;
 256
 257         spin_lock_bh(&bp->indirect_lock);
 258         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 259         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 260         spin_unlock_bh(&bp->indirect_lock);
 261         return val;
 262 }
 263
 264 static void
 265 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 266 {
 267         spin_lock_bh(&bp->indirect_lock);
 268         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 269         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 270         spin_unlock_bh(&bp->indirect_lock);
 271 }
 272
 273 static void
 274 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 275 {
 276         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 277 }
 278
 279 static u32
 280 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 281 {
 282         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 283 }
 284
 285 static void
 286 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 287 {
 288         offset += cid_addr;
 289         spin_lock_bh(&bp->indirect_lock);
 290         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 291                 int i;
 292
 293                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 294                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 295                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 296                 for (i = 0; i < 5; i++) {
 297                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 298                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 299                                 break;
 300                         udelay(5);
 301                 }
 302         } else {
 303                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 304                 REG_WR(bp, BNX2_CTX_DATA, val);
 305         }
 306         spin_unlock_bh(&bp->indirect_lock);
 307 }
 308
 309 static int
 310 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 311 {
 312         u32 val1;
 313         int i, ret;
 314
 315         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 316                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 317                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 318
 319                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 320                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 321
 322                 udelay(40);
 323         }
 324
 325         val1 = (bp->phy_addr << 21) | (reg << 16) |
 326                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 327                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 328         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 329
 330         for (i = 0; i < 50; i++) {
 331                 udelay(10);
 332
 333                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 334                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 335                         udelay(5);
 336
 337                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 338                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 339
 340                         break;
 341                 }
 342         }
 343
 344         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 345                 *val = 0x0;
 346                 ret = -EBUSY;
 347         }
 348         else {
 349                 *val = val1;
 350                 ret = 0;
 351         }
 352
 353         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 354                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 355                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 356
 357                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 358                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 359
 360                 udelay(40);
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int
 367 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 368 {
 369         u32 val1;
 370         int i, ret;
 371
 372         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 373                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 374                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 375
 376                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 377                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 378
 379                 udelay(40);
 380         }
 381
 382         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 383                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 384                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 385         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 386
 387         for (i = 0; i < 50; i++) {
 388                 udelay(10);
 389
 390                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 391                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 392                         udelay(5);
 393                         break;
 394                 }
 395         }
 396
 397         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 398                 ret = -EBUSY;
 399         else
 400                 ret = 0;
 401
 402         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 403                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 404                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 405
 406                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 407                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 408
 409                 udelay(40);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static void
 416 bnx2_disable_int(struct bnx2 *bp)
 417 {
 418         int i;
 419         struct bnx2_napi *bnapi;
 420
 421         for (i = 0; i < bp->irq_nvecs; i++) {
 422                 bnapi = &bp->bnx2_napi[i];
 423                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 424                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 425         }
 426         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 427 }
 428
 429 static void
 430 bnx2_enable_int(struct bnx2 *bp)
 431 {
 432         int i;
 433         struct bnx2_napi *bnapi;
 434
 435         for (i = 0; i < bp->irq_nvecs; i++) {
 436                 bnapi = &bp->bnx2_napi[i];
 437
 438                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 439                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 440                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 441                        bnapi->last_status_idx);
 442
 443                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 444                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 445                        bnapi->last_status_idx);
 446         }
 447         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 448 }
 449
 450 static void
 451 bnx2_disable_int_sync(struct bnx2 *bp)
 452 {
 453         int i;
 454
 455         atomic_inc(&bp->intr_sem);
 456         bnx2_disable_int(bp);
 457         for (i = 0; i < bp->irq_nvecs; i++)
 458                 synchronize_irq(bp->irq_tbl[i].vector);
 459 }
 460
 461 static void
 462 bnx2_napi_disable(struct bnx2 *bp)
 463 {
 464         int i;
 465
 466         for (i = 0; i < bp->irq_nvecs; i++)
 467                 napi_disable(&bp->bnx2_napi[i].napi);
 468 }
 469
 470 static void
 471 bnx2_napi_enable(struct bnx2 *bp)
 472 {
 473         int i;
 474
 475         for (i = 0; i < bp->irq_nvecs; i++)
 476                 napi_enable(&bp->bnx2_napi[i].napi);
 477 }
 478
 479 static void
 480 bnx2_netif_stop(struct bnx2 *bp)
 481 {
 482         bnx2_disable_int_sync(bp);
 483         if (netif_running(bp->dev)) {
 484                 bnx2_napi_disable(bp);
 485                 netif_tx_disable(bp->dev);
 486                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 487         }
 488 }
 489
 490 static void
 491 bnx2_netif_start(struct bnx2 *bp)
 492 {
 493         if (atomic_dec_and_test(&bp->intr_sem)) {
 494                 if (netif_running(bp->dev)) {
 495                         netif_tx_wake_all_queues(bp->dev);
 496                         bnx2_napi_enable(bp);
 497                         bnx2_enable_int(bp);
 498                 }
 499         }
 500 }
 501
 502 static void
 503 bnx2_free_tx_mem(struct bnx2 *bp)
 504 {
 505         int i;
 506
 507         for (i = 0; i < bp->num_tx_rings; i++) {
 508                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 509                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 510
 511                 if (txr->tx_desc_ring) {
 512                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 513                                             txr->tx_desc_ring,
 514                                             txr->tx_desc_mapping);
 515                         txr->tx_desc_ring = NULL;
 516                 }
 517                 kfree(txr->tx_buf_ring);
 518                 txr->tx_buf_ring = NULL;
 519         }
 520 }
 521
 522 static void
 523 bnx2_free_rx_mem(struct bnx2 *bp)
 524 {
 525         int i;
 526
 527         for (i = 0; i < bp->num_rx_rings; i++) {
 528                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 529                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 530                 int j;
 531
 532                 for (j = 0; j < bp->rx_max_ring; j++) {
 533                         if (rxr->rx_desc_ring[j])
 534                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 535                                                     rxr->rx_desc_ring[j],
 536                                                     rxr->rx_desc_mapping[j]);
 537                         rxr->rx_desc_ring[j] = NULL;
 538                 }
 539                 if (rxr->rx_buf_ring)
 540                         vfree(rxr->rx_buf_ring);
 541                 rxr->rx_buf_ring = NULL;
 542
 543                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 544                         if (rxr->rx_pg_desc_ring[j])
 545                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 546                                                     rxr->rx_pg_desc_ring[i],
 547                                                     rxr->rx_pg_desc_mapping[i]);
 548                         rxr->rx_pg_desc_ring[i] = NULL;
 549                 }
 550                 if (rxr->rx_pg_ring)
 551                         vfree(rxr->rx_pg_ring);
 552                 rxr->rx_pg_ring = NULL;
 553         }
 554 }
 555
 556 static int
 557 bnx2_alloc_tx_mem(struct bnx2 *bp)
 558 {
 559         int i;
 560
 561         for (i = 0; i < bp->num_tx_rings; i++) {
 562                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 563                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 564
 565                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 566                 if (txr->tx_buf_ring == NULL)
 567                         return -ENOMEM;
 568
 569                 txr->tx_desc_ring =
 570                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 571                                              &txr->tx_desc_mapping);
 572                 if (txr->tx_desc_ring == NULL)
 573                         return -ENOMEM;
 574         }
 575         return 0;
 576 }
 577
 578 static int
 579 bnx2_alloc_rx_mem(struct bnx2 *bp)
 580 {
 581         int i;
 582
 583         for (i = 0; i < bp->num_rx_rings; i++) {
 584                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 585                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 586                 int j;
 587
 588                 rxr->rx_buf_ring =
 589                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 590                 if (rxr->rx_buf_ring == NULL)
 591                         return -ENOMEM;
 592
 593                 memset(rxr->rx_buf_ring, 0,
 594                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 595
 596                 for (j = 0; j < bp->rx_max_ring; j++) {
 597                         rxr->rx_desc_ring[j] =
 598                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 599                                                      &rxr->rx_desc_mapping[j]);
 600                         if (rxr->rx_desc_ring[j] == NULL)
 601                                 return -ENOMEM;
 602
 603                 }
 604
 605                 if (bp->rx_pg_ring_size) {
 606                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 607                                                   bp->rx_max_pg_ring);
 608                         if (rxr->rx_pg_ring == NULL)
 609                                 return -ENOMEM;
 610
 611                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 612                                bp->rx_max_pg_ring);
 613                 }
 614
 615                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 616                         rxr->rx_pg_desc_ring[j] =
 617                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 618                                                 &rxr->rx_pg_desc_mapping[j]);
 619                         if (rxr->rx_pg_desc_ring[j] == NULL)
 620                                 return -ENOMEM;
 621
 622                 }
 623         }
 624         return 0;
 625 }
 626
 627 static void
 628 bnx2_free_mem(struct bnx2 *bp)
 629 {
 630         int i;
 631         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 632
 633         bnx2_free_tx_mem(bp);
 634         bnx2_free_rx_mem(bp);
 635
 636         for (i = 0; i < bp->ctx_pages; i++) {
 637                 if (bp->ctx_blk[i]) {
 638                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 639                                             bp->ctx_blk[i],
 640                                             bp->ctx_blk_mapping[i]);
 641                         bp->ctx_blk[i] = NULL;
 642                 }
 643         }
 644         if (bnapi->status_blk.msi) {
 645                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 646                                     bnapi->status_blk.msi,
 647                                     bp->status_blk_mapping);
 648                 bnapi->status_blk.msi = NULL;
 649                 bp->stats_blk = NULL;
 650         }
 651 }
 652
 653 static int
 654 bnx2_alloc_mem(struct bnx2 *bp)
 655 {
 656         int i, status_blk_size, err;
 657         struct bnx2_napi *bnapi;
 658         void *status_blk;
 659
 660         /* Combine status and statistics blocks into one allocation. */
 661         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 662         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 663                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 664                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 665         bp->status_stats_size = status_blk_size +
 666                                 sizeof(struct statistics_block);
 667
 668         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 669                                           &bp->status_blk_mapping);
 670         if (status_blk == NULL)
 671                 goto alloc_mem_err;
 672
 673         memset(status_blk, 0, bp->status_stats_size);
 674
 675         bnapi = &bp->bnx2_napi[0];
 676         bnapi->status_blk.msi = status_blk;
 677         bnapi->hw_tx_cons_ptr =
 678                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 679         bnapi->hw_rx_cons_ptr =
 680                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 681         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 682                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 683                         struct status_block_msix *sblk;
 684
 685                         bnapi = &bp->bnx2_napi[i];
 686
 687                         sblk = (void *) (status_blk +
 688                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 689                         bnapi->status_blk.msix = sblk;
 690                         bnapi->hw_tx_cons_ptr =
 691                                 &sblk->status_tx_quick_consumer_index;
 692                         bnapi->hw_rx_cons_ptr =
 693                                 &sblk->status_rx_quick_consumer_index;
 694                         bnapi->int_num = i << 24;
 695                 }
 696         }
 697
 698         bp->stats_blk = status_blk + status_blk_size;
 699
 700         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 701
 702         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 703                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 704                 if (bp->ctx_pages == 0)
 705                         bp->ctx_pages = 1;
 706                 for (i = 0; i < bp->ctx_pages; i++) {
 707                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 708                                                 BCM_PAGE_SIZE,
 709                                                 &bp->ctx_blk_mapping[i]);
 710                         if (bp->ctx_blk[i] == NULL)
 711                                 goto alloc_mem_err;
 712                 }
 713         }
 714
 715         err = bnx2_alloc_rx_mem(bp);
 716         if (err)
 717                 goto alloc_mem_err;
 718
 719         err = bnx2_alloc_tx_mem(bp);
 720         if (err)
 721                 goto alloc_mem_err;
 722
 723         return 0;
 724
 725 alloc_mem_err:
 726         bnx2_free_mem(bp);
 727         return -ENOMEM;
 728 }
 729
 730 static void
 731 bnx2_report_fw_link(struct bnx2 *bp)
 732 {
 733         u32 fw_link_status = 0;
 734
 735         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 736                 return;
 737
 738         if (bp->link_up) {
 739                 u32 bmsr;
 740
 741                 switch (bp->line_speed) {
 742                 case SPEED_10:
 743                         if (bp->duplex == DUPLEX_HALF)
 744                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 745                         else
 746                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 747                         break;
 748                 case SPEED_100:
 749                         if (bp->duplex == DUPLEX_HALF)
 750                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 751                         else
 752                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 753                         break;
 754                 case SPEED_1000:
 755                         if (bp->duplex == DUPLEX_HALF)
 756                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 757                         else
 758                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 759                         break;
 760                 case SPEED_2500:
 761                         if (bp->duplex == DUPLEX_HALF)
 762                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 763                         else
 764                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 765                         break;
 766                 }
 767
 768                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 769
 770                 if (bp->autoneg) {
 771                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 772
 773                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 774                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 775
 776                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 777                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 778                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 779                         else
 780                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 781                 }
 782         }
 783         else
 784                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 785
 786         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 787 }
 788
 789 static char *
 790 bnx2_xceiver_str(struct bnx2 *bp)
 791 {
 792         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 793                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 794                  "Copper"));
 795 }
 796
 797 static void
 798 bnx2_report_link(struct bnx2 *bp)
 799 {
 800         if (bp->link_up) {
 801                 netif_carrier_on(bp->dev);
 802                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 803                        bnx2_xceiver_str(bp));
 804
 805                 printk("%d Mbps ", bp->line_speed);
 806
 807                 if (bp->duplex == DUPLEX_FULL)
 808                         printk("full duplex");
 809                 else
 810                         printk("half duplex");
 811
 812                 if (bp->flow_ctrl) {
 813                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 814                                 printk(", receive ");
 815                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 816                                         printk("& transmit ");
 817                         }
 818                         else {
 819                                 printk(", transmit ");
 820                         }
 821                         printk("flow control ON");
 822                 }
 823                 printk("\n");
 824         }
 825         else {
 826                 netif_carrier_off(bp->dev);
 827                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 828                        bnx2_xceiver_str(bp));
 829         }
 830
 831         bnx2_report_fw_link(bp);
 832 }
 833
 834 static void
 835 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 836 {
 837         u32 local_adv, remote_adv;
 838
 839         bp->flow_ctrl = 0;
 840         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 841                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 842
 843                 if (bp->duplex == DUPLEX_FULL) {
 844                         bp->flow_ctrl = bp->req_flow_ctrl;
 845                 }
 846                 return;
 847         }
 848
 849         if (bp->duplex != DUPLEX_FULL) {
 850                 return;
 851         }
 852
 853         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 854             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 855                 u32 val;
 856
 857                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 858                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 859                         bp->flow_ctrl |= FLOW_CTRL_TX;
 860                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 861                         bp->flow_ctrl |= FLOW_CTRL_RX;
 862                 return;
 863         }
 864
 865         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 866         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 867
 868         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 869                 u32 new_local_adv = 0;
 870                 u32 new_remote_adv = 0;
 871
 872                 if (local_adv & ADVERTISE_1000XPAUSE)
 873                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 874                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 875                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 876                 if (remote_adv & ADVERTISE_1000XPAUSE)
 877                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 878                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 879                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 880
 881                 local_adv = new_local_adv;
 882                 remote_adv = new_remote_adv;
 883         }
 884
 885         /* See Table 28B-3 of 802.3ab-1999 spec. */
 886         if (local_adv & ADVERTISE_PAUSE_CAP) {
 887                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 888                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 889                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 890                         }
 891                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 892                                 bp->flow_ctrl = FLOW_CTRL_RX;
 893                         }
 894                 }
 895                 else {
 896                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 897                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 898                         }
 899                 }
 900         }
 901         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 902                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 903                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 904
 905                         bp->flow_ctrl = FLOW_CTRL_TX;
 906                 }
 907         }
 908 }
 909
 910 static int
 911 bnx2_5709s_linkup(struct bnx2 *bp)
 912 {
 913         u32 val, speed;
 914
 915         bp->link_up = 1;
 916
 917         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 918         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 919         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 920
 921         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 922                 bp->line_speed = bp->req_line_speed;
 923                 bp->duplex = bp->req_duplex;
 924                 return 0;
 925         }
 926         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 927         switch (speed) {
 928                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 929                         bp->line_speed = SPEED_10;
 930                         break;
 931                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 932                         bp->line_speed = SPEED_100;
 933                         break;
 934                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 935                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 936                         bp->line_speed = SPEED_1000;
 937                         break;
 938                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 939                         bp->line_speed = SPEED_2500;
 940                         break;
 941         }
 942         if (val & MII_BNX2_GP_TOP_AN_FD)
 943                 bp->duplex = DUPLEX_FULL;
 944         else
 945                 bp->duplex = DUPLEX_HALF;
 946         return 0;
 947 }
 948
 949 static int
 950 bnx2_5708s_linkup(struct bnx2 *bp)
 951 {
 952         u32 val;
 953
 954         bp->link_up = 1;
 955         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 956         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 957                 case BCM5708S_1000X_STAT1_SPEED_10:
 958                         bp->line_speed = SPEED_10;
 959                         break;
 960                 case BCM5708S_1000X_STAT1_SPEED_100:
 961                         bp->line_speed = SPEED_100;
 962                         break;
 963                 case BCM5708S_1000X_STAT1_SPEED_1G:
 964                         bp->line_speed = SPEED_1000;
 965                         break;
 966                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 967                         bp->line_speed = SPEED_2500;
 968                         break;
 969         }
 970         if (val & BCM5708S_1000X_STAT1_FD)
 971                 bp->duplex = DUPLEX_FULL;
 972         else
 973                 bp->duplex = DUPLEX_HALF;
 974
 975         return 0;
 976 }
 977
 978 static int
 979 bnx2_5706s_linkup(struct bnx2 *bp)
 980 {
 981         u32 bmcr, local_adv, remote_adv, common;
 982
 983         bp->link_up = 1;
 984         bp->line_speed = SPEED_1000;
 985
 986         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 987         if (bmcr & BMCR_FULLDPLX) {
 988                 bp->duplex = DUPLEX_FULL;
 989         }
 990         else {
 991                 bp->duplex = DUPLEX_HALF;
 992         }
 993
 994         if (!(bmcr & BMCR_ANENABLE)) {
 995                 return 0;
 996         }
 997
 998         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 999         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1000
1001         common = local_adv & remote_adv;
1002         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1003
1004                 if (common & ADVERTISE_1000XFULL) {
1005                         bp->duplex = DUPLEX_FULL;
1006                 }
1007                 else {
1008                         bp->duplex = DUPLEX_HALF;
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int
1016 bnx2_copper_linkup(struct bnx2 *bp)
1017 {
1018         u32 bmcr;
1019
1020         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1021         if (bmcr & BMCR_ANENABLE) {
1022                 u32 local_adv, remote_adv, common;
1023
1024                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1026
1027                 common = local_adv & (remote_adv >> 2);
1028                 if (common & ADVERTISE_1000FULL) {
1029                         bp->line_speed = SPEED_1000;
1030                         bp->duplex = DUPLEX_FULL;
1031                 }
1032                 else if (common & ADVERTISE_1000HALF) {
1033                         bp->line_speed = SPEED_1000;
1034                         bp->duplex = DUPLEX_HALF;
1035                 }
1036                 else {
1037                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1039
1040                         common = local_adv & remote_adv;
1041                         if (common & ADVERTISE_100FULL) {
1042                                 bp->line_speed = SPEED_100;
1043                                 bp->duplex = DUPLEX_FULL;
1044                         }
1045                         else if (common & ADVERTISE_100HALF) {
1046                                 bp->line_speed = SPEED_100;
1047                                 bp->duplex = DUPLEX_HALF;
1048                         }
1049                         else if (common & ADVERTISE_10FULL) {
1050                                 bp->line_speed = SPEED_10;
1051                                 bp->duplex = DUPLEX_FULL;
1052                         }
1053                         else if (common & ADVERTISE_10HALF) {
1054                                 bp->line_speed = SPEED_10;
1055                                 bp->duplex = DUPLEX_HALF;
1056                         }
1057                         else {
1058                                 bp->line_speed = 0;
1059                                 bp->link_up = 0;
1060                         }
1061                 }
1062         }
1063         else {
1064                 if (bmcr & BMCR_SPEED100) {
1065                         bp->line_speed = SPEED_100;
1066                 }
1067                 else {
1068                         bp->line_speed = SPEED_10;
1069                 }
1070                 if (bmcr & BMCR_FULLDPLX) {
1071                         bp->duplex = DUPLEX_FULL;
1072                 }
1073                 else {
1074                         bp->duplex = DUPLEX_HALF;
1075                 }
1076         }
1077
1078         return 0;
1079 }
1080
1081 static void
1082 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1083 {
1084         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1085
1086         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1088         val |= 0x02 << 8;
1089
1090         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091                 u32 lo_water, hi_water;
1092
1093                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1095                 else
1096                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097                 if (lo_water >= bp->rx_ring_size)
1098                         lo_water = 0;
1099
1100                 hi_water = bp->rx_ring_size / 4;
1101
1102                 if (hi_water <= lo_water)
1103                         lo_water = 0;
1104
1105                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1107
1108                 if (hi_water > 0xf)
1109                         hi_water = 0xf;
1110                 else if (hi_water == 0)
1111                         lo_water = 0;
1112                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1113         }
1114         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1115 }
1116
1117 static void
1118 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119 {
1120         int i;
1121         u32 cid;
1122
1123         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124                 if (i == 1)
1125                         cid = RX_RSS_CID;
1126                 bnx2_init_rx_context(bp, cid);
1127         }
1128 }
1129
1130 static void
1131 bnx2_set_mac_link(struct bnx2 *bp)
1132 {
1133         u32 val;
1134
1135         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137                 (bp->duplex == DUPLEX_HALF)) {
1138                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1139         }
1140
1141         /* Configure the EMAC mode register. */
1142         val = REG_RD(bp, BNX2_EMAC_MODE);
1143
1144         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1145                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1146                 BNX2_EMAC_MODE_25G_MODE);
1147
1148         if (bp->link_up) {
1149                 switch (bp->line_speed) {
1150                         case SPEED_10:
1151                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1153                                         break;
1154                                 }
1155                                 /* fall through */
1156                         case SPEED_100:
1157                                 val |= BNX2_EMAC_MODE_PORT_MII;
1158                                 break;
1159                         case SPEED_2500:
1160                                 val |= BNX2_EMAC_MODE_25G_MODE;
1161                                 /* fall through */
1162                         case SPEED_1000:
1163                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1164                                 break;
1165                 }
1166         }
1167         else {
1168                 val |= BNX2_EMAC_MODE_PORT_GMII;
1169         }
1170
1171         /* Set the MAC to operate in the appropriate duplex mode. */
1172         if (bp->duplex == DUPLEX_HALF)
1173                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174         REG_WR(bp, BNX2_EMAC_MODE, val);
1175
1176         /* Enable/disable rx PAUSE. */
1177         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1178
1179         if (bp->flow_ctrl & FLOW_CTRL_RX)
1180                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1182
1183         /* Enable/disable tx PAUSE. */
1184         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1186
1187         if (bp->flow_ctrl & FLOW_CTRL_TX)
1188                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1190
1191         /* Acknowledge the interrupt. */
1192         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1193
1194         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1195                 bnx2_init_all_rx_contexts(bp);
1196 }
1197
1198 static void
1199 bnx2_enable_bmsr1(struct bnx2 *bp)
1200 {
1201         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1202             (CHIP_NUM(bp) == CHIP_NUM_5709))
1203                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204                                MII_BNX2_BLK_ADDR_GP_STATUS);
1205 }
1206
1207 static void
1208 bnx2_disable_bmsr1(struct bnx2 *bp)
1209 {
1210         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1211             (CHIP_NUM(bp) == CHIP_NUM_5709))
1212                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1214 }
1215
1216 static int
1217 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1218 {
1219         u32 up1;
1220         int ret = 1;
1221
1222         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1223                 return 0;
1224
1225         if (bp->autoneg & AUTONEG_SPEED)
1226                 bp->advertising |= ADVERTISED_2500baseX_Full;
1227
1228         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1230
1231         bnx2_read_phy(bp, bp->mii_up1, &up1);
1232         if (!(up1 & BCM5708S_UP1_2G5)) {
1233                 up1 |= BCM5708S_UP1_2G5;
1234                 bnx2_write_phy(bp, bp->mii_up1, up1);
1235                 ret = 0;
1236         }
1237
1238         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1241
1242         return ret;
1243 }
1244
1245 static int
1246 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1247 {
1248         u32 up1;
1249         int ret = 0;
1250
1251         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1252                 return 0;
1253
1254         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1256
1257         bnx2_read_phy(bp, bp->mii_up1, &up1);
1258         if (up1 & BCM5708S_UP1_2G5) {
1259                 up1 &= ~BCM5708S_UP1_2G5;
1260                 bnx2_write_phy(bp, bp->mii_up1, up1);
1261                 ret = 1;
1262         }
1263
1264         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1267
1268         return ret;
1269 }
1270
1271 static void
1272 bnx2_enable_forced_2g5(struct bnx2 *bp)
1273 {
1274         u32 bmcr;
1275
1276         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1277                 return;
1278
1279         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1280                 u32 val;
1281
1282                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1284                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1288
1289                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1292
1293         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1294                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1296         }
1297
1298         if (bp->autoneg & AUTONEG_SPEED) {
1299                 bmcr &= ~BMCR_ANENABLE;
1300                 if (bp->req_duplex == DUPLEX_FULL)
1301                         bmcr |= BMCR_FULLDPLX;
1302         }
1303         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1304 }
1305
1306 static void
1307 bnx2_disable_forced_2g5(struct bnx2 *bp)
1308 {
1309         u32 bmcr;
1310
1311         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1312                 return;
1313
1314         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1315                 u32 val;
1316
1317                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1319                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1322
1323                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1326
1327         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1328                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1330         }
1331
1332         if (bp->autoneg & AUTONEG_SPEED)
1333                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1335 }
1336
1337 static void
1338 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1339 {
1340         u32 val;
1341
1342         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1344         if (start)
1345                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1346         else
1347                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1348 }
1349
1350 static int
1351 bnx2_set_link(struct bnx2 *bp)
1352 {
1353         u32 bmsr;
1354         u8 link_up;
1355
1356         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1357                 bp->link_up = 1;
1358                 return 0;
1359         }
1360
1361         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1362                 return 0;
1363
1364         link_up = bp->link_up;
1365
1366         bnx2_enable_bmsr1(bp);
1367         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369         bnx2_disable_bmsr1(bp);
1370
1371         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1372             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1373                 u32 val, an_dbg;
1374
1375                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1376                         bnx2_5706s_force_link_dn(bp, 0);
1377                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1378                 }
1379                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1380
1381                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1384
1385                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1387                         bmsr |= BMSR_LSTATUS;
1388                 else
1389                         bmsr &= ~BMSR_LSTATUS;
1390         }
1391
1392         if (bmsr & BMSR_LSTATUS) {
1393                 bp->link_up = 1;
1394
1395                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1396                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397                                 bnx2_5706s_linkup(bp);
1398                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399                                 bnx2_5708s_linkup(bp);
1400                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401                                 bnx2_5709s_linkup(bp);
1402                 }
1403                 else {
1404                         bnx2_copper_linkup(bp);
1405                 }
1406                 bnx2_resolve_flow_ctrl(bp);
1407         }
1408         else {
1409                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1410                     (bp->autoneg & AUTONEG_SPEED))
1411                         bnx2_disable_forced_2g5(bp);
1412
1413                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1414                         u32 bmcr;
1415
1416                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417                         bmcr |= BMCR_ANENABLE;
1418                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1419
1420                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1421                 }
1422                 bp->link_up = 0;
1423         }
1424
1425         if (bp->link_up != link_up) {
1426                 bnx2_report_link(bp);
1427         }
1428
1429         bnx2_set_mac_link(bp);
1430
1431         return 0;
1432 }
1433
1434 static int
1435 bnx2_reset_phy(struct bnx2 *bp)
1436 {
1437         int i;
1438         u32 reg;
1439
1440         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1441
1442 #define PHY_RESET_MAX_WAIT 100
1443         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1444                 udelay(10);
1445
1446                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1447                 if (!(reg & BMCR_RESET)) {
1448                         udelay(20);
1449                         break;
1450                 }
1451         }
1452         if (i == PHY_RESET_MAX_WAIT) {
1453                 return -EBUSY;
1454         }
1455         return 0;
1456 }
1457
1458 static u32
1459 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1460 {
1461         u32 adv = 0;
1462
1463         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1465
1466                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1467                         adv = ADVERTISE_1000XPAUSE;
1468                 }
1469                 else {
1470                         adv = ADVERTISE_PAUSE_CAP;
1471                 }
1472         }
1473         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1474                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1475                         adv = ADVERTISE_1000XPSE_ASYM;
1476                 }
1477                 else {
1478                         adv = ADVERTISE_PAUSE_ASYM;
1479                 }
1480         }
1481         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1482                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1483                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1484                 }
1485                 else {
1486                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487                 }
1488         }
1489         return adv;
1490 }
1491
1492 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1493
1494 static int
1495 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1496 {
1497         u32 speed_arg = 0, pause_adv;
1498
1499         pause_adv = bnx2_phy_get_pause_adv(bp);
1500
1501         if (bp->autoneg & AUTONEG_SPEED) {
1502                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503                 if (bp->advertising & ADVERTISED_10baseT_Half)
1504                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505                 if (bp->advertising & ADVERTISED_10baseT_Full)
1506                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507                 if (bp->advertising & ADVERTISED_100baseT_Half)
1508                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509                 if (bp->advertising & ADVERTISED_100baseT_Full)
1510                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1515         } else {
1516                 if (bp->req_line_speed == SPEED_2500)
1517                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518                 else if (bp->req_line_speed == SPEED_1000)
1519                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520                 else if (bp->req_line_speed == SPEED_100) {
1521                         if (bp->req_duplex == DUPLEX_FULL)
1522                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1523                         else
1524                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525                 } else if (bp->req_line_speed == SPEED_10) {
1526                         if (bp->req_duplex == DUPLEX_FULL)
1527                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1528                         else
1529                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1530                 }
1531         }
1532
1533         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1535         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1536                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1537
1538         if (port == PORT_TP)
1539                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1541
1542         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1543
1544         spin_unlock_bh(&bp->phy_lock);
1545         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1546         spin_lock_bh(&bp->phy_lock);
1547
1548         return 0;
1549 }
1550
1551 static int
1552 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1553 {
1554         u32 adv, bmcr;
1555         u32 new_adv = 0;
1556
1557         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1558                 return (bnx2_setup_remote_phy(bp, port));
1559
1560         if (!(bp->autoneg & AUTONEG_SPEED)) {
1561                 u32 new_bmcr;
1562                 int force_link_down = 0;
1563
1564                 if (bp->req_line_speed == SPEED_2500) {
1565                         if (!bnx2_test_and_enable_2g5(bp))
1566                                 force_link_down = 1;
1567                 } else if (bp->req_line_speed == SPEED_1000) {
1568                         if (bnx2_test_and_disable_2g5(bp))
1569                                 force_link_down = 1;
1570                 }
1571                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1572                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1573
1574                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1575                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1576                 new_bmcr |= BMCR_SPEED1000;
1577
1578                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579                         if (bp->req_line_speed == SPEED_2500)
1580                                 bnx2_enable_forced_2g5(bp);
1581                         else if (bp->req_line_speed == SPEED_1000) {
1582                                 bnx2_disable_forced_2g5(bp);
1583                                 new_bmcr &= ~0x2000;
1584                         }
1585
1586                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1587                         if (bp->req_line_speed == SPEED_2500)
1588                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1589                         else
1590                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1591                 }
1592
1593                 if (bp->req_duplex == DUPLEX_FULL) {
1594                         adv |= ADVERTISE_1000XFULL;
1595                         new_bmcr |= BMCR_FULLDPLX;
1596                 }
1597                 else {
1598                         adv |= ADVERTISE_1000XHALF;
1599                         new_bmcr &= ~BMCR_FULLDPLX;
1600                 }
1601                 if ((new_bmcr != bmcr) || (force_link_down)) {
1602                         /* Force a link down visible on the other side */
1603                         if (bp->link_up) {
1604                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1605                                                ~(ADVERTISE_1000XFULL |
1606                                                  ADVERTISE_1000XHALF));
1607                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1608                                         BMCR_ANRESTART | BMCR_ANENABLE);
1609
1610                                 bp->link_up = 0;
1611                                 netif_carrier_off(bp->dev);
1612                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1613                                 bnx2_report_link(bp);
1614                         }
1615                         bnx2_write_phy(bp, bp->mii_adv, adv);
1616                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1617                 } else {
1618                         bnx2_resolve_flow_ctrl(bp);
1619                         bnx2_set_mac_link(bp);
1620                 }
1621                 return 0;
1622         }
1623
1624         bnx2_test_and_enable_2g5(bp);
1625
1626         if (bp->advertising & ADVERTISED_1000baseT_Full)
1627                 new_adv |= ADVERTISE_1000XFULL;
1628
1629         new_adv |= bnx2_phy_get_pause_adv(bp);
1630
1631         bnx2_read_phy(bp, bp->mii_adv, &adv);
1632         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1633
1634         bp->serdes_an_pending = 0;
1635         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636                 /* Force a link down visible on the other side */
1637                 if (bp->link_up) {
1638                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1639                         spin_unlock_bh(&bp->phy_lock);
1640                         msleep(20);
1641                         spin_lock_bh(&bp->phy_lock);
1642                 }
1643
1644                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1646                         BMCR_ANENABLE);
1647                 /* Speed up link-up time when the link partner
1648                  * does not autonegotiate which is very common
1649                  * in blade servers. Some blade servers use
1650                  * IPMI for kerboard input and it's important
1651                  * to minimize link disruptions. Autoneg. involves
1652                  * exchanging base pages plus 3 next pages and
1653                  * normally completes in about 120 msec.
1654                  */
1655                 bp->current_interval = SERDES_AN_TIMEOUT;
1656                 bp->serdes_an_pending = 1;
1657                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1658         } else {
1659                 bnx2_resolve_flow_ctrl(bp);
1660                 bnx2_set_mac_link(bp);
1661         }
1662
1663         return 0;
1664 }
1665
1666 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1667         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1668                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669                 (ADVERTISED_1000baseT_Full)
1670
1671 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1672         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1673         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1674         ADVERTISED_1000baseT_Full)
1675
1676 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1678
1679 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1680
1681 static void
1682 bnx2_set_default_remote_link(struct bnx2 *bp)
1683 {
1684         u32 link;
1685
1686         if (bp->phy_port == PORT_TP)
1687                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1688         else
1689                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1690
1691         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692                 bp->req_line_speed = 0;
1693                 bp->autoneg |= AUTONEG_SPEED;
1694                 bp->advertising = ADVERTISED_Autoneg;
1695                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696                         bp->advertising |= ADVERTISED_10baseT_Half;
1697                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698                         bp->advertising |= ADVERTISED_10baseT_Full;
1699                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700                         bp->advertising |= ADVERTISED_100baseT_Half;
1701                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702                         bp->advertising |= ADVERTISED_100baseT_Full;
1703                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704                         bp->advertising |= ADVERTISED_1000baseT_Full;
1705                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706                         bp->advertising |= ADVERTISED_2500baseX_Full;
1707         } else {
1708                 bp->autoneg = 0;
1709                 bp->advertising = 0;
1710                 bp->req_duplex = DUPLEX_FULL;
1711                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712                         bp->req_line_speed = SPEED_10;
1713                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714                                 bp->req_duplex = DUPLEX_HALF;
1715                 }
1716                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717                         bp->req_line_speed = SPEED_100;
1718                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719                                 bp->req_duplex = DUPLEX_HALF;
1720                 }
1721                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722                         bp->req_line_speed = SPEED_1000;
1723                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724                         bp->req_line_speed = SPEED_2500;
1725         }
1726 }
1727
1728 static void
1729 bnx2_set_default_link(struct bnx2 *bp)
1730 {
1731         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732                 bnx2_set_default_remote_link(bp);
1733                 return;
1734         }
1735
1736         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737         bp->req_line_speed = 0;
1738         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1739                 u32 reg;
1740
1741                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1742
1743                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1744                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1746                         bp->autoneg = 0;
1747                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1748                         bp->req_duplex = DUPLEX_FULL;
1749                 }
1750         } else
1751                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1752 }
1753
1754 static void
1755 bnx2_send_heart_beat(struct bnx2 *bp)
1756 {
1757         u32 msg;
1758         u32 addr;
1759
1760         spin_lock(&bp->indirect_lock);
1761         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765         spin_unlock(&bp->indirect_lock);
1766 }
1767
1768 static void
1769 bnx2_remote_phy_event(struct bnx2 *bp)
1770 {
1771         u32 msg;
1772         u8 link_up = bp->link_up;
1773         u8 old_port;
1774
1775         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1776
1777         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778                 bnx2_send_heart_beat(bp);
1779
1780         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1781
1782         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1783                 bp->link_up = 0;
1784         else {
1785                 u32 speed;
1786
1787                 bp->link_up = 1;
1788                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789                 bp->duplex = DUPLEX_FULL;
1790                 switch (speed) {
1791                         case BNX2_LINK_STATUS_10HALF:
1792                                 bp->duplex = DUPLEX_HALF;
1793                         case BNX2_LINK_STATUS_10FULL:
1794                                 bp->line_speed = SPEED_10;
1795                                 break;
1796                         case BNX2_LINK_STATUS_100HALF:
1797                                 bp->duplex = DUPLEX_HALF;
1798                         case BNX2_LINK_STATUS_100BASE_T4:
1799                         case BNX2_LINK_STATUS_100FULL:
1800                                 bp->line_speed = SPEED_100;
1801                                 break;
1802                         case BNX2_LINK_STATUS_1000HALF:
1803                                 bp->duplex = DUPLEX_HALF;
1804                         case BNX2_LINK_STATUS_1000FULL:
1805                                 bp->line_speed = SPEED_1000;
1806                                 break;
1807                         case BNX2_LINK_STATUS_2500HALF:
1808                                 bp->duplex = DUPLEX_HALF;
1809                         case BNX2_LINK_STATUS_2500FULL:
1810                                 bp->line_speed = SPEED_2500;
1811                                 break;
1812                         default:
1813                                 bp->line_speed = 0;
1814                                 break;
1815                 }
1816
1817                 bp->flow_ctrl = 0;
1818                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820                         if (bp->duplex == DUPLEX_FULL)
1821                                 bp->flow_ctrl = bp->req_flow_ctrl;
1822                 } else {
1823                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1825                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1827                 }
1828
1829                 old_port = bp->phy_port;
1830                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831                         bp->phy_port = PORT_FIBRE;
1832                 else
1833                         bp->phy_port = PORT_TP;
1834
1835                 if (old_port != bp->phy_port)
1836                         bnx2_set_default_link(bp);
1837
1838         }
1839         if (bp->link_up != link_up)
1840                 bnx2_report_link(bp);
1841
1842         bnx2_set_mac_link(bp);
1843 }
1844
1845 static int
1846 bnx2_set_remote_link(struct bnx2 *bp)
1847 {
1848         u32 evt_code;
1849
1850         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1851         switch (evt_code) {
1852                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853                         bnx2_remote_phy_event(bp);
1854                         break;
1855                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1856                 default:
1857                         bnx2_send_heart_beat(bp);
1858                         break;
1859         }
1860         return 0;
1861 }
1862
1863 static int
1864 bnx2_setup_copper_phy(struct bnx2 *bp)
1865 {
1866         u32 bmcr;
1867         u32 new_bmcr;
1868
1869         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1870
1871         if (bp->autoneg & AUTONEG_SPEED) {
1872                 u32 adv_reg, adv1000_reg;
1873                 u32 new_adv_reg = 0;
1874                 u32 new_adv1000_reg = 0;
1875
1876                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1877                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878                         ADVERTISE_PAUSE_ASYM);
1879
1880                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881                 adv1000_reg &= PHY_ALL_1000_SPEED;
1882
1883                 if (bp->advertising & ADVERTISED_10baseT_Half)
1884                         new_adv_reg |= ADVERTISE_10HALF;
1885                 if (bp->advertising & ADVERTISED_10baseT_Full)
1886                         new_adv_reg |= ADVERTISE_10FULL;
1887                 if (bp->advertising & ADVERTISED_100baseT_Half)
1888                         new_adv_reg |= ADVERTISE_100HALF;
1889                 if (bp->advertising & ADVERTISED_100baseT_Full)
1890                         new_adv_reg |= ADVERTISE_100FULL;
1891                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892                         new_adv1000_reg |= ADVERTISE_1000FULL;
1893
1894                 new_adv_reg |= ADVERTISE_CSMA;
1895
1896                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1897
1898                 if ((adv1000_reg != new_adv1000_reg) ||
1899                         (adv_reg != new_adv_reg) ||
1900                         ((bmcr & BMCR_ANENABLE) == 0)) {
1901
1902                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1903                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1904                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1905                                 BMCR_ANENABLE);
1906                 }
1907                 else if (bp->link_up) {
1908                         /* Flow ctrl may have changed from auto to forced */
1909                         /* or vice-versa. */
1910
1911                         bnx2_resolve_flow_ctrl(bp);
1912                         bnx2_set_mac_link(bp);
1913                 }
1914                 return 0;
1915         }
1916
1917         new_bmcr = 0;
1918         if (bp->req_line_speed == SPEED_100) {
1919                 new_bmcr |= BMCR_SPEED100;
1920         }
1921         if (bp->req_duplex == DUPLEX_FULL) {
1922                 new_bmcr |= BMCR_FULLDPLX;
1923         }
1924         if (new_bmcr != bmcr) {
1925                 u32 bmsr;
1926
1927                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1929
1930                 if (bmsr & BMSR_LSTATUS) {
1931                         /* Force link down */
1932                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1933                         spin_unlock_bh(&bp->phy_lock);
1934                         msleep(50);
1935                         spin_lock_bh(&bp->phy_lock);
1936
1937                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1939                 }
1940
1941                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1942
1943                 /* Normally, the new speed is setup after the link has
1944                  * gone down and up again. In some cases, link will not go
1945                  * down so we need to set up the new speed here.
1946                  */
1947                 if (bmsr & BMSR_LSTATUS) {
1948                         bp->line_speed = bp->req_line_speed;
1949                         bp->duplex = bp->req_duplex;
1950                         bnx2_resolve_flow_ctrl(bp);
1951                         bnx2_set_mac_link(bp);
1952                 }
1953         } else {
1954                 bnx2_resolve_flow_ctrl(bp);
1955                 bnx2_set_mac_link(bp);
1956         }
1957         return 0;
1958 }
1959
1960 static int
1961 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1962 {
1963         if (bp->loopback == MAC_LOOPBACK)
1964                 return 0;
1965
1966         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1967                 return (bnx2_setup_serdes_phy(bp, port));
1968         }
1969         else {
1970                 return (bnx2_setup_copper_phy(bp));
1971         }
1972 }
1973
1974 static int
1975 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1976 {
1977         u32 val;
1978
1979         bp->mii_bmcr = MII_BMCR + 0x10;
1980         bp->mii_bmsr = MII_BMSR + 0x10;
1981         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982         bp->mii_adv = MII_ADVERTISE + 0x10;
1983         bp->mii_lpa = MII_LPA + 0x10;
1984         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1985
1986         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1988
1989         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1990         if (reset_phy)
1991                 bnx2_reset_phy(bp);
1992
1993         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1994
1995         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1999
2000         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2002         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2003                 val |= BCM5708S_UP1_2G5;
2004         else
2005                 val &= ~BCM5708S_UP1_2G5;
2006         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2007
2008         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2012
2013         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2014
2015         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2018
2019         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2020
2021         return 0;
2022 }
2023
2024 static int
2025 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2026 {
2027         u32 val;
2028
2029         if (reset_phy)
2030                 bnx2_reset_phy(bp);
2031
2032         bp->mii_up1 = BCM5708S_UP1;
2033
2034         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2037
2038         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2041
2042         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2045
2046         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2047                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048                 val |= BCM5708S_UP1_2G5;
2049                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2050         }
2051
2052         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2053             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2055                 /* increase tx signal amplitude */
2056                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057                                BCM5708S_BLK_ADDR_TX_MISC);
2058                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2062         }
2063
2064         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2065               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2066
2067         if (val) {
2068                 u32 is_backplane;
2069
2070                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2071                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073                                        BCM5708S_BLK_ADDR_TX_MISC);
2074                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076                                        BCM5708S_BLK_ADDR_DIG);
2077                 }
2078         }
2079         return 0;
2080 }
2081
2082 static int
2083 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2084 {
2085         if (reset_phy)
2086                 bnx2_reset_phy(bp);
2087
2088         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2089
2090         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2092
2093         if (bp->dev->mtu > 1500) {
2094                 u32 val;
2095
2096                 /* Set extended packet length bit */
2097                 bnx2_write_phy(bp, 0x18, 0x7);
2098                 bnx2_read_phy(bp, 0x18, &val);
2099                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2100
2101                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102                 bnx2_read_phy(bp, 0x1c, &val);
2103                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2104         }
2105         else {
2106                 u32 val;
2107
2108                 bnx2_write_phy(bp, 0x18, 0x7);
2109                 bnx2_read_phy(bp, 0x18, &val);
2110                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2111
2112                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113                 bnx2_read_phy(bp, 0x1c, &val);
2114                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int
2121 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2122 {
2123         u32 val;
2124
2125         if (reset_phy)
2126                 bnx2_reset_phy(bp);
2127
2128         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2129                 bnx2_write_phy(bp, 0x18, 0x0c00);
2130                 bnx2_write_phy(bp, 0x17, 0x000a);
2131                 bnx2_write_phy(bp, 0x15, 0x310b);
2132                 bnx2_write_phy(bp, 0x17, 0x201f);
2133                 bnx2_write_phy(bp, 0x15, 0x9506);
2134                 bnx2_write_phy(bp, 0x17, 0x401f);
2135                 bnx2_write_phy(bp, 0x15, 0x14e2);
2136                 bnx2_write_phy(bp, 0x18, 0x0400);
2137         }
2138
2139         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2140                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2142                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2143                 val &= ~(1 << 8);
2144                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2145         }
2146
2147         if (bp->dev->mtu > 1500) {
2148                 /* Set extended packet length bit */
2149                 bnx2_write_phy(bp, 0x18, 0x7);
2150                 bnx2_read_phy(bp, 0x18, &val);
2151                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2152
2153                 bnx2_read_phy(bp, 0x10, &val);
2154                 bnx2_write_phy(bp, 0x10, val | 0x1);
2155         }
2156         else {
2157                 bnx2_write_phy(bp, 0x18, 0x7);
2158                 bnx2_read_phy(bp, 0x18, &val);
2159                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2160
2161                 bnx2_read_phy(bp, 0x10, &val);
2162                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2163         }
2164
2165         /* ethernet@wirespeed */
2166         bnx2_write_phy(bp, 0x18, 0x7007);
2167         bnx2_read_phy(bp, 0x18, &val);
2168         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2169         return 0;
2170 }
2171
2172
2173 static int
2174 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2175 {
2176         u32 val;
2177         int rc = 0;
2178
2179         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2181
2182         bp->mii_bmcr = MII_BMCR;
2183         bp->mii_bmsr = MII_BMSR;
2184         bp->mii_bmsr1 = MII_BMSR;
2185         bp->mii_adv = MII_ADVERTISE;
2186         bp->mii_lpa = MII_LPA;
2187
2188         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2189
2190         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2191                 goto setup_phy;
2192
2193         bnx2_read_phy(bp, MII_PHYSID1, &val);
2194         bp->phy_id = val << 16;
2195         bnx2_read_phy(bp, MII_PHYSID2, &val);
2196         bp->phy_id |= val & 0xffff;
2197
2198         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2199                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2200                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2201                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2202                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2203                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2204                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2205         }
2206         else {
2207                 rc = bnx2_init_copper_phy(bp, reset_phy);
2208         }
2209
2210 setup_phy:
2211         if (!rc)
2212                 rc = bnx2_setup_phy(bp, bp->phy_port);
2213
2214         return rc;
2215 }
2216
2217 static int
2218 bnx2_set_mac_loopback(struct bnx2 *bp)
2219 {
2220         u32 mac_mode;
2221
2222         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2226         bp->link_up = 1;
2227         return 0;
2228 }
2229
2230 static int bnx2_test_link(struct bnx2 *);
2231
2232 static int
2233 bnx2_set_phy_loopback(struct bnx2 *bp)
2234 {
2235         u32 mac_mode;
2236         int rc, i;
2237
2238         spin_lock_bh(&bp->phy_lock);
2239         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2240                             BMCR_SPEED1000);
2241         spin_unlock_bh(&bp->phy_lock);
2242         if (rc)
2243                 return rc;
2244
2245         for (i = 0; i < 10; i++) {
2246                 if (bnx2_test_link(bp) == 0)
2247                         break;
2248                 msleep(100);
2249         }
2250
2251         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2254                       BNX2_EMAC_MODE_25G_MODE);
2255
2256         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2258         bp->link_up = 1;
2259         return 0;
2260 }
2261
2262 static int
2263 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2264 {
2265         int i;
2266         u32 val;
2267
2268         bp->fw_wr_seq++;
2269         msg_data |= bp->fw_wr_seq;
2270
2271         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2272
2273         if (!ack)
2274                 return 0;
2275
2276         /* wait for an acknowledgement. */
2277         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2278                 msleep(10);
2279
2280                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2281
2282                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2283                         break;
2284         }
2285         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2286                 return 0;
2287
2288         /* If we timed out, inform the firmware that this is the case. */
2289         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2290                 if (!silent)
2291                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2292                                             "%x\n", msg_data);
2293
2294                 msg_data &= ~BNX2_DRV_MSG_CODE;
2295                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2296
2297                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2298
2299                 return -EBUSY;
2300         }
2301
2302         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2303                 return -EIO;
2304
2305         return 0;
2306 }
2307
2308 static int
2309 bnx2_init_5709_context(struct bnx2 *bp)
2310 {
2311         int i, ret = 0;
2312         u32 val;
2313
2314         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315         val |= (BCM_PAGE_BITS - 8) << 16;
2316         REG_WR(bp, BNX2_CTX_COMMAND, val);
2317         for (i = 0; i < 10; i++) {
2318                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2320                         break;
2321                 udelay(2);
2322         }
2323         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2324                 return -EBUSY;
2325
2326         for (i = 0; i < bp->ctx_pages; i++) {
2327                 int j;
2328
2329                 if (bp->ctx_blk[i])
2330                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2331                 else
2332                         return -ENOMEM;
2333
2334                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338                        (u64) bp->ctx_blk_mapping[i] >> 32);
2339                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341                 for (j = 0; j < 10; j++) {
2342
2343                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2345                                 break;
2346                         udelay(5);
2347                 }
2348                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2349                         ret = -EBUSY;
2350                         break;
2351                 }
2352         }
2353         return ret;
2354 }
2355
2356 static void
2357 bnx2_init_context(struct bnx2 *bp)
2358 {
2359         u32 vcid;
2360
2361         vcid = 96;
2362         while (vcid) {
2363                 u32 vcid_addr, pcid_addr, offset;
2364                 int i;
2365
2366                 vcid--;
2367
2368                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2369                         u32 new_vcid;
2370
2371                         vcid_addr = GET_PCID_ADDR(vcid);
2372                         if (vcid & 0x8) {
2373                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2374                         }
2375                         else {
2376                                 new_vcid = vcid;
2377                         }
2378                         pcid_addr = GET_PCID_ADDR(new_vcid);
2379                 }
2380                 else {
2381                         vcid_addr = GET_CID_ADDR(vcid);
2382                         pcid_addr = vcid_addr;
2383                 }
2384
2385                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386                         vcid_addr += (i << PHY_CTX_SHIFT);
2387                         pcid_addr += (i << PHY_CTX_SHIFT);
2388
2389                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2390                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2391
2392                         /* Zero out the context. */
2393                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2394                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2395                 }
2396         }
2397 }
2398
2399 static int
2400 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2401 {
2402         u16 *good_mbuf;
2403         u32 good_mbuf_cnt;
2404         u32 val;
2405
2406         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407         if (good_mbuf == NULL) {
2408                 printk(KERN_ERR PFX "Failed to allocate memory in "
2409                                     "bnx2_alloc_bad_rbuf\n");
2410                 return -ENOMEM;
2411         }
2412
2413         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2415
2416         good_mbuf_cnt = 0;
2417
2418         /* Allocate a bunch of mbufs and save the good ones in an array. */
2419         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2420         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2421                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2423
2424                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2425
2426                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2427
2428                 /* The addresses with Bit 9 set are bad memory blocks. */
2429                 if (!(val & (1 << 9))) {
2430                         good_mbuf[good_mbuf_cnt] = (u16) val;
2431                         good_mbuf_cnt++;
2432                 }
2433
2434                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2435         }
2436
2437         /* Free the good ones back to the mbuf pool thus discarding
2438          * all the bad ones. */
2439         while (good_mbuf_cnt) {
2440                 good_mbuf_cnt--;
2441
2442                 val = good_mbuf[good_mbuf_cnt];
2443                 val = (val << 9) | val | 1;
2444
2445                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2446         }
2447         kfree(good_mbuf);
2448         return 0;
2449 }
2450
2451 static void
2452 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2453 {
2454         u32 val;
2455
2456         val = (mac_addr[0] << 8) | mac_addr[1];
2457
2458         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2459
2460         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2461                 (mac_addr[4] << 8) | mac_addr[5];
2462
2463         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2464 }
2465
2466 static inline int
2467 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2468 {
2469         dma_addr_t mapping;
2470         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2471         struct rx_bd *rxbd =
2472                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2473         struct page *page = alloc_page(GFP_ATOMIC);
2474
2475         if (!page)
2476                 return -ENOMEM;
2477         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478                                PCI_DMA_FROMDEVICE);
2479         rx_pg->page = page;
2480         pci_unmap_addr_set(rx_pg, mapping, mapping);
2481         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2482         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2483         return 0;
2484 }
2485
2486 static void
2487 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2488 {
2489         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2490         struct page *page = rx_pg->page;
2491
2492         if (!page)
2493                 return;
2494
2495         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2496                        PCI_DMA_FROMDEVICE);
2497
2498         __free_page(page);
2499         rx_pg->page = NULL;
2500 }
2501
2502 static inline int
2503 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2504 {
2505         struct sk_buff *skb;
2506         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2507         dma_addr_t mapping;
2508         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2509         unsigned long align;
2510
2511         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2512         if (skb == NULL) {
2513                 return -ENOMEM;
2514         }
2515
2516         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2517                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2518
2519         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2520                 PCI_DMA_FROMDEVICE);
2521
2522         rx_buf->skb = skb;
2523         pci_unmap_addr_set(rx_buf, mapping, mapping);
2524
2525         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2526         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2527
2528         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2529
2530         return 0;
2531 }
2532
2533 static int
2534 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2535 {
2536         struct status_block *sblk = bnapi->status_blk.msi;
2537         u32 new_link_state, old_link_state;
2538         int is_set = 1;
2539
2540         new_link_state = sblk->status_attn_bits & event;
2541         old_link_state = sblk->status_attn_bits_ack & event;
2542         if (new_link_state != old_link_state) {
2543                 if (new_link_state)
2544                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2545                 else
2546                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2547         } else
2548                 is_set = 0;
2549
2550         return is_set;
2551 }
2552
2553 static void
2554 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2555 {
2556         spin_lock(&bp->phy_lock);
2557
2558         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2559                 bnx2_set_link(bp);
2560         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2561                 bnx2_set_remote_link(bp);
2562
2563         spin_unlock(&bp->phy_lock);
2564
2565 }
2566
2567 static inline u16
2568 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2569 {
2570         u16 cons;
2571
2572         /* Tell compiler that status block fields can change. */
2573         barrier();
2574         cons = *bnapi->hw_tx_cons_ptr;
2575         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2576                 cons++;
2577         return cons;
2578 }
2579
2580 static int
2581 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2582 {
2583         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2584         u16 hw_cons, sw_cons, sw_ring_cons;
2585         int tx_pkt = 0, index;
2586         struct netdev_queue *txq;
2587
2588         index = (bnapi - bp->bnx2_napi);
2589         txq = netdev_get_tx_queue(bp->dev, index);
2590
2591         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2592         sw_cons = txr->tx_cons;
2593
2594         while (sw_cons != hw_cons) {
2595                 struct sw_bd *tx_buf;
2596                 struct sk_buff *skb;
2597                 int i, last;
2598
2599                 sw_ring_cons = TX_RING_IDX(sw_cons);
2600
2601                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2602                 skb = tx_buf->skb;
2603
2604                 /* partial BD completions possible with TSO packets */
2605                 if (skb_is_gso(skb)) {
2606                         u16 last_idx, last_ring_idx;
2607
2608                         last_idx = sw_cons +
2609                                 skb_shinfo(skb)->nr_frags + 1;
2610                         last_ring_idx = sw_ring_cons +
2611                                 skb_shinfo(skb)->nr_frags + 1;
2612                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2613                                 last_idx++;
2614                         }
2615                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2616                                 break;
2617                         }
2618                 }
2619
2620                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2621                         skb_headlen(skb), PCI_DMA_TODEVICE);
2622
2623                 tx_buf->skb = NULL;
2624                 last = skb_shinfo(skb)->nr_frags;
2625
2626                 for (i = 0; i < last; i++) {
2627                         sw_cons = NEXT_TX_BD(sw_cons);
2628
2629                         pci_unmap_page(bp->pdev,
2630                                 pci_unmap_addr(
2631                                         &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2632                                         mapping),
2633                                 skb_shinfo(skb)->frags[i].size,
2634                                 PCI_DMA_TODEVICE);
2635                 }
2636
2637                 sw_cons = NEXT_TX_BD(sw_cons);
2638
2639                 dev_kfree_skb(skb);
2640                 tx_pkt++;
2641                 if (tx_pkt == budget)
2642                         break;
2643
2644                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2645         }
2646
2647         txr->hw_tx_cons = hw_cons;
2648         txr->tx_cons = sw_cons;
2649
2650         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2651          * before checking for netif_tx_queue_stopped().  Without the
2652          * memory barrier, there is a small possibility that bnx2_start_xmit()
2653          * will miss it and cause the queue to be stopped forever.
2654          */
2655         smp_mb();
2656
2657         if (unlikely(netif_tx_queue_stopped(txq)) &&
2658                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2659                 __netif_tx_lock(txq, smp_processor_id());
2660                 if ((netif_tx_queue_stopped(txq)) &&
2661                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2662                         netif_tx_wake_queue(txq);
2663                 __netif_tx_unlock(txq);
2664         }
2665
2666         return tx_pkt;
2667 }
2668
2669 static void
2670 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2671                         struct sk_buff *skb, int count)
2672 {
2673         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2674         struct rx_bd *cons_bd, *prod_bd;
2675         dma_addr_t mapping;
2676         int i;
2677         u16 hw_prod = rxr->rx_pg_prod, prod;
2678         u16 cons = rxr->rx_pg_cons;
2679
2680         for (i = 0; i < count; i++) {
2681                 prod = RX_PG_RING_IDX(hw_prod);
2682
2683                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2684                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2685                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2686                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2687
2688                 if (i == 0 && skb) {
2689                         struct page *page;
2690                         struct skb_shared_info *shinfo;
2691
2692                         shinfo = skb_shinfo(skb);
2693                         shinfo->nr_frags--;
2694                         page = shinfo->frags[shinfo->nr_frags].page;
2695                         shinfo->frags[shinfo->nr_frags].page = NULL;
2696                         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2697                                                PCI_DMA_FROMDEVICE);
2698                         cons_rx_pg->page = page;
2699                         pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2700                         dev_kfree_skb(skb);
2701                 }
2702                 if (prod != cons) {
2703                         prod_rx_pg->page = cons_rx_pg->page;
2704                         cons_rx_pg->page = NULL;
2705                         pci_unmap_addr_set(prod_rx_pg, mapping,
2706                                 pci_unmap_addr(cons_rx_pg, mapping));
2707
2708                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2709                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2710
2711                 }
2712                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2713                 hw_prod = NEXT_RX_BD(hw_prod);
2714         }
2715         rxr->rx_pg_prod = hw_prod;
2716         rxr->rx_pg_cons = cons;
2717 }
2718
2719 static inline void
2720 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2721                   struct sk_buff *skb, u16 cons, u16 prod)
2722 {
2723         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2724         struct rx_bd *cons_bd, *prod_bd;
2725
2726         cons_rx_buf = &rxr->rx_buf_ring[cons];
2727         prod_rx_buf = &rxr->rx_buf_ring[prod];
2728
2729         pci_dma_sync_single_for_device(bp->pdev,
2730                 pci_unmap_addr(cons_rx_buf, mapping),
2731                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2732
2733         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2734
2735         prod_rx_buf->skb = skb;
2736
2737         if (cons == prod)
2738                 return;
2739
2740         pci_unmap_addr_set(prod_rx_buf, mapping,
2741                         pci_unmap_addr(cons_rx_buf, mapping));
2742
2743         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2744         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2745         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2746         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2747 }
2748
2749 static int
2750 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2751             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2752             u32 ring_idx)
2753 {
2754         int err;
2755         u16 prod = ring_idx & 0xffff;
2756
2757         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2758         if (unlikely(err)) {
2759                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2760                 if (hdr_len) {
2761                         unsigned int raw_len = len + 4;
2762                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2763
2764                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2765                 }
2766                 return err;
2767         }
2768
2769         skb_reserve(skb, BNX2_RX_OFFSET);
2770         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2771                          PCI_DMA_FROMDEVICE);
2772
2773         if (hdr_len == 0) {
2774                 skb_put(skb, len);
2775                 return 0;
2776         } else {
2777                 unsigned int i, frag_len, frag_size, pages;
2778                 struct sw_pg *rx_pg;
2779                 u16 pg_cons = rxr->rx_pg_cons;
2780                 u16 pg_prod = rxr->rx_pg_prod;
2781
2782                 frag_size = len + 4 - hdr_len;
2783                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2784                 skb_put(skb, hdr_len);
2785
2786                 for (i = 0; i < pages; i++) {
2787                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2788                         if (unlikely(frag_len <= 4)) {
2789                                 unsigned int tail = 4 - frag_len;
2790
2791                                 rxr->rx_pg_cons = pg_cons;
2792                                 rxr->rx_pg_prod = pg_prod;
2793                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2794                                                         pages - i);
2795                                 skb->len -= tail;
2796                                 if (i == 0) {
2797                                         skb->tail -= tail;
2798                                 } else {
2799                                         skb_frag_t *frag =
2800                                                 &skb_shinfo(skb)->frags[i - 1];
2801                                         frag->size -= tail;
2802                                         skb->data_len -= tail;
2803                                         skb->truesize -= tail;
2804                                 }
2805                                 return 0;
2806                         }
2807                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2808
2809                         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2810                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2811
2812                         if (i == pages - 1)
2813                                 frag_len -= 4;
2814
2815                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2816                         rx_pg->page = NULL;
2817
2818                         err = bnx2_alloc_rx_page(bp, rxr,
2819                                                  RX_PG_RING_IDX(pg_prod));
2820                         if (unlikely(err)) {
2821                                 rxr->rx_pg_cons = pg_cons;
2822                                 rxr->rx_pg_prod = pg_prod;
2823                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2824                                                         pages - i);
2825                                 return err;
2826                         }
2827
2828                         frag_size -= frag_len;
2829                         skb->data_len += frag_len;
2830                         skb->truesize += frag_len;
2831                         skb->len += frag_len;
2832
2833                         pg_prod = NEXT_RX_BD(pg_prod);
2834                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2835                 }
2836                 rxr->rx_pg_prod = pg_prod;
2837                 rxr->rx_pg_cons = pg_cons;
2838         }
2839         return 0;
2840 }
2841
2842 static inline u16
2843 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2844 {
2845         u16 cons;
2846
2847         /* Tell compiler that status block fields can change. */
2848         barrier();
2849         cons = *bnapi->hw_rx_cons_ptr;
2850         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2851                 cons++;
2852         return cons;
2853 }
2854
2855 static int
2856 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2857 {
2858         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2859         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2860         struct l2_fhdr *rx_hdr;
2861         int rx_pkt = 0, pg_ring_used = 0;
2862
2863         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2864         sw_cons = rxr->rx_cons;
2865         sw_prod = rxr->rx_prod;
2866
2867         /* Memory barrier necessary as speculative reads of the rx
2868          * buffer can be ahead of the index in the status block
2869          */
2870         rmb();
2871         while (sw_cons != hw_cons) {
2872                 unsigned int len, hdr_len;
2873                 u32 status;
2874                 struct sw_bd *rx_buf;
2875                 struct sk_buff *skb;
2876                 dma_addr_t dma_addr;
2877                 u16 vtag = 0;
2878                 int hw_vlan __maybe_unused = 0;
2879
2880                 sw_ring_cons = RX_RING_IDX(sw_cons);
2881                 sw_ring_prod = RX_RING_IDX(sw_prod);
2882
2883                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2884                 skb = rx_buf->skb;
2885
2886                 rx_buf->skb = NULL;
2887
2888                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2889
2890                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2891                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2892                         PCI_DMA_FROMDEVICE);
2893
2894                 rx_hdr = (struct l2_fhdr *) skb->data;
2895                 len = rx_hdr->l2_fhdr_pkt_len;
2896
2897                 if ((status = rx_hdr->l2_fhdr_status) &
2898                         (L2_FHDR_ERRORS_BAD_CRC |
2899                         L2_FHDR_ERRORS_PHY_DECODE |
2900                         L2_FHDR_ERRORS_ALIGNMENT |
2901                         L2_FHDR_ERRORS_TOO_SHORT |
2902                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2903
2904                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2905                                           sw_ring_prod);
2906                         goto next_rx;
2907                 }
2908                 hdr_len = 0;
2909                 if (status & L2_FHDR_STATUS_SPLIT) {
2910                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2911                         pg_ring_used = 1;
2912                 } else if (len > bp->rx_jumbo_thresh) {
2913                         hdr_len = bp->rx_jumbo_thresh;
2914                         pg_ring_used = 1;
2915                 }
2916
2917                 len -= 4;
2918
2919                 if (len <= bp->rx_copy_thresh) {
2920                         struct sk_buff *new_skb;
2921
2922                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
2923                         if (new_skb == NULL) {
2924                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2925                                                   sw_ring_prod);
2926                                 goto next_rx;
2927                         }
2928
2929                         /* aligned copy */
2930                         skb_copy_from_linear_data_offset(skb,
2931                                                          BNX2_RX_OFFSET - 6,
2932                                       new_skb->data, len + 6);
2933                         skb_reserve(new_skb, 6);
2934                         skb_put(new_skb, len);
2935
2936                         bnx2_reuse_rx_skb(bp, rxr, skb,
2937                                 sw_ring_cons, sw_ring_prod);
2938
2939                         skb = new_skb;
2940                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2941                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2942                         goto next_rx;
2943
2944                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2945                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2946                         vtag = rx_hdr->l2_fhdr_vlan_tag;
2947 #ifdef BCM_VLAN
2948                         if (bp->vlgrp)
2949                                 hw_vlan = 1;
2950                         else
2951 #endif
2952                         {
2953                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2954                                         __skb_push(skb, 4);
2955
2956                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2957                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
2958                                 ve->h_vlan_TCI = htons(vtag);
2959                                 len += 4;
2960                         }
2961                 }
2962
2963                 skb->protocol = eth_type_trans(skb, bp->dev);
2964
2965                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2966                         (ntohs(skb->protocol) != 0x8100)) {
2967
2968                         dev_kfree_skb(skb);
2969                         goto next_rx;
2970
2971                 }
2972
2973                 skb->ip_summed = CHECKSUM_NONE;
2974                 if (bp->rx_csum &&
2975                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2976                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2977
2978                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2979                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2980                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2981                 }
2982
2983 #ifdef BCM_VLAN
2984                 if (hw_vlan)
2985                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
2986                 else
2987 #endif
2988                         netif_receive_skb(skb);
2989
2990                 bp->dev->last_rx = jiffies;
2991                 rx_pkt++;
2992
2993 next_rx:
2994                 sw_cons = NEXT_RX_BD(sw_cons);
2995                 sw_prod = NEXT_RX_BD(sw_prod);
2996
2997                 if ((rx_pkt == budget))
2998                         break;
2999
3000                 /* Refresh hw_cons to see if there is new work */
3001                 if (sw_cons == hw_cons) {
3002                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3003                         rmb();
3004                 }
3005         }
3006         rxr->rx_cons = sw_cons;
3007         rxr->rx_prod = sw_prod;
3008
3009         if (pg_ring_used)
3010                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3011
3012         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3013
3014         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3015
3016         mmiowb();
3017
3018         return rx_pkt;
3019
3020 }
3021
3022 /* MSI ISR - The only difference between this and the INTx ISR
3023  * is that the MSI interrupt is always serviced.
3024  */
3025 static irqreturn_t
3026 bnx2_msi(int irq, void *dev_instance)
3027 {
3028         struct bnx2_napi *bnapi = dev_instance;
3029         struct bnx2 *bp = bnapi->bp;
3030         struct net_device *dev = bp->dev;
3031
3032         prefetch(bnapi->status_blk.msi);
3033         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3034                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3035                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3036
3037         /* Return here if interrupt is disabled. */
3038         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3039                 return IRQ_HANDLED;
3040
3041         netif_rx_schedule(dev, &bnapi->napi);
3042
3043         return IRQ_HANDLED;
3044 }
3045
3046 static irqreturn_t
3047 bnx2_msi_1shot(int irq, void *dev_instance)
3048 {
3049         struct bnx2_napi *bnapi = dev_instance;
3050         struct bnx2 *bp = bnapi->bp;
3051         struct net_device *dev = bp->dev;
3052
3053         prefetch(bnapi->status_blk.msi);
3054
3055         /* Return here if interrupt is disabled. */
3056         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3057                 return IRQ_HANDLED;
3058
3059         netif_rx_schedule(dev, &bnapi->napi);
3060
3061         return IRQ_HANDLED;
3062 }
3063
3064 static irqreturn_t
3065 bnx2_interrupt(int irq, void *dev_instance)
3066 {
3067         struct bnx2_napi *bnapi = dev_instance;
3068         struct bnx2 *bp = bnapi->bp;
3069         struct net_device *dev = bp->dev;
3070         struct status_block *sblk = bnapi->status_blk.msi;
3071
3072         /* When using INTx, it is possible for the interrupt to arrive
3073          * at the CPU before the status block posted prior to the
3074          * interrupt. Reading a register will flush the status block.
3075          * When using MSI, the MSI message will always complete after
3076          * the status block write.
3077          */
3078         if ((sblk->status_idx == bnapi->last_status_idx) &&
3079             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3080              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3081                 return IRQ_NONE;
3082
3083         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3084                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3085                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3086
3087         /* Read back to deassert IRQ immediately to avoid too many
3088          * spurious interrupts.
3089          */
3090         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3091
3092         /* Return here if interrupt is shared and is disabled. */
3093         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3094                 return IRQ_HANDLED;
3095
3096         if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3097                 bnapi->last_status_idx = sblk->status_idx;
3098                 __netif_rx_schedule(dev, &bnapi->napi);
3099         }
3100
3101         return IRQ_HANDLED;
3102 }
3103
3104 static inline int
3105 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3106 {
3107         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3108         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3109
3110         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3111             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3112                 return 1;
3113         return 0;
3114 }
3115
3116 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3117                                  STATUS_ATTN_BITS_TIMER_ABORT)
3118
3119 static inline int
3120 bnx2_has_work(struct bnx2_napi *bnapi)
3121 {
3122         struct status_block *sblk = bnapi->status_blk.msi;
3123
3124         if (bnx2_has_fast_work(bnapi))
3125                 return 1;
3126
3127         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3128             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3129                 return 1;
3130
3131         return 0;
3132 }
3133
3134 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3135 {
3136         struct status_block *sblk = bnapi->status_blk.msi;
3137         u32 status_attn_bits = sblk->status_attn_bits;
3138         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3139
3140         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3141             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3142
3143                 bnx2_phy_int(bp, bnapi);
3144
3145                 /* This is needed to take care of transient status
3146                  * during link changes.
3147                  */
3148                 REG_WR(bp, BNX2_HC_COMMAND,
3149                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3150                 REG_RD(bp, BNX2_HC_COMMAND);
3151         }
3152 }
3153
3154 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3155                           int work_done, int budget)
3156 {
3157         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3158         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3159
3160         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3161                 bnx2_tx_int(bp, bnapi, 0);
3162
3163         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3164                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3165
3166         return work_done;
3167 }
3168
3169 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3170 {
3171         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3172         struct bnx2 *bp = bnapi->bp;
3173         int work_done = 0;
3174         struct status_block_msix *sblk = bnapi->status_blk.msix;
3175
3176         while (1) {
3177                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3178                 if (unlikely(work_done >= budget))
3179                         break;
3180
3181                 bnapi->last_status_idx = sblk->status_idx;
3182                 /* status idx must be read before checking for more work. */
3183                 rmb();
3184                 if (likely(!bnx2_has_fast_work(bnapi))) {
3185
3186                         netif_rx_complete(bp->dev, napi);
3187                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3188                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3189                                bnapi->last_status_idx);
3190                         break;
3191                 }
3192         }
3193         return work_done;
3194 }
3195
3196 static int bnx2_poll(struct napi_struct *napi, int budget)
3197 {
3198         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3199         struct bnx2 *bp = bnapi->bp;
3200         int work_done = 0;
3201         struct status_block *sblk = bnapi->status_blk.msi;
3202
3203         while (1) {
3204                 bnx2_poll_link(bp, bnapi);
3205
3206                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3207
3208                 if (unlikely(work_done >= budget))
3209                         break;
3210
3211                 /* bnapi->last_status_idx is used below to tell the hw how
3212                  * much work has been processed, so we must read it before
3213                  * checking for more work.
3214                  */
3215                 bnapi->last_status_idx = sblk->status_idx;
3216                 rmb();
3217                 if (likely(!bnx2_has_work(bnapi))) {
3218                         netif_rx_complete(bp->dev, napi);
3219                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3220                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3221                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3222                                        bnapi->last_status_idx);
3223                                 break;
3224                         }
3225                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3226                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3227                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3228                                bnapi->last_status_idx);
3229
3230                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3231                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3232                                bnapi->last_status_idx);
3233                         break;
3234                 }
3235         }
3236
3237         return work_done;
3238 }
3239
3240 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3241  * from set_multicast.
3242  */
3243 static void
3244 bnx2_set_rx_mode(struct net_device *dev)
3245 {
3246         struct bnx2 *bp = netdev_priv(dev);
3247         u32 rx_mode, sort_mode;
3248         struct dev_addr_list *uc_ptr;
3249         int i;
3250
3251         spin_lock_bh(&bp->phy_lock);
3252
3253         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3254                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3255         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3256 #ifdef BCM_VLAN
3257         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3258                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3259 #else
3260         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3261                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3262 #endif
3263         if (dev->flags & IFF_PROMISC) {
3264                 /* Promiscuous mode. */
3265                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3266                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3267                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3268         }
3269         else if (dev->flags & IFF_ALLMULTI) {
3270                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3271                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3272                                0xffffffff);
3273                 }
3274                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3275         }
3276         else {
3277                 /* Accept one or more multicast(s). */
3278                 struct dev_mc_list *mclist;
3279                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3280                 u32 regidx;
3281                 u32 bit;
3282                 u32 crc;
3283
3284                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3285
3286                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3287                      i++, mclist = mclist->next) {
3288
3289                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3290                         bit = crc & 0xff;
3291                         regidx = (bit & 0xe0) >> 5;
3292                         bit &= 0x1f;
3293                         mc_filter[regidx] |= (1 << bit);
3294                 }
3295
3296                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3297                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3298                                mc_filter[i]);
3299                 }
3300
3301                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3302         }
3303
3304         uc_ptr = NULL;
3305         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3306                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3307                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3308                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3309         } else if (!(dev->flags & IFF_PROMISC)) {
3310                 uc_ptr = dev->uc_list;
3311
3312                 /* Add all entries into to the match filter list */
3313                 for (i = 0; i < dev->uc_count; i++) {
3314                         bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3315                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3316                         sort_mode |= (1 <<
3317                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3318                         uc_ptr = uc_ptr->next;
3319                 }
3320
3321         }
3322
3323         if (rx_mode != bp->rx_mode) {
3324                 bp->rx_mode = rx_mode;
3325                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3326         }
3327
3328         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3329         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3330         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3331
3332         spin_unlock_bh(&bp->phy_lock);
3333 }
3334
3335 static void
3336 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3337         u32 rv2p_proc)
3338 {
3339         int i;
3340         u32 val;
3341
3342         if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3343                 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3344                 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3345                 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3346                 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3347         }
3348
3349         for (i = 0; i < rv2p_code_len; i += 8) {
3350                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3351                 rv2p_code++;
3352                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3353                 rv2p_code++;
3354
3355                 if (rv2p_proc == RV2P_PROC1) {
3356                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3357                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3358                 }
3359                 else {
3360                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3361                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3362                 }
3363         }
3364
3365         /* Reset the processor, un-stall is done later. */
3366         if (rv2p_proc == RV2P_PROC1) {
3367                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3368         }
3369         else {
3370                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3371         }
3372 }
3373
3374 static int
3375 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3376 {
3377         u32 offset;
3378         u32 val;
3379         int rc;
3380
3381         /* Halt the CPU. */
3382         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3383         val |= cpu_reg->mode_value_halt;
3384         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3385         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3386
3387         /* Load the Text area. */
3388         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3389         if (fw->gz_text) {
3390                 int j;
3391
3392                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3393                                        fw->gz_text_len);
3394                 if (rc < 0)
3395                         return rc;
3396
3397                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3398                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3399                 }
3400         }
3401
3402         /* Load the Data area. */
3403         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3404         if (fw->data) {
3405                 int j;
3406
3407                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3408                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3409                 }
3410         }
3411
3412         /* Load the SBSS area. */
3413         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3414         if (fw->sbss_len) {
3415                 int j;
3416
3417                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3418                         bnx2_reg_wr_ind(bp, offset, 0);
3419                 }
3420         }
3421
3422         /* Load the BSS area. */
3423         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3424         if (fw->bss_len) {
3425                 int j;
3426
3427                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3428                         bnx2_reg_wr_ind(bp, offset, 0);
3429                 }
3430         }
3431
3432         /* Load the Read-Only area. */
3433         offset = cpu_reg->spad_base +
3434                 (fw->rodata_addr - cpu_reg->mips_view_base);
3435         if (fw->rodata) {
3436                 int j;
3437
3438                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3439                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3440                 }
3441         }
3442
3443         /* Clear the pre-fetch instruction. */
3444         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3445         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3446
3447         /* Start the CPU. */
3448         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3449         val &= ~cpu_reg->mode_value_halt;
3450         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3451         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3452
3453         return 0;
3454 }
3455
3456 static int
3457 bnx2_init_cpus(struct bnx2 *bp)
3458 {
3459         struct fw_info *fw;
3460         int rc, rv2p_len;
3461         void *text, *rv2p;
3462
3463         /* Initialize the RV2P processor. */
3464         text = vmalloc(FW_BUF_SIZE);
3465         if (!text)
3466                 return -ENOMEM;
3467         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3468                 rv2p = bnx2_xi_rv2p_proc1;
3469                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3470         } else {
3471                 rv2p = bnx2_rv2p_proc1;
3472                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3473         }
3474         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3475         if (rc < 0)
3476                 goto init_cpu_err;
3477
3478         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3479
3480         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3481                 rv2p = bnx2_xi_rv2p_proc2;
3482                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3483         } else {
3484                 rv2p = bnx2_rv2p_proc2;
3485                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3486         }
3487         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3488         if (rc < 0)
3489                 goto init_cpu_err;
3490
3491         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3492
3493         /* Initialize the RX Processor. */
3494         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3495                 fw = &bnx2_rxp_fw_09;
3496         else
3497                 fw = &bnx2_rxp_fw_06;
3498
3499         fw->text = text;
3500         rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3501         if (rc)
3502                 goto init_cpu_err;
3503
3504         /* Initialize the TX Processor. */
3505         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3506                 fw = &bnx2_txp_fw_09;
3507         else
3508                 fw = &bnx2_txp_fw_06;
3509
3510         fw->text = text;
3511         rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3512         if (rc)
3513                 goto init_cpu_err;
3514
3515         /* Initialize the TX Patch-up Processor. */
3516         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3517                 fw = &bnx2_tpat_fw_09;
3518         else
3519                 fw = &bnx2_tpat_fw_06;
3520
3521         fw->text = text;
3522         rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3523         if (rc)
3524                 goto init_cpu_err;
3525
3526         /* Initialize the Completion Processor. */
3527         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3528                 fw = &bnx2_com_fw_09;
3529         else
3530                 fw = &bnx2_com_fw_06;
3531
3532         fw->text = text;
3533         rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3534         if (rc)
3535                 goto init_cpu_err;
3536
3537         /* Initialize the Command Processor. */
3538         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3539                 fw = &bnx2_cp_fw_09;
3540         else
3541                 fw = &bnx2_cp_fw_06;
3542
3543         fw->text = text;
3544         rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3545
3546 init_cpu_err:
3547         vfree(text);
3548         return rc;
3549 }
3550
3551 static int
3552 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3553 {
3554         u16 pmcsr;
3555
3556         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3557
3558         switch (state) {
3559         case PCI_D0: {
3560                 u32 val;
3561
3562                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3563                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3564                         PCI_PM_CTRL_PME_STATUS);
3565
3566                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3567                         /* delay required during transition out of D3hot */
3568                         msleep(20);
3569
3570                 val = REG_RD(bp, BNX2_EMAC_MODE);
3571                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3572                 val &= ~BNX2_EMAC_MODE_MPKT;
3573                 REG_WR(bp, BNX2_EMAC_MODE, val);
3574
3575                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3576                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3577                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3578                 break;
3579         }
3580         case PCI_D3hot: {
3581                 int i;
3582                 u32 val, wol_msg;
3583
3584                 if (bp->wol) {
3585                         u32 advertising;
3586                         u8 autoneg;
3587
3588                         autoneg = bp->autoneg;
3589                         advertising = bp->advertising;
3590
3591                         if (bp->phy_port == PORT_TP) {
3592                                 bp->autoneg = AUTONEG_SPEED;
3593                                 bp->advertising = ADVERTISED_10baseT_Half |
3594                                         ADVERTISED_10baseT_Full |
3595                                         ADVERTISED_100baseT_Half |
3596                                         ADVERTISED_100baseT_Full |
3597                                         ADVERTISED_Autoneg;
3598                         }
3599
3600                         spin_lock_bh(&bp->phy_lock);
3601                         bnx2_setup_phy(bp, bp->phy_port);
3602                         spin_unlock_bh(&bp->phy_lock);
3603
3604                         bp->autoneg = autoneg;
3605                         bp->advertising = advertising;
3606
3607                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3608
3609                         val = REG_RD(bp, BNX2_EMAC_MODE);
3610
3611                         /* Enable port mode. */
3612                         val &= ~BNX2_EMAC_MODE_PORT;
3613                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3614                                BNX2_EMAC_MODE_ACPI_RCVD |
3615                                BNX2_EMAC_MODE_MPKT;
3616                         if (bp->phy_port == PORT_TP)
3617                                 val |= BNX2_EMAC_MODE_PORT_MII;
3618                         else {
3619                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3620                                 if (bp->line_speed == SPEED_2500)
3621                                         val |= BNX2_EMAC_MODE_25G_MODE;
3622                         }
3623
3624                         REG_WR(bp, BNX2_EMAC_MODE, val);
3625
3626                         /* receive all multicast */
3627                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3628                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3629                                        0xffffffff);
3630                         }
3631                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3632                                BNX2_EMAC_RX_MODE_SORT_MODE);
3633
3634                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3635                               BNX2_RPM_SORT_USER0_MC_EN;
3636                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3637                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3638                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3639                                BNX2_RPM_SORT_USER0_ENA);
3640
3641                         /* Need to enable EMAC and RPM for WOL. */
3642                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3643                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3644                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3645                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3646
3647                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3648                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3649                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3650
3651                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3652                 }
3653                 else {
3654                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3655                 }
3656
3657                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3658                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3659                                      1, 0);
3660
3661                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3662                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3663                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3664
3665                         if (bp->wol)
3666                                 pmcsr |= 3;
3667                 }
3668                 else {
3669                         pmcsr |= 3;
3670                 }
3671                 if (bp->wol) {
3672                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3673                 }
3674                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3675                                       pmcsr);
3676
3677                 /* No more memory access after this point until
3678                  * device is brought back to D0.
3679                  */
3680                 udelay(50);
3681                 break;
3682         }
3683         default:
3684                 return -EINVAL;
3685         }
3686         return 0;
3687 }
3688
3689 static int
3690 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3691 {
3692         u32 val;
3693         int j;
3694
3695         /* Request access to the flash interface. */
3696         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3697         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3698                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3699                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3700                         break;
3701
3702                 udelay(5);
3703         }
3704
3705         if (j >= NVRAM_TIMEOUT_COUNT)
3706                 return -EBUSY;
3707
3708         return 0;
3709 }
3710
3711 static int
3712 bnx2_release_nvram_lock(struct bnx2 *bp)
3713 {
3714         int j;
3715         u32 val;
3716
3717         /* Relinquish nvram interface. */
3718         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3719
3720         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3721                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3722                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3723                         break;
3724
3725                 udelay(5);
3726         }
3727
3728         if (j >= NVRAM_TIMEOUT_COUNT)
3729                 return -EBUSY;
3730
3731         return 0;
3732 }
3733
3734
3735 static int
3736 bnx2_enable_nvram_write(struct bnx2 *bp)
3737 {
3738         u32 val;
3739
3740         val = REG_RD(bp, BNX2_MISC_CFG);
3741         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3742
3743         if (bp->flash_info->flags & BNX2_NV_WREN) {
3744                 int j;
3745
3746                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3747                 REG_WR(bp, BNX2_NVM_COMMAND,
3748                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3749
3750                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3751                         udelay(5);
3752
3753                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3754                         if (val & BNX2_NVM_COMMAND_DONE)
3755                                 break;
3756                 }
3757
3758                 if (j >= NVRAM_TIMEOUT_COUNT)
3759                         return -EBUSY;
3760         }
3761         return 0;
3762 }
3763
3764 static void
3765 bnx2_disable_nvram_write(struct bnx2 *bp)
3766 {
3767         u32 val;
3768
3769         val = REG_RD(bp, BNX2_MISC_CFG);
3770         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3771 }
3772
3773
3774 static void
3775 bnx2_enable_nvram_access(struct bnx2 *bp)
3776 {
3777         u32 val;
3778
3779         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3780         /* Enable both bits, even on read. */
3781         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3782                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3783 }
3784
3785 static void
3786 bnx2_disable_nvram_access(struct bnx2 *bp)
3787 {
3788         u32 val;
3789
3790         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3791         /* Disable both bits, even after read. */
3792         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3793                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3794                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3795 }
3796
3797 static int
3798 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3799 {
3800         u32 cmd;
3801         int j;
3802
3803         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3804                 /* Buffered flash, no erase needed */
3805                 return 0;
3806
3807         /* Build an erase command */
3808         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3809               BNX2_NVM_COMMAND_DOIT;
3810
3811         /* Need to clear DONE bit separately. */
3812         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3813
3814         /* Address of the NVRAM to read from. */
3815         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3816
3817         /* Issue an erase command. */
3818         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3819
3820         /* Wait for completion. */
3821         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3822                 u32 val;
3823
3824                 udelay(5);
3825
3826                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3827                 if (val & BNX2_NVM_COMMAND_DONE)
3828                         break;
3829         }
3830
3831         if (j >= NVRAM_TIMEOUT_COUNT)
3832                 return -EBUSY;
3833
3834         return 0;
3835 }
3836
3837 static int
3838 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3839 {
3840         u32 cmd;
3841         int j;
3842
3843         /* Build the command word. */
3844         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3845
3846         /* Calculate an offset of a buffered flash, not needed for 5709. */
3847         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3848                 offset = ((offset / bp->flash_info->page_size) <<
3849                            bp->flash_info->page_bits) +
3850                           (offset % bp->flash_info->page_size);
3851         }
3852
3853         /* Need to clear DONE bit separately. */
3854         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3855
3856         /* Address of the NVRAM to read from. */
3857         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3858
3859         /* Issue a read command. */
3860         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3861
3862         /* Wait for completion. */
3863         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3864                 u32 val;
3865
3866                 udelay(5);
3867
3868                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3869                 if (val & BNX2_NVM_COMMAND_DONE) {
3870                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3871                         memcpy(ret_val, &v, 4);
3872                         break;
3873                 }
3874         }
3875         if (j >= NVRAM_TIMEOUT_COUNT)
3876                 return -EBUSY;
3877
3878         return 0;
3879 }
3880
3881
3882 static int
3883 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3884 {
3885         u32 cmd;
3886         __be32 val32;
3887         int j;
3888
3889         /* Build the command word. */
3890         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3891
3892         /* Calculate an offset of a buffered flash, not needed for 5709. */
3893         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3894                 offset = ((offset / bp->flash_info->page_size) <<
3895                           bp->flash_info->page_bits) +
3896                          (offset % bp->flash_info->page_size);
3897         }
3898
3899         /* Need to clear DONE bit separately. */
3900         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3901
3902         memcpy(&val32, val, 4);
3903
3904         /* Write the data. */
3905         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3906
3907         /* Address of the NVRAM to write to. */
3908         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3909
3910         /* Issue the write command. */
3911         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3912
3913         /* Wait for completion. */
3914         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3915                 udelay(5);
3916
3917                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3918                         break;
3919         }
3920         if (j >= NVRAM_TIMEOUT_COUNT)
3921                 return -EBUSY;
3922
3923         return 0;
3924 }
3925
3926 static int
3927 bnx2_init_nvram(struct bnx2 *bp)
3928 {
3929         u32 val;
3930         int j, entry_count, rc = 0;
3931         struct flash_spec *flash;
3932
3933         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3934                 bp->flash_info = &flash_5709;
3935                 goto get_flash_size;
3936         }
3937
3938         /* Determine the selected interface. */
3939         val = REG_RD(bp, BNX2_NVM_CFG1);
3940
3941         entry_count = ARRAY_SIZE(flash_table);
3942
3943         if (val & 0x40000000) {
3944
3945                 /* Flash interface has been reconfigured */
3946                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3947                      j++, flash++) {
3948                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3949                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3950                                 bp->flash_info = flash;
3951                                 break;
3952                         }
3953                 }
3954         }
3955         else {
3956                 u32 mask;
3957                 /* Not yet been reconfigured */
3958
3959                 if (val & (1 << 23))
3960                         mask = FLASH_BACKUP_STRAP_MASK;
3961                 else
3962                         mask = FLASH_STRAP_MASK;
3963
3964                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3965                         j++, flash++) {
3966
3967                         if ((val & mask) == (flash->strapping & mask)) {
3968                                 bp->flash_info = flash;
3969
3970                                 /* Request access to the flash interface. */
3971                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3972                                         return rc;
3973
3974                                 /* Enable access to flash interface */
3975                                 bnx2_enable_nvram_access(bp);
3976
3977                                 /* Reconfigure the flash interface */
3978                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3979                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3980                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3981                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3982
3983                                 /* Disable access to flash interface */
3984                                 bnx2_disable_nvram_access(bp);
3985                                 bnx2_release_nvram_lock(bp);
3986
3987                                 break;
3988                         }
3989                 }
3990         } /* if (val & 0x40000000) */
3991
3992         if (j == entry_count) {
3993                 bp->flash_info = NULL;
3994                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3995                 return -ENODEV;
3996         }
3997
3998 get_flash_size:
3999         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4000         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4001         if (val)
4002                 bp->flash_size = val;
4003         else
4004                 bp->flash_size = bp->flash_info->total_size;
4005
4006         return rc;
4007 }
4008
4009 static int
4010 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4011                 int buf_size)
4012 {
4013         int rc = 0;
4014         u32 cmd_flags, offset32, len32, extra;
4015
4016         if (buf_size == 0)
4017                 return 0;
4018
4019         /* Request access to the flash interface. */
4020         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4021                 return rc;
4022
4023         /* Enable access to flash interface */
4024         bnx2_enable_nvram_access(bp);
4025
4026         len32 = buf_size;
4027         offset32 = offset;
4028         extra = 0;
4029
4030         cmd_flags = 0;
4031
4032         if (offset32 & 3) {
4033                 u8 buf[4];
4034                 u32 pre_len;
4035
4036                 offset32 &= ~3;
4037                 pre_len = 4 - (offset & 3);
4038
4039                 if (pre_len >= len32) {
4040                         pre_len = len32;
4041                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4042                                     BNX2_NVM_COMMAND_LAST;
4043                 }
4044                 else {
4045                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4046                 }
4047
4048                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4049
4050                 if (rc)
4051                         return rc;
4052
4053                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4054
4055                 offset32 += 4;
4056                 ret_buf += pre_len;
4057                 len32 -= pre_len;
4058         }
4059         if (len32 & 3) {
4060                 extra = 4 - (len32 & 3);
4061                 len32 = (len32 + 4) & ~3;
4062         }
4063
4064         if (len32 == 4) {
4065                 u8 buf[4];
4066
4067                 if (cmd_flags)
4068                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4069                 else
4070                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4071                                     BNX2_NVM_COMMAND_LAST;
4072
4073                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4074
4075                 memcpy(ret_buf, buf, 4 - extra);
4076         }
4077         else if (len32 > 0) {
4078                 u8 buf[4];
4079
4080                 /* Read the first word. */
4081                 if (cmd_flags)
4082                         cmd_flags = 0;
4083                 else
4084                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4085
4086                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4087
4088                 /* Advance to the next dword. */
4089                 offset32 += 4;
4090                 ret_buf += 4;
4091                 len32 -= 4;
4092
4093                 while (len32 > 4 && rc == 0) {
4094                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4095
4096                         /* Advance to the next dword. */
4097                         offset32 += 4;
4098                         ret_buf += 4;
4099                         len32 -= 4;
4100                 }
4101
4102                 if (rc)
4103                         return rc;
4104
4105                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4106                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4107
4108                 memcpy(ret_buf, buf, 4 - extra);
4109         }
4110
4111         /* Disable access to flash interface */
4112         bnx2_disable_nvram_access(bp);
4113
4114         bnx2_release_nvram_lock(bp);
4115
4116         return rc;
4117 }
4118
4119 static int
4120 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4121                 int buf_size)
4122 {
4123         u32 written, offset32, len32;
4124         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4125         int rc = 0;
4126         int align_start, align_end;
4127
4128         buf = data_buf;
4129         offset32 = offset;
4130         len32 = buf_size;
4131         align_start = align_end = 0;
4132
4133         if ((align_start = (offset32 & 3))) {
4134                 offset32 &= ~3;
4135                 len32 += align_start;
4136                 if (len32 < 4)
4137                         len32 = 4;
4138                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4139                         return rc;
4140         }
4141
4142         if (len32 & 3) {
4143                 align_end = 4 - (len32 & 3);
4144                 len32 += align_end;
4145                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4146                         return rc;
4147         }
4148
4149         if (align_start || align_end) {
4150                 align_buf = kmalloc(len32, GFP_KERNEL);
4151                 if (align_buf == NULL)
4152                         return -ENOMEM;
4153                 if (align_start) {
4154                         memcpy(align_buf, start, 4);
4155                 }
4156                 if (align_end) {
4157                         memcpy(align_buf + len32 - 4, end, 4);
4158                 }
4159                 memcpy(align_buf + align_start, data_buf, buf_size);
4160                 buf = align_buf;
4161         }
4162
4163         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4164                 flash_buffer = kmalloc(264, GFP_KERNEL);
4165                 if (flash_buffer == NULL) {
4166                         rc = -ENOMEM;
4167                         goto nvram_write_end;
4168                 }
4169         }
4170
4171         written = 0;
4172         while ((written < len32) && (rc == 0)) {
4173                 u32 page_start, page_end, data_start, data_end;
4174                 u32 addr, cmd_flags;
4175                 int i;
4176
4177                 /* Find the page_start addr */
4178                 page_start = offset32 + written;
4179                 page_start -= (page_start % bp->flash_info->page_size);
4180                 /* Find the page_end addr */
4181                 page_end = page_start + bp->flash_info->page_size;
4182                 /* Find the data_start addr */
4183                 data_start = (written == 0) ? offset32 : page_start;
4184                 /* Find the data_end addr */
4185                 data_end = (page_end > offset32 + len32) ?
4186                         (offset32 + len32) : page_end;
4187
4188                 /* Request access to the flash interface. */
4189                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4190                         goto nvram_write_end;
4191
4192                 /* Enable access to flash interface */
4193                 bnx2_enable_nvram_access(bp);
4194
4195                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4196                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4197                         int j;
4198
4199                         /* Read the whole page into the buffer
4200                          * (non-buffer flash only) */
4201                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4202                                 if (j == (bp->flash_info->page_size - 4)) {
4203                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4204                                 }
4205                                 rc = bnx2_nvram_read_dword(bp,
4206                                         page_start + j,
4207                                         &flash_buffer[j],
4208                                         cmd_flags);
4209
4210                                 if (rc)
4211                                         goto nvram_write_end;
4212
4213                                 cmd_flags = 0;
4214                         }
4215                 }
4216
4217                 /* Enable writes to flash interface (unlock write-protect) */
4218                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4219                         goto nvram_write_end;
4220
4221                 /* Loop to write back the buffer data from page_start to
4222                  * data_start */
4223                 i = 0;
4224                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4225                         /* Erase the page */
4226                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4227                                 goto nvram_write_end;
4228
4229                         /* Re-enable the write again for the actual write */
4230                         bnx2_enable_nvram_write(bp);
4231
4232                         for (addr = page_start; addr < data_start;
4233                                 addr += 4, i += 4) {
4234
4235                                 rc = bnx2_nvram_write_dword(bp, addr,
4236                                         &flash_buffer[i], cmd_flags);
4237
4238                                 if (rc != 0)
4239                                         goto nvram_write_end;
4240
4241                                 cmd_flags = 0;
4242                         }
4243                 }
4244
4245                 /* Loop to write the new data from data_start to data_end */
4246                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4247                         if ((addr == page_end - 4) ||
4248                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4249                                  (addr == data_end - 4))) {
4250
4251                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4252                         }
4253                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4254                                 cmd_flags);
4255
4256                         if (rc != 0)
4257                                 goto nvram_write_end;
4258
4259                         cmd_flags = 0;
4260                         buf += 4;
4261                 }
4262
4263                 /* Loop to write back the buffer data from data_end
4264                  * to page_end */
4265                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4266                         for (addr = data_end; addr < page_end;
4267                                 addr += 4, i += 4) {
4268
4269                                 if (addr == page_end-4) {
4270                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4271                                 }
4272                                 rc = bnx2_nvram_write_dword(bp, addr,
4273                                         &flash_buffer[i], cmd_flags);
4274
4275                                 if (rc != 0)
4276                                         goto nvram_write_end;
4277
4278                                 cmd_flags = 0;
4279                         }
4280                 }
4281
4282                 /* Disable writes to flash interface (lock write-protect) */
4283                 bnx2_disable_nvram_write(bp);
4284
4285                 /* Disable access to flash interface */
4286                 bnx2_disable_nvram_access(bp);
4287                 bnx2_release_nvram_lock(bp);
4288
4289                 /* Increment written */
4290                 written += data_end - data_start;
4291         }
4292
4293 nvram_write_end:
4294         kfree(flash_buffer);
4295         kfree(align_buf);
4296         return rc;
4297 }
4298
4299 static void
4300 bnx2_init_fw_cap(struct bnx2 *bp)
4301 {
4302         u32 val, sig = 0;
4303
4304         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4305         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4306
4307         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4308                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4309
4310         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4311         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4312                 return;
4313
4314         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4315                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4316                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4317         }
4318
4319         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4320             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4321                 u32 link;
4322
4323                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4324
4325                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4326                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4327                         bp->phy_port = PORT_FIBRE;
4328                 else
4329                         bp->phy_port = PORT_TP;
4330
4331                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4332                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4333         }
4334
4335         if (netif_running(bp->dev) && sig)
4336                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4337 }
4338
4339 static void
4340 bnx2_setup_msix_tbl(struct bnx2 *bp)
4341 {
4342         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4343
4344         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4345         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4346 }
4347
4348 static int
4349 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4350 {
4351         u32 val;
4352         int i, rc = 0;
4353         u8 old_port;
4354
4355         /* Wait for the current PCI transaction to complete before
4356          * issuing a reset. */
4357         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4358                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4359                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4360                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4361                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4362         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4363         udelay(5);
4364
4365         /* Wait for the firmware to tell us it is ok to issue a reset. */
4366         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4367
4368         /* Deposit a driver reset signature so the firmware knows that
4369          * this is a soft reset. */
4370         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4371                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4372
4373         /* Do a dummy read to force the chip to complete all current transaction
4374          * before we issue a reset. */
4375         val = REG_RD(bp, BNX2_MISC_ID);
4376
4377         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4378                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4379                 REG_RD(bp, BNX2_MISC_COMMAND);
4380                 udelay(5);
4381
4382                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4383                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4384
4385                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4386
4387         } else {
4388                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4389                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4390                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4391
4392                 /* Chip reset. */
4393                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4394
4395                 /* Reading back any register after chip reset will hang the
4396                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4397                  * of margin for write posting.
4398                  */
4399                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4400                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4401                         msleep(20);
4402
4403                 /* Reset takes approximate 30 usec */
4404                 for (i = 0; i < 10; i++) {
4405                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4406                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4407                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4408                                 break;
4409                         udelay(10);
4410                 }
4411
4412                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4413                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4414                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4415                         return -EBUSY;
4416                 }
4417         }
4418
4419         /* Make sure byte swapping is properly configured. */
4420         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4421         if (val != 0x01020304) {
4422                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4423                 return -ENODEV;
4424         }
4425
4426         /* Wait for the firmware to finish its initialization. */
4427         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4428         if (rc)
4429                 return rc;
4430
4431         spin_lock_bh(&bp->phy_lock);
4432         old_port = bp->phy_port;
4433         bnx2_init_fw_cap(bp);
4434         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4435             old_port != bp->phy_port)
4436                 bnx2_set_default_remote_link(bp);
4437         spin_unlock_bh(&bp->phy_lock);
4438
4439         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4440                 /* Adjust the voltage regular to two steps lower.  The default
4441                  * of this register is 0x0000000e. */
4442                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4443
4444                 /* Remove bad rbuf memory from the free pool. */
4445                 rc = bnx2_alloc_bad_rbuf(bp);
4446         }
4447
4448         if (bp->flags & BNX2_FLAG_USING_MSIX)
4449                 bnx2_setup_msix_tbl(bp);
4450
4451         return rc;
4452 }
4453
4454 static int
4455 bnx2_init_chip(struct bnx2 *bp)
4456 {
4457         u32 val;
4458         int rc, i;
4459
4460         /* Make sure the interrupt is not active. */
4461         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4462
4463         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4464               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4465 #ifdef __BIG_ENDIAN
4466               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4467 #endif
4468               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4469               DMA_READ_CHANS << 12 |
4470               DMA_WRITE_CHANS << 16;
4471
4472         val |= (0x2 << 20) | (1 << 11);
4473
4474         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4475                 val |= (1 << 23);
4476
4477         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4478             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4479                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4480
4481         REG_WR(bp, BNX2_DMA_CONFIG, val);
4482
4483         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4484                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4485                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4486                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4487         }
4488
4489         if (bp->flags & BNX2_FLAG_PCIX) {
4490                 u16 val16;
4491
4492                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4493                                      &val16);
4494                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4495                                       val16 & ~PCI_X_CMD_ERO);
4496         }
4497
4498         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4499                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4500                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4501                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4502
4503         /* Initialize context mapping and zero out the quick contexts.  The
4504          * context block must have already been enabled. */
4505         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4506                 rc = bnx2_init_5709_context(bp);
4507                 if (rc)
4508                         return rc;
4509         } else
4510                 bnx2_init_context(bp);
4511
4512         if ((rc = bnx2_init_cpus(bp)) != 0)
4513                 return rc;
4514
4515         bnx2_init_nvram(bp);
4516
4517         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4518
4519         val = REG_RD(bp, BNX2_MQ_CONFIG);
4520         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4521         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4522         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4523                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4524
4525         REG_WR(bp, BNX2_MQ_CONFIG, val);
4526
4527         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4528         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4529         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4530
4531         val = (BCM_PAGE_BITS - 8) << 24;
4532         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4533
4534         /* Configure page size. */
4535         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4536         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4537         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4538         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4539
4540         val = bp->mac_addr[0] +
4541               (bp->mac_addr[1] << 8) +
4542               (bp->mac_addr[2] << 16) +
4543               bp->mac_addr[3] +
4544               (bp->mac_addr[4] << 8) +
4545               (bp->mac_addr[5] << 16);
4546         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4547
4548         /* Program the MTU.  Also include 4 bytes for CRC32. */
4549         val = bp->dev->mtu + ETH_HLEN + 4;
4550         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4551                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4552         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4553
4554         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4555                 bp->bnx2_napi[i].last_status_idx = 0;
4556
4557         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4558
4559         /* Set up how to generate a link change interrupt. */
4560         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4561
4562         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4563                (u64) bp->status_blk_mapping & 0xffffffff);
4564         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4565
4566         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4567                (u64) bp->stats_blk_mapping & 0xffffffff);
4568         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4569                (u64) bp->stats_blk_mapping >> 32);
4570
4571         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4572                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4573
4574         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4575                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4576
4577         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4578                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4579
4580         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4581
4582         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4583
4584         REG_WR(bp, BNX2_HC_COM_TICKS,
4585                (bp->com_ticks_int << 16) | bp->com_ticks);
4586
4587         REG_WR(bp, BNX2_HC_CMD_TICKS,
4588                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4589
4590         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4591                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4592         else
4593                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4594         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4595
4596         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4597                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4598         else {
4599                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4600                       BNX2_HC_CONFIG_COLLECT_STATS;
4601         }
4602
4603         if (bp->irq_nvecs > 1) {
4604                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4605                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4606
4607                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4608         }
4609
4610         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4611                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4612
4613         REG_WR(bp, BNX2_HC_CONFIG, val);
4614
4615         for (i = 1; i < bp->irq_nvecs; i++) {
4616                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4617                            BNX2_HC_SB_CONFIG_1;
4618
4619                 REG_WR(bp, base,
4620                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4621                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4622                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4623
4624                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4625                         (bp->tx_quick_cons_trip_int << 16) |
4626                          bp->tx_quick_cons_trip);
4627
4628                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4629                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4630
4631                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4632                        (bp->rx_quick_cons_trip_int << 16) |
4633                         bp->rx_quick_cons_trip);
4634
4635                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4636                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4637         }
4638
4639         /* Clear internal stats counters. */
4640         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4641
4642         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4643
4644         /* Initialize the receive filter. */
4645         bnx2_set_rx_mode(bp->dev);
4646
4647         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4648                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4649                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4650                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4651         }
4652         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4653                           1, 0);
4654
4655         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4656         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4657
4658         udelay(20);
4659
4660         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4661
4662         return rc;
4663 }
4664
4665 static void
4666 bnx2_clear_ring_states(struct bnx2 *bp)
4667 {
4668         struct bnx2_napi *bnapi;
4669         struct bnx2_tx_ring_info *txr;
4670         struct bnx2_rx_ring_info *rxr;
4671         int i;
4672
4673         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4674                 bnapi = &bp->bnx2_napi[i];
4675                 txr = &bnapi->tx_ring;
4676                 rxr = &bnapi->rx_ring;
4677
4678                 txr->tx_cons = 0;
4679                 txr->hw_tx_cons = 0;
4680                 rxr->rx_prod_bseq = 0;
4681                 rxr->rx_prod = 0;
4682                 rxr->rx_cons = 0;
4683                 rxr->rx_pg_prod = 0;
4684                 rxr->rx_pg_cons = 0;
4685         }
4686 }
4687
4688 static void
4689 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4690 {
4691         u32 val, offset0, offset1, offset2, offset3;
4692         u32 cid_addr = GET_CID_ADDR(cid);
4693
4694         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4695                 offset0 = BNX2_L2CTX_TYPE_XI;
4696                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4697                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4698                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4699         } else {
4700                 offset0 = BNX2_L2CTX_TYPE;
4701                 offset1 = BNX2_L2CTX_CMD_TYPE;
4702                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4703                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4704         }
4705         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4706         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4707
4708         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4709         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4710
4711         val = (u64) txr->tx_desc_mapping >> 32;
4712         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4713
4714         val = (u64) txr->tx_desc_mapping & 0xffffffff;
4715         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4716 }
4717
4718 static void
4719 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4720 {
4721         struct tx_bd *txbd;
4722         u32 cid = TX_CID;
4723         struct bnx2_napi *bnapi;
4724         struct bnx2_tx_ring_info *txr;
4725
4726         bnapi = &bp->bnx2_napi[ring_num];
4727         txr = &bnapi->tx_ring;
4728
4729         if (ring_num == 0)
4730                 cid = TX_CID;
4731         else
4732                 cid = TX_TSS_CID + ring_num - 1;
4733
4734         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4735
4736         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4737
4738         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4739         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4740
4741         txr->tx_prod = 0;
4742         txr->tx_prod_bseq = 0;
4743
4744         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4745         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4746
4747         bnx2_init_tx_context(bp, cid, txr);
4748 }
4749
4750 static void
4751 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4752                      int num_rings)
4753 {
4754         int i;
4755         struct rx_bd *rxbd;
4756
4757         for (i = 0; i < num_rings; i++) {
4758                 int j;
4759
4760                 rxbd = &rx_ring[i][0];
4761                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4762                         rxbd->rx_bd_len = buf_size;
4763                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4764                 }
4765                 if (i == (num_rings - 1))
4766                         j = 0;
4767                 else
4768                         j = i + 1;
4769                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4770                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4771         }
4772 }
4773
4774 static void
4775 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4776 {
4777         int i;
4778         u16 prod, ring_prod;
4779         u32 cid, rx_cid_addr, val;
4780         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4781         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4782
4783         if (ring_num == 0)
4784                 cid = RX_CID;
4785         else
4786                 cid = RX_RSS_CID + ring_num - 1;
4787
4788         rx_cid_addr = GET_CID_ADDR(cid);
4789
4790         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4791                              bp->rx_buf_use_size, bp->rx_max_ring);
4792
4793         bnx2_init_rx_context(bp, cid);
4794
4795         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4796                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4797                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4798         }
4799
4800         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4801         if (bp->rx_pg_ring_size) {
4802                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4803                                      rxr->rx_pg_desc_mapping,
4804                                      PAGE_SIZE, bp->rx_max_pg_ring);
4805                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4806                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4807                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4808                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4809
4810                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4811                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4812
4813                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4814                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4815
4816                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4817                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4818         }
4819
4820         val = (u64) rxr->rx_desc_mapping[0] >> 32;
4821         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4822
4823         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4824         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4825
4826         ring_prod = prod = rxr->rx_pg_prod;
4827         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4828                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4829                         break;
4830                 prod = NEXT_RX_BD(prod);
4831                 ring_prod = RX_PG_RING_IDX(prod);
4832         }
4833         rxr->rx_pg_prod = prod;
4834
4835         ring_prod = prod = rxr->rx_prod;
4836         for (i = 0; i < bp->rx_ring_size; i++) {
4837                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4838                         break;
4839                 prod = NEXT_RX_BD(prod);
4840                 ring_prod = RX_RING_IDX(prod);
4841         }
4842         rxr->rx_prod = prod;
4843
4844         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4845         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4846         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4847
4848         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4849         REG_WR16(bp, rxr->rx_bidx_addr, prod);
4850
4851         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4852 }
4853
4854 static void
4855 bnx2_init_all_rings(struct bnx2 *bp)
4856 {
4857         int i;
4858         u32 val;
4859
4860         bnx2_clear_ring_states(bp);
4861
4862         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4863         for (i = 0; i < bp->num_tx_rings; i++)
4864                 bnx2_init_tx_ring(bp, i);
4865
4866         if (bp->num_tx_rings > 1)
4867                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4868                        (TX_TSS_CID << 7));
4869
4870         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4871         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4872
4873         for (i = 0; i < bp->num_rx_rings; i++)
4874                 bnx2_init_rx_ring(bp, i);
4875
4876         if (bp->num_rx_rings > 1) {
4877                 u32 tbl_32;
4878                 u8 *tbl = (u8 *) &tbl_32;
4879
4880                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4881                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4882
4883                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4884                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
4885                         if ((i % 4) == 3)
4886                                 bnx2_reg_wr_ind(bp,
4887                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
4888                                                 cpu_to_be32(tbl_32));
4889                 }
4890
4891                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4892                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4893
4894                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4895
4896         }
4897 }
4898
4899 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4900 {
4901         u32 max, num_rings = 1;
4902
4903         while (ring_size > MAX_RX_DESC_CNT) {
4904                 ring_size -= MAX_RX_DESC_CNT;
4905                 num_rings++;
4906         }
4907         /* round to next power of 2 */
4908         max = max_size;
4909         while ((max & num_rings) == 0)
4910                 max >>= 1;
4911
4912         if (num_rings != max)
4913                 max <<= 1;
4914
4915         return max;
4916 }
4917
4918 static void
4919 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4920 {
4921         u32 rx_size, rx_space, jumbo_size;
4922
4923         /* 8 for CRC and VLAN */
4924         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4925
4926         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4927                 sizeof(struct skb_shared_info);
4928
4929         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4930         bp->rx_pg_ring_size = 0;
4931         bp->rx_max_pg_ring = 0;
4932         bp->rx_max_pg_ring_idx = 0;
4933         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4934                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4935
4936                 jumbo_size = size * pages;
4937                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4938                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4939
4940                 bp->rx_pg_ring_size = jumbo_size;
4941                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4942                                                         MAX_RX_PG_RINGS);
4943                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4944                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4945                 bp->rx_copy_thresh = 0;
4946         }
4947
4948         bp->rx_buf_use_size = rx_size;
4949         /* hw alignment */
4950         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4951         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4952         bp->rx_ring_size = size;
4953         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4954         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4955 }
4956
4957 static void
4958 bnx2_free_tx_skbs(struct bnx2 *bp)
4959 {
4960         int i;
4961
4962         for (i = 0; i < bp->num_tx_rings; i++) {
4963                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4964                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4965                 int j;
4966
4967                 if (txr->tx_buf_ring == NULL)
4968                         continue;
4969
4970                 for (j = 0; j < TX_DESC_CNT; ) {
4971                         struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4972                         struct sk_buff *skb = tx_buf->skb;
4973                         int k, last;
4974
4975                         if (skb == NULL) {
4976                                 j++;
4977                                 continue;
4978                         }
4979
4980                         pci_unmap_single(bp->pdev,
4981                                          pci_unmap_addr(tx_buf, mapping),
4982                         skb_headlen(skb), PCI_DMA_TODEVICE);
4983
4984                         tx_buf->skb = NULL;
4985
4986                         last = skb_shinfo(skb)->nr_frags;
4987                         for (k = 0; k < last; k++) {
4988                                 tx_buf = &txr->tx_buf_ring[j + k + 1];
4989                                 pci_unmap_page(bp->pdev,
4990                                         pci_unmap_addr(tx_buf, mapping),
4991                                         skb_shinfo(skb)->frags[j].size,
4992                                         PCI_DMA_TODEVICE);
4993                         }
4994                         dev_kfree_skb(skb);
4995                         j += k + 1;
4996                 }
4997         }
4998 }
4999
5000 static void
5001 bnx2_free_rx_skbs(struct bnx2 *bp)
5002 {
5003         int i;
5004
5005         for (i = 0; i < bp->num_rx_rings; i++) {
5006                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5007                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5008                 int j;
5009
5010                 if (rxr->rx_buf_ring == NULL)
5011                         return;
5012
5013                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5014                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5015                         struct sk_buff *skb = rx_buf->skb;
5016
5017                         if (skb == NULL)
5018                                 continue;
5019
5020                         pci_unmap_single(bp->pdev,
5021                                          pci_unmap_addr(rx_buf, mapping),
5022                                          bp->rx_buf_use_size,
5023                                          PCI_DMA_FROMDEVICE);
5024
5025                         rx_buf->skb = NULL;
5026
5027                         dev_kfree_skb(skb);
5028                 }
5029                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5030                         bnx2_free_rx_page(bp, rxr, j);
5031         }
5032 }
5033
5034 static void
5035 bnx2_free_skbs(struct bnx2 *bp)
5036 {
5037         bnx2_free_tx_skbs(bp);
5038         bnx2_free_rx_skbs(bp);
5039 }
5040
5041 static int
5042 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5043 {
5044         int rc;
5045
5046         rc = bnx2_reset_chip(bp, reset_code);
5047         bnx2_free_skbs(bp);
5048         if (rc)
5049                 return rc;
5050
5051         if ((rc = bnx2_init_chip(bp)) != 0)
5052                 return rc;
5053
5054         bnx2_init_all_rings(bp);
5055         return 0;
5056 }
5057
5058 static int
5059 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5060 {
5061         int rc;
5062
5063         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5064                 return rc;
5065
5066         spin_lock_bh(&bp->phy_lock);
5067         bnx2_init_phy(bp, reset_phy);
5068         bnx2_set_link(bp);
5069         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5070                 bnx2_remote_phy_event(bp);
5071         spin_unlock_bh(&bp->phy_lock);
5072         return 0;
5073 }
5074
5075 static int
5076 bnx2_test_registers(struct bnx2 *bp)
5077 {
5078         int ret;
5079         int i, is_5709;
5080         static const struct {
5081                 u16   offset;
5082                 u16   flags;
5083 #define BNX2_FL_NOT_5709        1
5084                 u32   rw_mask;
5085                 u32   ro_mask;
5086         } reg_tbl[] = {
5087                 { 0x006c, 0, 0x00000000, 0x0000003f },
5088                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5089                 { 0x0094, 0, 0x00000000, 0x00000000 },
5090
5091                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5092                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5093                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5094                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5095                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5096                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5097                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5098                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5099                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5100
5101                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5102                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5103                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5104                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5105                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5106                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5107
5108                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5109                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5110                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5111
5112                 { 0x1000, 0, 0x00000000, 0x00000001 },
5113                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5114
5115                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5116                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5117                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5118                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5119                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5120                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5121                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5122                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5123                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5124                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5125
5126                 { 0x1800, 0, 0x00000000, 0x00000001 },
5127                 { 0x1804, 0, 0x00000000, 0x00000003 },
5128
5129                 { 0x2800, 0, 0x00000000, 0x00000001 },
5130                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5131                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5132                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5133                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5134                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5135                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5136                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5137                 { 0x2840, 0, 0x00000000, 0xffffffff },
5138                 { 0x2844, 0, 0x00000000, 0xffffffff },
5139                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5140                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5141
5142                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5143                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5144
5145                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5146                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5147                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5148                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5149                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5150                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5151                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5152                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5153                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5154
5155                 { 0x5004, 0, 0x00000000, 0x0000007f },
5156                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5157
5158                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5159                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5160                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5161                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5162                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5163                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5164                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5165                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5166                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5167
5168                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5169                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5170                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5171                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5172                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5173                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5174                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5175                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5176                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5177                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5178                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5179                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5180                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5181                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5182                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5183                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5184                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5185                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5186                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5187                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5188                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5189                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5190                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5191
5192                 { 0xffff, 0, 0x00000000, 0x00000000 },
5193         };
5194
5195         ret = 0;
5196         is_5709 = 0;
5197         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5198                 is_5709 = 1;
5199
5200         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5201                 u32 offset, rw_mask, ro_mask, save_val, val;
5202                 u16 flags = reg_tbl[i].flags;
5203
5204                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5205                         continue;
5206
5207                 offset = (u32) reg_tbl[i].offset;
5208                 rw_mask = reg_tbl[i].rw_mask;
5209                 ro_mask = reg_tbl[i].ro_mask;
5210
5211                 save_val = readl(bp->regview + offset);
5212
5213                 writel(0, bp->regview + offset);
5214
5215                 val = readl(bp->regview + offset);
5216                 if ((val & rw_mask) != 0) {
5217                         goto reg_test_err;
5218                 }
5219
5220                 if ((val & ro_mask) != (save_val & ro_mask)) {
5221                         goto reg_test_err;
5222                 }
5223
5224                 writel(0xffffffff, bp->regview + offset);
5225
5226                 val = readl(bp->regview + offset);
5227                 if ((val & rw_mask) != rw_mask) {
5228                         goto reg_test_err;
5229                 }
5230
5231                 if ((val & ro_mask) != (save_val & ro_mask)) {
5232                         goto reg_test_err;
5233                 }
5234
5235                 writel(save_val, bp->regview + offset);
5236                 continue;
5237
5238 reg_test_err:
5239                 writel(save_val, bp->regview + offset);
5240                 ret = -ENODEV;
5241                 break;
5242         }
5243         return ret;
5244 }
5245
5246 static int
5247 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5248 {
5249         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5250                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5251         int i;
5252
5253         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5254                 u32 offset;
5255
5256                 for (offset = 0; offset < size; offset += 4) {
5257
5258                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5259
5260                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5261                                 test_pattern[i]) {
5262                                 return -ENODEV;
5263                         }
5264                 }
5265         }
5266         return 0;
5267 }
5268
5269 static int
5270 bnx2_test_memory(struct bnx2 *bp)
5271 {
5272         int ret = 0;
5273         int i;
5274         static struct mem_entry {
5275                 u32   offset;
5276                 u32   len;
5277         } mem_tbl_5706[] = {
5278                 { 0x60000,  0x4000 },
5279                 { 0xa0000,  0x3000 },
5280                 { 0xe0000,  0x4000 },
5281                 { 0x120000, 0x4000 },
5282                 { 0x1a0000, 0x4000 },
5283                 { 0x160000, 0x4000 },
5284                 { 0xffffffff, 0    },
5285         },
5286         mem_tbl_5709[] = {
5287                 { 0x60000,  0x4000 },
5288                 { 0xa0000,  0x3000 },
5289                 { 0xe0000,  0x4000 },
5290                 { 0x120000, 0x4000 },
5291                 { 0x1a0000, 0x4000 },
5292                 { 0xffffffff, 0    },
5293         };
5294         struct mem_entry *mem_tbl;
5295
5296         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5297                 mem_tbl = mem_tbl_5709;
5298         else
5299                 mem_tbl = mem_tbl_5706;
5300
5301         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5302                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5303                         mem_tbl[i].len)) != 0) {
5304                         return ret;
5305                 }
5306         }
5307
5308         return ret;
5309 }
5310
5311 #define BNX2_MAC_LOOPBACK       0
5312 #define BNX2_PHY_LOOPBACK       1
5313
5314 static int
5315 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5316 {
5317         unsigned int pkt_size, num_pkts, i;
5318         struct sk_buff *skb, *rx_skb;
5319         unsigned char *packet;
5320         u16 rx_start_idx, rx_idx;
5321         dma_addr_t map;
5322         struct tx_bd *txbd;
5323         struct sw_bd *rx_buf;
5324         struct l2_fhdr *rx_hdr;
5325         int ret = -ENODEV;
5326         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5327         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5328         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5329
5330         tx_napi = bnapi;
5331
5332         txr = &tx_napi->tx_ring;
5333         rxr = &bnapi->rx_ring;
5334         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5335                 bp->loopback = MAC_LOOPBACK;
5336                 bnx2_set_mac_loopback(bp);
5337         }
5338         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5339                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5340                         return 0;
5341
5342                 bp->loopback = PHY_LOOPBACK;
5343                 bnx2_set_phy_loopback(bp);
5344         }
5345         else
5346                 return -EINVAL;
5347
5348         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5349         skb = netdev_alloc_skb(bp->dev, pkt_size);
5350         if (!skb)
5351                 return -ENOMEM;
5352         packet = skb_put(skb, pkt_size);
5353         memcpy(packet, bp->dev->dev_addr, 6);
5354         memset(packet + 6, 0x0, 8);
5355         for (i = 14; i < pkt_size; i++)
5356                 packet[i] = (unsigned char) (i & 0xff);
5357
5358         map = pci_map_single(bp->pdev, skb->data, pkt_size,
5359                 PCI_DMA_TODEVICE);
5360
5361         REG_WR(bp, BNX2_HC_COMMAND,
5362                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5363
5364         REG_RD(bp, BNX2_HC_COMMAND);
5365
5366         udelay(5);
5367         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5368
5369         num_pkts = 0;
5370
5371         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5372
5373         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5374         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5375         txbd->tx_bd_mss_nbytes = pkt_size;
5376         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5377
5378         num_pkts++;
5379         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5380         txr->tx_prod_bseq += pkt_size;
5381
5382         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5383         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5384
5385         udelay(100);
5386
5387         REG_WR(bp, BNX2_HC_COMMAND,
5388                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5389
5390         REG_RD(bp, BNX2_HC_COMMAND);
5391
5392         udelay(5);
5393
5394         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5395         dev_kfree_skb(skb);
5396
5397         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5398                 goto loopback_test_done;
5399
5400         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5401         if (rx_idx != rx_start_idx + num_pkts) {
5402                 goto loopback_test_done;
5403         }
5404
5405         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5406         rx_skb = rx_buf->skb;
5407
5408         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5409         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5410
5411         pci_dma_sync_single_for_cpu(bp->pdev,
5412                 pci_unmap_addr(rx_buf, mapping),
5413                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5414
5415         if (rx_hdr->l2_fhdr_status &
5416                 (L2_FHDR_ERRORS_BAD_CRC |
5417                 L2_FHDR_ERRORS_PHY_DECODE |
5418                 L2_FHDR_ERRORS_ALIGNMENT |
5419                 L2_FHDR_ERRORS_TOO_SHORT |
5420                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5421
5422                 goto loopback_test_done;
5423         }
5424
5425         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5426                 goto loopback_test_done;
5427         }
5428
5429         for (i = 14; i < pkt_size; i++) {
5430                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5431                         goto loopback_test_done;
5432                 }
5433         }
5434
5435         ret = 0;
5436
5437 loopback_test_done:
5438         bp->loopback = 0;
5439         return ret;
5440 }
5441
5442 #define BNX2_MAC_LOOPBACK_FAILED        1
5443 #define BNX2_PHY_LOOPBACK_FAILED        2
5444 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5445                                          BNX2_PHY_LOOPBACK_FAILED)
5446
5447 static int
5448 bnx2_test_loopback(struct bnx2 *bp)
5449 {
5450         int rc = 0;
5451
5452         if (!netif_running(bp->dev))
5453                 return BNX2_LOOPBACK_FAILED;
5454
5455         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5456         spin_lock_bh(&bp->phy_lock);
5457         bnx2_init_phy(bp, 1);
5458         spin_unlock_bh(&bp->phy_lock);
5459         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5460                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5461         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5462                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5463         return rc;
5464 }
5465
5466 #define NVRAM_SIZE 0x200
5467 #define CRC32_RESIDUAL 0xdebb20e3
5468
5469 static int
5470 bnx2_test_nvram(struct bnx2 *bp)
5471 {
5472         __be32 buf[NVRAM_SIZE / 4];
5473         u8 *data = (u8 *) buf;
5474         int rc = 0;
5475         u32 magic, csum;
5476
5477         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5478                 goto test_nvram_done;
5479
5480         magic = be32_to_cpu(buf[0]);
5481         if (magic != 0x669955aa) {
5482                 rc = -ENODEV;
5483                 goto test_nvram_done;
5484         }
5485
5486         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5487                 goto test_nvram_done;
5488
5489         csum = ether_crc_le(0x100, data);
5490         if (csum != CRC32_RESIDUAL) {
5491                 rc = -ENODEV;
5492                 goto test_nvram_done;
5493         }
5494
5495         csum = ether_crc_le(0x100, data + 0x100);
5496         if (csum != CRC32_RESIDUAL) {
5497                 rc = -ENODEV;
5498         }
5499
5500 test_nvram_done:
5501         return rc;
5502 }
5503
5504 static int
5505 bnx2_test_link(struct bnx2 *bp)
5506 {
5507         u32 bmsr;
5508
5509         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5510                 if (bp->link_up)
5511                         return 0;
5512                 return -ENODEV;
5513         }
5514         spin_lock_bh(&bp->phy_lock);
5515         bnx2_enable_bmsr1(bp);
5516         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5517         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5518         bnx2_disable_bmsr1(bp);
5519         spin_unlock_bh(&bp->phy_lock);
5520
5521         if (bmsr & BMSR_LSTATUS) {
5522                 return 0;
5523         }
5524         return -ENODEV;
5525 }
5526
5527 static int
5528 bnx2_test_intr(struct bnx2 *bp)
5529 {
5530         int i;
5531         u16 status_idx;
5532
5533         if (!netif_running(bp->dev))
5534                 return -ENODEV;
5535
5536         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5537
5538         /* This register is not touched during run-time. */
5539         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5540         REG_RD(bp, BNX2_HC_COMMAND);
5541
5542         for (i = 0; i < 10; i++) {
5543                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5544                         status_idx) {
5545
5546                         break;
5547                 }
5548
5549                 msleep_interruptible(10);
5550         }
5551         if (i < 10)
5552                 return 0;
5553
5554         return -ENODEV;
5555 }
5556
5557 /* Determining link for parallel detection. */
5558 static int
5559 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5560 {
5561         u32 mode_ctl, an_dbg, exp;
5562
5563         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5564                 return 0;
5565
5566         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5567         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5568
5569         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5570                 return 0;
5571
5572         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5573         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5574         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5575
5576         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5577                 return 0;
5578
5579         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5580         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5581         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5582
5583         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5584                 return 0;
5585
5586         return 1;
5587 }
5588
5589 static void
5590 bnx2_5706_serdes_timer(struct bnx2 *bp)
5591 {
5592         int check_link = 1;
5593
5594         spin_lock(&bp->phy_lock);
5595         if (bp->serdes_an_pending) {
5596                 bp->serdes_an_pending--;
5597                 check_link = 0;
5598         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5599                 u32 bmcr;
5600
5601                 bp->current_interval = BNX2_TIMER_INTERVAL;
5602
5603                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5604
5605                 if (bmcr & BMCR_ANENABLE) {
5606                         if (bnx2_5706_serdes_has_link(bp)) {
5607                                 bmcr &= ~BMCR_ANENABLE;
5608                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5609                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5610                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5611                         }
5612                 }
5613         }
5614         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5615                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5616                 u32 phy2;
5617
5618                 bnx2_write_phy(bp, 0x17, 0x0f01);
5619                 bnx2_read_phy(bp, 0x15, &phy2);
5620                 if (phy2 & 0x20) {
5621                         u32 bmcr;
5622
5623                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5624                         bmcr |= BMCR_ANENABLE;
5625                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5626
5627                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5628                 }
5629         } else
5630                 bp->current_interval = BNX2_TIMER_INTERVAL;
5631
5632         if (check_link) {
5633                 u32 val;
5634
5635                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5636                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5637                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5638
5639                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5640                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5641                                 bnx2_5706s_force_link_dn(bp, 1);
5642                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5643                         } else
5644                                 bnx2_set_link(bp);
5645                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5646                         bnx2_set_link(bp);
5647         }
5648         spin_unlock(&bp->phy_lock);
5649 }
5650
5651 static void
5652 bnx2_5708_serdes_timer(struct bnx2 *bp)
5653 {
5654         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5655                 return;
5656
5657         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5658                 bp->serdes_an_pending = 0;
5659                 return;
5660         }
5661
5662         spin_lock(&bp->phy_lock);
5663         if (bp->serdes_an_pending)
5664                 bp->serdes_an_pending--;
5665         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5666                 u32 bmcr;
5667
5668                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5669                 if (bmcr & BMCR_ANENABLE) {
5670                         bnx2_enable_forced_2g5(bp);
5671                         bp->current_interval = SERDES_FORCED_TIMEOUT;
5672                 } else {
5673                         bnx2_disable_forced_2g5(bp);
5674                         bp->serdes_an_pending = 2;
5675                         bp->current_interval = BNX2_TIMER_INTERVAL;
5676                 }
5677
5678         } else
5679                 bp->current_interval = BNX2_TIMER_INTERVAL;
5680
5681         spin_unlock(&bp->phy_lock);
5682 }
5683
5684 static void
5685 bnx2_timer(unsigned long data)
5686 {
5687         struct bnx2 *bp = (struct bnx2 *) data;
5688
5689         if (!netif_running(bp->dev))
5690                 return;
5691
5692         if (atomic_read(&bp->intr_sem) != 0)
5693                 goto bnx2_restart_timer;
5694
5695         bnx2_send_heart_beat(bp);
5696
5697         bp->stats_blk->stat_FwRxDrop =
5698                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5699
5700         /* workaround occasional corrupted counters */
5701         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5702                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5703                                             BNX2_HC_COMMAND_STATS_NOW);
5704
5705         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5706                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5707                         bnx2_5706_serdes_timer(bp);
5708                 else
5709                         bnx2_5708_serdes_timer(bp);
5710         }
5711
5712 bnx2_restart_timer:
5713         mod_timer(&bp->timer, jiffies + bp->current_interval);
5714 }
5715
5716 static int
5717 bnx2_request_irq(struct bnx2 *bp)
5718 {
5719         unsigned long flags;
5720         struct bnx2_irq *irq;
5721         int rc = 0, i;
5722
5723         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5724                 flags = 0;
5725         else
5726                 flags = IRQF_SHARED;
5727
5728         for (i = 0; i < bp->irq_nvecs; i++) {
5729                 irq = &bp->irq_tbl[i];
5730                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5731                                  &bp->bnx2_napi[i]);
5732                 if (rc)
5733                         break;
5734                 irq->requested = 1;
5735         }
5736         return rc;
5737 }
5738
5739 static void
5740 bnx2_free_irq(struct bnx2 *bp)
5741 {
5742         struct bnx2_irq *irq;
5743         int i;
5744
5745         for (i = 0; i < bp->irq_nvecs; i++) {
5746                 irq = &bp->irq_tbl[i];
5747                 if (irq->requested)
5748                         free_irq(irq->vector, &bp->bnx2_napi[i]);
5749                 irq->requested = 0;
5750         }
5751         if (bp->flags & BNX2_FLAG_USING_MSI)
5752                 pci_disable_msi(bp->pdev);
5753         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5754                 pci_disable_msix(bp->pdev);
5755
5756         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5757 }
5758
5759 static void
5760 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5761 {
5762         int i, rc;
5763         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5764
5765         bnx2_setup_msix_tbl(bp);
5766         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5767         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5768         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5769
5770         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5771                 msix_ent[i].entry = i;
5772                 msix_ent[i].vector = 0;
5773
5774                 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5775                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5776         }
5777
5778         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5779         if (rc != 0)
5780                 return;
5781
5782         bp->irq_nvecs = msix_vecs;
5783         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5784         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5785                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5786 }
5787
5788 static void
5789 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5790 {
5791         int cpus = num_online_cpus();
5792         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5793
5794         bp->irq_tbl[0].handler = bnx2_interrupt;
5795         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5796         bp->irq_nvecs = 1;
5797         bp->irq_tbl[0].vector = bp->pdev->irq;
5798
5799         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5800                 bnx2_enable_msix(bp, msix_vecs);
5801
5802         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5803             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5804                 if (pci_enable_msi(bp->pdev) == 0) {
5805                         bp->flags |= BNX2_FLAG_USING_MSI;
5806                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5807                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5808                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5809                         } else
5810                                 bp->irq_tbl[0].handler = bnx2_msi;
5811
5812                         bp->irq_tbl[0].vector = bp->pdev->irq;
5813                 }
5814         }
5815
5816         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5817         bp->dev->real_num_tx_queues = bp->num_tx_rings;
5818
5819         bp->num_rx_rings = bp->irq_nvecs;
5820 }
5821
5822 /* Called with rtnl_lock */
5823 static int
5824 bnx2_open(struct net_device *dev)
5825 {
5826         struct bnx2 *bp = netdev_priv(dev);
5827         int rc;
5828
5829         netif_carrier_off(dev);
5830
5831         bnx2_set_power_state(bp, PCI_D0);
5832         bnx2_disable_int(bp);
5833
5834         bnx2_setup_int_mode(bp, disable_msi);
5835         bnx2_napi_enable(bp);
5836         rc = bnx2_alloc_mem(bp);
5837         if (rc)
5838                 goto open_err;
5839
5840         rc = bnx2_request_irq(bp);
5841         if (rc)
5842                 goto open_err;
5843
5844         rc = bnx2_init_nic(bp, 1);
5845         if (rc)
5846                 goto open_err;
5847
5848         mod_timer(&bp->timer, jiffies + bp->current_interval);
5849
5850         atomic_set(&bp->intr_sem, 0);
5851
5852         bnx2_enable_int(bp);
5853
5854         if (bp->flags & BNX2_FLAG_USING_MSI) {
5855                 /* Test MSI to make sure it is working
5856                  * If MSI test fails, go back to INTx mode
5857                  */
5858                 if (bnx2_test_intr(bp) != 0) {
5859                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5860                                " using MSI, switching to INTx mode. Please"
5861                                " report this failure to the PCI maintainer"
5862                                " and include system chipset information.\n",
5863                                bp->dev->name);
5864
5865                         bnx2_disable_int(bp);
5866                         bnx2_free_irq(bp);
5867
5868                         bnx2_setup_int_mode(bp, 1);
5869
5870                         rc = bnx2_init_nic(bp, 0);
5871
5872                         if (!rc)
5873                                 rc = bnx2_request_irq(bp);
5874
5875                         if (rc) {
5876                                 del_timer_sync(&bp->timer);
5877                                 goto open_err;
5878                         }
5879                         bnx2_enable_int(bp);
5880                 }
5881         }
5882         if (bp->flags & BNX2_FLAG_USING_MSI)
5883                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5884         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5885                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5886
5887         netif_tx_start_all_queues(dev);
5888
5889         return 0;
5890
5891 open_err:
5892         bnx2_napi_disable(bp);
5893         bnx2_free_skbs(bp);
5894         bnx2_free_irq(bp);
5895         bnx2_free_mem(bp);
5896         return rc;
5897 }
5898
5899 static void
5900 bnx2_reset_task(struct work_struct *work)
5901 {
5902         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5903
5904         if (!netif_running(bp->dev))
5905                 return;
5906
5907         bnx2_netif_stop(bp);
5908
5909         bnx2_init_nic(bp, 1);
5910
5911         atomic_set(&bp->intr_sem, 1);
5912         bnx2_netif_start(bp);
5913 }
5914
5915 static void
5916 bnx2_tx_timeout(struct net_device *dev)
5917 {
5918         struct bnx2 *bp = netdev_priv(dev);
5919
5920         /* This allows the netif to be shutdown gracefully before resetting */
5921         schedule_work(&bp->reset_task);
5922 }
5923
5924 #ifdef BCM_VLAN
5925 /* Called with rtnl_lock */
5926 static void
5927 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5928 {
5929         struct bnx2 *bp = netdev_priv(dev);
5930
5931         bnx2_netif_stop(bp);
5932
5933         bp->vlgrp = vlgrp;
5934         bnx2_set_rx_mode(dev);
5935         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5936                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5937
5938         bnx2_netif_start(bp);
5939 }
5940 #endif
5941
5942 /* Called with netif_tx_lock.
5943  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5944  * netif_wake_queue().
5945  */
5946 static int
5947 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5948 {
5949         struct bnx2 *bp = netdev_priv(dev);
5950         dma_addr_t mapping;
5951         struct tx_bd *txbd;
5952         struct sw_bd *tx_buf;
5953         u32 len, vlan_tag_flags, last_frag, mss;
5954         u16 prod, ring_prod;
5955         int i;
5956         struct bnx2_napi *bnapi;
5957         struct bnx2_tx_ring_info *txr;
5958         struct netdev_queue *txq;
5959
5960         /*  Determine which tx ring we will be placed on */
5961         i = skb_get_queue_mapping(skb);
5962         bnapi = &bp->bnx2_napi[i];
5963         txr = &bnapi->tx_ring;
5964         txq = netdev_get_tx_queue(dev, i);
5965
5966         if (unlikely(bnx2_tx_avail(bp, txr) <
5967             (skb_shinfo(skb)->nr_frags + 1))) {
5968                 netif_tx_stop_queue(txq);
5969                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5970                         dev->name);
5971
5972                 return NETDEV_TX_BUSY;
5973         }
5974         len = skb_headlen(skb);
5975         prod = txr->tx_prod;
5976         ring_prod = TX_RING_IDX(prod);
5977
5978         vlan_tag_flags = 0;
5979         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5980                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5981         }
5982
5983 #ifdef BCM_VLAN
5984         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5985                 vlan_tag_flags |=
5986                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5987         }
5988 #endif
5989         if ((mss = skb_shinfo(skb)->gso_size)) {
5990                 u32 tcp_opt_len, ip_tcp_len;
5991                 struct iphdr *iph;
5992
5993                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5994
5995                 tcp_opt_len = tcp_optlen(skb);
5996
5997                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5998                         u32 tcp_off = skb_transport_offset(skb) -
5999                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6000
6001                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6002                                           TX_BD_FLAGS_SW_FLAGS;
6003                         if (likely(tcp_off == 0))
6004                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6005                         else {
6006                                 tcp_off >>= 3;
6007                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6008                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6009                                                   ((tcp_off & 0x10) <<
6010                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6011                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6012                         }
6013                 } else {
6014                         if (skb_header_cloned(skb) &&
6015                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6016                                 dev_kfree_skb(skb);
6017                                 return NETDEV_TX_OK;
6018                         }
6019
6020                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6021
6022                         iph = ip_hdr(skb);
6023                         iph->check = 0;
6024                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
6025                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6026                                                                  iph->daddr, 0,
6027                                                                  IPPROTO_TCP,
6028                                                                  0);
6029                         if (tcp_opt_len || (iph->ihl > 5)) {
6030                                 vlan_tag_flags |= ((iph->ihl - 5) +
6031                                                    (tcp_opt_len >> 2)) << 8;
6032                         }
6033                 }
6034         } else
6035                 mss = 0;
6036
6037         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6038
6039         tx_buf = &txr->tx_buf_ring[ring_prod];
6040         tx_buf->skb = skb;
6041         pci_unmap_addr_set(tx_buf, mapping, mapping);
6042
6043         txbd = &txr->tx_desc_ring[ring_prod];
6044
6045         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6046         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6047         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6048         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6049
6050         last_frag = skb_shinfo(skb)->nr_frags;
6051
6052         for (i = 0; i < last_frag; i++) {
6053                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6054
6055                 prod = NEXT_TX_BD(prod);
6056                 ring_prod = TX_RING_IDX(prod);
6057                 txbd = &txr->tx_desc_ring[ring_prod];
6058
6059                 len = frag->size;
6060                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6061                         len, PCI_DMA_TODEVICE);
6062                 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
6063                                 mapping, mapping);
6064
6065                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6066                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6067                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6068                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6069
6070         }
6071         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6072
6073         prod = NEXT_TX_BD(prod);
6074         txr->tx_prod_bseq += skb->len;
6075
6076         REG_WR16(bp, txr->tx_bidx_addr, prod);
6077         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6078
6079         mmiowb();
6080
6081         txr->tx_prod = prod;
6082         dev->trans_start = jiffies;
6083
6084         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6085                 netif_tx_stop_queue(txq);
6086                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6087                         netif_tx_wake_queue(txq);
6088         }
6089
6090         return NETDEV_TX_OK;
6091 }
6092
6093 /* Called with rtnl_lock */
6094 static int
6095 bnx2_close(struct net_device *dev)
6096 {
6097         struct bnx2 *bp = netdev_priv(dev);
6098         u32 reset_code;
6099
6100         cancel_work_sync(&bp->reset_task);
6101
6102         bnx2_disable_int_sync(bp);
6103         bnx2_napi_disable(bp);
6104         del_timer_sync(&bp->timer);
6105         if (bp->flags & BNX2_FLAG_NO_WOL)
6106                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6107         else if (bp->wol)
6108                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6109         else
6110                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6111         bnx2_reset_chip(bp, reset_code);
6112         bnx2_free_irq(bp);
6113         bnx2_free_skbs(bp);
6114         bnx2_free_mem(bp);
6115         bp->link_up = 0;
6116         netif_carrier_off(bp->dev);
6117         bnx2_set_power_state(bp, PCI_D3hot);
6118         return 0;
6119 }
6120
6121 #define GET_NET_STATS64(ctr)                                    \
6122         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6123         (unsigned long) (ctr##_lo)
6124
6125 #define GET_NET_STATS32(ctr)            \
6126         (ctr##_lo)
6127
6128 #if (BITS_PER_LONG == 64)
6129 #define GET_NET_STATS   GET_NET_STATS64
6130 #else
6131 #define GET_NET_STATS   GET_NET_STATS32
6132 #endif
6133
6134 static struct net_device_stats *
6135 bnx2_get_stats(struct net_device *dev)
6136 {
6137         struct bnx2 *bp = netdev_priv(dev);
6138         struct statistics_block *stats_blk = bp->stats_blk;
6139         struct net_device_stats *net_stats = &bp->net_stats;
6140
6141         if (bp->stats_blk == NULL) {
6142                 return net_stats;
6143         }
6144         net_stats->rx_packets =
6145                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6146                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6147                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6148
6149         net_stats->tx_packets =
6150                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6151                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6152                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6153
6154         net_stats->rx_bytes =
6155                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6156
6157         net_stats->tx_bytes =
6158                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6159
6160         net_stats->multicast =
6161                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6162
6163         net_stats->collisions =
6164                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6165
6166         net_stats->rx_length_errors =
6167                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6168                 stats_blk->stat_EtherStatsOverrsizePkts);
6169
6170         net_stats->rx_over_errors =
6171                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6172
6173         net_stats->rx_frame_errors =
6174                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6175
6176         net_stats->rx_crc_errors =
6177                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6178
6179         net_stats->rx_errors = net_stats->rx_length_errors +
6180                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6181                 net_stats->rx_crc_errors;
6182
6183         net_stats->tx_aborted_errors =
6184                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6185                 stats_blk->stat_Dot3StatsLateCollisions);
6186
6187         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6188             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6189                 net_stats->tx_carrier_errors = 0;
6190         else {
6191                 net_stats->tx_carrier_errors =
6192                         (unsigned long)
6193                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6194         }
6195
6196         net_stats->tx_errors =
6197                 (unsigned long)
6198                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6199                 +
6200                 net_stats->tx_aborted_errors +
6201                 net_stats->tx_carrier_errors;
6202
6203         net_stats->rx_missed_errors =
6204                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6205                 stats_blk->stat_FwRxDrop);
6206
6207         return net_stats;
6208 }
6209
6210 /* All ethtool functions called with rtnl_lock */
6211
6212 static int
6213 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6214 {
6215         struct bnx2 *bp = netdev_priv(dev);
6216         int support_serdes = 0, support_copper = 0;
6217
6218         cmd->supported = SUPPORTED_Autoneg;
6219         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6220                 support_serdes = 1;
6221                 support_copper = 1;
6222         } else if (bp->phy_port == PORT_FIBRE)
6223                 support_serdes = 1;
6224         else
6225                 support_copper = 1;
6226
6227         if (support_serdes) {
6228                 cmd->supported |= SUPPORTED_1000baseT_Full |
6229                         SUPPORTED_FIBRE;
6230                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6231                         cmd->supported |= SUPPORTED_2500baseX_Full;
6232
6233         }
6234         if (support_copper) {
6235                 cmd->supported |= SUPPORTED_10baseT_Half |
6236                         SUPPORTED_10baseT_Full |
6237                         SUPPORTED_100baseT_Half |
6238                         SUPPORTED_100baseT_Full |
6239                         SUPPORTED_1000baseT_Full |
6240                         SUPPORTED_TP;
6241
6242         }
6243
6244         spin_lock_bh(&bp->phy_lock);
6245         cmd->port = bp->phy_port;
6246         cmd->advertising = bp->advertising;
6247
6248         if (bp->autoneg & AUTONEG_SPEED) {
6249                 cmd->autoneg = AUTONEG_ENABLE;
6250         }
6251         else {
6252                 cmd->autoneg = AUTONEG_DISABLE;
6253         }
6254
6255         if (netif_carrier_ok(dev)) {
6256                 cmd->speed = bp->line_speed;
6257                 cmd->duplex = bp->duplex;
6258         }
6259         else {
6260                 cmd->speed = -1;
6261                 cmd->duplex = -1;
6262         }
6263         spin_unlock_bh(&bp->phy_lock);
6264
6265         cmd->transceiver = XCVR_INTERNAL;
6266         cmd->phy_address = bp->phy_addr;
6267
6268         return 0;
6269 }
6270
6271 static int
6272 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6273 {
6274         struct bnx2 *bp = netdev_priv(dev);
6275         u8 autoneg = bp->autoneg;
6276         u8 req_duplex = bp->req_duplex;
6277         u16 req_line_speed = bp->req_line_speed;
6278         u32 advertising = bp->advertising;
6279         int err = -EINVAL;
6280
6281         spin_lock_bh(&bp->phy_lock);
6282
6283         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6284                 goto err_out_unlock;
6285
6286         if (cmd->port != bp->phy_port &&
6287             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6288                 goto err_out_unlock;
6289
6290         /* If device is down, we can store the settings only if the user
6291          * is setting the currently active port.
6292          */
6293         if (!netif_running(dev) && cmd->port != bp->phy_port)
6294                 goto err_out_unlock;
6295
6296         if (cmd->autoneg == AUTONEG_ENABLE) {
6297                 autoneg |= AUTONEG_SPEED;
6298
6299                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6300
6301                 /* allow advertising 1 speed */
6302                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6303                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6304                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6305                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6306
6307                         if (cmd->port == PORT_FIBRE)
6308                                 goto err_out_unlock;
6309
6310                         advertising = cmd->advertising;
6311
6312                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6313                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6314                             (cmd->port == PORT_TP))
6315                                 goto err_out_unlock;
6316                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6317                         advertising = cmd->advertising;
6318                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6319                         goto err_out_unlock;
6320                 else {
6321                         if (cmd->port == PORT_FIBRE)
6322                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6323                         else
6324                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6325                 }
6326                 advertising |= ADVERTISED_Autoneg;
6327         }
6328         else {
6329                 if (cmd->port == PORT_FIBRE) {
6330                         if ((cmd->speed != SPEED_1000 &&
6331                              cmd->speed != SPEED_2500) ||
6332                             (cmd->duplex != DUPLEX_FULL))
6333                                 goto err_out_unlock;
6334
6335                         if (cmd->speed == SPEED_2500 &&
6336                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6337                                 goto err_out_unlock;
6338                 }
6339                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6340                         goto err_out_unlock;
6341
6342                 autoneg &= ~AUTONEG_SPEED;
6343                 req_line_speed = cmd->speed;
6344                 req_duplex = cmd->duplex;
6345                 advertising = 0;
6346         }
6347
6348         bp->autoneg = autoneg;
6349         bp->advertising = advertising;
6350         bp->req_line_speed = req_line_speed;
6351         bp->req_duplex = req_duplex;
6352
6353         err = 0;
6354         /* If device is down, the new settings will be picked up when it is
6355          * brought up.
6356          */
6357         if (netif_running(dev))
6358                 err = bnx2_setup_phy(bp, cmd->port);
6359
6360 err_out_unlock:
6361         spin_unlock_bh(&bp->phy_lock);
6362
6363         return err;
6364 }
6365
6366 static void
6367 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6368 {
6369         struct bnx2 *bp = netdev_priv(dev);
6370
6371         strcpy(info->driver, DRV_MODULE_NAME);
6372         strcpy(info->version, DRV_MODULE_VERSION);
6373         strcpy(info->bus_info, pci_name(bp->pdev));
6374         strcpy(info->fw_version, bp->fw_version);
6375 }
6376
6377 #define BNX2_REGDUMP_LEN                (32 * 1024)
6378
6379 static int
6380 bnx2_get_regs_len(struct net_device *dev)
6381 {
6382         return BNX2_REGDUMP_LEN;
6383 }
6384
6385 static void
6386 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6387 {
6388         u32 *p = _p, i, offset;
6389         u8 *orig_p = _p;
6390         struct bnx2 *bp = netdev_priv(dev);
6391         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6392                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6393                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6394                                  0x1040, 0x1048, 0x1080, 0x10a4,
6395                                  0x1400, 0x1490, 0x1498, 0x14f0,
6396                                  0x1500, 0x155c, 0x1580, 0x15dc,
6397                                  0x1600, 0x1658, 0x1680, 0x16d8,
6398                                  0x1800, 0x1820, 0x1840, 0x1854,
6399                                  0x1880, 0x1894, 0x1900, 0x1984,
6400                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6401                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6402                                  0x2000, 0x2030, 0x23c0, 0x2400,
6403                                  0x2800, 0x2820, 0x2830, 0x2850,
6404                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6405                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6406                                  0x4080, 0x4090, 0x43c0, 0x4458,
6407                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6408                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6409                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6410                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6411                                  0x6800, 0x6848, 0x684c, 0x6860,
6412                                  0x6888, 0x6910, 0x8000 };
6413
6414         regs->version = 0;
6415
6416         memset(p, 0, BNX2_REGDUMP_LEN);
6417
6418         if (!netif_running(bp->dev))
6419                 return;
6420
6421         i = 0;
6422         offset = reg_boundaries[0];
6423         p += offset;
6424         while (offset < BNX2_REGDUMP_LEN) {
6425                 *p++ = REG_RD(bp, offset);
6426                 offset += 4;
6427                 if (offset == reg_boundaries[i + 1]) {
6428                         offset = reg_boundaries[i + 2];
6429                         p = (u32 *) (orig_p + offset);
6430                         i += 2;
6431                 }
6432         }
6433 }
6434
6435 static void
6436 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6437 {
6438         struct bnx2 *bp = netdev_priv(dev);
6439
6440         if (bp->flags & BNX2_FLAG_NO_WOL) {
6441                 wol->supported = 0;
6442                 wol->wolopts = 0;
6443         }
6444         else {
6445                 wol->supported = WAKE_MAGIC;
6446                 if (bp->wol)
6447                         wol->wolopts = WAKE_MAGIC;
6448                 else
6449                         wol->wolopts = 0;
6450         }
6451         memset(&wol->sopass, 0, sizeof(wol->sopass));
6452 }
6453
6454 static int
6455 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6456 {
6457         struct bnx2 *bp = netdev_priv(dev);
6458
6459         if (wol->wolopts & ~WAKE_MAGIC)
6460                 return -EINVAL;
6461
6462         if (wol->wolopts & WAKE_MAGIC) {
6463                 if (bp->flags & BNX2_FLAG_NO_WOL)
6464                         return -EINVAL;
6465
6466                 bp->wol = 1;
6467         }
6468         else {
6469                 bp->wol = 0;
6470         }
6471         return 0;
6472 }
6473
6474 static int
6475 bnx2_nway_reset(struct net_device *dev)
6476 {
6477         struct bnx2 *bp = netdev_priv(dev);
6478         u32 bmcr;
6479
6480         if (!(bp->autoneg & AUTONEG_SPEED)) {
6481                 return -EINVAL;
6482         }
6483
6484         spin_lock_bh(&bp->phy_lock);
6485
6486         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6487                 int rc;
6488
6489                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6490                 spin_unlock_bh(&bp->phy_lock);
6491                 return rc;
6492         }
6493
6494         /* Force a link down visible on the other side */
6495         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6496                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6497                 spin_unlock_bh(&bp->phy_lock);
6498
6499                 msleep(20);
6500
6501                 spin_lock_bh(&bp->phy_lock);
6502
6503                 bp->current_interval = SERDES_AN_TIMEOUT;
6504                 bp->serdes_an_pending = 1;
6505                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6506         }
6507
6508         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6509         bmcr &= ~BMCR_LOOPBACK;
6510         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6511
6512         spin_unlock_bh(&bp->phy_lock);
6513
6514         return 0;
6515 }
6516
6517 static int
6518 bnx2_get_eeprom_len(struct net_device *dev)
6519 {
6520         struct bnx2 *bp = netdev_priv(dev);
6521
6522         if (bp->flash_info == NULL)
6523                 return 0;
6524
6525         return (int) bp->flash_size;
6526 }
6527
6528 static int
6529 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6530                 u8 *eebuf)
6531 {
6532         struct bnx2 *bp = netdev_priv(dev);
6533         int rc;
6534
6535         /* parameters already validated in ethtool_get_eeprom */
6536
6537         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6538
6539         return rc;
6540 }
6541
6542 static int
6543 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6544                 u8 *eebuf)
6545 {
6546         struct bnx2 *bp = netdev_priv(dev);
6547         int rc;
6548
6549         /* parameters already validated in ethtool_set_eeprom */
6550
6551         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6552
6553         return rc;
6554 }
6555
6556 static int
6557 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6558 {
6559         struct bnx2 *bp = netdev_priv(dev);
6560
6561         memset(coal, 0, sizeof(struct ethtool_coalesce));
6562
6563         coal->rx_coalesce_usecs = bp->rx_ticks;
6564         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6565         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6566         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6567
6568         coal->tx_coalesce_usecs = bp->tx_ticks;
6569         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6570         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6571         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6572
6573         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6574
6575         return 0;
6576 }
6577
6578 static int
6579 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6580 {
6581         struct bnx2 *bp = netdev_priv(dev);
6582
6583         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6584         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6585
6586         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6587         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6588
6589         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6590         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6591
6592         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6593         if (bp->rx_quick_cons_trip_int > 0xff)
6594                 bp->rx_quick_cons_trip_int = 0xff;
6595
6596         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6597         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6598
6599         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6600         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6601
6602         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6603         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6604
6605         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6606         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6607                 0xff;
6608
6609         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6610         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6611                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6612                         bp->stats_ticks = USEC_PER_SEC;
6613         }
6614         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6615                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6616         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6617
6618         if (netif_running(bp->dev)) {
6619                 bnx2_netif_stop(bp);
6620                 bnx2_init_nic(bp, 0);
6621                 bnx2_netif_start(bp);
6622         }
6623
6624         return 0;
6625 }
6626
6627 static void
6628 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6629 {
6630         struct bnx2 *bp = netdev_priv(dev);
6631
6632         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6633         ering->rx_mini_max_pending = 0;
6634         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6635
6636         ering->rx_pending = bp->rx_ring_size;
6637         ering->rx_mini_pending = 0;
6638         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6639
6640         ering->tx_max_pending = MAX_TX_DESC_CNT;
6641         ering->tx_pending = bp->tx_ring_size;
6642 }
6643
6644 static int
6645 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6646 {
6647         if (netif_running(bp->dev)) {
6648                 bnx2_netif_stop(bp);
6649                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6650                 bnx2_free_skbs(bp);
6651                 bnx2_free_mem(bp);
6652         }
6653
6654         bnx2_set_rx_ring_size(bp, rx);
6655         bp->tx_ring_size = tx;
6656
6657         if (netif_running(bp->dev)) {
6658                 int rc;
6659
6660                 rc = bnx2_alloc_mem(bp);
6661                 if (rc)
6662                         return rc;
6663                 bnx2_init_nic(bp, 0);
6664                 bnx2_netif_start(bp);
6665         }
6666         return 0;
6667 }
6668
6669 static int
6670 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6671 {
6672         struct bnx2 *bp = netdev_priv(dev);
6673         int rc;
6674
6675         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6676                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6677                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6678
6679                 return -EINVAL;
6680         }
6681         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6682         return rc;
6683 }
6684
6685 static void
6686 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6687 {
6688         struct bnx2 *bp = netdev_priv(dev);
6689
6690         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6691         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6692         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6693 }
6694
6695 static int
6696 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6697 {
6698         struct bnx2 *bp = netdev_priv(dev);
6699
6700         bp->req_flow_ctrl = 0;
6701         if (epause->rx_pause)
6702                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6703         if (epause->tx_pause)
6704                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6705
6706         if (epause->autoneg) {
6707                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6708         }
6709         else {
6710                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6711         }
6712
6713         spin_lock_bh(&bp->phy_lock);
6714
6715         bnx2_setup_phy(bp, bp->phy_port);
6716
6717         spin_unlock_bh(&bp->phy_lock);
6718
6719         return 0;
6720 }
6721
6722 static u32
6723 bnx2_get_rx_csum(struct net_device *dev)
6724 {
6725         struct bnx2 *bp = netdev_priv(dev);
6726
6727         return bp->rx_csum;
6728 }
6729
6730 static int
6731 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6732 {
6733         struct bnx2 *bp = netdev_priv(dev);
6734
6735         bp->rx_csum = data;
6736         return 0;
6737 }
6738
6739 static int
6740 bnx2_set_tso(struct net_device *dev, u32 data)
6741 {
6742         struct bnx2 *bp = netdev_priv(dev);
6743
6744         if (data) {
6745                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6746                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6747                         dev->features |= NETIF_F_TSO6;
6748         } else
6749                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6750                                    NETIF_F_TSO_ECN);
6751         return 0;
6752 }
6753
6754 #define BNX2_NUM_STATS 46
6755
6756 static struct {
6757         char string[ETH_GSTRING_LEN];
6758 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6759         { "rx_bytes" },
6760         { "rx_error_bytes" },
6761         { "tx_bytes" },
6762         { "tx_error_bytes" },
6763         { "rx_ucast_packets" },
6764         { "rx_mcast_packets" },
6765         { "rx_bcast_packets" },
6766         { "tx_ucast_packets" },
6767         { "tx_mcast_packets" },
6768         { "tx_bcast_packets" },
6769         { "tx_mac_errors" },
6770         { "tx_carrier_errors" },
6771         { "rx_crc_errors" },
6772         { "rx_align_errors" },
6773         { "tx_single_collisions" },
6774         { "tx_multi_collisions" },
6775         { "tx_deferred" },
6776         { "tx_excess_collisions" },
6777         { "tx_late_collisions" },
6778         { "tx_total_collisions" },
6779         { "rx_fragments" },
6780         { "rx_jabbers" },
6781         { "rx_undersize_packets" },
6782         { "rx_oversize_packets" },
6783         { "rx_64_byte_packets" },
6784         { "rx_65_to_127_byte_packets" },
6785         { "rx_128_to_255_byte_packets" },
6786         { "rx_256_to_511_byte_packets" },
6787         { "rx_512_to_1023_byte_packets" },
6788         { "rx_1024_to_1522_byte_packets" },
6789         { "rx_1523_to_9022_byte_packets" },
6790         { "tx_64_byte_packets" },
6791         { "tx_65_to_127_byte_packets" },
6792         { "tx_128_to_255_byte_packets" },
6793         { "tx_256_to_511_byte_packets" },
6794         { "tx_512_to_1023_byte_packets" },
6795         { "tx_1024_to_1522_byte_packets" },
6796         { "tx_1523_to_9022_byte_packets" },
6797         { "rx_xon_frames" },
6798         { "rx_xoff_frames" },
6799         { "tx_xon_frames" },
6800         { "tx_xoff_frames" },
6801         { "rx_mac_ctrl_frames" },
6802         { "rx_filtered_packets" },
6803         { "rx_discards" },
6804         { "rx_fw_discards" },
6805 };
6806
6807 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6808
6809 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6810     STATS_OFFSET32(stat_IfHCInOctets_hi),
6811     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6812     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6813     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6814     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6815     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6816     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6817     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6818     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6819     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6820     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6821     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6822     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6823     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6824     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6825     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6826     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6827     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6828     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6829     STATS_OFFSET32(stat_EtherStatsCollisions),
6830     STATS_OFFSET32(stat_EtherStatsFragments),
6831     STATS_OFFSET32(stat_EtherStatsJabbers),
6832     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6833     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6834     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6835     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6836     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6837     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6838     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6839     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6840     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6841     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6842     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6843     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6844     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6845     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6846     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6847     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6848     STATS_OFFSET32(stat_XonPauseFramesReceived),
6849     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6850     STATS_OFFSET32(stat_OutXonSent),
6851     STATS_OFFSET32(stat_OutXoffSent),
6852     STATS_OFFSET32(stat_MacControlFramesReceived),
6853     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6854     STATS_OFFSET32(stat_IfInMBUFDiscards),
6855     STATS_OFFSET32(stat_FwRxDrop),
6856 };
6857
6858 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6859  * skipped because of errata.
6860  */
6861 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6862         8,0,8,8,8,8,8,8,8,8,
6863         4,0,4,4,4,4,4,4,4,4,
6864         4,4,4,4,4,4,4,4,4,4,
6865         4,4,4,4,4,4,4,4,4,4,
6866         4,4,4,4,4,4,
6867 };
6868
6869 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6870         8,0,8,8,8,8,8,8,8,8,
6871         4,4,4,4,4,4,4,4,4,4,
6872         4,4,4,4,4,4,4,4,4,4,
6873         4,4,4,4,4,4,4,4,4,4,
6874         4,4,4,4,4,4,
6875 };
6876
6877 #define BNX2_NUM_TESTS 6
6878
6879 static struct {
6880         char string[ETH_GSTRING_LEN];
6881 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6882         { "register_test (offline)" },
6883         { "memory_test (offline)" },
6884         { "loopback_test (offline)" },
6885         { "nvram_test (online)" },
6886         { "interrupt_test (online)" },
6887         { "link_test (online)" },
6888 };
6889
6890 static int
6891 bnx2_get_sset_count(struct net_device *dev, int sset)
6892 {
6893         switch (sset) {
6894         case ETH_SS_TEST:
6895                 return BNX2_NUM_TESTS;
6896         case ETH_SS_STATS:
6897                 return BNX2_NUM_STATS;
6898         default:
6899                 return -EOPNOTSUPP;
6900         }
6901 }
6902
6903 static void
6904 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6905 {
6906         struct bnx2 *bp = netdev_priv(dev);
6907
6908         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6909         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6910                 int i;
6911
6912                 bnx2_netif_stop(bp);
6913                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6914                 bnx2_free_skbs(bp);
6915
6916                 if (bnx2_test_registers(bp) != 0) {
6917                         buf[0] = 1;
6918                         etest->flags |= ETH_TEST_FL_FAILED;
6919                 }
6920                 if (bnx2_test_memory(bp) != 0) {
6921                         buf[1] = 1;
6922                         etest->flags |= ETH_TEST_FL_FAILED;
6923                 }
6924                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6925                         etest->flags |= ETH_TEST_FL_FAILED;
6926
6927                 if (!netif_running(bp->dev)) {
6928                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6929                 }
6930                 else {
6931                         bnx2_init_nic(bp, 1);
6932                         bnx2_netif_start(bp);
6933                 }
6934
6935                 /* wait for link up */
6936                 for (i = 0; i < 7; i++) {
6937                         if (bp->link_up)
6938                                 break;
6939                         msleep_interruptible(1000);
6940                 }
6941         }
6942
6943         if (bnx2_test_nvram(bp) != 0) {
6944                 buf[3] = 1;
6945                 etest->flags |= ETH_TEST_FL_FAILED;
6946         }
6947         if (bnx2_test_intr(bp) != 0) {
6948                 buf[4] = 1;
6949                 etest->flags |= ETH_TEST_FL_FAILED;
6950         }
6951
6952         if (bnx2_test_link(bp) != 0) {
6953                 buf[5] = 1;
6954                 etest->flags |= ETH_TEST_FL_FAILED;
6955
6956         }
6957 }
6958
6959 static void
6960 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6961 {
6962         switch (stringset) {
6963         case ETH_SS_STATS:
6964                 memcpy(buf, bnx2_stats_str_arr,
6965                         sizeof(bnx2_stats_str_arr));
6966                 break;
6967         case ETH_SS_TEST:
6968                 memcpy(buf, bnx2_tests_str_arr,
6969                         sizeof(bnx2_tests_str_arr));
6970                 break;
6971         }
6972 }
6973
6974 static void
6975 bnx2_get_ethtool_stats(struct net_device *dev,
6976                 struct ethtool_stats *stats, u64 *buf)
6977 {
6978         struct bnx2 *bp = netdev_priv(dev);
6979         int i;
6980         u32 *hw_stats = (u32 *) bp->stats_blk;
6981         u8 *stats_len_arr = NULL;
6982
6983         if (hw_stats == NULL) {
6984                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6985                 return;
6986         }
6987
6988         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6989             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6990             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6991             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6992                 stats_len_arr = bnx2_5706_stats_len_arr;
6993         else
6994                 stats_len_arr = bnx2_5708_stats_len_arr;
6995
6996         for (i = 0; i < BNX2_NUM_STATS; i++) {
6997                 if (stats_len_arr[i] == 0) {
6998                         /* skip this counter */
6999                         buf[i] = 0;
7000                         continue;
7001                 }
7002                 if (stats_len_arr[i] == 4) {
7003                         /* 4-byte counter */
7004                         buf[i] = (u64)
7005                                 *(hw_stats + bnx2_stats_offset_arr[i]);
7006                         continue;
7007                 }
7008                 /* 8-byte counter */
7009                 buf[i] = (((u64) *(hw_stats +
7010                                         bnx2_stats_offset_arr[i])) << 32) +
7011                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7012         }
7013 }
7014
7015 static int
7016 bnx2_phys_id(struct net_device *dev, u32 data)
7017 {
7018         struct bnx2 *bp = netdev_priv(dev);
7019         int i;
7020         u32 save;
7021
7022         if (data == 0)
7023                 data = 2;
7024
7025         save = REG_RD(bp, BNX2_MISC_CFG);
7026         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7027
7028         for (i = 0; i < (data * 2); i++) {
7029                 if ((i % 2) == 0) {
7030                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7031                 }
7032                 else {
7033                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7034                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7035                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7036                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7037                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7038                                 BNX2_EMAC_LED_TRAFFIC);
7039                 }
7040                 msleep_interruptible(500);
7041                 if (signal_pending(current))
7042                         break;
7043         }
7044         REG_WR(bp, BNX2_EMAC_LED, 0);
7045         REG_WR(bp, BNX2_MISC_CFG, save);
7046         return 0;
7047 }
7048
7049 static int
7050 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7051 {
7052         struct bnx2 *bp = netdev_priv(dev);
7053
7054         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7055                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7056         else
7057                 return (ethtool_op_set_tx_csum(dev, data));
7058 }
7059
7060 static const struct ethtool_ops bnx2_ethtool_ops = {
7061         .get_settings           = bnx2_get_settings,
7062         .set_settings           = bnx2_set_settings,
7063         .get_drvinfo            = bnx2_get_drvinfo,
7064         .get_regs_len           = bnx2_get_regs_len,
7065         .get_regs               = bnx2_get_regs,
7066         .get_wol                = bnx2_get_wol,
7067         .set_wol                = bnx2_set_wol,
7068         .nway_reset             = bnx2_nway_reset,
7069         .get_link               = ethtool_op_get_link,
7070         .get_eeprom_len         = bnx2_get_eeprom_len,
7071         .get_eeprom             = bnx2_get_eeprom,
7072         .set_eeprom             = bnx2_set_eeprom,
7073         .get_coalesce           = bnx2_get_coalesce,
7074         .set_coalesce           = bnx2_set_coalesce,
7075         .get_ringparam          = bnx2_get_ringparam,
7076         .set_ringparam          = bnx2_set_ringparam,
7077         .get_pauseparam         = bnx2_get_pauseparam,
7078         .set_pauseparam         = bnx2_set_pauseparam,
7079         .get_rx_csum            = bnx2_get_rx_csum,
7080         .set_rx_csum            = bnx2_set_rx_csum,
7081         .set_tx_csum            = bnx2_set_tx_csum,
7082         .set_sg                 = ethtool_op_set_sg,
7083         .set_tso                = bnx2_set_tso,
7084         .self_test              = bnx2_self_test,
7085         .get_strings            = bnx2_get_strings,
7086         .phys_id                = bnx2_phys_id,
7087         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7088         .get_sset_count         = bnx2_get_sset_count,
7089 };
7090
7091 /* Called with rtnl_lock */
7092 static int
7093 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7094 {
7095         struct mii_ioctl_data *data = if_mii(ifr);
7096         struct bnx2 *bp = netdev_priv(dev);
7097         int err;
7098
7099         switch(cmd) {
7100         case SIOCGMIIPHY:
7101                 data->phy_id = bp->phy_addr;
7102
7103                 /* fallthru */
7104         case SIOCGMIIREG: {
7105                 u32 mii_regval;
7106
7107                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7108                         return -EOPNOTSUPP;
7109
7110                 if (!netif_running(dev))
7111                         return -EAGAIN;
7112
7113                 spin_lock_bh(&bp->phy_lock);
7114                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7115                 spin_unlock_bh(&bp->phy_lock);
7116
7117                 data->val_out = mii_regval;
7118
7119                 return err;
7120         }
7121
7122         case SIOCSMIIREG:
7123                 if (!capable(CAP_NET_ADMIN))
7124                         return -EPERM;
7125
7126                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7127                         return -EOPNOTSUPP;
7128
7129                 if (!netif_running(dev))
7130                         return -EAGAIN;
7131
7132                 spin_lock_bh(&bp->phy_lock);
7133                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7134                 spin_unlock_bh(&bp->phy_lock);
7135
7136                 return err;
7137
7138         default:
7139                 /* do nothing */
7140                 break;
7141         }
7142         return -EOPNOTSUPP;
7143 }
7144
7145 /* Called with rtnl_lock */
7146 static int
7147 bnx2_change_mac_addr(struct net_device *dev, void *p)
7148 {
7149         struct sockaddr *addr = p;
7150         struct bnx2 *bp = netdev_priv(dev);
7151
7152         if (!is_valid_ether_addr(addr->sa_data))
7153                 return -EINVAL;
7154
7155         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7156         if (netif_running(dev))
7157                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7158
7159         return 0;
7160 }
7161
7162 /* Called with rtnl_lock */
7163 static int
7164 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7165 {
7166         struct bnx2 *bp = netdev_priv(dev);
7167
7168         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7169                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7170                 return -EINVAL;
7171
7172         dev->mtu = new_mtu;
7173         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7174 }
7175
7176 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7177 static void
7178 poll_bnx2(struct net_device *dev)
7179 {
7180         struct bnx2 *bp = netdev_priv(dev);
7181
7182         disable_irq(bp->pdev->irq);
7183         bnx2_interrupt(bp->pdev->irq, dev);
7184         enable_irq(bp->pdev->irq);
7185 }
7186 #endif
7187
7188 static void __devinit
7189 bnx2_get_5709_media(struct bnx2 *bp)
7190 {
7191         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7192         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7193         u32 strap;
7194
7195         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7196                 return;
7197         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7198                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7199                 return;
7200         }
7201
7202         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7203                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7204         else
7205                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7206
7207         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7208                 switch (strap) {
7209                 case 0x4:
7210                 case 0x5:
7211                 case 0x6:
7212                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7213                         return;
7214                 }
7215         } else {
7216                 switch (strap) {
7217                 case 0x1:
7218                 case 0x2:
7219                 case 0x4:
7220                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7221                         return;
7222                 }
7223         }
7224 }
7225
7226 static void __devinit
7227 bnx2_get_pci_speed(struct bnx2 *bp)
7228 {
7229         u32 reg;
7230
7231         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7232         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7233                 u32 clkreg;
7234
7235                 bp->flags |= BNX2_FLAG_PCIX;
7236
7237                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7238
7239                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7240                 switch (clkreg) {
7241                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7242                         bp->bus_speed_mhz = 133;
7243                         break;
7244
7245                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7246                         bp->bus_speed_mhz = 100;
7247                         break;
7248
7249                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7250                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7251                         bp->bus_speed_mhz = 66;
7252                         break;
7253
7254                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7255                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7256                         bp->bus_speed_mhz = 50;
7257                         break;
7258
7259                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7260                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7261                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7262                         bp->bus_speed_mhz = 33;
7263                         break;
7264                 }
7265         }
7266         else {
7267                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7268                         bp->bus_speed_mhz = 66;
7269                 else
7270                         bp->bus_speed_mhz = 33;
7271         }
7272
7273         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7274                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7275
7276 }
7277
7278 static int __devinit
7279 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7280 {
7281         struct bnx2 *bp;
7282         unsigned long mem_len;
7283         int rc, i, j;
7284         u32 reg;
7285         u64 dma_mask, persist_dma_mask;
7286
7287         SET_NETDEV_DEV(dev, &pdev->dev);
7288         bp = netdev_priv(dev);
7289
7290         bp->flags = 0;
7291         bp->phy_flags = 0;
7292
7293         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7294         rc = pci_enable_device(pdev);
7295         if (rc) {
7296                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7297                 goto err_out;
7298         }
7299
7300         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7301                 dev_err(&pdev->dev,
7302                         "Cannot find PCI device base address, aborting.\n");
7303                 rc = -ENODEV;
7304                 goto err_out_disable;
7305         }
7306
7307         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7308         if (rc) {
7309                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7310                 goto err_out_disable;
7311         }
7312
7313         pci_set_master(pdev);
7314         pci_save_state(pdev);
7315
7316         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7317         if (bp->pm_cap == 0) {
7318                 dev_err(&pdev->dev,
7319                         "Cannot find power management capability, aborting.\n");
7320                 rc = -EIO;
7321                 goto err_out_release;
7322         }
7323
7324         bp->dev = dev;
7325         bp->pdev = pdev;
7326
7327         spin_lock_init(&bp->phy_lock);
7328         spin_lock_init(&bp->indirect_lock);
7329         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7330
7331         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7332         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7333         dev->mem_end = dev->mem_start + mem_len;
7334         dev->irq = pdev->irq;
7335
7336         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7337
7338         if (!bp->regview) {
7339                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7340                 rc = -ENOMEM;
7341                 goto err_out_release;
7342         }
7343
7344         /* Configure byte swap and enable write to the reg_window registers.
7345          * Rely on CPU to do target byte swapping on big endian systems
7346          * The chip's target access swapping will not swap all accesses
7347          */
7348         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7349                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7350                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7351
7352         bnx2_set_power_state(bp, PCI_D0);
7353
7354         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7355
7356         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7357                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7358                         dev_err(&pdev->dev,
7359                                 "Cannot find PCIE capability, aborting.\n");
7360                         rc = -EIO;
7361                         goto err_out_unmap;
7362                 }
7363                 bp->flags |= BNX2_FLAG_PCIE;
7364                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7365                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7366         } else {
7367                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7368                 if (bp->pcix_cap == 0) {
7369                         dev_err(&pdev->dev,
7370                                 "Cannot find PCIX capability, aborting.\n");
7371                         rc = -EIO;
7372                         goto err_out_unmap;
7373                 }
7374         }
7375
7376         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7377                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7378                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7379         }
7380
7381         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7382                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7383                         bp->flags |= BNX2_FLAG_MSI_CAP;
7384         }
7385
7386         /* 5708 cannot support DMA addresses > 40-bit.  */
7387         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7388                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7389         else
7390                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7391
7392         /* Configure DMA attributes. */
7393         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7394                 dev->features |= NETIF_F_HIGHDMA;
7395                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7396                 if (rc) {
7397                         dev_err(&pdev->dev,
7398                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7399                         goto err_out_unmap;
7400                 }
7401         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7402                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7403                 goto err_out_unmap;
7404         }
7405
7406         if (!(bp->flags & BNX2_FLAG_PCIE))
7407                 bnx2_get_pci_speed(bp);
7408
7409         /* 5706A0 may falsely detect SERR and PERR. */
7410         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7411                 reg = REG_RD(bp, PCI_COMMAND);
7412                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7413                 REG_WR(bp, PCI_COMMAND, reg);
7414         }
7415         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7416                 !(bp->flags & BNX2_FLAG_PCIX)) {
7417
7418                 dev_err(&pdev->dev,
7419                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7420                 goto err_out_unmap;
7421         }
7422
7423         bnx2_init_nvram(bp);
7424
7425         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7426
7427         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7428             BNX2_SHM_HDR_SIGNATURE_SIG) {
7429                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7430
7431                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7432         } else
7433                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7434
7435         /* Get the permanent MAC address.  First we need to make sure the
7436          * firmware is actually running.
7437          */
7438         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7439
7440         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7441             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7442                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7443                 rc = -ENODEV;
7444                 goto err_out_unmap;
7445         }
7446
7447         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7448         for (i = 0, j = 0; i < 3; i++) {
7449                 u8 num, k, skip0;
7450
7451                 num = (u8) (reg >> (24 - (i * 8)));
7452                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7453                         if (num >= k || !skip0 || k == 1) {
7454                                 bp->fw_version[j++] = (num / k) + '0';
7455                                 skip0 = 0;
7456                         }
7457                 }
7458                 if (i != 2)
7459                         bp->fw_version[j++] = '.';
7460         }
7461         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7462         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7463                 bp->wol = 1;
7464
7465         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7466                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7467
7468                 for (i = 0; i < 30; i++) {
7469                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7470                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7471                                 break;
7472                         msleep(10);
7473                 }
7474         }
7475         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7476         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7477         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7478             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7479                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7480
7481                 bp->fw_version[j++] = ' ';
7482                 for (i = 0; i < 3; i++) {
7483                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7484                         reg = swab32(reg);
7485                         memcpy(&bp->fw_version[j], &reg, 4);
7486                         j += 4;
7487                 }
7488         }
7489
7490         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7491         bp->mac_addr[0] = (u8) (reg >> 8);
7492         bp->mac_addr[1] = (u8) reg;
7493
7494         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7495         bp->mac_addr[2] = (u8) (reg >> 24);
7496         bp->mac_addr[3] = (u8) (reg >> 16);
7497         bp->mac_addr[4] = (u8) (reg >> 8);
7498         bp->mac_addr[5] = (u8) reg;
7499
7500         bp->tx_ring_size = MAX_TX_DESC_CNT;
7501         bnx2_set_rx_ring_size(bp, 255);
7502
7503         bp->rx_csum = 1;
7504
7505         bp->tx_quick_cons_trip_int = 20;
7506         bp->tx_quick_cons_trip = 20;
7507         bp->tx_ticks_int = 80;
7508         bp->tx_ticks = 80;
7509
7510         bp->rx_quick_cons_trip_int = 6;
7511         bp->rx_quick_cons_trip = 6;
7512         bp->rx_ticks_int = 18;
7513         bp->rx_ticks = 18;
7514
7515         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7516
7517         bp->current_interval = BNX2_TIMER_INTERVAL;
7518
7519         bp->phy_addr = 1;
7520
7521         /* Disable WOL support if we are running on a SERDES chip. */
7522         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7523                 bnx2_get_5709_media(bp);
7524         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7525                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7526
7527         bp->phy_port = PORT_TP;
7528         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7529                 bp->phy_port = PORT_FIBRE;
7530                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7531                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7532                         bp->flags |= BNX2_FLAG_NO_WOL;
7533                         bp->wol = 0;
7534                 }
7535                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7536                         /* Don't do parallel detect on this board because of
7537                          * some board problems.  The link will not go down
7538                          * if we do parallel detect.
7539                          */
7540                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7541                             pdev->subsystem_device == 0x310c)
7542                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7543                 } else {
7544                         bp->phy_addr = 2;
7545                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7546                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7547                 }
7548         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7549                    CHIP_NUM(bp) == CHIP_NUM_5708)
7550                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7551         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7552                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7553                   CHIP_REV(bp) == CHIP_REV_Bx))
7554                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7555
7556         bnx2_init_fw_cap(bp);
7557
7558         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7559             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7560             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7561                 bp->flags |= BNX2_FLAG_NO_WOL;
7562                 bp->wol = 0;
7563         }
7564
7565         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7566                 bp->tx_quick_cons_trip_int =
7567                         bp->tx_quick_cons_trip;
7568                 bp->tx_ticks_int = bp->tx_ticks;
7569                 bp->rx_quick_cons_trip_int =
7570                         bp->rx_quick_cons_trip;
7571                 bp->rx_ticks_int = bp->rx_ticks;
7572                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7573                 bp->com_ticks_int = bp->com_ticks;
7574                 bp->cmd_ticks_int = bp->cmd_ticks;
7575         }
7576
7577         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7578          *
7579          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7580          * with byte enables disabled on the unused 32-bit word.  This is legal
7581          * but causes problems on the AMD 8132 which will eventually stop
7582          * responding after a while.
7583          *
7584          * AMD believes this incompatibility is unique to the 5706, and
7585          * prefers to locally disable MSI rather than globally disabling it.
7586          */
7587         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7588                 struct pci_dev *amd_8132 = NULL;
7589
7590                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7591                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7592                                                   amd_8132))) {
7593
7594                         if (amd_8132->revision >= 0x10 &&
7595                             amd_8132->revision <= 0x13) {
7596                                 disable_msi = 1;
7597                                 pci_dev_put(amd_8132);
7598                                 break;
7599                         }
7600                 }
7601         }
7602
7603         bnx2_set_default_link(bp);
7604         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7605
7606         init_timer(&bp->timer);
7607         bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7608         bp->timer.data = (unsigned long) bp;
7609         bp->timer.function = bnx2_timer;
7610
7611         return 0;
7612
7613 err_out_unmap:
7614         if (bp->regview) {
7615                 iounmap(bp->regview);
7616                 bp->regview = NULL;
7617         }
7618
7619 err_out_release:
7620         pci_release_regions(pdev);
7621
7622 err_out_disable:
7623         pci_disable_device(pdev);
7624         pci_set_drvdata(pdev, NULL);
7625
7626 err_out:
7627         return rc;
7628 }
7629
7630 static char * __devinit
7631 bnx2_bus_string(struct bnx2 *bp, char *str)
7632 {
7633         char *s = str;
7634
7635         if (bp->flags & BNX2_FLAG_PCIE) {
7636                 s += sprintf(s, "PCI Express");
7637         } else {
7638                 s += sprintf(s, "PCI");
7639                 if (bp->flags & BNX2_FLAG_PCIX)
7640                         s += sprintf(s, "-X");
7641                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7642                         s += sprintf(s, " 32-bit");
7643                 else
7644                         s += sprintf(s, " 64-bit");
7645                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7646         }
7647         return str;
7648 }
7649
7650 static void __devinit
7651 bnx2_init_napi(struct bnx2 *bp)
7652 {
7653         int i;
7654
7655         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7656                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7657                 int (*poll)(struct napi_struct *, int);
7658
7659                 if (i == 0)
7660                         poll = bnx2_poll;
7661                 else
7662                         poll = bnx2_poll_msix;
7663
7664                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7665                 bnapi->bp = bp;
7666         }
7667 }
7668
7669 static int __devinit
7670 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7671 {
7672         static int version_printed = 0;
7673         struct net_device *dev = NULL;
7674         struct bnx2 *bp;
7675         int rc;
7676         char str[40];
7677         DECLARE_MAC_BUF(mac);
7678
7679         if (version_printed++ == 0)
7680                 printk(KERN_INFO "%s", version);
7681
7682         /* dev zeroed in init_etherdev */
7683         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7684
7685         if (!dev)
7686                 return -ENOMEM;
7687
7688         rc = bnx2_init_board(pdev, dev);
7689         if (rc < 0) {
7690                 free_netdev(dev);
7691                 return rc;
7692         }
7693
7694         dev->open = bnx2_open;
7695         dev->hard_start_xmit = bnx2_start_xmit;
7696         dev->stop = bnx2_close;
7697         dev->get_stats = bnx2_get_stats;
7698         dev->set_rx_mode = bnx2_set_rx_mode;
7699         dev->do_ioctl = bnx2_ioctl;
7700         dev->set_mac_address = bnx2_change_mac_addr;
7701         dev->change_mtu = bnx2_change_mtu;
7702         dev->tx_timeout = bnx2_tx_timeout;
7703         dev->watchdog_timeo = TX_TIMEOUT;
7704 #ifdef BCM_VLAN
7705         dev->vlan_rx_register = bnx2_vlan_rx_register;
7706 #endif
7707         dev->ethtool_ops = &bnx2_ethtool_ops;
7708
7709         bp = netdev_priv(dev);
7710         bnx2_init_napi(bp);
7711
7712 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7713         dev->poll_controller = poll_bnx2;
7714 #endif
7715
7716         pci_set_drvdata(pdev, dev);
7717
7718         memcpy(dev->dev_addr, bp->mac_addr, 6);
7719         memcpy(dev->perm_addr, bp->mac_addr, 6);
7720
7721         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7722         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7723                 dev->features |= NETIF_F_IPV6_CSUM;
7724
7725 #ifdef BCM_VLAN
7726         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7727 #endif
7728         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7729         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7730                 dev->features |= NETIF_F_TSO6;
7731
7732         if ((rc = register_netdev(dev))) {
7733                 dev_err(&pdev->dev, "Cannot register net device\n");
7734                 if (bp->regview)
7735                         iounmap(bp->regview);
7736                 pci_release_regions(pdev);
7737                 pci_disable_device(pdev);
7738                 pci_set_drvdata(pdev, NULL);
7739                 free_netdev(dev);
7740                 return rc;
7741         }
7742
7743         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7744                 "IRQ %d, node addr %s\n",
7745                 dev->name,
7746                 board_info[ent->driver_data].name,
7747                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7748                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7749                 bnx2_bus_string(bp, str),
7750                 dev->base_addr,
7751                 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7752
7753         return 0;
7754 }
7755
7756 static void __devexit
7757 bnx2_remove_one(struct pci_dev *pdev)
7758 {
7759         struct net_device *dev = pci_get_drvdata(pdev);
7760         struct bnx2 *bp = netdev_priv(dev);
7761
7762         flush_scheduled_work();
7763
7764         unregister_netdev(dev);
7765
7766         if (bp->regview)
7767                 iounmap(bp->regview);
7768
7769         free_netdev(dev);
7770         pci_release_regions(pdev);
7771         pci_disable_device(pdev);
7772         pci_set_drvdata(pdev, NULL);
7773 }
7774
7775 static int
7776 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7777 {
7778         struct net_device *dev = pci_get_drvdata(pdev);
7779         struct bnx2 *bp = netdev_priv(dev);
7780         u32 reset_code;
7781
7782         /* PCI register 4 needs to be saved whether netif_running() or not.
7783          * MSI address and data need to be saved if using MSI and
7784          * netif_running().
7785          */
7786         pci_save_state(pdev);
7787         if (!netif_running(dev))
7788                 return 0;
7789
7790         flush_scheduled_work();
7791         bnx2_netif_stop(bp);
7792         netif_device_detach(dev);
7793         del_timer_sync(&bp->timer);
7794         if (bp->flags & BNX2_FLAG_NO_WOL)
7795                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7796         else if (bp->wol)
7797                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7798         else
7799                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7800         bnx2_reset_chip(bp, reset_code);
7801         bnx2_free_skbs(bp);
7802         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7803         return 0;
7804 }
7805
7806 static int
7807 bnx2_resume(struct pci_dev *pdev)
7808 {
7809         struct net_device *dev = pci_get_drvdata(pdev);
7810         struct bnx2 *bp = netdev_priv(dev);
7811
7812         pci_restore_state(pdev);
7813         if (!netif_running(dev))
7814                 return 0;
7815
7816         bnx2_set_power_state(bp, PCI_D0);
7817         netif_device_attach(dev);
7818         bnx2_init_nic(bp, 1);
7819         bnx2_netif_start(bp);
7820         return 0;
7821 }
7822
7823 /**
7824  * bnx2_io_error_detected - called when PCI error is detected
7825  * @pdev: Pointer to PCI device
7826  * @state: The current pci connection state
7827  *
7828  * This function is called after a PCI bus error affecting
7829  * this device has been detected.
7830  */
7831 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7832                                                pci_channel_state_t state)
7833 {
7834         struct net_device *dev = pci_get_drvdata(pdev);
7835         struct bnx2 *bp = netdev_priv(dev);
7836
7837         rtnl_lock();
7838         netif_device_detach(dev);
7839
7840         if (netif_running(dev)) {
7841                 bnx2_netif_stop(bp);
7842                 del_timer_sync(&bp->timer);
7843                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7844         }
7845
7846         pci_disable_device(pdev);
7847         rtnl_unlock();
7848
7849         /* Request a slot slot reset. */
7850         return PCI_ERS_RESULT_NEED_RESET;
7851 }
7852
7853 /**
7854  * bnx2_io_slot_reset - called after the pci bus has been reset.
7855  * @pdev: Pointer to PCI device
7856  *
7857  * Restart the card from scratch, as if from a cold-boot.
7858  */
7859 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7860 {
7861         struct net_device *dev = pci_get_drvdata(pdev);
7862         struct bnx2 *bp = netdev_priv(dev);
7863
7864         rtnl_lock();
7865         if (pci_enable_device(pdev)) {
7866                 dev_err(&pdev->dev,
7867                         "Cannot re-enable PCI device after reset.\n");
7868                 rtnl_unlock();
7869                 return PCI_ERS_RESULT_DISCONNECT;
7870         }
7871         pci_set_master(pdev);
7872         pci_restore_state(pdev);
7873
7874         if (netif_running(dev)) {
7875                 bnx2_set_power_state(bp, PCI_D0);
7876                 bnx2_init_nic(bp, 1);
7877         }
7878
7879         rtnl_unlock();
7880         return PCI_ERS_RESULT_RECOVERED;
7881 }
7882
7883 /**
7884  * bnx2_io_resume - called when traffic can start flowing again.
7885  * @pdev: Pointer to PCI device
7886  *
7887  * This callback is called when the error recovery driver tells us that
7888  * its OK to resume normal operation.
7889  */
7890 static void bnx2_io_resume(struct pci_dev *pdev)
7891 {
7892         struct net_device *dev = pci_get_drvdata(pdev);
7893         struct bnx2 *bp = netdev_priv(dev);
7894
7895         rtnl_lock();
7896         if (netif_running(dev))
7897                 bnx2_netif_start(bp);
7898
7899         netif_device_attach(dev);
7900         rtnl_unlock();
7901 }
7902
7903 static struct pci_error_handlers bnx2_err_handler = {
7904         .error_detected = bnx2_io_error_detected,
7905         .slot_reset     = bnx2_io_slot_reset,
7906         .resume         = bnx2_io_resume,
7907 };
7908
7909 static struct pci_driver bnx2_pci_driver = {
7910         .name           = DRV_MODULE_NAME,
7911         .id_table       = bnx2_pci_tbl,
7912         .probe          = bnx2_init_one,
7913         .remove         = __devexit_p(bnx2_remove_one),
7914         .suspend        = bnx2_suspend,
7915         .resume         = bnx2_resume,
7916         .err_handler    = &bnx2_err_handler,
7917 };
7918
7919 static int __init bnx2_init(void)
7920 {
7921         return pci_register_driver(&bnx2_pci_driver);
7922 }
7923
7924 static void __exit bnx2_cleanup(void)
7925 {
7926         pci_unregister_driver(&bnx2_pci_driver);
7927 }
7928
7929 module_init(bnx2_init);
7930 module_exit(bnx2_cleanup);
7931
7932
7933