git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63
  64
  65 /******************\
  66 * Internal defines *
  67 \******************/
  68
  69 /* Module info */
  70 MODULE_AUTHOR("Jiri Slaby");
  71 MODULE_AUTHOR("Nick Kossifidis");
  72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  74 MODULE_LICENSE("Dual BSD/GPL");
  75 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
  76
  77
  78 /* Known PCI ids */
  79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  80         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  81         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  82         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  83         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  84         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  85         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  86         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  87         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  88         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  89         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  90         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  91         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  95         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  96         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
  97         { 0 }
  98 };
  99 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 100
 101 /* Known SREVs */
 102 static struct ath5k_srev_name srev_names[] = {
 103         { "5210",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5210 },
 104         { "5311",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5311 },
 105         { "5311A",      AR5K_VERSION_VER,       AR5K_SREV_VER_AR5311A },
 106         { "5311B",      AR5K_VERSION_VER,       AR5K_SREV_VER_AR5311B },
 107         { "5211",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5211 },
 108         { "5212",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5212 },
 109         { "5213",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5213 },
 110         { "5213A",      AR5K_VERSION_VER,       AR5K_SREV_VER_AR5213A },
 111         { "2413",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR2413 },
 112         { "2414",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR2414 },
 113         { "2424",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR2424 },
 114         { "5424",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5424 },
 115         { "5413",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5413 },
 116         { "5414",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5414 },
 117         { "5416",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5416 },
 118         { "5418",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR5418 },
 119         { "2425",       AR5K_VERSION_VER,       AR5K_SREV_VER_AR2425 },
 120         { "xxxxx",      AR5K_VERSION_VER,       AR5K_SREV_UNKNOWN },
 121         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 122         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 123         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 124         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 125         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 126         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 127         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 128         { "SChip",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_SC0 },
 129         { "SChip",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_SC1 },
 130         { "SChip",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_SC2 },
 131         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 132         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 133 };
 134
 135 static struct ieee80211_rate ath5k_rates[] = {
 136         { .bitrate = 10,
 137           .hw_value = ATH5K_RATE_CODE_1M, },
 138         { .bitrate = 20,
 139           .hw_value = ATH5K_RATE_CODE_2M,
 140           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 141           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 142         { .bitrate = 55,
 143           .hw_value = ATH5K_RATE_CODE_5_5M,
 144           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 145           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 146         { .bitrate = 110,
 147           .hw_value = ATH5K_RATE_CODE_11M,
 148           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 149           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 150         { .bitrate = 60,
 151           .hw_value = ATH5K_RATE_CODE_6M,
 152           .flags = 0 },
 153         { .bitrate = 90,
 154           .hw_value = ATH5K_RATE_CODE_9M,
 155           .flags = 0 },
 156         { .bitrate = 120,
 157           .hw_value = ATH5K_RATE_CODE_12M,
 158           .flags = 0 },
 159         { .bitrate = 180,
 160           .hw_value = ATH5K_RATE_CODE_18M,
 161           .flags = 0 },
 162         { .bitrate = 240,
 163           .hw_value = ATH5K_RATE_CODE_24M,
 164           .flags = 0 },
 165         { .bitrate = 360,
 166           .hw_value = ATH5K_RATE_CODE_36M,
 167           .flags = 0 },
 168         { .bitrate = 480,
 169           .hw_value = ATH5K_RATE_CODE_48M,
 170           .flags = 0 },
 171         { .bitrate = 540,
 172           .hw_value = ATH5K_RATE_CODE_54M,
 173           .flags = 0 },
 174         /* XR missing */
 175 };
 176
 177 /*
 178  * Prototypes - PCI stack related functions
 179  */
 180 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 181                                 const struct pci_device_id *id);
 182 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 183 #ifdef CONFIG_PM
 184 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 185                                         pm_message_t state);
 186 static int              ath5k_pci_resume(struct pci_dev *pdev);
 187 #else
 188 #define ath5k_pci_suspend NULL
 189 #define ath5k_pci_resume NULL
 190 #endif /* CONFIG_PM */
 191
 192 static struct pci_driver ath5k_pci_driver = {
 193         .name           = "ath5k_pci",
 194         .id_table       = ath5k_pci_id_table,
 195         .probe          = ath5k_pci_probe,
 196         .remove         = __devexit_p(ath5k_pci_remove),
 197         .suspend        = ath5k_pci_suspend,
 198         .resume         = ath5k_pci_resume,
 199 };
 200
 201
 202
 203 /*
 204  * Prototypes - MAC 802.11 stack related functions
 205  */
 206 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 207 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 208 static int ath5k_reset_wake(struct ath5k_softc *sc);
 209 static int ath5k_start(struct ieee80211_hw *hw);
 210 static void ath5k_stop(struct ieee80211_hw *hw);
 211 static int ath5k_add_interface(struct ieee80211_hw *hw,
 212                 struct ieee80211_if_init_conf *conf);
 213 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 214                 struct ieee80211_if_init_conf *conf);
 215 static int ath5k_config(struct ieee80211_hw *hw,
 216                 struct ieee80211_conf *conf);
 217 static int ath5k_config_interface(struct ieee80211_hw *hw,
 218                 struct ieee80211_vif *vif,
 219                 struct ieee80211_if_conf *conf);
 220 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 221                 unsigned int changed_flags,
 222                 unsigned int *new_flags,
 223                 int mc_count, struct dev_mc_list *mclist);
 224 static int ath5k_set_key(struct ieee80211_hw *hw,
 225                 enum set_key_cmd cmd,
 226                 const u8 *local_addr, const u8 *addr,
 227                 struct ieee80211_key_conf *key);
 228 static int ath5k_get_stats(struct ieee80211_hw *hw,
 229                 struct ieee80211_low_level_stats *stats);
 230 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 231                 struct ieee80211_tx_queue_stats *stats);
 232 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 233 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 234 static int ath5k_beacon_update(struct ieee80211_hw *hw,
 235                 struct sk_buff *skb);
 236
 237 static struct ieee80211_ops ath5k_hw_ops = {
 238         .tx             = ath5k_tx,
 239         .start          = ath5k_start,
 240         .stop           = ath5k_stop,
 241         .add_interface  = ath5k_add_interface,
 242         .remove_interface = ath5k_remove_interface,
 243         .config         = ath5k_config,
 244         .config_interface = ath5k_config_interface,
 245         .configure_filter = ath5k_configure_filter,
 246         .set_key        = ath5k_set_key,
 247         .get_stats      = ath5k_get_stats,
 248         .conf_tx        = NULL,
 249         .get_tx_stats   = ath5k_get_tx_stats,
 250         .get_tsf        = ath5k_get_tsf,
 251         .reset_tsf      = ath5k_reset_tsf,
 252 };
 253
 254 /*
 255  * Prototypes - Internal functions
 256  */
 257 /* Attach detach */
 258 static int      ath5k_attach(struct pci_dev *pdev,
 259                         struct ieee80211_hw *hw);
 260 static void     ath5k_detach(struct pci_dev *pdev,
 261                         struct ieee80211_hw *hw);
 262 /* Channel/mode setup */
 263 static inline short ath5k_ieee2mhz(short chan);
 264 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 265                                 struct ieee80211_channel *channels,
 266                                 unsigned int mode,
 267                                 unsigned int max);
 268 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 269 static int      ath5k_chan_set(struct ath5k_softc *sc,
 270                                 struct ieee80211_channel *chan);
 271 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 272                                 unsigned int mode);
 273 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 274
 275 /* Descriptor setup */
 276 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 277                                 struct pci_dev *pdev);
 278 static void     ath5k_desc_free(struct ath5k_softc *sc,
 279                                 struct pci_dev *pdev);
 280 /* Buffers setup */
 281 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 282                                 struct ath5k_buf *bf);
 283 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 284                                 struct ath5k_buf *bf);
 285 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 286                                 struct ath5k_buf *bf)
 287 {
 288         BUG_ON(!bf);
 289         if (!bf->skb)
 290                 return;
 291         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 292                         PCI_DMA_TODEVICE);
 293         dev_kfree_skb_any(bf->skb);
 294         bf->skb = NULL;
 295 }
 296
 297 /* Queues setup */
 298 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 299                                 int qtype, int subtype);
 300 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 301 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 302 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 303                                 struct ath5k_txq *txq);
 304 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 305 static void     ath5k_txq_release(struct ath5k_softc *sc);
 306 /* Rx handling */
 307 static int      ath5k_rx_start(struct ath5k_softc *sc);
 308 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 309 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 310                                         struct ath5k_desc *ds,
 311                                         struct sk_buff *skb,
 312                                         struct ath5k_rx_status *rs);
 313 static void     ath5k_tasklet_rx(unsigned long data);
 314 /* Tx handling */
 315 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 316                                 struct ath5k_txq *txq);
 317 static void     ath5k_tasklet_tx(unsigned long data);
 318 /* Beacon handling */
 319 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 320                                         struct ath5k_buf *bf);
 321 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 322 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 323 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 324
 325 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 326 {
 327         u64 tsf = ath5k_hw_get_tsf64(ah);
 328
 329         if ((tsf & 0x7fff) < rstamp)
 330                 tsf -= 0x8000;
 331
 332         return (tsf & ~0x7fff) | rstamp;
 333 }
 334
 335 /* Interrupt handling */
 336 static int      ath5k_init(struct ath5k_softc *sc);
 337 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 338 static int      ath5k_stop_hw(struct ath5k_softc *sc);
 339 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 340 static void     ath5k_tasklet_reset(unsigned long data);
 341
 342 static void     ath5k_calibrate(unsigned long data);
 343 /* LED functions */
 344 static int      ath5k_init_leds(struct ath5k_softc *sc);
 345 static void     ath5k_led_enable(struct ath5k_softc *sc);
 346 static void     ath5k_led_off(struct ath5k_softc *sc);
 347 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 348
 349 /*
 350  * Module init/exit functions
 351  */
 352 static int __init
 353 init_ath5k_pci(void)
 354 {
 355         int ret;
 356
 357         ath5k_debug_init();
 358
 359         ret = pci_register_driver(&ath5k_pci_driver);
 360         if (ret) {
 361                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 362                 return ret;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static void __exit
 369 exit_ath5k_pci(void)
 370 {
 371         pci_unregister_driver(&ath5k_pci_driver);
 372
 373         ath5k_debug_finish();
 374 }
 375
 376 module_init(init_ath5k_pci);
 377 module_exit(exit_ath5k_pci);
 378
 379
 380 /********************\
 381 * PCI Initialization *
 382 \********************/
 383
 384 static const char *
 385 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 386 {
 387         const char *name = "xxxxx";
 388         unsigned int i;
 389
 390         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 391                 if (srev_names[i].sr_type != type)
 392                         continue;
 393                 if ((val & 0xff) < srev_names[i + 1].sr_val) {
 394                         name = srev_names[i].sr_name;
 395                         break;
 396                 }
 397         }
 398
 399         return name;
 400 }
 401
 402 static int __devinit
 403 ath5k_pci_probe(struct pci_dev *pdev,
 404                 const struct pci_device_id *id)
 405 {
 406         void __iomem *mem;
 407         struct ath5k_softc *sc;
 408         struct ieee80211_hw *hw;
 409         int ret;
 410         u8 csz;
 411
 412         ret = pci_enable_device(pdev);
 413         if (ret) {
 414                 dev_err(&pdev->dev, "can't enable device\n");
 415                 goto err;
 416         }
 417
 418         /* XXX 32-bit addressing only */
 419         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 420         if (ret) {
 421                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 422                 goto err_dis;
 423         }
 424
 425         /*
 426          * Cache line size is used to size and align various
 427          * structures used to communicate with the hardware.
 428          */
 429         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 430         if (csz == 0) {
 431                 /*
 432                  * Linux 2.4.18 (at least) writes the cache line size
 433                  * register as a 16-bit wide register which is wrong.
 434                  * We must have this setup properly for rx buffer
 435                  * DMA to work so force a reasonable value here if it
 436                  * comes up zero.
 437                  */
 438                 csz = L1_CACHE_BYTES / sizeof(u32);
 439                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 440         }
 441         /*
 442          * The default setting of latency timer yields poor results,
 443          * set it to the value used by other systems.  It may be worth
 444          * tweaking this setting more.
 445          */
 446         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 447
 448         /* Enable bus mastering */
 449         pci_set_master(pdev);
 450
 451         /*
 452          * Disable the RETRY_TIMEOUT register (0x41) to keep
 453          * PCI Tx retries from interfering with C3 CPU state.
 454          */
 455         pci_write_config_byte(pdev, 0x41, 0);
 456
 457         ret = pci_request_region(pdev, 0, "ath5k");
 458         if (ret) {
 459                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 460                 goto err_dis;
 461         }
 462
 463         mem = pci_iomap(pdev, 0, 0);
 464         if (!mem) {
 465                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 466                 ret = -EIO;
 467                 goto err_reg;
 468         }
 469
 470         /*
 471          * Allocate hw (mac80211 main struct)
 472          * and hw->priv (driver private data)
 473          */
 474         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 475         if (hw == NULL) {
 476                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 477                 ret = -ENOMEM;
 478                 goto err_map;
 479         }
 480
 481         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 482
 483         /* Initialize driver private data */
 484         SET_IEEE80211_DEV(hw, &pdev->dev);
 485         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 486                     IEEE80211_HW_SIGNAL_DBM |
 487                     IEEE80211_HW_NOISE_DBM;
 488
 489         hw->wiphy->interface_modes =
 490                 BIT(NL80211_IFTYPE_STATION) |
 491                 BIT(NL80211_IFTYPE_ADHOC) |
 492                 BIT(NL80211_IFTYPE_MESH_POINT);
 493
 494         hw->extra_tx_headroom = 2;
 495         hw->channel_change_time = 5000;
 496         sc = hw->priv;
 497         sc->hw = hw;
 498         sc->pdev = pdev;
 499
 500         ath5k_debug_init_device(sc);
 501
 502         /*
 503          * Mark the device as detached to avoid processing
 504          * interrupts until setup is complete.
 505          */
 506         __set_bit(ATH_STAT_INVALID, sc->status);
 507
 508         sc->iobase = mem; /* So we can unmap it on detach */
 509         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 510         sc->opmode = NL80211_IFTYPE_STATION;
 511         mutex_init(&sc->lock);
 512         spin_lock_init(&sc->rxbuflock);
 513         spin_lock_init(&sc->txbuflock);
 514         spin_lock_init(&sc->block);
 515
 516         /* Set private data */
 517         pci_set_drvdata(pdev, hw);
 518
 519         /* Setup interrupt handler */
 520         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 521         if (ret) {
 522                 ATH5K_ERR(sc, "request_irq failed\n");
 523                 goto err_free;
 524         }
 525
 526         /* Initialize device */
 527         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 528         if (IS_ERR(sc->ah)) {
 529                 ret = PTR_ERR(sc->ah);
 530                 goto err_irq;
 531         }
 532
 533         /* Finish private driver data initialization */
 534         ret = ath5k_attach(pdev, hw);
 535         if (ret)
 536                 goto err_ah;
 537
 538         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 539                         ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
 540                                         sc->ah->ah_mac_srev,
 541                                         sc->ah->ah_phy_revision);
 542
 543         if (!sc->ah->ah_single_chip) {
 544                 /* Single chip radio (!RF5111) */
 545                 if (sc->ah->ah_radio_5ghz_revision &&
 546                         !sc->ah->ah_radio_2ghz_revision) {
 547                         /* No 5GHz support -> report 2GHz radio */
 548                         if (!test_bit(AR5K_MODE_11A,
 549                                 sc->ah->ah_capabilities.cap_mode)) {
 550                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 551                                         ath5k_chip_name(AR5K_VERSION_RAD,
 552                                                 sc->ah->ah_radio_5ghz_revision),
 553                                                 sc->ah->ah_radio_5ghz_revision);
 554                         /* No 2GHz support (5110 and some
 555                          * 5Ghz only cards) -> report 5Ghz radio */
 556                         } else if (!test_bit(AR5K_MODE_11B,
 557                                 sc->ah->ah_capabilities.cap_mode)) {
 558                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 559                                         ath5k_chip_name(AR5K_VERSION_RAD,
 560                                                 sc->ah->ah_radio_5ghz_revision),
 561                                                 sc->ah->ah_radio_5ghz_revision);
 562                         /* Multiband radio */
 563                         } else {
 564                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 565                                         " (0x%x)\n",
 566                                         ath5k_chip_name(AR5K_VERSION_RAD,
 567                                                 sc->ah->ah_radio_5ghz_revision),
 568                                                 sc->ah->ah_radio_5ghz_revision);
 569                         }
 570                 }
 571                 /* Multi chip radio (RF5111 - RF2111) ->
 572                  * report both 2GHz/5GHz radios */
 573                 else if (sc->ah->ah_radio_5ghz_revision &&
 574                                 sc->ah->ah_radio_2ghz_revision){
 575                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 576                                 ath5k_chip_name(AR5K_VERSION_RAD,
 577                                         sc->ah->ah_radio_5ghz_revision),
 578                                         sc->ah->ah_radio_5ghz_revision);
 579                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 580                                 ath5k_chip_name(AR5K_VERSION_RAD,
 581                                         sc->ah->ah_radio_2ghz_revision),
 582                                         sc->ah->ah_radio_2ghz_revision);
 583                 }
 584         }
 585
 586
 587         /* ready to process interrupts */
 588         __clear_bit(ATH_STAT_INVALID, sc->status);
 589
 590         return 0;
 591 err_ah:
 592         ath5k_hw_detach(sc->ah);
 593 err_irq:
 594         free_irq(pdev->irq, sc);
 595 err_free:
 596         ieee80211_free_hw(hw);
 597 err_map:
 598         pci_iounmap(pdev, mem);
 599 err_reg:
 600         pci_release_region(pdev, 0);
 601 err_dis:
 602         pci_disable_device(pdev);
 603 err:
 604         return ret;
 605 }
 606
 607 static void __devexit
 608 ath5k_pci_remove(struct pci_dev *pdev)
 609 {
 610         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 611         struct ath5k_softc *sc = hw->priv;
 612
 613         ath5k_debug_finish_device(sc);
 614         ath5k_detach(pdev, hw);
 615         ath5k_hw_detach(sc->ah);
 616         free_irq(pdev->irq, sc);
 617         pci_iounmap(pdev, sc->iobase);
 618         pci_release_region(pdev, 0);
 619         pci_disable_device(pdev);
 620         ieee80211_free_hw(hw);
 621 }
 622
 623 #ifdef CONFIG_PM
 624 static int
 625 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 626 {
 627         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 628         struct ath5k_softc *sc = hw->priv;
 629
 630         ath5k_led_off(sc);
 631
 632         ath5k_stop_hw(sc);
 633
 634         free_irq(pdev->irq, sc);
 635         pci_save_state(pdev);
 636         pci_disable_device(pdev);
 637         pci_set_power_state(pdev, PCI_D3hot);
 638
 639         return 0;
 640 }
 641
 642 static int
 643 ath5k_pci_resume(struct pci_dev *pdev)
 644 {
 645         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 646         struct ath5k_softc *sc = hw->priv;
 647         struct ath5k_hw *ah = sc->ah;
 648         int i, err;
 649
 650         pci_restore_state(pdev);
 651
 652         err = pci_enable_device(pdev);
 653         if (err)
 654                 return err;
 655
 656         /*
 657          * Suspend/Resume resets the PCI configuration space, so we have to
 658          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 659          * PCI Tx retries from interfering with C3 CPU state
 660          */
 661         pci_write_config_byte(pdev, 0x41, 0);
 662
 663         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 664         if (err) {
 665                 ATH5K_ERR(sc, "request_irq failed\n");
 666                 goto err_no_irq;
 667         }
 668
 669         err = ath5k_init(sc);
 670         if (err)
 671                 goto err_irq;
 672         ath5k_led_enable(sc);
 673
 674         /*
 675          * Reset the key cache since some parts do not
 676          * reset the contents on initial power up or resume.
 677          *
 678          * FIXME: This may need to be revisited when mac80211 becomes
 679          *        aware of suspend/resume.
 680          */
 681         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
 682                 ath5k_hw_reset_key(ah, i);
 683
 684         return 0;
 685 err_irq:
 686         free_irq(pdev->irq, sc);
 687 err_no_irq:
 688         pci_disable_device(pdev);
 689         return err;
 690 }
 691 #endif /* CONFIG_PM */
 692
 693
 694 /***********************\
 695 * Driver Initialization *
 696 \***********************/
 697
 698 static int
 699 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 700 {
 701         struct ath5k_softc *sc = hw->priv;
 702         struct ath5k_hw *ah = sc->ah;
 703         u8 mac[ETH_ALEN];
 704         unsigned int i;
 705         int ret;
 706
 707         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 708
 709         /*
 710          * Check if the MAC has multi-rate retry support.
 711          * We do this by trying to setup a fake extended
 712          * descriptor.  MAC's that don't have support will
 713          * return false w/o doing anything.  MAC's that do
 714          * support it will return true w/o doing anything.
 715          */
 716         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 717         if (ret < 0)
 718                 goto err;
 719         if (ret > 0)
 720                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 721
 722         /*
 723          * Reset the key cache since some parts do not
 724          * reset the contents on initial power up.
 725          */
 726         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
 727                 ath5k_hw_reset_key(ah, i);
 728
 729         /*
 730          * Collect the channel list.  The 802.11 layer
 731          * is resposible for filtering this list based
 732          * on settings like the phy mode and regulatory
 733          * domain restrictions.
 734          */
 735         ret = ath5k_setup_bands(hw);
 736         if (ret) {
 737                 ATH5K_ERR(sc, "can't get channels\n");
 738                 goto err;
 739         }
 740
 741         /* NB: setup here so ath5k_rate_update is happy */
 742         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 743                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 744         else
 745                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 746
 747         /*
 748          * Allocate tx+rx descriptors and populate the lists.
 749          */
 750         ret = ath5k_desc_alloc(sc, pdev);
 751         if (ret) {
 752                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 753                 goto err;
 754         }
 755
 756         /*
 757          * Allocate hardware transmit queues: one queue for
 758          * beacon frames and one data queue for each QoS
 759          * priority.  Note that hw functions handle reseting
 760          * these queues at the needed time.
 761          */
 762         ret = ath5k_beaconq_setup(ah);
 763         if (ret < 0) {
 764                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 765                 goto err_desc;
 766         }
 767         sc->bhalq = ret;
 768
 769         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 770         if (IS_ERR(sc->txq)) {
 771                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 772                 ret = PTR_ERR(sc->txq);
 773                 goto err_bhal;
 774         }
 775
 776         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 777         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 778         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 779         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 780
 781         ath5k_hw_get_lladdr(ah, mac);
 782         SET_IEEE80211_PERM_ADDR(hw, mac);
 783         /* All MAC address bits matter for ACKs */
 784         memset(sc->bssidmask, 0xff, ETH_ALEN);
 785         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 786
 787         ret = ieee80211_register_hw(hw);
 788         if (ret) {
 789                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 790                 goto err_queues;
 791         }
 792
 793         ath5k_init_leds(sc);
 794
 795         return 0;
 796 err_queues:
 797         ath5k_txq_release(sc);
 798 err_bhal:
 799         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 800 err_desc:
 801         ath5k_desc_free(sc, pdev);
 802 err:
 803         return ret;
 804 }
 805
 806 static void
 807 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 808 {
 809         struct ath5k_softc *sc = hw->priv;
 810
 811         /*
 812          * NB: the order of these is important:
 813          * o call the 802.11 layer before detaching ath5k_hw to
 814          *   insure callbacks into the driver to delete global
 815          *   key cache entries can be handled
 816          * o reclaim the tx queue data structures after calling
 817          *   the 802.11 layer as we'll get called back to reclaim
 818          *   node state and potentially want to use them
 819          * o to cleanup the tx queues the hal is called, so detach
 820          *   it last
 821          * XXX: ??? detach ath5k_hw ???
 822          * Other than that, it's straightforward...
 823          */
 824         ieee80211_unregister_hw(hw);
 825         ath5k_desc_free(sc, pdev);
 826         ath5k_txq_release(sc);
 827         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 828         ath5k_unregister_leds(sc);
 829
 830         /*
 831          * NB: can't reclaim these until after ieee80211_ifdetach
 832          * returns because we'll get called back to reclaim node
 833          * state and potentially want to use them.
 834          */
 835 }
 836
 837
 838
 839
 840 /********************\
 841 * Channel/mode setup *
 842 \********************/
 843
 844 /*
 845  * Convert IEEE channel number to MHz frequency.
 846  */
 847 static inline short
 848 ath5k_ieee2mhz(short chan)
 849 {
 850         if (chan <= 14 || chan >= 27)
 851                 return ieee80211chan2mhz(chan);
 852         else
 853                 return 2212 + chan * 20;
 854 }
 855
 856 static unsigned int
 857 ath5k_copy_channels(struct ath5k_hw *ah,
 858                 struct ieee80211_channel *channels,
 859                 unsigned int mode,
 860                 unsigned int max)
 861 {
 862         unsigned int i, count, size, chfreq, freq, ch;
 863
 864         if (!test_bit(mode, ah->ah_modes))
 865                 return 0;
 866
 867         switch (mode) {
 868         case AR5K_MODE_11A:
 869         case AR5K_MODE_11A_TURBO:
 870                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 871                 size = 220 ;
 872                 chfreq = CHANNEL_5GHZ;
 873                 break;
 874         case AR5K_MODE_11B:
 875         case AR5K_MODE_11G:
 876         case AR5K_MODE_11G_TURBO:
 877                 size = 26;
 878                 chfreq = CHANNEL_2GHZ;
 879                 break;
 880         default:
 881                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 882                 return 0;
 883         }
 884
 885         for (i = 0, count = 0; i < size && max > 0; i++) {
 886                 ch = i + 1 ;
 887                 freq = ath5k_ieee2mhz(ch);
 888
 889                 /* Check if channel is supported by the chipset */
 890                 if (!ath5k_channel_ok(ah, freq, chfreq))
 891                         continue;
 892
 893                 /* Write channel info and increment counter */
 894                 channels[count].center_freq = freq;
 895                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 896                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 897                 switch (mode) {
 898                 case AR5K_MODE_11A:
 899                 case AR5K_MODE_11G:
 900                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 901                         break;
 902                 case AR5K_MODE_11A_TURBO:
 903                 case AR5K_MODE_11G_TURBO:
 904                         channels[count].hw_value = chfreq |
 905                                 CHANNEL_OFDM | CHANNEL_TURBO;
 906                         break;
 907                 case AR5K_MODE_11B:
 908                         channels[count].hw_value = CHANNEL_B;
 909                 }
 910
 911                 count++;
 912                 max--;
 913         }
 914
 915         return count;
 916 }
 917
 918 static void
 919 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 920 {
 921         u8 i;
 922
 923         for (i = 0; i < AR5K_MAX_RATES; i++)
 924                 sc->rate_idx[b->band][i] = -1;
 925
 926         for (i = 0; i < b->n_bitrates; i++) {
 927                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 928                 if (b->bitrates[i].hw_value_short)
 929                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 930         }
 931 }
 932
 933 static int
 934 ath5k_setup_bands(struct ieee80211_hw *hw)
 935 {
 936         struct ath5k_softc *sc = hw->priv;
 937         struct ath5k_hw *ah = sc->ah;
 938         struct ieee80211_supported_band *sband;
 939         int max_c, count_c = 0;
 940         int i;
 941
 942         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 943         max_c = ARRAY_SIZE(sc->channels);
 944
 945         /* 2GHz band */
 946         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 947         sband->band = IEEE80211_BAND_2GHZ;
 948         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 949
 950         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 951                 /* G mode */
 952                 memcpy(sband->bitrates, &ath5k_rates[0],
 953                        sizeof(struct ieee80211_rate) * 12);
 954                 sband->n_bitrates = 12;
 955
 956                 sband->channels = sc->channels;
 957                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 958                                         AR5K_MODE_11G, max_c);
 959
 960                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 961                 count_c = sband->n_channels;
 962                 max_c -= count_c;
 963         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 964                 /* B mode */
 965                 memcpy(sband->bitrates, &ath5k_rates[0],
 966                        sizeof(struct ieee80211_rate) * 4);
 967                 sband->n_bitrates = 4;
 968
 969                 /* 5211 only supports B rates and uses 4bit rate codes
 970                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 971                  * fix them up here:
 972                  */
 973                 if (ah->ah_version == AR5K_AR5211) {
 974                         for (i = 0; i < 4; i++) {
 975                                 sband->bitrates[i].hw_value =
 976                                         sband->bitrates[i].hw_value & 0xF;
 977                                 sband->bitrates[i].hw_value_short =
 978                                         sband->bitrates[i].hw_value_short & 0xF;
 979                         }
 980                 }
 981
 982                 sband->channels = sc->channels;
 983                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 984                                         AR5K_MODE_11B, max_c);
 985
 986                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 987                 count_c = sband->n_channels;
 988                 max_c -= count_c;
 989         }
 990         ath5k_setup_rate_idx(sc, sband);
 991
 992         /* 5GHz band, A mode */
 993         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
 994                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
 995                 sband->band = IEEE80211_BAND_5GHZ;
 996                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
 997
 998                 memcpy(sband->bitrates, &ath5k_rates[4],
 999                        sizeof(struct ieee80211_rate) * 8);
1000                 sband->n_bitrates = 8;
1001
1002                 sband->channels = &sc->channels[count_c];
1003                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1004                                         AR5K_MODE_11A, max_c);
1005
1006                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1007         }
1008         ath5k_setup_rate_idx(sc, sband);
1009
1010         ath5k_debug_dump_bands(sc);
1011
1012         return 0;
1013 }
1014
1015 /*
1016  * Set/change channels.  If the channel is really being changed,
1017  * it's done by reseting the chip.  To accomplish this we must
1018  * first cleanup any pending DMA, then restart stuff after a la
1019  * ath5k_init.
1020  */
1021 static int
1022 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1023 {
1024         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1025                 sc->curchan->center_freq, chan->center_freq);
1026
1027         if (chan->center_freq != sc->curchan->center_freq ||
1028                 chan->hw_value != sc->curchan->hw_value) {
1029
1030                 sc->curchan = chan;
1031                 sc->curband = &sc->sbands[chan->band];
1032
1033                 /*
1034                  * To switch channels clear any pending DMA operations;
1035                  * wait long enough for the RX fifo to drain, reset the
1036                  * hardware at the new frequency, and then re-enable
1037                  * the relevant bits of the h/w.
1038                  */
1039                 return ath5k_reset(sc, true, true);
1040         }
1041
1042         return 0;
1043 }
1044
1045 static void
1046 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1047 {
1048         sc->curmode = mode;
1049
1050         if (mode == AR5K_MODE_11A) {
1051                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1052         } else {
1053                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1054         }
1055 }
1056
1057 static void
1058 ath5k_mode_setup(struct ath5k_softc *sc)
1059 {
1060         struct ath5k_hw *ah = sc->ah;
1061         u32 rfilt;
1062
1063         /* configure rx filter */
1064         rfilt = sc->filter_flags;
1065         ath5k_hw_set_rx_filter(ah, rfilt);
1066
1067         if (ath5k_hw_hasbssidmask(ah))
1068                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1069
1070         /* configure operational mode */
1071         ath5k_hw_set_opmode(ah);
1072
1073         ath5k_hw_set_mcast_filter(ah, 0, 0);
1074         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1075 }
1076
1077 static inline int
1078 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1079 {
1080         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1081         return sc->rate_idx[sc->curband->band][hw_rix];
1082 }
1083
1084 /***************\
1085 * Buffers setup *
1086 \***************/
1087
1088 static int
1089 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1090 {
1091         struct ath5k_hw *ah = sc->ah;
1092         struct sk_buff *skb = bf->skb;
1093         struct ath5k_desc *ds;
1094
1095         if (likely(skb == NULL)) {
1096                 unsigned int off;
1097
1098                 /*
1099                  * Allocate buffer with headroom_needed space for the
1100                  * fake physical layer header at the start.
1101                  */
1102                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1103                 if (unlikely(skb == NULL)) {
1104                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1105                                         sc->rxbufsize + sc->cachelsz - 1);
1106                         return -ENOMEM;
1107                 }
1108                 /*
1109                  * Cache-line-align.  This is important (for the
1110                  * 5210 at least) as not doing so causes bogus data
1111                  * in rx'd frames.
1112                  */
1113                 off = ((unsigned long)skb->data) % sc->cachelsz;
1114                 if (off != 0)
1115                         skb_reserve(skb, sc->cachelsz - off);
1116
1117                 bf->skb = skb;
1118                 bf->skbaddr = pci_map_single(sc->pdev,
1119                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1120                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1121                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1122                         dev_kfree_skb(skb);
1123                         bf->skb = NULL;
1124                         return -ENOMEM;
1125                 }
1126         }
1127
1128         /*
1129          * Setup descriptors.  For receive we always terminate
1130          * the descriptor list with a self-linked entry so we'll
1131          * not get overrun under high load (as can happen with a
1132          * 5212 when ANI processing enables PHY error frames).
1133          *
1134          * To insure the last descriptor is self-linked we create
1135          * each descriptor as self-linked and add it to the end.  As
1136          * each additional descriptor is added the previous self-linked
1137          * entry is ``fixed'' naturally.  This should be safe even
1138          * if DMA is happening.  When processing RX interrupts we
1139          * never remove/process the last, self-linked, entry on the
1140          * descriptor list.  This insures the hardware always has
1141          * someplace to write a new frame.
1142          */
1143         ds = bf->desc;
1144         ds->ds_link = bf->daddr;        /* link to self */
1145         ds->ds_data = bf->skbaddr;
1146         ah->ah_setup_rx_desc(ah, ds,
1147                 skb_tailroom(skb),      /* buffer size */
1148                 0);
1149
1150         if (sc->rxlink != NULL)
1151                 *sc->rxlink = bf->daddr;
1152         sc->rxlink = &ds->ds_link;
1153         return 0;
1154 }
1155
1156 static int
1157 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1158 {
1159         struct ath5k_hw *ah = sc->ah;
1160         struct ath5k_txq *txq = sc->txq;
1161         struct ath5k_desc *ds = bf->desc;
1162         struct sk_buff *skb = bf->skb;
1163         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1164         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1165         int ret;
1166
1167         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1168
1169         /* XXX endianness */
1170         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1171                         PCI_DMA_TODEVICE);
1172
1173         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1174                 flags |= AR5K_TXDESC_NOACK;
1175
1176         pktlen = skb->len;
1177
1178         if (info->control.hw_key) {
1179                 keyidx = info->control.hw_key->hw_key_idx;
1180                 pktlen += info->control.icv_len;
1181         }
1182         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1183                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1184                 (sc->power_level * 2),
1185                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1186                 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1187         if (ret)
1188                 goto err_unmap;
1189
1190         ds->ds_link = 0;
1191         ds->ds_data = bf->skbaddr;
1192
1193         spin_lock_bh(&txq->lock);
1194         list_add_tail(&bf->list, &txq->q);
1195         sc->tx_stats[txq->qnum].len++;
1196         if (txq->link == NULL) /* is this first packet? */
1197                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1198         else /* no, so only link it */
1199                 *txq->link = bf->daddr;
1200
1201         txq->link = &ds->ds_link;
1202         ath5k_hw_start_tx_dma(ah, txq->qnum);
1203         mmiowb();
1204         spin_unlock_bh(&txq->lock);
1205
1206         return 0;
1207 err_unmap:
1208         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1209         return ret;
1210 }
1211
1212 /*******************\
1213 * Descriptors setup *
1214 \*******************/
1215
1216 static int
1217 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1218 {
1219         struct ath5k_desc *ds;
1220         struct ath5k_buf *bf;
1221         dma_addr_t da;
1222         unsigned int i;
1223         int ret;
1224
1225         /* allocate descriptors */
1226         sc->desc_len = sizeof(struct ath5k_desc) *
1227                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1228         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1229         if (sc->desc == NULL) {
1230                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1231                 ret = -ENOMEM;
1232                 goto err;
1233         }
1234         ds = sc->desc;
1235         da = sc->desc_daddr;
1236         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1237                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1238
1239         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1240                         sizeof(struct ath5k_buf), GFP_KERNEL);
1241         if (bf == NULL) {
1242                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1243                 ret = -ENOMEM;
1244                 goto err_free;
1245         }
1246         sc->bufptr = bf;
1247
1248         INIT_LIST_HEAD(&sc->rxbuf);
1249         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1250                 bf->desc = ds;
1251                 bf->daddr = da;
1252                 list_add_tail(&bf->list, &sc->rxbuf);
1253         }
1254
1255         INIT_LIST_HEAD(&sc->txbuf);
1256         sc->txbuf_len = ATH_TXBUF;
1257         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1258                         da += sizeof(*ds)) {
1259                 bf->desc = ds;
1260                 bf->daddr = da;
1261                 list_add_tail(&bf->list, &sc->txbuf);
1262         }
1263
1264         /* beacon buffer */
1265         bf->desc = ds;
1266         bf->daddr = da;
1267         sc->bbuf = bf;
1268
1269         return 0;
1270 err_free:
1271         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1272 err:
1273         sc->desc = NULL;
1274         return ret;
1275 }
1276
1277 static void
1278 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1279 {
1280         struct ath5k_buf *bf;
1281
1282         ath5k_txbuf_free(sc, sc->bbuf);
1283         list_for_each_entry(bf, &sc->txbuf, list)
1284                 ath5k_txbuf_free(sc, bf);
1285         list_for_each_entry(bf, &sc->rxbuf, list)
1286                 ath5k_txbuf_free(sc, bf);
1287
1288         /* Free memory associated with all descriptors */
1289         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1290
1291         kfree(sc->bufptr);
1292         sc->bufptr = NULL;
1293 }
1294
1295
1296
1297
1298
1299 /**************\
1300 * Queues setup *
1301 \**************/
1302
1303 static struct ath5k_txq *
1304 ath5k_txq_setup(struct ath5k_softc *sc,
1305                 int qtype, int subtype)
1306 {
1307         struct ath5k_hw *ah = sc->ah;
1308         struct ath5k_txq *txq;
1309         struct ath5k_txq_info qi = {
1310                 .tqi_subtype = subtype,
1311                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1312                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1313                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1314         };
1315         int qnum;
1316
1317         /*
1318          * Enable interrupts only for EOL and DESC conditions.
1319          * We mark tx descriptors to receive a DESC interrupt
1320          * when a tx queue gets deep; otherwise waiting for the
1321          * EOL to reap descriptors.  Note that this is done to
1322          * reduce interrupt load and this only defers reaping
1323          * descriptors, never transmitting frames.  Aside from
1324          * reducing interrupts this also permits more concurrency.
1325          * The only potential downside is if the tx queue backs
1326          * up in which case the top half of the kernel may backup
1327          * due to a lack of tx descriptors.
1328          */
1329         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1330                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1331         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1332         if (qnum < 0) {
1333                 /*
1334                  * NB: don't print a message, this happens
1335                  * normally on parts with too few tx queues
1336                  */
1337                 return ERR_PTR(qnum);
1338         }
1339         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1340                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1341                         qnum, ARRAY_SIZE(sc->txqs));
1342                 ath5k_hw_release_tx_queue(ah, qnum);
1343                 return ERR_PTR(-EINVAL);
1344         }
1345         txq = &sc->txqs[qnum];
1346         if (!txq->setup) {
1347                 txq->qnum = qnum;
1348                 txq->link = NULL;
1349                 INIT_LIST_HEAD(&txq->q);
1350                 spin_lock_init(&txq->lock);
1351                 txq->setup = true;
1352         }
1353         return &sc->txqs[qnum];
1354 }
1355
1356 static int
1357 ath5k_beaconq_setup(struct ath5k_hw *ah)
1358 {
1359         struct ath5k_txq_info qi = {
1360                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1361                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1362                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1363                 /* NB: for dynamic turbo, don't enable any other interrupts */
1364                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1365         };
1366
1367         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1368 }
1369
1370 static int
1371 ath5k_beaconq_config(struct ath5k_softc *sc)
1372 {
1373         struct ath5k_hw *ah = sc->ah;
1374         struct ath5k_txq_info qi;
1375         int ret;
1376
1377         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1378         if (ret)
1379                 return ret;
1380         if (sc->opmode == NL80211_IFTYPE_AP ||
1381                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1382                 /*
1383                  * Always burst out beacon and CAB traffic
1384                  * (aifs = cwmin = cwmax = 0)
1385                  */
1386                 qi.tqi_aifs = 0;
1387                 qi.tqi_cw_min = 0;
1388                 qi.tqi_cw_max = 0;
1389         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1390                 /*
1391                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1392                  */
1393                 qi.tqi_aifs = 0;
1394                 qi.tqi_cw_min = 0;
1395                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1396         }
1397
1398         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1399                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1400                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1401
1402         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1403         if (ret) {
1404                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1405                         "hardware queue!\n", __func__);
1406                 return ret;
1407         }
1408
1409         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1410 }
1411
1412 static void
1413 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1414 {
1415         struct ath5k_buf *bf, *bf0;
1416
1417         /*
1418          * NB: this assumes output has been stopped and
1419          *     we do not need to block ath5k_tx_tasklet
1420          */
1421         spin_lock_bh(&txq->lock);
1422         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1423                 ath5k_debug_printtxbuf(sc, bf);
1424
1425                 ath5k_txbuf_free(sc, bf);
1426
1427                 spin_lock_bh(&sc->txbuflock);
1428                 sc->tx_stats[txq->qnum].len--;
1429                 list_move_tail(&bf->list, &sc->txbuf);
1430                 sc->txbuf_len++;
1431                 spin_unlock_bh(&sc->txbuflock);
1432         }
1433         txq->link = NULL;
1434         spin_unlock_bh(&txq->lock);
1435 }
1436
1437 /*
1438  * Drain the transmit queues and reclaim resources.
1439  */
1440 static void
1441 ath5k_txq_cleanup(struct ath5k_softc *sc)
1442 {
1443         struct ath5k_hw *ah = sc->ah;
1444         unsigned int i;
1445
1446         /* XXX return value */
1447         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1448                 /* don't touch the hardware if marked invalid */
1449                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1450                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1451                         ath5k_hw_get_txdp(ah, sc->bhalq));
1452                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1453                         if (sc->txqs[i].setup) {
1454                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1455                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1456                                         "link %p\n",
1457                                         sc->txqs[i].qnum,
1458                                         ath5k_hw_get_txdp(ah,
1459                                                         sc->txqs[i].qnum),
1460                                         sc->txqs[i].link);
1461                         }
1462         }
1463         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1464
1465         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1466                 if (sc->txqs[i].setup)
1467                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1468 }
1469
1470 static void
1471 ath5k_txq_release(struct ath5k_softc *sc)
1472 {
1473         struct ath5k_txq *txq = sc->txqs;
1474         unsigned int i;
1475
1476         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1477                 if (txq->setup) {
1478                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1479                         txq->setup = false;
1480                 }
1481 }
1482
1483
1484
1485
1486 /*************\
1487 * RX Handling *
1488 \*************/
1489
1490 /*
1491  * Enable the receive h/w following a reset.
1492  */
1493 static int
1494 ath5k_rx_start(struct ath5k_softc *sc)
1495 {
1496         struct ath5k_hw *ah = sc->ah;
1497         struct ath5k_buf *bf;
1498         int ret;
1499
1500         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1501
1502         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1503                 sc->cachelsz, sc->rxbufsize);
1504
1505         sc->rxlink = NULL;
1506
1507         spin_lock_bh(&sc->rxbuflock);
1508         list_for_each_entry(bf, &sc->rxbuf, list) {
1509                 ret = ath5k_rxbuf_setup(sc, bf);
1510                 if (ret != 0) {
1511                         spin_unlock_bh(&sc->rxbuflock);
1512                         goto err;
1513                 }
1514         }
1515         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1516         spin_unlock_bh(&sc->rxbuflock);
1517
1518         ath5k_hw_set_rxdp(ah, bf->daddr);
1519         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1520         ath5k_mode_setup(sc);           /* set filters, etc. */
1521         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1522
1523         return 0;
1524 err:
1525         return ret;
1526 }
1527
1528 /*
1529  * Disable the receive h/w in preparation for a reset.
1530  */
1531 static void
1532 ath5k_rx_stop(struct ath5k_softc *sc)
1533 {
1534         struct ath5k_hw *ah = sc->ah;
1535
1536         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1537         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1538         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1539
1540         ath5k_debug_printrxbuffs(sc, ah);
1541
1542         sc->rxlink = NULL;              /* just in case */
1543 }
1544
1545 static unsigned int
1546 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1547                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1548 {
1549         struct ieee80211_hdr *hdr = (void *)skb->data;
1550         unsigned int keyix, hlen;
1551
1552         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1553                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1554                 return RX_FLAG_DECRYPTED;
1555
1556         /* Apparently when a default key is used to decrypt the packet
1557            the hw does not set the index used to decrypt.  In such cases
1558            get the index from the packet. */
1559         hlen = ieee80211_hdrlen(hdr->frame_control);
1560         if (ieee80211_has_protected(hdr->frame_control) &&
1561             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1562             skb->len >= hlen + 4) {
1563                 keyix = skb->data[hlen + 3] >> 6;
1564
1565                 if (test_bit(keyix, sc->keymap))
1566                         return RX_FLAG_DECRYPTED;
1567         }
1568
1569         return 0;
1570 }
1571
1572
1573 static void
1574 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1575                      struct ieee80211_rx_status *rxs)
1576 {
1577         u64 tsf, bc_tstamp;
1578         u32 hw_tu;
1579         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1580
1581         if (ieee80211_is_beacon(mgmt->frame_control) &&
1582             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1583             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1584                 /*
1585                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1586                  * have updated the local TSF. We have to work around various
1587                  * hardware bugs, though...
1588                  */
1589                 tsf = ath5k_hw_get_tsf64(sc->ah);
1590                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1591                 hw_tu = TSF_TO_TU(tsf);
1592
1593                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1594                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1595                         (unsigned long long)bc_tstamp,
1596                         (unsigned long long)rxs->mactime,
1597                         (unsigned long long)(rxs->mactime - bc_tstamp),
1598                         (unsigned long long)tsf);
1599
1600                 /*
1601                  * Sometimes the HW will give us a wrong tstamp in the rx
1602                  * status, causing the timestamp extension to go wrong.
1603                  * (This seems to happen especially with beacon frames bigger
1604                  * than 78 byte (incl. FCS))
1605                  * But we know that the receive timestamp must be later than the
1606                  * timestamp of the beacon since HW must have synced to that.
1607                  *
1608                  * NOTE: here we assume mactime to be after the frame was
1609                  * received, not like mac80211 which defines it at the start.
1610                  */
1611                 if (bc_tstamp > rxs->mactime) {
1612                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1613                                 "fixing mactime from %llx to %llx\n",
1614                                 (unsigned long long)rxs->mactime,
1615                                 (unsigned long long)tsf);
1616                         rxs->mactime = tsf;
1617                 }
1618
1619                 /*
1620                  * Local TSF might have moved higher than our beacon timers,
1621                  * in that case we have to update them to continue sending
1622                  * beacons. This also takes care of synchronizing beacon sending
1623                  * times with other stations.
1624                  */
1625                 if (hw_tu >= sc->nexttbtt)
1626                         ath5k_beacon_update_timers(sc, bc_tstamp);
1627         }
1628 }
1629
1630
1631 static void
1632 ath5k_tasklet_rx(unsigned long data)
1633 {
1634         struct ieee80211_rx_status rxs = {};
1635         struct ath5k_rx_status rs = {};
1636         struct sk_buff *skb;
1637         struct ath5k_softc *sc = (void *)data;
1638         struct ath5k_buf *bf, *bf_last;
1639         struct ath5k_desc *ds;
1640         int ret;
1641         int hdrlen;
1642         int pad;
1643
1644         spin_lock(&sc->rxbuflock);
1645         if (list_empty(&sc->rxbuf)) {
1646                 ATH5K_WARN(sc, "empty rx buf pool\n");
1647                 goto unlock;
1648         }
1649         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1650         do {
1651                 rxs.flag = 0;
1652
1653                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1654                 BUG_ON(bf->skb == NULL);
1655                 skb = bf->skb;
1656                 ds = bf->desc;
1657
1658                 /*
1659                  * last buffer must not be freed to ensure proper hardware
1660                  * function. When the hardware finishes also a packet next to
1661                  * it, we are sure, it doesn't use it anymore and we can go on.
1662                  */
1663                 if (bf_last == bf)
1664                         bf->flags |= 1;
1665                 if (bf->flags) {
1666                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1667                                         struct ath5k_buf, list);
1668                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1669                                         &rs);
1670                         if (ret)
1671                                 break;
1672                         bf->flags &= ~1;
1673                         /* skip the overwritten one (even status is martian) */
1674                         goto next;
1675                 }
1676
1677                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1678                 if (unlikely(ret == -EINPROGRESS))
1679                         break;
1680                 else if (unlikely(ret)) {
1681                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1682                         spin_unlock(&sc->rxbuflock);
1683                         return;
1684                 }
1685
1686                 if (unlikely(rs.rs_more)) {
1687                         ATH5K_WARN(sc, "unsupported jumbo\n");
1688                         goto next;
1689                 }
1690
1691                 if (unlikely(rs.rs_status)) {
1692                         if (rs.rs_status & AR5K_RXERR_PHY)
1693                                 goto next;
1694                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1695                                 /*
1696                                  * Decrypt error.  If the error occurred
1697                                  * because there was no hardware key, then
1698                                  * let the frame through so the upper layers
1699                                  * can process it.  This is necessary for 5210
1700                                  * parts which have no way to setup a ``clear''
1701                                  * key cache entry.
1702                                  *
1703                                  * XXX do key cache faulting
1704                                  */
1705                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1706                                     !(rs.rs_status & AR5K_RXERR_CRC))
1707                                         goto accept;
1708                         }
1709                         if (rs.rs_status & AR5K_RXERR_MIC) {
1710                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1711                                 goto accept;
1712                         }
1713
1714                         /* let crypto-error packets fall through in MNTR */
1715                         if ((rs.rs_status &
1716                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1717                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1718                                 goto next;
1719                 }
1720 accept:
1721                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1722                                 PCI_DMA_FROMDEVICE);
1723                 bf->skb = NULL;
1724
1725                 skb_put(skb, rs.rs_datalen);
1726
1727                 /*
1728                  * the hardware adds a padding to 4 byte boundaries between
1729                  * the header and the payload data if the header length is
1730                  * not multiples of 4 - remove it
1731                  */
1732                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1733                 if (hdrlen & 3) {
1734                         pad = hdrlen % 4;
1735                         memmove(skb->data + pad, skb->data, hdrlen);
1736                         skb_pull(skb, pad);
1737                 }
1738
1739                 /*
1740                  * always extend the mac timestamp, since this information is
1741                  * also needed for proper IBSS merging.
1742                  *
1743                  * XXX: it might be too late to do it here, since rs_tstamp is
1744                  * 15bit only. that means TSF extension has to be done within
1745                  * 32768usec (about 32ms). it might be necessary to move this to
1746                  * the interrupt handler, like it is done in madwifi.
1747                  *
1748                  * Unfortunately we don't know when the hardware takes the rx
1749                  * timestamp (beginning of phy frame, data frame, end of rx?).
1750                  * The only thing we know is that it is hardware specific...
1751                  * On AR5213 it seems the rx timestamp is at the end of the
1752                  * frame, but i'm not sure.
1753                  *
1754                  * NOTE: mac80211 defines mactime at the beginning of the first
1755                  * data symbol. Since we don't have any time references it's
1756                  * impossible to comply to that. This affects IBSS merge only
1757                  * right now, so it's not too bad...
1758                  */
1759                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1760                 rxs.flag |= RX_FLAG_TSFT;
1761
1762                 rxs.freq = sc->curchan->center_freq;
1763                 rxs.band = sc->curband->band;
1764
1765                 rxs.noise = sc->ah->ah_noise_floor;
1766                 rxs.signal = rxs.noise + rs.rs_rssi;
1767                 rxs.qual = rs.rs_rssi * 100 / 64;
1768
1769                 rxs.antenna = rs.rs_antenna;
1770                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1771                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1772
1773                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1774                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1775                         rxs.flag |= RX_FLAG_SHORTPRE;
1776
1777                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1778
1779                 /* check beacons in IBSS mode */
1780                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1781                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1782
1783                 __ieee80211_rx(sc->hw, skb, &rxs);
1784 next:
1785                 list_move_tail(&bf->list, &sc->rxbuf);
1786         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1787 unlock:
1788         spin_unlock(&sc->rxbuflock);
1789 }
1790
1791
1792
1793
1794 /*************\
1795 * TX Handling *
1796 \*************/
1797
1798 static void
1799 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1800 {
1801         struct ath5k_tx_status ts = {};
1802         struct ath5k_buf *bf, *bf0;
1803         struct ath5k_desc *ds;
1804         struct sk_buff *skb;
1805         struct ieee80211_tx_info *info;
1806         int ret;
1807
1808         spin_lock(&txq->lock);
1809         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1810                 ds = bf->desc;
1811
1812                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1813                 if (unlikely(ret == -EINPROGRESS))
1814                         break;
1815                 else if (unlikely(ret)) {
1816                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1817                                 ret, txq->qnum);
1818                         break;
1819                 }
1820
1821                 skb = bf->skb;
1822                 info = IEEE80211_SKB_CB(skb);
1823                 bf->skb = NULL;
1824
1825                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1826                                 PCI_DMA_TODEVICE);
1827
1828                 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1829                 if (unlikely(ts.ts_status)) {
1830                         sc->ll_stats.dot11ACKFailureCount++;
1831                         if (ts.ts_status & AR5K_TXERR_XRETRY)
1832                                 info->status.excessive_retries = 1;
1833                         else if (ts.ts_status & AR5K_TXERR_FILT)
1834                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1835                 } else {
1836                         info->flags |= IEEE80211_TX_STAT_ACK;
1837                         info->status.ack_signal = ts.ts_rssi;
1838                 }
1839
1840                 ieee80211_tx_status(sc->hw, skb);
1841                 sc->tx_stats[txq->qnum].count++;
1842
1843                 spin_lock(&sc->txbuflock);
1844                 sc->tx_stats[txq->qnum].len--;
1845                 list_move_tail(&bf->list, &sc->txbuf);
1846                 sc->txbuf_len++;
1847                 spin_unlock(&sc->txbuflock);
1848         }
1849         if (likely(list_empty(&txq->q)))
1850                 txq->link = NULL;
1851         spin_unlock(&txq->lock);
1852         if (sc->txbuf_len > ATH_TXBUF / 5)
1853                 ieee80211_wake_queues(sc->hw);
1854 }
1855
1856 static void
1857 ath5k_tasklet_tx(unsigned long data)
1858 {
1859         struct ath5k_softc *sc = (void *)data;
1860
1861         ath5k_tx_processq(sc, sc->txq);
1862 }
1863
1864
1865 /*****************\
1866 * Beacon handling *
1867 \*****************/
1868
1869 /*
1870  * Setup the beacon frame for transmit.
1871  */
1872 static int
1873 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1874 {
1875         struct sk_buff *skb = bf->skb;
1876         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1877         struct ath5k_hw *ah = sc->ah;
1878         struct ath5k_desc *ds;
1879         int ret, antenna = 0;
1880         u32 flags;
1881
1882         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1883                         PCI_DMA_TODEVICE);
1884         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1885                         "skbaddr %llx\n", skb, skb->data, skb->len,
1886                         (unsigned long long)bf->skbaddr);
1887         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1888                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1889                 return -EIO;
1890         }
1891
1892         ds = bf->desc;
1893
1894         flags = AR5K_TXDESC_NOACK;
1895         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1896                 ds->ds_link = bf->daddr;        /* self-linked */
1897                 flags |= AR5K_TXDESC_VEOL;
1898                 /*
1899                  * Let hardware handle antenna switching if txantenna is not set
1900                  */
1901         } else {
1902                 ds->ds_link = 0;
1903                 /*
1904                  * Switch antenna every 4 beacons if txantenna is not set
1905                  * XXX assumes two antennas
1906                  */
1907                 if (antenna == 0)
1908                         antenna = sc->bsent & 4 ? 2 : 1;
1909         }
1910
1911         ds->ds_data = bf->skbaddr;
1912         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1913                         ieee80211_get_hdrlen_from_skb(skb),
1914                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1915                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1916                         1, AR5K_TXKEYIX_INVALID,
1917                         antenna, flags, 0, 0);
1918         if (ret)
1919                 goto err_unmap;
1920
1921         return 0;
1922 err_unmap:
1923         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1924         return ret;
1925 }
1926
1927 /*
1928  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1929  * frame contents are done as needed and the slot time is
1930  * also adjusted based on current state.
1931  *
1932  * this is usually called from interrupt context (ath5k_intr())
1933  * but also from ath5k_beacon_config() in IBSS mode which in turn
1934  * can be called from a tasklet and user context
1935  */
1936 static void
1937 ath5k_beacon_send(struct ath5k_softc *sc)
1938 {
1939         struct ath5k_buf *bf = sc->bbuf;
1940         struct ath5k_hw *ah = sc->ah;
1941
1942         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1943
1944         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1945                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
1946                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1947                 return;
1948         }
1949         /*
1950          * Check if the previous beacon has gone out.  If
1951          * not don't don't try to post another, skip this
1952          * period and wait for the next.  Missed beacons
1953          * indicate a problem and should not occur.  If we
1954          * miss too many consecutive beacons reset the device.
1955          */
1956         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1957                 sc->bmisscount++;
1958                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1959                         "missed %u consecutive beacons\n", sc->bmisscount);
1960                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
1961                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1962                                 "stuck beacon time (%u missed)\n",
1963                                 sc->bmisscount);
1964                         tasklet_schedule(&sc->restq);
1965                 }
1966                 return;
1967         }
1968         if (unlikely(sc->bmisscount != 0)) {
1969                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1970                         "resume beacon xmit after %u misses\n",
1971                         sc->bmisscount);
1972                 sc->bmisscount = 0;
1973         }
1974
1975         /*
1976          * Stop any current dma and put the new frame on the queue.
1977          * This should never fail since we check above that no frames
1978          * are still pending on the queue.
1979          */
1980         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1981                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1982                 /* NB: hw still stops DMA, so proceed */
1983         }
1984
1985         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1986         ath5k_hw_start_tx_dma(ah, sc->bhalq);
1987         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1988                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1989
1990         sc->bsent++;
1991 }
1992
1993
1994 /**
1995  * ath5k_beacon_update_timers - update beacon timers
1996  *
1997  * @sc: struct ath5k_softc pointer we are operating on
1998  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1999  *          beacon timer update based on the current HW TSF.
2000  *
2001  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2002  * of a received beacon or the current local hardware TSF and write it to the
2003  * beacon timer registers.
2004  *
2005  * This is called in a variety of situations, e.g. when a beacon is received,
2006  * when a TSF update has been detected, but also when an new IBSS is created or
2007  * when we otherwise know we have to update the timers, but we keep it in this
2008  * function to have it all together in one place.
2009  */
2010 static void
2011 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2012 {
2013         struct ath5k_hw *ah = sc->ah;
2014         u32 nexttbtt, intval, hw_tu, bc_tu;
2015         u64 hw_tsf;
2016
2017         intval = sc->bintval & AR5K_BEACON_PERIOD;
2018         if (WARN_ON(!intval))
2019                 return;
2020
2021         /* beacon TSF converted to TU */
2022         bc_tu = TSF_TO_TU(bc_tsf);
2023
2024         /* current TSF converted to TU */
2025         hw_tsf = ath5k_hw_get_tsf64(ah);
2026         hw_tu = TSF_TO_TU(hw_tsf);
2027
2028 #define FUDGE 3
2029         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2030         if (bc_tsf == -1) {
2031                 /*
2032                  * no beacons received, called internally.
2033                  * just need to refresh timers based on HW TSF.
2034                  */
2035                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2036         } else if (bc_tsf == 0) {
2037                 /*
2038                  * no beacon received, probably called by ath5k_reset_tsf().
2039                  * reset TSF to start with 0.
2040                  */
2041                 nexttbtt = intval;
2042                 intval |= AR5K_BEACON_RESET_TSF;
2043         } else if (bc_tsf > hw_tsf) {
2044                 /*
2045                  * beacon received, SW merge happend but HW TSF not yet updated.
2046                  * not possible to reconfigure timers yet, but next time we
2047                  * receive a beacon with the same BSSID, the hardware will
2048                  * automatically update the TSF and then we need to reconfigure
2049                  * the timers.
2050                  */
2051                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2052                         "need to wait for HW TSF sync\n");
2053                 return;
2054         } else {
2055                 /*
2056                  * most important case for beacon synchronization between STA.
2057                  *
2058                  * beacon received and HW TSF has been already updated by HW.
2059                  * update next TBTT based on the TSF of the beacon, but make
2060                  * sure it is ahead of our local TSF timer.
2061                  */
2062                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2063         }
2064 #undef FUDGE
2065
2066         sc->nexttbtt = nexttbtt;
2067
2068         intval |= AR5K_BEACON_ENA;
2069         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2070
2071         /*
2072          * debugging output last in order to preserve the time critical aspect
2073          * of this function
2074          */
2075         if (bc_tsf == -1)
2076                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2077                         "reconfigured timers based on HW TSF\n");
2078         else if (bc_tsf == 0)
2079                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2080                         "reset HW TSF and timers\n");
2081         else
2082                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2083                         "updated timers based on beacon TSF\n");
2084
2085         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2086                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2087                           (unsigned long long) bc_tsf,
2088                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2089         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2090                 intval & AR5K_BEACON_PERIOD,
2091                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2092                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2093 }
2094
2095
2096 /**
2097  * ath5k_beacon_config - Configure the beacon queues and interrupts
2098  *
2099  * @sc: struct ath5k_softc pointer we are operating on
2100  *
2101  * When operating in station mode we want to receive a BMISS interrupt when we
2102  * stop seeing beacons from the AP we've associated with so we can look for
2103  * another AP to associate with.
2104  *
2105  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2106  * interrupts to detect TSF updates only.
2107  *
2108  * AP mode is missing.
2109  */
2110 static void
2111 ath5k_beacon_config(struct ath5k_softc *sc)
2112 {
2113         struct ath5k_hw *ah = sc->ah;
2114
2115         ath5k_hw_set_imr(ah, 0);
2116         sc->bmisscount = 0;
2117         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2118
2119         if (sc->opmode == NL80211_IFTYPE_STATION) {
2120                 sc->imask |= AR5K_INT_BMISS;
2121         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2122                 /*
2123                  * In IBSS mode we use a self-linked tx descriptor and let the
2124                  * hardware send the beacons automatically. We have to load it
2125                  * only once here.
2126                  * We use the SWBA interrupt only to keep track of the beacon
2127                  * timers in order to detect automatic TSF updates.
2128                  */
2129                 ath5k_beaconq_config(sc);
2130
2131                 sc->imask |= AR5K_INT_SWBA;
2132
2133                 if (ath5k_hw_hasveol(ah)) {
2134                         spin_lock(&sc->block);
2135                         ath5k_beacon_send(sc);
2136                         spin_unlock(&sc->block);
2137                 }
2138         }
2139         /* TODO else AP */
2140
2141         ath5k_hw_set_imr(ah, sc->imask);
2142 }
2143
2144
2145 /********************\
2146 * Interrupt handling *
2147 \********************/
2148
2149 static int
2150 ath5k_init(struct ath5k_softc *sc)
2151 {
2152         int ret;
2153
2154         mutex_lock(&sc->lock);
2155
2156         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2157
2158         /*
2159          * Stop anything previously setup.  This is safe
2160          * no matter this is the first time through or not.
2161          */
2162         ath5k_stop_locked(sc);
2163
2164         /*
2165          * The basic interface to setting the hardware in a good
2166          * state is ``reset''.  On return the hardware is known to
2167          * be powered up and with interrupts disabled.  This must
2168          * be followed by initialization of the appropriate bits
2169          * and then setup of the interrupt mask.
2170          */
2171         sc->curchan = sc->hw->conf.channel;
2172         sc->curband = &sc->sbands[sc->curchan->band];
2173         sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2174                 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2175                 AR5K_INT_MIB;
2176         ret = ath5k_reset(sc, false, false);
2177         if (ret)
2178                 goto done;
2179
2180         /* Set ack to be sent at low bit-rates */
2181         ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2182
2183         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2184                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2185
2186         ret = 0;
2187 done:
2188         mmiowb();
2189         mutex_unlock(&sc->lock);
2190         return ret;
2191 }
2192
2193 static int
2194 ath5k_stop_locked(struct ath5k_softc *sc)
2195 {
2196         struct ath5k_hw *ah = sc->ah;
2197
2198         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2199                         test_bit(ATH_STAT_INVALID, sc->status));
2200
2201         /*
2202          * Shutdown the hardware and driver:
2203          *    stop output from above
2204          *    disable interrupts
2205          *    turn off timers
2206          *    turn off the radio
2207          *    clear transmit machinery
2208          *    clear receive machinery
2209          *    drain and release tx queues
2210          *    reclaim beacon resources
2211          *    power down hardware
2212          *
2213          * Note that some of this work is not possible if the
2214          * hardware is gone (invalid).
2215          */
2216         ieee80211_stop_queues(sc->hw);
2217
2218         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2219                 ath5k_led_off(sc);
2220                 ath5k_hw_set_imr(ah, 0);
2221                 synchronize_irq(sc->pdev->irq);
2222         }
2223         ath5k_txq_cleanup(sc);
2224         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2225                 ath5k_rx_stop(sc);
2226                 ath5k_hw_phy_disable(ah);
2227         } else
2228                 sc->rxlink = NULL;
2229
2230         return 0;
2231 }
2232
2233 /*
2234  * Stop the device, grabbing the top-level lock to protect
2235  * against concurrent entry through ath5k_init (which can happen
2236  * if another thread does a system call and the thread doing the
2237  * stop is preempted).
2238  */
2239 static int
2240 ath5k_stop_hw(struct ath5k_softc *sc)
2241 {
2242         int ret;
2243
2244         mutex_lock(&sc->lock);
2245         ret = ath5k_stop_locked(sc);
2246         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2247                 /*
2248                  * Set the chip in full sleep mode.  Note that we are
2249                  * careful to do this only when bringing the interface
2250                  * completely to a stop.  When the chip is in this state
2251                  * it must be carefully woken up or references to
2252                  * registers in the PCI clock domain may freeze the bus
2253                  * (and system).  This varies by chip and is mostly an
2254                  * issue with newer parts that go to sleep more quickly.
2255                  */
2256                 if (sc->ah->ah_mac_srev >= 0x78) {
2257                         /*
2258                          * XXX
2259                          * don't put newer MAC revisions > 7.8 to sleep because
2260                          * of the above mentioned problems
2261                          */
2262                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2263                                 "not putting device to sleep\n");
2264                 } else {
2265                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2266                                 "putting device to full sleep\n");
2267                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2268                 }
2269         }
2270         ath5k_txbuf_free(sc, sc->bbuf);
2271         mmiowb();
2272         mutex_unlock(&sc->lock);
2273
2274         del_timer_sync(&sc->calib_tim);
2275         tasklet_kill(&sc->rxtq);
2276         tasklet_kill(&sc->txtq);
2277         tasklet_kill(&sc->restq);
2278
2279         return ret;
2280 }
2281
2282 static irqreturn_t
2283 ath5k_intr(int irq, void *dev_id)
2284 {
2285         struct ath5k_softc *sc = dev_id;
2286         struct ath5k_hw *ah = sc->ah;
2287         enum ath5k_int status;
2288         unsigned int counter = 1000;
2289
2290         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2291                                 !ath5k_hw_is_intr_pending(ah)))
2292                 return IRQ_NONE;
2293
2294         do {
2295                 /*
2296                  * Figure out the reason(s) for the interrupt.  Note
2297                  * that get_isr returns a pseudo-ISR that may include
2298                  * bits we haven't explicitly enabled so we mask the
2299                  * value to insure we only process bits we requested.
2300                  */
2301                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2302                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2303                                 status, sc->imask);
2304                 status &= sc->imask; /* discard unasked for bits */
2305                 if (unlikely(status & AR5K_INT_FATAL)) {
2306                         /*
2307                          * Fatal errors are unrecoverable.
2308                          * Typically these are caused by DMA errors.
2309                          */
2310                         tasklet_schedule(&sc->restq);
2311                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2312                         tasklet_schedule(&sc->restq);
2313                 } else {
2314                         if (status & AR5K_INT_SWBA) {
2315                                 /*
2316                                 * Software beacon alert--time to send a beacon.
2317                                 * Handle beacon transmission directly; deferring
2318                                 * this is too slow to meet timing constraints
2319                                 * under load.
2320                                 *
2321                                 * In IBSS mode we use this interrupt just to
2322                                 * keep track of the next TBTT (target beacon
2323                                 * transmission time) in order to detect wether
2324                                 * automatic TSF updates happened.
2325                                 */
2326                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2327                                          /* XXX: only if VEOL suppported */
2328                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2329                                         sc->nexttbtt += sc->bintval;
2330                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2331                                                   "SWBA nexttbtt: %x hw_tu: %x "
2332                                                   "TSF: %llx\n",
2333                                                   sc->nexttbtt,
2334                                                   TSF_TO_TU(tsf),
2335                                                   (unsigned long long) tsf);
2336                                 } else {
2337                                         spin_lock(&sc->block);
2338                                         ath5k_beacon_send(sc);
2339                                         spin_unlock(&sc->block);
2340                                 }
2341                         }
2342                         if (status & AR5K_INT_RXEOL) {
2343                                 /*
2344                                 * NB: the hardware should re-read the link when
2345                                 *     RXE bit is written, but it doesn't work at
2346                                 *     least on older hardware revs.
2347                                 */
2348                                 sc->rxlink = NULL;
2349                         }
2350                         if (status & AR5K_INT_TXURN) {
2351                                 /* bump tx trigger level */
2352                                 ath5k_hw_update_tx_triglevel(ah, true);
2353                         }
2354                         if (status & AR5K_INT_RX)
2355                                 tasklet_schedule(&sc->rxtq);
2356                         if (status & AR5K_INT_TX)
2357                                 tasklet_schedule(&sc->txtq);
2358                         if (status & AR5K_INT_BMISS) {
2359                         }
2360                         if (status & AR5K_INT_MIB) {
2361                                 /*
2362                                  * These stats are also used for ANI i think
2363                                  * so how about updating them more often ?
2364                                  */
2365                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2366                         }
2367                 }
2368         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2369
2370         if (unlikely(!counter))
2371                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2372
2373         return IRQ_HANDLED;
2374 }
2375
2376 static void
2377 ath5k_tasklet_reset(unsigned long data)
2378 {
2379         struct ath5k_softc *sc = (void *)data;
2380
2381         ath5k_reset_wake(sc);
2382 }
2383
2384 /*
2385  * Periodically recalibrate the PHY to account
2386  * for temperature/environment changes.
2387  */
2388 static void
2389 ath5k_calibrate(unsigned long data)
2390 {
2391         struct ath5k_softc *sc = (void *)data;
2392         struct ath5k_hw *ah = sc->ah;
2393
2394         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2395                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2396                 sc->curchan->hw_value);
2397
2398         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2399                 /*
2400                  * Rfgain is out of bounds, reset the chip
2401                  * to load new gain values.
2402                  */
2403                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2404                 ath5k_reset_wake(sc);
2405         }
2406         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2407                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2408                         ieee80211_frequency_to_channel(
2409                                 sc->curchan->center_freq));
2410
2411         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2412                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2413 }
2414
2415
2416
2417 /***************\
2418 * LED functions *
2419 \***************/
2420
2421 static void
2422 ath5k_led_enable(struct ath5k_softc *sc)
2423 {
2424         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2425                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2426                 ath5k_led_off(sc);
2427         }
2428 }
2429
2430 static void
2431 ath5k_led_on(struct ath5k_softc *sc)
2432 {
2433         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2434                 return;
2435         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2436 }
2437
2438 static void
2439 ath5k_led_off(struct ath5k_softc *sc)
2440 {
2441         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2442                 return;
2443         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2444 }
2445
2446 static void
2447 ath5k_led_brightness_set(struct led_classdev *led_dev,
2448         enum led_brightness brightness)
2449 {
2450         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2451                 led_dev);
2452
2453         if (brightness == LED_OFF)
2454                 ath5k_led_off(led->sc);
2455         else
2456                 ath5k_led_on(led->sc);
2457 }
2458
2459 static int
2460 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2461                    const char *name, char *trigger)
2462 {
2463         int err;
2464
2465         led->sc = sc;
2466         strncpy(led->name, name, sizeof(led->name));
2467         led->led_dev.name = led->name;
2468         led->led_dev.default_trigger = trigger;
2469         led->led_dev.brightness_set = ath5k_led_brightness_set;
2470
2471         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2472         if (err)
2473         {
2474                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2475                 led->sc = NULL;
2476         }
2477         return err;
2478 }
2479
2480 static void
2481 ath5k_unregister_led(struct ath5k_led *led)
2482 {
2483         if (!led->sc)
2484                 return;
2485         led_classdev_unregister(&led->led_dev);
2486         ath5k_led_off(led->sc);
2487         led->sc = NULL;
2488 }
2489
2490 static void
2491 ath5k_unregister_leds(struct ath5k_softc *sc)
2492 {
2493         ath5k_unregister_led(&sc->rx_led);
2494         ath5k_unregister_led(&sc->tx_led);
2495 }
2496
2497
2498 static int
2499 ath5k_init_leds(struct ath5k_softc *sc)
2500 {
2501         int ret = 0;
2502         struct ieee80211_hw *hw = sc->hw;
2503         struct pci_dev *pdev = sc->pdev;
2504         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2505
2506         /*
2507          * Auto-enable soft led processing for IBM cards and for
2508          * 5211 minipci cards.
2509          */
2510         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2511             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2512                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2513                 sc->led_pin = 0;
2514                 sc->led_on = 0;  /* active low */
2515         }
2516         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2517         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2518                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2519                 sc->led_pin = 1;
2520                 sc->led_on = 1;  /* active high */
2521         }
2522         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2523                 goto out;
2524
2525         ath5k_led_enable(sc);
2526
2527         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2528         ret = ath5k_register_led(sc, &sc->rx_led, name,
2529                 ieee80211_get_rx_led_name(hw));
2530         if (ret)
2531                 goto out;
2532
2533         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2534         ret = ath5k_register_led(sc, &sc->tx_led, name,
2535                 ieee80211_get_tx_led_name(hw));
2536 out:
2537         return ret;
2538 }
2539
2540
2541 /********************\
2542 * Mac80211 functions *
2543 \********************/
2544
2545 static int
2546 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2547 {
2548         struct ath5k_softc *sc = hw->priv;
2549         struct ath5k_buf *bf;
2550         unsigned long flags;
2551         int hdrlen;
2552         int pad;
2553
2554         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2555
2556         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2557                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2558
2559         /*
2560          * the hardware expects the header padded to 4 byte boundaries
2561          * if this is not the case we add the padding after the header
2562          */
2563         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2564         if (hdrlen & 3) {
2565                 pad = hdrlen % 4;
2566                 if (skb_headroom(skb) < pad) {
2567                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2568                                 " headroom to pad %d\n", hdrlen, pad);
2569                         return -1;
2570                 }
2571                 skb_push(skb, pad);
2572                 memmove(skb->data, skb->data+pad, hdrlen);
2573         }
2574
2575         spin_lock_irqsave(&sc->txbuflock, flags);
2576         if (list_empty(&sc->txbuf)) {
2577                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2578                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2579                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2580                 return -1;
2581         }
2582         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2583         list_del(&bf->list);
2584         sc->txbuf_len--;
2585         if (list_empty(&sc->txbuf))
2586                 ieee80211_stop_queues(hw);
2587         spin_unlock_irqrestore(&sc->txbuflock, flags);
2588
2589         bf->skb = skb;
2590
2591         if (ath5k_txbuf_setup(sc, bf)) {
2592                 bf->skb = NULL;
2593                 spin_lock_irqsave(&sc->txbuflock, flags);
2594                 list_add_tail(&bf->list, &sc->txbuf);
2595                 sc->txbuf_len++;
2596                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2597                 dev_kfree_skb_any(skb);
2598                 return 0;
2599         }
2600
2601         return 0;
2602 }
2603
2604 static int
2605 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2606 {
2607         struct ath5k_hw *ah = sc->ah;
2608         int ret;
2609
2610         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2611
2612         if (stop) {
2613                 ath5k_hw_set_imr(ah, 0);
2614                 ath5k_txq_cleanup(sc);
2615                 ath5k_rx_stop(sc);
2616         }
2617         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2618         if (ret) {
2619                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2620                 goto err;
2621         }
2622
2623         /*
2624          * This is needed only to setup initial state
2625          * but it's best done after a reset.
2626          */
2627         ath5k_hw_set_txpower_limit(sc->ah, 0);
2628
2629         ret = ath5k_rx_start(sc);
2630         if (ret) {
2631                 ATH5K_ERR(sc, "can't start recv logic\n");
2632                 goto err;
2633         }
2634
2635         /*
2636          * Change channels and update the h/w rate map if we're switching;
2637          * e.g. 11a to 11b/g.
2638          *
2639          * We may be doing a reset in response to an ioctl that changes the
2640          * channel so update any state that might change as a result.
2641          *
2642          * XXX needed?
2643          */
2644 /*      ath5k_chan_change(sc, c); */
2645
2646         ath5k_beacon_config(sc);
2647         /* intrs are enabled by ath5k_beacon_config */
2648
2649         return 0;
2650 err:
2651         return ret;
2652 }
2653
2654 static int
2655 ath5k_reset_wake(struct ath5k_softc *sc)
2656 {
2657         int ret;
2658
2659         ret = ath5k_reset(sc, true, true);
2660         if (!ret)
2661                 ieee80211_wake_queues(sc->hw);
2662
2663         return ret;
2664 }
2665
2666 static int ath5k_start(struct ieee80211_hw *hw)
2667 {
2668         return ath5k_init(hw->priv);
2669 }
2670
2671 static void ath5k_stop(struct ieee80211_hw *hw)
2672 {
2673         ath5k_stop_hw(hw->priv);
2674 }
2675
2676 static int ath5k_add_interface(struct ieee80211_hw *hw,
2677                 struct ieee80211_if_init_conf *conf)
2678 {
2679         struct ath5k_softc *sc = hw->priv;
2680         int ret;
2681
2682         mutex_lock(&sc->lock);
2683         if (sc->vif) {
2684                 ret = 0;
2685                 goto end;
2686         }
2687
2688         sc->vif = conf->vif;
2689
2690         switch (conf->type) {
2691         case NL80211_IFTYPE_STATION:
2692         case NL80211_IFTYPE_ADHOC:
2693         case NL80211_IFTYPE_MONITOR:
2694                 sc->opmode = conf->type;
2695                 break;
2696         default:
2697                 ret = -EOPNOTSUPP;
2698                 goto end;
2699         }
2700
2701         /* Set to a reasonable value. Note that this will
2702          * be set to mac80211's value at ath5k_config(). */
2703         sc->bintval = 1000;
2704
2705         ret = 0;
2706 end:
2707         mutex_unlock(&sc->lock);
2708         return ret;
2709 }
2710
2711 static void
2712 ath5k_remove_interface(struct ieee80211_hw *hw,
2713                         struct ieee80211_if_init_conf *conf)
2714 {
2715         struct ath5k_softc *sc = hw->priv;
2716
2717         mutex_lock(&sc->lock);
2718         if (sc->vif != conf->vif)
2719                 goto end;
2720
2721         sc->vif = NULL;
2722 end:
2723         mutex_unlock(&sc->lock);
2724 }
2725
2726 /*
2727  * TODO: Phy disable/diversity etc
2728  */
2729 static int
2730 ath5k_config(struct ieee80211_hw *hw,
2731                         struct ieee80211_conf *conf)
2732 {
2733         struct ath5k_softc *sc = hw->priv;
2734
2735         sc->bintval = conf->beacon_int;
2736         sc->power_level = conf->power_level;
2737
2738         return ath5k_chan_set(sc, conf->channel);
2739 }
2740
2741 static int
2742 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2743                         struct ieee80211_if_conf *conf)
2744 {
2745         struct ath5k_softc *sc = hw->priv;
2746         struct ath5k_hw *ah = sc->ah;
2747         int ret;
2748
2749         mutex_lock(&sc->lock);
2750         if (sc->vif != vif) {
2751                 ret = -EIO;
2752                 goto unlock;
2753         }
2754         if (conf->bssid) {
2755                 /* Cache for later use during resets */
2756                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2757                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2758                  * a clean way of letting us retrieve this yet. */
2759                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2760                 mmiowb();
2761         }
2762
2763         if (conf->changed & IEEE80211_IFCC_BEACON &&
2764             vif->type == NL80211_IFTYPE_ADHOC) {
2765                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2766                 if (!beacon) {
2767                         ret = -ENOMEM;
2768                         goto unlock;
2769                 }
2770                 /* call old handler for now */
2771                 ath5k_beacon_update(hw, beacon);
2772         }
2773
2774         mutex_unlock(&sc->lock);
2775
2776         return ath5k_reset_wake(sc);
2777 unlock:
2778         mutex_unlock(&sc->lock);
2779         return ret;
2780 }
2781
2782 #define SUPPORTED_FIF_FLAGS \
2783         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2784         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2785         FIF_BCN_PRBRESP_PROMISC
2786 /*
2787  * o always accept unicast, broadcast, and multicast traffic
2788  * o multicast traffic for all BSSIDs will be enabled if mac80211
2789  *   says it should be
2790  * o maintain current state of phy ofdm or phy cck error reception.
2791  *   If the hardware detects any of these type of errors then
2792  *   ath5k_hw_get_rx_filter() will pass to us the respective
2793  *   hardware filters to be able to receive these type of frames.
2794  * o probe request frames are accepted only when operating in
2795  *   hostap, adhoc, or monitor modes
2796  * o enable promiscuous mode according to the interface state
2797  * o accept beacons:
2798  *   - when operating in adhoc mode so the 802.11 layer creates
2799  *     node table entries for peers,
2800  *   - when operating in station mode for collecting rssi data when
2801  *     the station is otherwise quiet, or
2802  *   - when scanning
2803  */
2804 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2805                 unsigned int changed_flags,
2806                 unsigned int *new_flags,
2807                 int mc_count, struct dev_mc_list *mclist)
2808 {
2809         struct ath5k_softc *sc = hw->priv;
2810         struct ath5k_hw *ah = sc->ah;
2811         u32 mfilt[2], val, rfilt;
2812         u8 pos;
2813         int i;
2814
2815         mfilt[0] = 0;
2816         mfilt[1] = 0;
2817
2818         /* Only deal with supported flags */
2819         changed_flags &= SUPPORTED_FIF_FLAGS;
2820         *new_flags &= SUPPORTED_FIF_FLAGS;
2821
2822         /* If HW detects any phy or radar errors, leave those filters on.
2823          * Also, always enable Unicast, Broadcasts and Multicast
2824          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2825         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2826                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2827                 AR5K_RX_FILTER_MCAST);
2828
2829         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2830                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2831                         rfilt |= AR5K_RX_FILTER_PROM;
2832                         __set_bit(ATH_STAT_PROMISC, sc->status);
2833                 }
2834                 else
2835                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2836         }
2837
2838         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2839         if (*new_flags & FIF_ALLMULTI) {
2840                 mfilt[0] =  ~0;
2841                 mfilt[1] =  ~0;
2842         } else {
2843                 for (i = 0; i < mc_count; i++) {
2844                         if (!mclist)
2845                                 break;
2846                         /* calculate XOR of eight 6-bit values */
2847                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2848                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2849                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2850                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2851                         pos &= 0x3f;
2852                         mfilt[pos / 32] |= (1 << (pos % 32));
2853                         /* XXX: we might be able to just do this instead,
2854                         * but not sure, needs testing, if we do use this we'd
2855                         * neet to inform below to not reset the mcast */
2856                         /* ath5k_hw_set_mcast_filterindex(ah,
2857                          *      mclist->dmi_addr[5]); */
2858                         mclist = mclist->next;
2859                 }
2860         }
2861
2862         /* This is the best we can do */
2863         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2864                 rfilt |= AR5K_RX_FILTER_PHYERR;
2865
2866         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2867         * and probes for any BSSID, this needs testing */
2868         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2869                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2870
2871         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2872          * set we should only pass on control frames for this
2873          * station. This needs testing. I believe right now this
2874          * enables *all* control frames, which is OK.. but
2875          * but we should see if we can improve on granularity */
2876         if (*new_flags & FIF_CONTROL)
2877                 rfilt |= AR5K_RX_FILTER_CONTROL;
2878
2879         /* Additional settings per mode -- this is per ath5k */
2880
2881         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2882
2883         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2884                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2885                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2886         if (sc->opmode != NL80211_IFTYPE_STATION)
2887                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2888         if (sc->opmode != NL80211_IFTYPE_AP &&
2889                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2890                 test_bit(ATH_STAT_PROMISC, sc->status))
2891                 rfilt |= AR5K_RX_FILTER_PROM;
2892         if (sc->opmode == NL80211_IFTYPE_STATION ||
2893                 sc->opmode == NL80211_IFTYPE_ADHOC) {
2894                 rfilt |= AR5K_RX_FILTER_BEACON;
2895         }
2896
2897         /* Set filters */
2898         ath5k_hw_set_rx_filter(ah,rfilt);
2899
2900         /* Set multicast bits */
2901         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2902         /* Set the cached hw filter flags, this will alter actually
2903          * be set in HW */
2904         sc->filter_flags = rfilt;
2905 }
2906
2907 static int
2908 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2909                 const u8 *local_addr, const u8 *addr,
2910                 struct ieee80211_key_conf *key)
2911 {
2912         struct ath5k_softc *sc = hw->priv;
2913         int ret = 0;
2914
2915         switch(key->alg) {
2916         case ALG_WEP:
2917         /* XXX: fix hardware encryption, its not working. For now
2918          * allow software encryption */
2919                 /* break; */
2920         case ALG_TKIP:
2921         case ALG_CCMP:
2922                 return -EOPNOTSUPP;
2923         default:
2924                 WARN_ON(1);
2925                 return -EINVAL;
2926         }
2927
2928         mutex_lock(&sc->lock);
2929
2930         switch (cmd) {
2931         case SET_KEY:
2932                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2933                 if (ret) {
2934                         ATH5K_ERR(sc, "can't set the key\n");
2935                         goto unlock;
2936                 }
2937                 __set_bit(key->keyidx, sc->keymap);
2938                 key->hw_key_idx = key->keyidx;
2939                 break;
2940         case DISABLE_KEY:
2941                 ath5k_hw_reset_key(sc->ah, key->keyidx);
2942                 __clear_bit(key->keyidx, sc->keymap);
2943                 break;
2944         default:
2945                 ret = -EINVAL;
2946                 goto unlock;
2947         }
2948
2949 unlock:
2950         mmiowb();
2951         mutex_unlock(&sc->lock);
2952         return ret;
2953 }
2954
2955 static int
2956 ath5k_get_stats(struct ieee80211_hw *hw,
2957                 struct ieee80211_low_level_stats *stats)
2958 {
2959         struct ath5k_softc *sc = hw->priv;
2960         struct ath5k_hw *ah = sc->ah;
2961
2962         /* Force update */
2963         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2964
2965         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2966
2967         return 0;
2968 }
2969
2970 static int
2971 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2972                 struct ieee80211_tx_queue_stats *stats)
2973 {
2974         struct ath5k_softc *sc = hw->priv;
2975
2976         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2977
2978         return 0;
2979 }
2980
2981 static u64
2982 ath5k_get_tsf(struct ieee80211_hw *hw)
2983 {
2984         struct ath5k_softc *sc = hw->priv;
2985
2986         return ath5k_hw_get_tsf64(sc->ah);
2987 }
2988
2989 static void
2990 ath5k_reset_tsf(struct ieee80211_hw *hw)
2991 {
2992         struct ath5k_softc *sc = hw->priv;
2993
2994         /*
2995          * in IBSS mode we need to update the beacon timers too.
2996          * this will also reset the TSF if we call it with 0
2997          */
2998         if (sc->opmode == NL80211_IFTYPE_ADHOC)
2999                 ath5k_beacon_update_timers(sc, 0);
3000         else
3001                 ath5k_hw_reset_tsf(sc->ah);
3002 }
3003
3004 static int
3005 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3006 {
3007         struct ath5k_softc *sc = hw->priv;
3008         unsigned long flags;
3009         int ret;
3010
3011         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3012
3013         if (sc->opmode != NL80211_IFTYPE_ADHOC) {
3014                 ret = -EIO;
3015                 goto end;
3016         }
3017
3018         spin_lock_irqsave(&sc->block, flags);
3019         ath5k_txbuf_free(sc, sc->bbuf);
3020         sc->bbuf->skb = skb;
3021         ret = ath5k_beacon_setup(sc, sc->bbuf);
3022         if (ret)
3023                 sc->bbuf->skb = NULL;
3024         spin_unlock_irqrestore(&sc->block, flags);
3025         if (!ret) {
3026                 ath5k_beacon_config(sc);
3027                 mmiowb();
3028         }
3029
3030 end:
3031         return ret;
3032 }
3033