2 * Support for IBM PPC 405EP evaluation board (Bubinga).
4 * Author: SAW (IBM), derived from walnut.c.
5 * Maintained by MontaVista Software <source@mvista.com>
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
13 #include <linux/init.h>
14 #include <linux/smp.h>
15 #include <linux/threads.h>
16 #include <linux/param.h>
17 #include <linux/string.h>
18 #include <linux/blkdev.h>
19 #include <linux/pci.h>
20 #include <linux/rtc.h>
21 #include <linux/tty.h>
22 #include <linux/serial.h>
23 #include <linux/serial_core.h>
25 #include <asm/system.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/processor.h>
28 #include <asm/machdep.h>
35 #include <asm/ibm_ocp_pci.h>
37 #include <platforms/4xx/ibm405ep.h>
42 #define DBG(x...) printk(x)
49 void *bubinga_rtc_base;
51 /* Some IRQs unique to the board
52 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
55 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57 static char pci_irq_table[][4] =
59 * PCI IDSEL/INTPIN->INTLINE
63 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
64 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
65 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
66 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
69 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
70 return PCI_IRQ_TABLE_LOOKUP;
73 /* The serial clock for the chip is an internal clock determined by
74 * different clock speeds/dividers.
75 * Calculate the proper input baud rate and setup the serial driver.
78 bubinga_early_serial_map(void)
82 struct uart_port port;
84 /* Calculate the serial clock input frequency
86 * The base baud is the PLL OUTA (provided in the board info
87 * structure) divided by the external UART Divisor, divided
90 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
91 uart_clock = __res.bi_procfreq / uart_div;
93 /* Setup serial port access */
94 memset(&port, 0, sizeof(port));
95 port.membase = (void*)ACTING_UART0_IO_BASE;
96 port.irq = ACTING_UART0_INT;
97 port.uartclk = uart_clock;
99 port.iotype = UPIO_MEM;
100 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
103 if (early_serial_setup(&port) != 0) {
104 printk("Early serial init of port 0 failed\n");
107 port.membase = (void*)ACTING_UART1_IO_BASE;
108 port.irq = ACTING_UART1_INT;
111 if (early_serial_setup(&port) != 0) {
112 printk("Early serial init of port 1 failed\n");
117 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
120 unsigned int bar_response, bar;
122 * Expected PCI mapping:
124 * PLB addr PCI memory addr
125 * --------------------- ---------------------
126 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
127 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
129 * PLB addr PCI io addr
130 * --------------------- ---------------------
131 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
133 * The following code is simplified by assuming that the bootrom
134 * has been well behaved in following this mapping.
140 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
141 printk("PCI bridge regs before fixup \n");
142 for (i = 0; i <= 3; i++) {
143 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
144 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
145 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
146 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
148 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
149 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
150 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
151 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
155 /* added for IBM boot rom version 1.15 bios bar changes -AK */
157 /* Disable region first */
158 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
159 /* PLB starting addr, PCI: 0x80000000 */
160 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
161 /* PCI start addr, 0x80000000 */
162 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
163 /* 512MB range of PLB to PCI */
164 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
165 /* Enable no pre-fetch, enable region */
166 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
167 (PPC405_PCI_UPPER_MEM -
168 PPC405_PCI_MEM_BASE)) | 0x01));
170 /* Disable region one */
171 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
172 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
173 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
174 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
175 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
176 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
178 /* Disable region two */
179 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
180 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
181 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
182 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
183 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
184 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
185 out_le32((void *) &(pcip->ptm2la), 0x00000000);
187 /* Zero config bars */
188 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
189 early_write_config_dword(hose, hose->first_busno,
190 PCI_FUNC(hose->first_busno), bar,
192 early_read_config_dword(hose, hose->first_busno,
193 PCI_FUNC(hose->first_busno), bar,
195 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
196 hose->first_busno, PCI_SLOT(hose->first_busno),
197 PCI_FUNC(hose->first_busno), bar, bar_response);
199 /* end work arround */
202 printk("PCI bridge regs after fixup \n");
203 for (i = 0; i <= 3; i++) {
204 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
205 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
206 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
207 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
209 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
210 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
211 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
212 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
218 bubinga_setup_arch(void)
222 ibm_ocp_set_emac(0, 1);
224 bubinga_early_serial_map();
226 /* RTC step for the evb405ep */
227 bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
228 TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
229 bubinga_rtc_base, 8);
230 /* Identify the system */
231 printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
238 io_block_mapping(BUBINGA_RTC_VADDR,
239 BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
243 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
244 unsigned long r6, unsigned long r7)
246 ppc4xx_init(r3, r4, r5, r6, r7);
248 ppc_md.setup_arch = bubinga_setup_arch;
249 ppc_md.setup_io_mappings = bubinga_map_io;
251 #ifdef CONFIG_GEN_RTC
252 ppc_md.time_init = todc_time_init;
253 ppc_md.set_rtc_time = todc_set_rtc_time;
254 ppc_md.get_rtc_time = todc_get_rtc_time;
255 ppc_md.nvram_read_val = todc_direct_read_val;
256 ppc_md.nvram_write_val = todc_direct_write_val;
259 ppc_md.early_serial_map = bubinga_early_serial_map;