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   1 /*******************************************************************************
   2 *
   3 *      "swarm_cs4297a.c" --  Cirrus Logic-Crystal CS4297a linux audio driver.
   4 *
   5 *      Copyright (C) 2001  Broadcom Corporation.
   6 *      Copyright (C) 2000,2001  Cirrus Logic Corp.
   7 *            -- adapted from drivers by Thomas Sailer,
   8 *            -- but don't bug him; Problems should go to:
   9 *            -- tom woller (twoller@crystal.cirrus.com) or
  10 *               (audio@crystal.cirrus.com).
  11 *            -- adapted from cs4281 PCI driver for cs4297a on
  12 *               BCM1250 Synchronous Serial interface
  13 *               (Kip Walker, Broadcom Corp.)
  14 *      Copyright (C) 2004  Maciej W. Rozycki
  15 *      Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  16 *
  17 *      This program is free software; you can redistribute it and/or modify
  18 *      it under the terms of the GNU General Public License as published by
  19 *      the Free Software Foundation; either version 2 of the License, or
  20 *      (at your option) any later version.
  21 *
  22 *      This program is distributed in the hope that it will be useful,
  23 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 *      GNU General Public License for more details.
  26 *
  27 *      You should have received a copy of the GNU General Public License
  28 *      along with this program; if not, write to the Free Software
  29 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 * Module command line parameters:
  32 *   none
  33 *
  34 *  Supported devices:
  35 *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  36 *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  37 *  /dev/midi   simple MIDI UART interface, no ioctl
  38 *
  39 * Modification History
  40 * 08/20/00 trw - silence and no stopping DAC until release
  41 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  42 * 09/18/00 trw - added 16bit only record with conversion
  43 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  44 *                capture/playback rates)
  45 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  46 *                libOSSm.so)
  47 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  48 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  49 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  50 * 11/10/00 trw - fixed SMP and capture spinlock hang.
  51 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  52 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  53 * 12/08/00 trw - added PM support.
  54 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  55 *                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  56 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  57 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  58 *                defaultorder-100 as power of 2 for the buffer size. example:
  59 *                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  60 *
  61 *******************************************************************************/
  62
  63 #include <linux/list.h>
  64 #include <linux/module.h>
  65 #include <linux/string.h>
  66 #include <linux/ioport.h>
  67 #include <linux/sched.h>
  68 #include <linux/delay.h>
  69 #include <linux/sound.h>
  70 #include <linux/slab.h>
  71 #include <linux/soundcard.h>
  72 #include <linux/ac97_codec.h>
  73 #include <linux/pci.h>
  74 #include <linux/bitops.h>
  75 #include <linux/interrupt.h>
  76 #include <linux/init.h>
  77 #include <linux/poll.h>
  78 #include <linux/smp_lock.h>
  79 #include <linux/mutex.h>
  80
  81 #include <asm/byteorder.h>
  82 #include <asm/dma.h>
  83 #include <asm/io.h>
  84 #include <asm/uaccess.h>
  85
  86 #include <asm/sibyte/sb1250_regs.h>
  87 #include <asm/sibyte/sb1250_int.h>
  88 #include <asm/sibyte/sb1250_dma.h>
  89 #include <asm/sibyte/sb1250_scd.h>
  90 #include <asm/sibyte/sb1250_syncser.h>
  91 #include <asm/sibyte/sb1250_mac.h>
  92 #include <asm/sibyte/sb1250.h>
  93
  94 struct cs4297a_state;
  95
  96 static void stop_dac(struct cs4297a_state *s);
  97 static void stop_adc(struct cs4297a_state *s);
  98 static void start_dac(struct cs4297a_state *s);
  99 static void start_adc(struct cs4297a_state *s);
 100 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 101
 102 // ---------------------------------------------------------------------
 103
 104 #define CS4297a_MAGIC           0xf00beef1
 105
 106 // buffer order determines the size of the dma buffer for the driver.
 107 // under Linux, a smaller buffer allows more responsiveness from many of the
 108 // applications (e.g. games).  A larger buffer allows some of the apps (esound)
 109 // to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 110 // rather than 64k as some of the games work more responsively.
 111 // log base 2( buff sz = 32k).
 112
 113 //static unsigned long defaultorder = 3;
 114 //MODULE_PARM(defaultorder, "i");
 115
 116 //
 117 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 118 //
 119 #define CSDEBUG 0
 120 #if CSDEBUG
 121 #define CSDEBUG_INTERFACE 1
 122 #else
 123 #undef CSDEBUG_INTERFACE
 124 #endif
 125 //
 126 // cs_debugmask areas
 127 //
 128 #define CS_INIT         0x00000001      // initialization and probe functions
 129 #define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 130 #define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 131 #define CS_FUNCTION     0x00000008      // enter/leave functions
 132 #define CS_WAVE_WRITE   0x00000010      // write information for wave
 133 #define CS_WAVE_READ    0x00000020      // read information for wave
 134 #define CS_AC97         0x00000040      // AC97 register access
 135 #define CS_DESCR        0x00000080      // descriptor management
 136 #define CS_OPEN         0x00000400      // all open functions in the driver
 137 #define CS_RELEASE      0x00000800      // all release functions in the driver
 138 #define CS_PARMS        0x00001000      // functional and operational parameters
 139 #define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 140 #define CS_TMP          0x10000000      // tmp debug mask bit
 141
 142 //
 143 // CSDEBUG is usual mode is set to 1, then use the
 144 // cs_debuglevel and cs_debugmask to turn on or off debugging.
 145 // Debug level of 1 has been defined to be kernel errors and info
 146 // that should be printed on any released driver.
 147 //
 148 #if CSDEBUG
 149 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 150 #else
 151 #define CS_DBGOUT(mask,level,x)
 152 #endif
 153
 154 #if CSDEBUG
 155 static unsigned long cs_debuglevel = 4; // levels range from 1-9
 156 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
 157 module_param(cs_debuglevel, int, 0);
 158 module_param(cs_debugmask, int, 0);
 159 #endif
 160 #define CS_TRUE         1
 161 #define CS_FALSE        0
 162
 163 #define CS_TYPE_ADC 0
 164 #define CS_TYPE_DAC 1
 165
 166 #define SER_BASE    (A_SER_BASE_1 + KSEG1)
 167 #define SS_CSR(t)   (SER_BASE+t)
 168 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
 169 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
 170
 171 #define FRAME_BYTES            32
 172 #define FRAME_SAMPLE_BYTES      4
 173
 174 /* Should this be variable? */
 175 #define SAMPLE_BUF_SIZE        (16*1024)
 176 #define SAMPLE_FRAME_COUNT     (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
 177 /* The driver can explode/shrink the frames to/from a smaller sample
 178    buffer */
 179 #define DMA_BLOAT_FACTOR       1
 180 #define DMA_DESCR              (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
 181 #define DMA_BUF_SIZE           (DMA_DESCR * FRAME_BYTES)
 182
 183 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
 184 #define DMA_INT_CNT            ((1 << S_DMA_INT_PKTCNT) - 1)
 185
 186 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
 187 #define REG_LATENCY            150
 188
 189 #define FRAME_TX_US             20
 190
 191 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
 192
 193 static const char invalid_magic[] =
 194     KERN_CRIT "cs4297a: invalid magic value\n";
 195
 196 #define VALIDATE_STATE(s)                          \
 197 ({                                                 \
 198         if (!(s) || (s)->magic != CS4297a_MAGIC) { \
 199                 printk(invalid_magic);             \
 200                 return -ENXIO;                     \
 201         }                                          \
 202 })
 203
 204 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
 205
 206 typedef struct serdma_descr_s {
 207         u64 descr_a;
 208         u64 descr_b;
 209 } serdma_descr_t;
 210
 211 typedef unsigned long paddr_t;
 212
 213 typedef struct serdma_s {
 214         unsigned         ringsz;
 215         serdma_descr_t  *descrtab;
 216         serdma_descr_t  *descrtab_end;
 217         paddr_t          descrtab_phys;
 218
 219         serdma_descr_t  *descr_add;
 220         serdma_descr_t  *descr_rem;
 221
 222         u64  *dma_buf;           // buffer for DMA contents (frames)
 223         paddr_t          dma_buf_phys;
 224         u16  *sample_buf;               // tmp buffer for sample conversions
 225         u16  *sb_swptr;
 226         u16  *sb_hwptr;
 227         u16  *sb_end;
 228
 229         dma_addr_t dmaaddr;
 230 //        unsigned buforder;    // Log base 2 of 'dma_buf' size in bytes..
 231         unsigned numfrag;       // # of 'fragments' in the buffer.
 232         unsigned fragshift;     // Log base 2 of fragment size.
 233         unsigned hwptr, swptr;
 234         unsigned total_bytes;   // # bytes process since open.
 235         unsigned blocks;        // last returned blocks value GETOPTR
 236         unsigned wakeup;        // interrupt occurred on block
 237         int count;
 238         unsigned underrun;      // underrun flag
 239         unsigned error; // over/underrun
 240         wait_queue_head_t wait;
 241         wait_queue_head_t reg_wait;
 242         // redundant, but makes calculations easier
 243         unsigned fragsize;      // 2**fragshift..
 244         unsigned sbufsz;        // 2**buforder.
 245         unsigned fragsamples;
 246         // OSS stuff
 247         unsigned mapped:1;      // Buffer mapped in cs4297a_mmap()?
 248         unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 249         unsigned endcleared:1;
 250         unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 251         unsigned ossfragshift;
 252         int ossmaxfrags;
 253         unsigned subdivision;
 254 } serdma_t;
 255
 256 struct cs4297a_state {
 257         // magic
 258         unsigned int magic;
 259
 260         struct list_head list;
 261
 262         // soundcore stuff
 263         int dev_audio;
 264         int dev_mixer;
 265
 266         // hardware resources
 267         unsigned int irq;
 268
 269         struct {
 270                 unsigned int rx_ovrrn; /* FIFO */
 271                 unsigned int rx_overflow; /* staging buffer */
 272                 unsigned int tx_underrun;
 273                 unsigned int rx_bad;
 274                 unsigned int rx_good;
 275         } stats;
 276
 277         // mixer registers
 278         struct {
 279                 unsigned short vol[10];
 280                 unsigned int recsrc;
 281                 unsigned int modcnt;
 282                 unsigned short micpreamp;
 283         } mix;
 284
 285         // wave stuff
 286         struct properties {
 287                 unsigned fmt;
 288                 unsigned fmt_original;  // original requested format
 289                 unsigned channels;
 290                 unsigned rate;
 291         } prop_dac, prop_adc;
 292         unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 293         unsigned ena;
 294         spinlock_t lock;
 295         struct mutex open_mutex;
 296         struct mutex open_sem_adc;
 297         struct mutex open_sem_dac;
 298         mode_t open_mode;
 299         wait_queue_head_t open_wait;
 300         wait_queue_head_t open_wait_adc;
 301         wait_queue_head_t open_wait_dac;
 302
 303         dma_addr_t dmaaddr_sample_buf;
 304         unsigned buforder_sample_buf;   // Log base 2 of 'dma_buf' size in bytes..
 305
 306         serdma_t dma_dac, dma_adc;
 307
 308         volatile u16 read_value;
 309         volatile u16 read_reg;
 310         volatile u64 reg_request;
 311 };
 312
 313 #if 1
 314 #define prog_codec(a,b)
 315 #define dealloc_dmabuf(a,b);
 316 #endif
 317
 318 static int prog_dmabuf_adc(struct cs4297a_state *s)
 319 {
 320         s->dma_adc.ready = 1;
 321         return 0;
 322 }
 323
 324
 325 static int prog_dmabuf_dac(struct cs4297a_state *s)
 326 {
 327         s->dma_dac.ready = 1;
 328         return 0;
 329 }
 330
 331 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
 332                           unsigned len, unsigned char c)
 333 {
 334         if (bptr + len > bsize) {
 335                 unsigned x = bsize - bptr;
 336                 memset(((char *) buf) + bptr, c, x);
 337                 bptr = 0;
 338                 len -= x;
 339         }
 340         CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
 341                 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
 342                         (unsigned)c, (unsigned)((char *) buf) + bptr, len));
 343         memset(((char *) buf) + bptr, c, len);
 344 }
 345
 346 #if CSDEBUG
 347
 348 // DEBUG ROUTINES
 349
 350 #define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 351 #define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 352 #define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 353 #define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 354
 355 static void cs_printioctl(unsigned int x)
 356 {
 357         unsigned int i;
 358         unsigned char vidx;
 359         // Index of mixtable1[] member is Device ID
 360         // and must be <= SOUND_MIXER_NRDEVICES.
 361         // Value of array member is index into s->mix.vol[]
 362         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 363                 [SOUND_MIXER_PCM] = 1,  // voice
 364                 [SOUND_MIXER_LINE1] = 2,        // AUX
 365                 [SOUND_MIXER_CD] = 3,   // CD
 366                 [SOUND_MIXER_LINE] = 4, // Line
 367                 [SOUND_MIXER_SYNTH] = 5,        // FM
 368                 [SOUND_MIXER_MIC] = 6,  // Mic
 369                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
 370                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
 371                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
 372         };
 373
 374         switch (x) {
 375         case SOUND_MIXER_CS_GETDBGMASK:
 376                 CS_DBGOUT(CS_IOCTL, 4,
 377                           printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 378                 break;
 379         case SOUND_MIXER_CS_GETDBGLEVEL:
 380                 CS_DBGOUT(CS_IOCTL, 4,
 381                           printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 382                 break;
 383         case SOUND_MIXER_CS_SETDBGMASK:
 384                 CS_DBGOUT(CS_IOCTL, 4,
 385                           printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 386                 break;
 387         case SOUND_MIXER_CS_SETDBGLEVEL:
 388                 CS_DBGOUT(CS_IOCTL, 4,
 389                           printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 390                 break;
 391         case OSS_GETVERSION:
 392                 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 393                 break;
 394         case SNDCTL_DSP_SYNC:
 395                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 396                 break;
 397         case SNDCTL_DSP_SETDUPLEX:
 398                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 399                 break;
 400         case SNDCTL_DSP_GETCAPS:
 401                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 402                 break;
 403         case SNDCTL_DSP_RESET:
 404                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 405                 break;
 406         case SNDCTL_DSP_SPEED:
 407                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 408                 break;
 409         case SNDCTL_DSP_STEREO:
 410                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 411                 break;
 412         case SNDCTL_DSP_CHANNELS:
 413                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 414                 break;
 415         case SNDCTL_DSP_GETFMTS:
 416                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 417                 break;
 418         case SNDCTL_DSP_SETFMT:
 419                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 420                 break;
 421         case SNDCTL_DSP_POST:
 422                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 423                 break;
 424         case SNDCTL_DSP_GETTRIGGER:
 425                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 426                 break;
 427         case SNDCTL_DSP_SETTRIGGER:
 428                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 429                 break;
 430         case SNDCTL_DSP_GETOSPACE:
 431                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 432                 break;
 433         case SNDCTL_DSP_GETISPACE:
 434                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 435                 break;
 436         case SNDCTL_DSP_NONBLOCK:
 437                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 438                 break;
 439         case SNDCTL_DSP_GETODELAY:
 440                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 441                 break;
 442         case SNDCTL_DSP_GETIPTR:
 443                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 444                 break;
 445         case SNDCTL_DSP_GETOPTR:
 446                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 447                 break;
 448         case SNDCTL_DSP_GETBLKSIZE:
 449                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 450                 break;
 451         case SNDCTL_DSP_SETFRAGMENT:
 452                 CS_DBGOUT(CS_IOCTL, 4,
 453                           printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 454                 break;
 455         case SNDCTL_DSP_SUBDIVIDE:
 456                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 457                 break;
 458         case SOUND_PCM_READ_RATE:
 459                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 460                 break;
 461         case SOUND_PCM_READ_CHANNELS:
 462                 CS_DBGOUT(CS_IOCTL, 4,
 463                           printk("SOUND_PCM_READ_CHANNELS:\n"));
 464                 break;
 465         case SOUND_PCM_READ_BITS:
 466                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 467                 break;
 468         case SOUND_PCM_WRITE_FILTER:
 469                 CS_DBGOUT(CS_IOCTL, 4,
 470                           printk("SOUND_PCM_WRITE_FILTER:\n"));
 471                 break;
 472         case SNDCTL_DSP_SETSYNCRO:
 473                 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 474                 break;
 475         case SOUND_PCM_READ_FILTER:
 476                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 477                 break;
 478         case SOUND_MIXER_PRIVATE1:
 479                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 480                 break;
 481         case SOUND_MIXER_PRIVATE2:
 482                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 483                 break;
 484         case SOUND_MIXER_PRIVATE3:
 485                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 486                 break;
 487         case SOUND_MIXER_PRIVATE4:
 488                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 489                 break;
 490         case SOUND_MIXER_PRIVATE5:
 491                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 492                 break;
 493         case SOUND_MIXER_INFO:
 494                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 495                 break;
 496         case SOUND_OLD_MIXER_INFO:
 497                 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 498                 break;
 499
 500         default:
 501                 switch (_IOC_NR(x)) {
 502                 case SOUND_MIXER_VOLUME:
 503                         CS_DBGOUT(CS_IOCTL, 4,
 504                                   printk("SOUND_MIXER_VOLUME:\n"));
 505                         break;
 506                 case SOUND_MIXER_SPEAKER:
 507                         CS_DBGOUT(CS_IOCTL, 4,
 508                                   printk("SOUND_MIXER_SPEAKER:\n"));
 509                         break;
 510                 case SOUND_MIXER_RECLEV:
 511                         CS_DBGOUT(CS_IOCTL, 4,
 512                                   printk("SOUND_MIXER_RECLEV:\n"));
 513                         break;
 514                 case SOUND_MIXER_MIC:
 515                         CS_DBGOUT(CS_IOCTL, 4,
 516                                   printk("SOUND_MIXER_MIC:\n"));
 517                         break;
 518                 case SOUND_MIXER_SYNTH:
 519                         CS_DBGOUT(CS_IOCTL, 4,
 520                                   printk("SOUND_MIXER_SYNTH:\n"));
 521                         break;
 522                 case SOUND_MIXER_RECSRC:
 523                         CS_DBGOUT(CS_IOCTL, 4,
 524                                   printk("SOUND_MIXER_RECSRC:\n"));
 525                         break;
 526                 case SOUND_MIXER_DEVMASK:
 527                         CS_DBGOUT(CS_IOCTL, 4,
 528                                   printk("SOUND_MIXER_DEVMASK:\n"));
 529                         break;
 530                 case SOUND_MIXER_RECMASK:
 531                         CS_DBGOUT(CS_IOCTL, 4,
 532                                   printk("SOUND_MIXER_RECMASK:\n"));
 533                         break;
 534                 case SOUND_MIXER_STEREODEVS:
 535                         CS_DBGOUT(CS_IOCTL, 4,
 536                                   printk("SOUND_MIXER_STEREODEVS:\n"));
 537                         break;
 538                 case SOUND_MIXER_CAPS:
 539                         CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 540                         break;
 541                 default:
 542                         i = _IOC_NR(x);
 543                         if (i >= SOUND_MIXER_NRDEVICES
 544                             || !(vidx = mixtable1[i])) {
 545                                 CS_DBGOUT(CS_IOCTL, 4, printk
 546                                         ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 547                                                 x, i));
 548                         } else {
 549                                 CS_DBGOUT(CS_IOCTL, 4, printk
 550                                         ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 551                                                 x, i));
 552                         }
 553                         break;
 554                 }
 555         }
 556 }
 557 #endif
 558
 559
 560 static int ser_init(struct cs4297a_state *s)
 561 {
 562         int i;
 563
 564         CS_DBGOUT(CS_INIT, 2,
 565                   printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
 566
 567         __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
 568
 569         __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
 570         __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
 571         __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
 572
 573         __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
 574         __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
 575         __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
 576
 577         /* This looks good from experimentation */
 578         __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
 579                M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
 580               SS_CSR(R_SER_LINE_MODE));
 581
 582         /* This looks good from experimentation */
 583         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 584               SS_TXTBL(0));
 585         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 586               SS_TXTBL(1));
 587         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 588               SS_TXTBL(2));
 589         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
 590               M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
 591
 592         __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 593               SS_RXTBL(0));
 594         __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 595               SS_RXTBL(1));
 596         __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 597               SS_RXTBL(2));
 598         __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
 599               M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
 600
 601         for (i=4; i<16; i++) {
 602                 /* Just in case... */
 603                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
 604                 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int init_serdma(serdma_t *dma)
 611 {
 612         CS_DBGOUT(CS_INIT, 2,
 613                   printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
 614                          DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
 615
 616         /* Descriptors */
 617         dma->ringsz = DMA_DESCR;
 618         dma->descrtab = kmalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
 619         if (!dma->descrtab) {
 620                 printk(KERN_ERR "cs4297a: kmalloc descrtab failed\n");
 621                 return -1;
 622         }
 623         memset(dma->descrtab, 0, dma->ringsz * sizeof(serdma_descr_t));
 624         dma->descrtab_end = dma->descrtab + dma->ringsz;
 625         /* XXX bloddy mess, use proper DMA API here ...  */
 626         dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
 627         dma->descr_add = dma->descr_rem = dma->descrtab;
 628
 629         /* Frame buffer area */
 630         dma->dma_buf = kmalloc(DMA_BUF_SIZE, GFP_KERNEL);
 631         if (!dma->dma_buf) {
 632                 printk(KERN_ERR "cs4297a: kmalloc dma_buf failed\n");
 633                 kfree(dma->descrtab);
 634                 return -1;
 635         }
 636         memset(dma->dma_buf, 0, DMA_BUF_SIZE);
 637         dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
 638
 639         /* Samples buffer area */
 640         dma->sbufsz = SAMPLE_BUF_SIZE;
 641         dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
 642         if (!dma->sample_buf) {
 643                 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
 644                 kfree(dma->descrtab);
 645                 kfree(dma->dma_buf);
 646                 return -1;
 647         }
 648         dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
 649         dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
 650         dma->fragsize = dma->sbufsz >> 1;
 651
 652         CS_DBGOUT(CS_INIT, 4,
 653                   printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
 654                          (int)dma->descrtab, (int)dma->dma_buf,
 655                          (int)dma->sample_buf));
 656
 657         return 0;
 658 }
 659
 660 static int dma_init(struct cs4297a_state *s)
 661 {
 662         int i;
 663
 664         CS_DBGOUT(CS_INIT, 2,
 665                   printk(KERN_INFO "cs4297a: Setting up DMA\n"));
 666
 667         if (init_serdma(&s->dma_adc) ||
 668             init_serdma(&s->dma_dac))
 669                 return -1;
 670
 671         if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
 672             __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
 673                 panic("DMA state corrupted?!");
 674         }
 675
 676         /* Initialize now - the descr/buffer pairings will never
 677            change... */
 678         for (i=0; i<DMA_DESCR; i++) {
 679                 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
 680                         (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
 681                 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
 682                 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
 683                         (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
 684                 s->dma_adc.descrtab[i].descr_b = 0;
 685         }
 686
 687         __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
 688                V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
 689               SS_CSR(R_SER_DMA_CONFIG0_RX));
 690         __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
 691         __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
 692
 693         __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
 694         __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
 695         __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
 696
 697         /* Prep the receive DMA descriptor ring */
 698         __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 699
 700         __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
 701
 702         __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
 703               SS_CSR(R_SER_INT_MASK));
 704
 705         /* Enable the rx/tx; let the codec warm up to the sync and
 706            start sending good frames before the receive FIFO is
 707            enabled */
 708         __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 709         udelay(1000);
 710         __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 711
 712         /* XXXKW is this magic? (the "1" part) */
 713         while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
 714                 ;
 715
 716         CS_DBGOUT(CS_INIT, 4,
 717                   printk(KERN_INFO "cs4297a: status: %08x\n",
 718                          (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
 719
 720         return 0;
 721 }
 722
 723 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
 724 {
 725         serdma_t *d = &s->dma_dac;
 726         u64 *data_p;
 727         unsigned swptr;
 728         int flags;
 729         serdma_descr_t *descr;
 730
 731         if (s->reg_request) {
 732                 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
 733                 return -1;
 734         }
 735
 736         if (s->ena & FMODE_WRITE) {
 737                 /* Since a writer has the DSP open, we have to mux the
 738                    request in */
 739                 s->reg_request = data;
 740                 interruptible_sleep_on(&s->dma_dac.reg_wait);
 741                 /* XXXKW how can I deal with the starvation case where
 742                    the opener isn't writing? */
 743         } else {
 744                 /* Be safe when changing ring pointers */
 745                 spin_lock_irqsave(&s->lock, flags);
 746                 if (d->hwptr != d->swptr) {
 747                         printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
 748                                d->hwptr, d->swptr);
 749                         spin_unlock_irqrestore(&s->lock, flags);
 750                         return -1;
 751                 }
 752                 swptr = d->swptr;
 753                 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
 754                 spin_unlock_irqrestore(&s->lock, flags);
 755
 756                 descr = &d->descrtab[swptr];
 757                 data_p = &d->dma_buf[swptr * 4];
 758                 *data_p = cpu_to_be64(data);
 759                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
 760                 CS_DBGOUT(CS_DESCR, 4,
 761                           printk(KERN_INFO "cs4297a: add_tx  %p (%x -> %x)\n",
 762                                  data_p, swptr, d->hwptr));
 763         }
 764
 765         CS_DBGOUT(CS_FUNCTION, 6,
 766                   printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
 767
 768         return 0;
 769 }
 770
 771 //****************************************************************************
 772 // "cs4297a_read_ac97" -- Reads an AC97 register
 773 //****************************************************************************
 774 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
 775                             u32 * value)
 776 {
 777         CS_DBGOUT(CS_AC97, 1,
 778                   printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
 779         if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
 780                 return -1;
 781
 782         interruptible_sleep_on(&s->dma_adc.reg_wait);
 783         *value = s->read_value;
 784         CS_DBGOUT(CS_AC97, 2,
 785                   printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
 786
 787         return 0;
 788 }
 789
 790
 791 //****************************************************************************
 792 // "cs4297a_write_ac97()"-- writes an AC97 register
 793 //****************************************************************************
 794 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
 795                              u32 value)
 796 {
 797         CS_DBGOUT(CS_AC97, 1,
 798                   printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
 799         return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
 800 }
 801
 802 static void stop_dac(struct cs4297a_state *s)
 803 {
 804         unsigned long flags;
 805
 806         CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
 807         spin_lock_irqsave(&s->lock, flags);
 808         s->ena &= ~FMODE_WRITE;
 809 #if 0
 810         /* XXXKW what do I really want here?  My theory for now is
 811            that I just flip the "ena" bit, and the interrupt handler
 812            will stop processing the xmit channel */
 813         __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
 814               SS_CSR(R_SER_DMA_ENABLE));
 815 #endif
 816
 817         spin_unlock_irqrestore(&s->lock, flags);
 818 }
 819
 820
 821 static void start_dac(struct cs4297a_state *s)
 822 {
 823         unsigned long flags;
 824
 825         CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
 826         spin_lock_irqsave(&s->lock, flags);
 827         if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
 828                                         (s->dma_dac.count > 0
 829                                         && s->dma_dac.ready))) {
 830                 s->ena |= FMODE_WRITE;
 831                 /* XXXKW what do I really want here?  My theory for
 832                    now is that I just flip the "ena" bit, and the
 833                    interrupt handler will start processing the xmit
 834                    channel */
 835
 836                 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
 837                         "cs4297a: start_dac(): start dma\n"));
 838
 839         }
 840         spin_unlock_irqrestore(&s->lock, flags);
 841         CS_DBGOUT(CS_FUNCTION, 3,
 842                   printk(KERN_INFO "cs4297a: start_dac()-\n"));
 843 }
 844
 845
 846 static void stop_adc(struct cs4297a_state *s)
 847 {
 848         unsigned long flags;
 849
 850         CS_DBGOUT(CS_FUNCTION, 3,
 851                   printk(KERN_INFO "cs4297a: stop_adc()+\n"));
 852
 853         spin_lock_irqsave(&s->lock, flags);
 854         s->ena &= ~FMODE_READ;
 855
 856         if (s->conversion == 1) {
 857                 s->conversion = 0;
 858                 s->prop_adc.fmt = s->prop_adc.fmt_original;
 859         }
 860         /* Nothing to do really, I need to keep the DMA going
 861            XXXKW when do I get here, and is there more I should do? */
 862         spin_unlock_irqrestore(&s->lock, flags);
 863         CS_DBGOUT(CS_FUNCTION, 3,
 864                   printk(KERN_INFO "cs4297a: stop_adc()-\n"));
 865 }
 866
 867
 868 static void start_adc(struct cs4297a_state *s)
 869 {
 870         unsigned long flags;
 871
 872         CS_DBGOUT(CS_FUNCTION, 2,
 873                   printk(KERN_INFO "cs4297a: start_adc()+\n"));
 874
 875         if (!(s->ena & FMODE_READ) &&
 876             (s->dma_adc.mapped || s->dma_adc.count <=
 877              (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
 878             && s->dma_adc.ready) {
 879                 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
 880                         //
 881                         // now only use 16 bit capture, due to truncation issue
 882                         // in the chip, noticable distortion occurs.
 883                         // allocate buffer and then convert from 16 bit to
 884                         // 8 bit for the user buffer.
 885                         //
 886                         s->prop_adc.fmt_original = s->prop_adc.fmt;
 887                         if (s->prop_adc.fmt & AFMT_S8) {
 888                                 s->prop_adc.fmt &= ~AFMT_S8;
 889                                 s->prop_adc.fmt |= AFMT_S16_LE;
 890                         }
 891                         if (s->prop_adc.fmt & AFMT_U8) {
 892                                 s->prop_adc.fmt &= ~AFMT_U8;
 893                                 s->prop_adc.fmt |= AFMT_U16_LE;
 894                         }
 895                         //
 896                         // prog_dmabuf_adc performs a stop_adc() but that is
 897                         // ok since we really haven't started the DMA yet.
 898                         //
 899                         prog_codec(s, CS_TYPE_ADC);
 900
 901                         prog_dmabuf_adc(s);
 902                         s->conversion = 1;
 903                 }
 904                 spin_lock_irqsave(&s->lock, flags);
 905                 s->ena |= FMODE_READ;
 906                 /* Nothing to do really, I am probably already
 907                    DMAing...  XXXKW when do I get here, and is there
 908                    more I should do? */
 909                 spin_unlock_irqrestore(&s->lock, flags);
 910
 911                 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
 912                          "cs4297a: start_adc(): start adc\n"));
 913         }
 914         CS_DBGOUT(CS_FUNCTION, 2,
 915                   printk(KERN_INFO "cs4297a: start_adc()-\n"));
 916
 917 }
 918
 919
 920 // call with spinlock held!
 921 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
 922 {
 923         int good_diff, diff, diff2;
 924         u64 *data_p, data;
 925         u32 *s_ptr;
 926         unsigned hwptr;
 927         u32 status;
 928         serdma_t *d;
 929         serdma_descr_t *descr;
 930
 931         // update ADC pointer
 932         status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
 933
 934         if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
 935                 d = &s->dma_adc;
 936                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
 937                                      d->descrtab_phys) / sizeof(serdma_descr_t));
 938
 939                 if (s->ena & FMODE_READ) {
 940                         CS_DBGOUT(CS_FUNCTION, 2,
 941                                   printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
 942                                          d->swptr, d->hwptr, hwptr, intflag));
 943                         /* Number of DMA buffers available for software: */
 944                         diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
 945                         d->hwptr = hwptr;
 946                         good_diff = 0;
 947                         s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
 948                         descr = &d->descrtab[d->swptr];
 949                         while (diff2--) {
 950                                 u64 data = be64_to_cpu(*(u64 *)s_ptr);
 951                                 u64 descr_a;
 952                                 u16 left, right;
 953                                 descr_a = descr->descr_a;
 954                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
 955                                 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
 956                                         printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
 957                                 }
 958                                 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
 959                                     (!(descr_a & M_DMA_SERRX_SOP)) ||
 960                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
 961                                         s->stats.rx_bad++;
 962                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
 963                                         continue;
 964                                 }
 965                                 s->stats.rx_good++;
 966                                 if ((data >> 61) == 7) {
 967                                         s->read_value = (data >> 12) & 0xffff;
 968                                         s->read_reg = (data >> 40) & 0x7f;
 969                                         wake_up(&d->reg_wait);
 970                                 }
 971                                 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
 972                                         s->stats.rx_overflow++;
 973                                         printk(KERN_DEBUG "cs4297a: RX overflow\n");
 974                                         continue;
 975                                 }
 976                                 good_diff++;
 977                                 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
 978                                        ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
 979                                 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
 980                                 *d->sb_hwptr++ = cpu_to_be16(left);
 981                                 *d->sb_hwptr++ = cpu_to_be16(right);
 982                                 if (d->sb_hwptr == d->sb_end)
 983                                         d->sb_hwptr = d->sample_buf;
 984                                 descr++;
 985                                 if (descr == d->descrtab_end) {
 986                                         descr = d->descrtab;
 987                                         s_ptr = (u32 *)s->dma_adc.dma_buf;
 988                                 } else {
 989                                         s_ptr += 8;
 990                                 }
 991                         }
 992                         d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
 993                         d->count += good_diff * FRAME_SAMPLE_BYTES;
 994                         if (d->count > d->sbufsz) {
 995                                 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
 996                         }
 997                         d->swptr = (d->swptr + diff) % d->ringsz;
 998                         __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 999                         if (d->mapped) {
1000                                 if (d->count >= (signed) d->fragsize)
1001                                         wake_up(&d->wait);
1002                         } else {
1003                                 if (d->count > 0) {
1004                                         CS_DBGOUT(CS_WAVE_READ, 4,
1005                                                   printk(KERN_INFO
1006                                                          "cs4297a: update count -> %d\n", d->count));
1007                                         wake_up(&d->wait);
1008                                 }
1009                         }
1010                 } else {
1011                         /* Receive is going even if no one is
1012                            listening (for register accesses and to
1013                            avoid FIFO overrun) */
1014                         diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1015                         if (!diff) {
1016                                 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1017                         }
1018
1019                         descr = &d->descrtab[d->swptr];
1020                         data_p = &d->dma_buf[d->swptr*4];
1021
1022                         /* Force this to happen at least once; I got
1023                            here because of an interrupt, so there must
1024                            be a buffer to process. */
1025                         do {
1026                                 data = be64_to_cpu(*data_p);
1027                                 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1028                                         printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1029                                                (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1030                                                (long)CPHYSADDR((long)data_p));
1031                                 }
1032                                 if (!(data & (1LL << 63)) ||
1033                                     !(descr->descr_a & M_DMA_SERRX_SOP) ||
1034                                     (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1035                                         s->stats.rx_bad++;
1036                                         printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1037                                 } else {
1038                                         s->stats.rx_good++;
1039                                         if ((data >> 61) == 7) {
1040                                                 s->read_value = (data >> 12) & 0xffff;
1041                                                 s->read_reg = (data >> 40) & 0x7f;
1042                                                 wake_up(&d->reg_wait);
1043                                         }
1044                                 }
1045                                 descr->descr_a &= ~M_DMA_SERRX_SOP;
1046                                 descr++;
1047                                 d->swptr++;
1048                                 data_p += 4;
1049                                 if (descr == d->descrtab_end) {
1050                                         descr = d->descrtab;
1051                                         d->swptr = 0;
1052                                         data_p = d->dma_buf;
1053                                 }
1054                                 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1055                         } while (--diff);
1056                         d->hwptr = hwptr;
1057
1058                         CS_DBGOUT(CS_DESCR, 6,
1059                                   printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1060                 }
1061
1062                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1063                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1064                                 (unsigned)s, d->hwptr,
1065                                 d->total_bytes, d->count));
1066         }
1067
1068         /* XXXKW worry about s->reg_request -- there is a starvation
1069            case if s->ena has FMODE_WRITE on, but the client isn't
1070            doing writes */
1071
1072         // update DAC pointer
1073         //
1074         // check for end of buffer, means that we are going to wait for another interrupt
1075         // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1076         //
1077         if (s->ena & FMODE_WRITE) {
1078                 serdma_t *d = &s->dma_dac;
1079                 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1080                                      d->descrtab_phys) / sizeof(serdma_descr_t));
1081                 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1082                 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1083                                                    "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1084                                                    d->hwptr, hwptr, d->swptr, diff, d->count));
1085                 d->hwptr = hwptr;
1086                 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1087                 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1088                 if (d->mapped) {
1089                         d->count += diff * FRAME_SAMPLE_BYTES;
1090                         if (d->count >= d->fragsize) {
1091                                 d->wakeup = 1;
1092                                 wake_up(&d->wait);
1093                                 if (d->count > d->sbufsz)
1094                                         d->count &= d->sbufsz - 1;
1095                         }
1096                 } else {
1097                         d->count -= diff * FRAME_SAMPLE_BYTES;
1098                         if (d->count <= 0) {
1099                                 //
1100                                 // fill with silence, and do not shut down the DAC.
1101                                 // Continue to play silence until the _release.
1102                                 //
1103                                 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1104                                         "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1105                                                 (unsigned)(s->prop_dac.fmt &
1106                                                 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1107                                                 (unsigned)d->dma_buf,
1108                                                 d->ringsz));
1109                                 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1110                                 if (d->count < 0) {
1111                                         d->underrun = 1;
1112                                         s->stats.tx_underrun++;
1113                                         d->count = 0;
1114                                         CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1115                                          "cs4297a: cs4297a_update_ptr(): underrun\n"));
1116                                 }
1117                         } else if (d->count <=
1118                                    (signed) d->fragsize
1119                                    && !d->endcleared) {
1120                           /* XXXKW what is this for? */
1121                                 clear_advance(d->dma_buf,
1122                                               d->sbufsz,
1123                                               d->swptr,
1124                                               d->fragsize,
1125                                               0);
1126                                 d->endcleared = 1;
1127                         }
1128                         if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1129                         {
1130                                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1131                                           printk(KERN_INFO
1132                                                  "cs4297a: update count -> %d\n", d->count));
1133                                 wake_up(&d->wait);
1134                         }
1135                 }
1136                 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1137                         "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1138                                 (unsigned) s, d->hwptr,
1139                                 d->total_bytes, d->count));
1140         }
1141 }
1142
1143 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1144                        unsigned long arg)
1145 {
1146         // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1147         // Value of array member is recording source Device ID Mask.
1148         static const unsigned int mixer_src[8] = {
1149                 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1150                 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1151         };
1152
1153         // Index of mixtable1[] member is Device ID
1154         // and must be <= SOUND_MIXER_NRDEVICES.
1155         // Value of array member is index into s->mix.vol[]
1156         static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1157                 [SOUND_MIXER_PCM] = 1,  // voice
1158                 [SOUND_MIXER_LINE1] = 2,        // AUX
1159                 [SOUND_MIXER_CD] = 3,   // CD
1160                 [SOUND_MIXER_LINE] = 4, // Line
1161                 [SOUND_MIXER_SYNTH] = 5,        // FM
1162                 [SOUND_MIXER_MIC] = 6,  // Mic
1163                 [SOUND_MIXER_SPEAKER] = 7,      // Speaker
1164                 [SOUND_MIXER_RECLEV] = 8,       // Recording level
1165                 [SOUND_MIXER_VOLUME] = 9        // Master Volume
1166         };
1167
1168         static const unsigned mixreg[] = {
1169                 AC97_PCMOUT_VOL,
1170                 AC97_AUX_VOL,
1171                 AC97_CD_VOL,
1172                 AC97_LINEIN_VOL
1173         };
1174         unsigned char l, r, rl, rr, vidx;
1175         unsigned char attentbl[11] =
1176             { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1177         unsigned temp1;
1178         int i, val;
1179
1180         VALIDATE_STATE(s);
1181         CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1182                  "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1183                          (unsigned) s, cmd));
1184 #if CSDEBUG
1185         cs_printioctl(cmd);
1186 #endif
1187 #if CSDEBUG_INTERFACE
1188
1189         if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1190             (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1191             (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1192             (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1193         {
1194                 switch (cmd) {
1195
1196                 case SOUND_MIXER_CS_GETDBGMASK:
1197                         return put_user(cs_debugmask,
1198                                         (unsigned long *) arg);
1199
1200                 case SOUND_MIXER_CS_GETDBGLEVEL:
1201                         return put_user(cs_debuglevel,
1202                                         (unsigned long *) arg);
1203
1204                 case SOUND_MIXER_CS_SETDBGMASK:
1205                         if (get_user(val, (unsigned long *) arg))
1206                                 return -EFAULT;
1207                         cs_debugmask = val;
1208                         return 0;
1209
1210                 case SOUND_MIXER_CS_SETDBGLEVEL:
1211                         if (get_user(val, (unsigned long *) arg))
1212                                 return -EFAULT;
1213                         cs_debuglevel = val;
1214                         return 0;
1215                 default:
1216                         CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1217                                 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1218                         return 0;
1219                 }
1220         }
1221 #endif
1222
1223         if (cmd == SOUND_MIXER_PRIVATE1) {
1224                 return -EINVAL;
1225         }
1226         if (cmd == SOUND_MIXER_PRIVATE2) {
1227                 // enable/disable/query spatializer
1228                 if (get_user(val, (int *) arg))
1229                         return -EFAULT;
1230                 if (val != -1) {
1231                         temp1 = (val & 0x3f) >> 2;
1232                         cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1233                         cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1234                                          &temp1);
1235                         cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1236                                           temp1 | 0x2000);
1237                 }
1238                 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1239                 return put_user((temp1 << 2) | 3, (int *) arg);
1240         }
1241         if (cmd == SOUND_MIXER_INFO) {
1242                 mixer_info info;
1243                 memset(&info, 0, sizeof(info));
1244                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1245                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1246                 info.modify_counter = s->mix.modcnt;
1247                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1248                         return -EFAULT;
1249                 return 0;
1250         }
1251         if (cmd == SOUND_OLD_MIXER_INFO) {
1252                 _old_mixer_info info;
1253                 memset(&info, 0, sizeof(info));
1254                 strlcpy(info.id, "CS4297a", sizeof(info.id));
1255                 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1256                 if (copy_to_user((void *) arg, &info, sizeof(info)))
1257                         return -EFAULT;
1258                 return 0;
1259         }
1260         if (cmd == OSS_GETVERSION)
1261                 return put_user(SOUND_VERSION, (int *) arg);
1262
1263         if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1264                 return -EINVAL;
1265
1266         // If ioctl has only the SIOC_READ bit(bit 31)
1267         // on, process the only-read commands.
1268         if (_SIOC_DIR(cmd) == _SIOC_READ) {
1269                 switch (_IOC_NR(cmd)) {
1270                 case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1271                         cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1272                                          &temp1);
1273                         return put_user(mixer_src[temp1 & 7], (int *) arg);
1274
1275                 case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device
1276                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1277                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1278                                         (int *) arg);
1279
1280                 case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source
1281                         return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1282                                         (int *) arg);
1283
1284                 case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo
1285                         return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1286                                         SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1287                                         (int *) arg);
1288
1289                 case SOUND_MIXER_CAPS:
1290                         return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1291
1292                 default:
1293                         i = _IOC_NR(cmd);
1294                         if (i >= SOUND_MIXER_NRDEVICES
1295                             || !(vidx = mixtable1[i]))
1296                                 return -EINVAL;
1297                         return put_user(s->mix.vol[vidx - 1], (int *) arg);
1298                 }
1299         }
1300         // If ioctl doesn't have both the SIOC_READ and
1301         // the SIOC_WRITE bit set, return invalid.
1302         if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1303                 return -EINVAL;
1304
1305         // Increment the count of volume writes.
1306         s->mix.modcnt++;
1307
1308         // Isolate the command; it must be a write.
1309         switch (_IOC_NR(cmd)) {
1310
1311         case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source
1312                 if (get_user(val, (int *) arg))
1313                         return -EFAULT;
1314                 i = hweight32(val);     // i = # bits on in val.
1315                 if (i != 1)     // One & only 1 bit must be on.
1316                         return 0;
1317                 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1318                         if (val == mixer_src[i]) {
1319                                 temp1 = (i << 8) | i;
1320                                 cs4297a_write_ac97(s,
1321                                                   AC97_RECORD_SELECT,
1322                                                   temp1);
1323                                 return 0;
1324                         }
1325                 }
1326                 return 0;
1327
1328         case SOUND_MIXER_VOLUME:
1329                 if (get_user(val, (int *) arg))
1330                         return -EFAULT;
1331                 l = val & 0xff;
1332                 if (l > 100)
1333                         l = 100;        // Max soundcard.h vol is 100.
1334                 if (l < 6) {
1335                         rl = 63;
1336                         l = 0;
1337                 } else
1338                         rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
1339
1340                 r = (val >> 8) & 0xff;
1341                 if (r > 100)
1342                         r = 100;        // Max right volume is 100, too
1343                 if (r < 6) {
1344                         rr = 63;
1345                         r = 0;
1346                 } else
1347                         rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
1348
1349                 if ((rl > 60) && (rr > 60))     // If both l & r are 'low',
1350                         temp1 = 0x8000; //  turn on the mute bit.
1351                 else
1352                         temp1 = 0;
1353
1354                 temp1 |= (rl << 8) | rr;
1355
1356                 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1357                 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1358
1359 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1360                 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1361 #else
1362                 s->mix.vol[8] = val;
1363 #endif
1364                 return put_user(s->mix.vol[8], (int *) arg);
1365
1366         case SOUND_MIXER_SPEAKER:
1367                 if (get_user(val, (int *) arg))
1368                         return -EFAULT;
1369                 l = val & 0xff;
1370                 if (l > 100)
1371                         l = 100;
1372                 if (l < 3) {
1373                         rl = 0;
1374                         l = 0;
1375                 } else {
1376                         rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
1377                         l = (rl * 13 + 5) / 2;
1378                 }
1379
1380                 if (rl < 3) {
1381                         temp1 = 0x8000;
1382                         rl = 0;
1383                 } else
1384                         temp1 = 0;
1385                 rl = 15 - rl;   // Convert volume to attenuation.
1386                 temp1 |= rl << 1;
1387                 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1388
1389 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1390                 s->mix.vol[6] = l << 8;
1391 #else
1392                 s->mix.vol[6] = val;
1393 #endif
1394                 return put_user(s->mix.vol[6], (int *) arg);
1395
1396         case SOUND_MIXER_RECLEV:
1397                 if (get_user(val, (int *) arg))
1398                         return -EFAULT;
1399                 l = val & 0xff;
1400                 if (l > 100)
1401                         l = 100;
1402                 r = (val >> 8) & 0xff;
1403                 if (r > 100)
1404                         r = 100;
1405                 rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
1406                 rr = (r * 2 - 5) / 13;
1407                 if (rl < 3 && rr < 3)
1408                         temp1 = 0x8000;
1409                 else
1410                         temp1 = 0;
1411
1412                 temp1 = temp1 | (rl << 8) | rr;
1413                 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1414
1415 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1416                 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1417 #else
1418                 s->mix.vol[7] = val;
1419 #endif
1420                 return put_user(s->mix.vol[7], (int *) arg);
1421
1422         case SOUND_MIXER_MIC:
1423                 if (get_user(val, (int *) arg))
1424                         return -EFAULT;
1425                 l = val & 0xff;
1426                 if (l > 100)
1427                         l = 100;
1428                 if (l < 1) {
1429                         l = 0;
1430                         rl = 0;
1431                 } else {
1432                         rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
1433                         l = (rl * 16 + 4) / 5;
1434                 }
1435                 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1436                 temp1 &= 0x40;  // Isolate 20db gain bit.
1437                 if (rl < 3) {
1438                         temp1 |= 0x8000;
1439                         rl = 0;
1440                 }
1441                 rl = 31 - rl;   // Convert volume to attenuation.
1442                 temp1 |= rl;
1443                 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1444
1445 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1446                 s->mix.vol[5] = val << 8;
1447 #else
1448                 s->mix.vol[5] = val;
1449 #endif
1450                 return put_user(s->mix.vol[5], (int *) arg);
1451
1452
1453         case SOUND_MIXER_SYNTH:
1454                 if (get_user(val, (int *) arg))
1455                         return -EFAULT;
1456                 l = val & 0xff;
1457                 if (l > 100)
1458                         l = 100;
1459                 if (get_user(val, (int *) arg))
1460                         return -EFAULT;
1461                 r = (val >> 8) & 0xff;
1462                 if (r > 100)
1463                         r = 100;
1464                 rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
1465                 rr = (r * 2 - 11) / 3;
1466                 if (rl < 3)     // If l is low, turn on
1467                         temp1 = 0x0080; //  the mute bit.
1468                 else
1469                         temp1 = 0;
1470
1471                 rl = 63 - rl;   // Convert vol to attenuation.
1472 //              writel(temp1 | rl, s->pBA0 + FMLVC);
1473                 if (rr < 3)     //  If rr is low, turn on
1474                         temp1 = 0x0080; //   the mute bit.
1475                 else
1476                         temp1 = 0;
1477                 rr = 63 - rr;   // Convert vol to attenuation.
1478 //              writel(temp1 | rr, s->pBA0 + FMRVC);
1479
1480 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1481                 s->mix.vol[4] = (r << 8) | l;
1482 #else
1483                 s->mix.vol[4] = val;
1484 #endif
1485                 return put_user(s->mix.vol[4], (int *) arg);
1486
1487
1488         default:
1489                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1490                         "cs4297a: mixer_ioctl(): default\n"));
1491
1492                 i = _IOC_NR(cmd);
1493                 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1494                         return -EINVAL;
1495                 if (get_user(val, (int *) arg))
1496                         return -EFAULT;
1497                 l = val & 0xff;
1498                 if (l > 100)
1499                         l = 100;
1500                 if (l < 1) {
1501                         l = 0;
1502                         rl = 31;
1503                 } else
1504                         rl = (attentbl[(l * 10) / 100]) >> 1;
1505
1506                 r = (val >> 8) & 0xff;
1507                 if (r > 100)
1508                         r = 100;
1509                 if (r < 1) {
1510                         r = 0;
1511                         rr = 31;
1512                 } else
1513                         rr = (attentbl[(r * 10) / 100]) >> 1;
1514                 if ((rl > 30) && (rr > 30))
1515                         temp1 = 0x8000;
1516                 else
1517                         temp1 = 0;
1518                 temp1 = temp1 | (rl << 8) | rr;
1519                 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1520
1521 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1522                 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1523 #else
1524                 s->mix.vol[vidx - 1] = val;
1525 #endif
1526                 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1527         }
1528 }
1529
1530
1531 // ---------------------------------------------------------------------
1532
1533 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1534 {
1535         int minor = iminor(inode);
1536         struct cs4297a_state *s=NULL;
1537         struct list_head *entry;
1538
1539         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1540                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1541
1542         list_for_each(entry, &cs4297a_devs)
1543         {
1544                 s = list_entry(entry, struct cs4297a_state, list);
1545                 if(s->dev_mixer == minor)
1546                         break;
1547         }
1548         if (!s)
1549         {
1550                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1551                         printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1552                 return -ENODEV;
1553         }
1554         VALIDATE_STATE(s);
1555         file->private_data = s;
1556
1557         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1558                   printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1559
1560         return nonseekable_open(inode, file);
1561 }
1562
1563
1564 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1565 {
1566         struct cs4297a_state *s =
1567             (struct cs4297a_state *) file->private_data;
1568
1569         VALIDATE_STATE(s);
1570         return 0;
1571 }
1572
1573
1574 static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1575                                unsigned int cmd, unsigned long arg)
1576 {
1577         return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1578                            arg);
1579 }
1580
1581
1582 // ******************************************************************************************
1583 //   Mixer file operations struct.
1584 // ******************************************************************************************
1585 static /*const */ struct file_operations cs4297a_mixer_fops = {
1586         .owner          = THIS_MODULE,
1587         .llseek         = no_llseek,
1588         .ioctl          = cs4297a_ioctl_mixdev,
1589         .open           = cs4297a_open_mixdev,
1590         .release        = cs4297a_release_mixdev,
1591 };
1592
1593 // ---------------------------------------------------------------------
1594
1595
1596 static int drain_adc(struct cs4297a_state *s, int nonblock)
1597 {
1598         /* This routine serves no purpose currently - any samples
1599            sitting in the receive queue will just be processed by the
1600            background consumer.  This would be different if DMA
1601            actually stopped when there were no clients. */
1602         return 0;
1603 }
1604
1605 static int drain_dac(struct cs4297a_state *s, int nonblock)
1606 {
1607         DECLARE_WAITQUEUE(wait, current);
1608         unsigned long flags;
1609         unsigned hwptr;
1610         unsigned tmo;
1611         int count;
1612
1613         if (s->dma_dac.mapped)
1614                 return 0;
1615         if (nonblock)
1616                 return -EBUSY;
1617         add_wait_queue(&s->dma_dac.wait, &wait);
1618         while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1619                (s->dma_dac.count > 0)) {
1620                 if (!signal_pending(current)) {
1621                         set_current_state(TASK_INTERRUPTIBLE);
1622                         /* XXXKW is this calculation working? */
1623                         tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1624                         schedule_timeout(tmo + 1);
1625                 } else {
1626                         /* XXXKW do I care if there is a signal pending? */
1627                 }
1628         }
1629         spin_lock_irqsave(&s->lock, flags);
1630         /* Reset the bookkeeping */
1631         hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1632                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1633         s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1634         spin_unlock_irqrestore(&s->lock, flags);
1635         remove_wait_queue(&s->dma_dac.wait, &wait);
1636         current->state = TASK_RUNNING;
1637         return 0;
1638 }
1639
1640
1641 // ---------------------------------------------------------------------
1642
1643 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1644                            loff_t * ppos)
1645 {
1646         struct cs4297a_state *s =
1647             (struct cs4297a_state *) file->private_data;
1648         ssize_t ret;
1649         unsigned long flags;
1650         int cnt, count_fr, cnt_by;
1651         unsigned copied = 0;
1652
1653         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1654                   printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1655
1656         VALIDATE_STATE(s);
1657         if (s->dma_adc.mapped)
1658                 return -ENXIO;
1659         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1660                 return ret;
1661         if (!access_ok(VERIFY_WRITE, buffer, count))
1662                 return -EFAULT;
1663         ret = 0;
1664 //
1665 // "count" is the amount of bytes to read (from app), is decremented each loop
1666 //      by the amount of bytes that have been returned to the user buffer.
1667 // "cnt" is the running total of each read from the buffer (changes each loop)
1668 // "buffer" points to the app's buffer
1669 // "ret" keeps a running total of the amount of bytes that have been copied
1670 //      to the user buffer.
1671 // "copied" is the total bytes copied into the user buffer for each loop.
1672 //
1673         while (count > 0) {
1674                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1675                         "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1676                                 count, s->dma_adc.count,
1677                                 s->dma_adc.swptr, s->dma_adc.hwptr));
1678                 spin_lock_irqsave(&s->lock, flags);
1679
1680                 /* cnt will be the number of available samples (16-bit
1681                    stereo); it starts out as the maxmimum consequetive
1682                    samples */
1683                 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1684                 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1685
1686                 // dma_adc.count is the current total bytes that have not been read.
1687                 // if the amount of unread bytes from the current sw pointer to the
1688                 // end of the buffer is greater than the current total bytes that
1689                 // have not been read, then set the "cnt" (unread bytes) to the
1690                 // amount of unread bytes.
1691
1692                 if (count_fr < cnt)
1693                         cnt = count_fr;
1694                 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1695                 spin_unlock_irqrestore(&s->lock, flags);
1696                 //
1697                 // if we are converting from 8/16 then we need to copy
1698                 // twice the number of 16 bit bytes then 8 bit bytes.
1699                 //
1700                 if (s->conversion) {
1701                         if (cnt_by > (count * 2)) {
1702                                 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1703                                 cnt_by = count * 2;
1704                         }
1705                 } else {
1706                         if (cnt_by > count) {
1707                                 cnt = count / FRAME_SAMPLE_BYTES;
1708                                 cnt_by = count;
1709                         }
1710                 }
1711                 //
1712                 // "cnt" NOW is the smaller of the amount that will be read,
1713                 // and the amount that is requested in this read (or partial).
1714                 // if there are no bytes in the buffer to read, then start the
1715                 // ADC and wait for the interrupt handler to wake us up.
1716                 //
1717                 if (cnt <= 0) {
1718
1719                         // start up the dma engine and then continue back to the top of
1720                         // the loop when wake up occurs.
1721                         start_adc(s);
1722                         if (file->f_flags & O_NONBLOCK)
1723                                 return ret ? ret : -EAGAIN;
1724                         interruptible_sleep_on(&s->dma_adc.wait);
1725                         if (signal_pending(current))
1726                                 return ret ? ret : -ERESTARTSYS;
1727                         continue;
1728                 }
1729                 // there are bytes in the buffer to read.
1730                 // copy from the hw buffer over to the user buffer.
1731                 // user buffer is designated by "buffer"
1732                 // virtual address to copy from is dma_buf+swptr
1733                 // the "cnt" is the number of bytes to read.
1734
1735                 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1736                         "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1737                 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1738                          " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1739                                  s->dma_adc.sbufsz, s->dma_adc.count,
1740                                  (unsigned) buffer, ret));
1741
1742                 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1743                         return ret ? ret : -EFAULT;
1744                 copied = cnt_by;
1745
1746                 /* Return the descriptors */
1747                 spin_lock_irqsave(&s->lock, flags);
1748                 CS_DBGOUT(CS_FUNCTION, 2,
1749                           printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1750                 s->dma_adc.count -= cnt_by;
1751                 s->dma_adc.sb_swptr += cnt * 2;
1752                 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1753                         s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1754                 spin_unlock_irqrestore(&s->lock, flags);
1755                 count -= copied;
1756                 buffer += copied;
1757                 ret += copied;
1758                 start_adc(s);
1759         }
1760         CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1761                   printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1762         return ret;
1763 }
1764
1765
1766 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1767                             size_t count, loff_t * ppos)
1768 {
1769         struct cs4297a_state *s =
1770             (struct cs4297a_state *) file->private_data;
1771         ssize_t ret;
1772         unsigned long flags;
1773         unsigned swptr, hwptr;
1774         int cnt;
1775
1776         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1777                   printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1778                          count));
1779         VALIDATE_STATE(s);
1780
1781         if (s->dma_dac.mapped)
1782                 return -ENXIO;
1783         if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1784                 return ret;
1785         if (!access_ok(VERIFY_READ, buffer, count))
1786                 return -EFAULT;
1787         ret = 0;
1788         while (count > 0) {
1789                 serdma_t *d = &s->dma_dac;
1790                 int copy_cnt;
1791                 u32 *s_tmpl;
1792                 u32 *t_tmpl;
1793                 u32 left, right;
1794                 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1795
1796                 /* XXXXXX this is broken for BLOAT_FACTOR */
1797                 spin_lock_irqsave(&s->lock, flags);
1798                 if (d->count < 0) {
1799                         d->count = 0;
1800                         d->swptr = d->hwptr;
1801                 }
1802                 if (d->underrun) {
1803                         d->underrun = 0;
1804                         hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1805                                              d->descrtab_phys) / sizeof(serdma_descr_t));
1806                         d->swptr = d->hwptr = hwptr;
1807                 }
1808                 swptr = d->swptr;
1809                 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1810                 /* Will this write fill up the buffer? */
1811                 if (d->count + cnt > d->sbufsz)
1812                         cnt = d->sbufsz - d->count;
1813                 spin_unlock_irqrestore(&s->lock, flags);
1814                 if (cnt > count)
1815                         cnt = count;
1816                 if (cnt <= 0) {
1817                         start_dac(s);
1818                         if (file->f_flags & O_NONBLOCK)
1819                                 return ret ? ret : -EAGAIN;
1820                         interruptible_sleep_on(&d->wait);
1821                         if (signal_pending(current))
1822                                 return ret ? ret : -ERESTARTSYS;
1823                         continue;
1824                 }
1825                 if (copy_from_user(d->sample_buf, buffer, cnt))
1826                         return ret ? ret : -EFAULT;
1827
1828                 copy_cnt = cnt;
1829                 s_tmpl = (u32 *)d->sample_buf;
1830                 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1831
1832                 /* XXXKW assuming 16-bit stereo! */
1833                 do {
1834                         u32 tmp;
1835
1836                         t_tmpl[0] = cpu_to_be32(0x98000000);
1837
1838                         tmp = be32_to_cpu(s_tmpl[0]);
1839                         left = tmp & 0xffff;
1840                         right = tmp >> 16;
1841                         if (swap) {
1842                                 left = swab16(left);
1843                                 right = swab16(right);
1844                         }
1845                         t_tmpl[1] = cpu_to_be32(left >> 8);
1846                         t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1847                                                 (right << 4));
1848
1849                         s_tmpl++;
1850                         t_tmpl += 8;
1851                         copy_cnt -= 4;
1852                 } while (copy_cnt);
1853
1854                 /* Mux in any pending read/write accesses */
1855                 if (s->reg_request) {
1856                         *(u64 *)(d->dma_buf + (swptr * 4)) |=
1857                                 cpu_to_be64(s->reg_request);
1858                         s->reg_request = 0;
1859                         wake_up(&s->dma_dac.reg_wait);
1860                 }
1861
1862                 CS_DBGOUT(CS_WAVE_WRITE, 4,
1863                           printk(KERN_INFO
1864                                  "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1865
1866                 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1867                 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1868                 spin_lock_irqsave(&s->lock, flags);
1869                 d->swptr = swptr;
1870                 d->count += cnt;
1871                 d->endcleared = 0;
1872                 spin_unlock_irqrestore(&s->lock, flags);
1873                 count -= cnt;
1874                 buffer += cnt;
1875                 ret += cnt;
1876                 start_dac(s);
1877         }
1878         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1879                   printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1880         return ret;
1881 }
1882
1883
1884 static unsigned int cs4297a_poll(struct file *file,
1885                                 struct poll_table_struct *wait)
1886 {
1887         struct cs4297a_state *s =
1888             (struct cs4297a_state *) file->private_data;
1889         unsigned long flags;
1890         unsigned int mask = 0;
1891
1892         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1893                   printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1894         VALIDATE_STATE(s);
1895         if (file->f_mode & FMODE_WRITE) {
1896                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1897                           printk(KERN_INFO
1898                                  "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1899                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1900                         return 0;
1901                 poll_wait(file, &s->dma_dac.wait, wait);
1902         }
1903         if (file->f_mode & FMODE_READ) {
1904                 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1905                           printk(KERN_INFO
1906                                  "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1907                 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1908                         return 0;
1909                 poll_wait(file, &s->dma_adc.wait, wait);
1910         }
1911         spin_lock_irqsave(&s->lock, flags);
1912         cs4297a_update_ptr(s,CS_FALSE);
1913         if (file->f_mode & FMODE_WRITE) {
1914                 if (s->dma_dac.mapped) {
1915                         if (s->dma_dac.count >=
1916                             (signed) s->dma_dac.fragsize) {
1917                                 if (s->dma_dac.wakeup)
1918                                         mask |= POLLOUT | POLLWRNORM;
1919                                 else
1920                                         mask = 0;
1921                                 s->dma_dac.wakeup = 0;
1922                         }
1923                 } else {
1924                         if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1925                                 mask |= POLLOUT | POLLWRNORM;
1926                 }
1927         } else if (file->f_mode & FMODE_READ) {
1928                 if (s->dma_adc.mapped) {
1929                         if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1930                                 mask |= POLLIN | POLLRDNORM;
1931                 } else {
1932                         if (s->dma_adc.count > 0)
1933                                 mask |= POLLIN | POLLRDNORM;
1934                 }
1935         }
1936         spin_unlock_irqrestore(&s->lock, flags);
1937         CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1938                   printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1939                          mask));
1940         return mask;
1941 }
1942
1943
1944 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1945 {
1946         /* XXXKW currently no mmap support */
1947         return -EINVAL;
1948         return 0;
1949 }
1950
1951
1952 static int cs4297a_ioctl(struct inode *inode, struct file *file,
1953                         unsigned int cmd, unsigned long arg)
1954 {
1955         struct cs4297a_state *s =
1956             (struct cs4297a_state *) file->private_data;
1957         unsigned long flags;
1958         audio_buf_info abinfo;
1959         count_info cinfo;
1960         int val, mapped, ret;
1961
1962         CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1963                  "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1964                          (unsigned) file, cmd));
1965 #if CSDEBUG
1966         cs_printioctl(cmd);
1967 #endif
1968         VALIDATE_STATE(s);
1969         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1970             ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1971         switch (cmd) {
1972         case OSS_GETVERSION:
1973                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1974                         "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1975                                  SOUND_VERSION));
1976                 return put_user(SOUND_VERSION, (int *) arg);
1977
1978         case SNDCTL_DSP_SYNC:
1979                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1980                          "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1981                 if (file->f_mode & FMODE_WRITE)
1982                         return drain_dac(s,
1983                                          0 /*file->f_flags & O_NONBLOCK */
1984                                          );
1985                 return 0;
1986
1987         case SNDCTL_DSP_SETDUPLEX:
1988                 return 0;
1989
1990         case SNDCTL_DSP_GETCAPS:
1991                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1992                                 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
1993                                 (int *) arg);
1994
1995         case SNDCTL_DSP_RESET:
1996                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1997                          "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
1998                 if (file->f_mode & FMODE_WRITE) {
1999                         stop_dac(s);
2000                         synchronize_irq(s->irq);
2001                         s->dma_dac.count = s->dma_dac.total_bytes =
2002                                 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2003                         s->dma_dac.swptr = s->dma_dac.hwptr =
2004                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2005                                        s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2006                 }
2007                 if (file->f_mode & FMODE_READ) {
2008                         stop_adc(s);
2009                         synchronize_irq(s->irq);
2010                         s->dma_adc.count = s->dma_adc.total_bytes =
2011                                 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2012                         s->dma_adc.swptr = s->dma_adc.hwptr =
2013                                 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2014                                        s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2015                 }
2016                 return 0;
2017
2018         case SNDCTL_DSP_SPEED:
2019                 if (get_user(val, (int *) arg))
2020                         return -EFAULT;
2021                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2022                          "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2023                 val = 48000;
2024                 return put_user(val, (int *) arg);
2025
2026         case SNDCTL_DSP_STEREO:
2027                 if (get_user(val, (int *) arg))
2028                         return -EFAULT;
2029                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2030                          "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2031                 if (file->f_mode & FMODE_READ) {
2032                         stop_adc(s);
2033                         s->dma_adc.ready = 0;
2034                         s->prop_adc.channels = val ? 2 : 1;
2035                 }
2036                 if (file->f_mode & FMODE_WRITE) {
2037                         stop_dac(s);
2038                         s->dma_dac.ready = 0;
2039                         s->prop_dac.channels = val ? 2 : 1;
2040                 }
2041                 return 0;
2042
2043         case SNDCTL_DSP_CHANNELS:
2044                 if (get_user(val, (int *) arg))
2045                         return -EFAULT;
2046                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2047                          "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2048                                  val));
2049                 if (val != 0) {
2050                         if (file->f_mode & FMODE_READ) {
2051                                 stop_adc(s);
2052                                 s->dma_adc.ready = 0;
2053                                 if (val >= 2)
2054                                         s->prop_adc.channels = 2;
2055                                 else
2056                                         s->prop_adc.channels = 1;
2057                         }
2058                         if (file->f_mode & FMODE_WRITE) {
2059                                 stop_dac(s);
2060                                 s->dma_dac.ready = 0;
2061                                 if (val >= 2)
2062                                         s->prop_dac.channels = 2;
2063                                 else
2064                                         s->prop_dac.channels = 1;
2065                         }
2066                 }
2067
2068                 if (file->f_mode & FMODE_WRITE)
2069                         val = s->prop_dac.channels;
2070                 else if (file->f_mode & FMODE_READ)
2071                         val = s->prop_adc.channels;
2072
2073                 return put_user(val, (int *) arg);
2074
2075         case SNDCTL_DSP_GETFMTS:        // Returns a mask
2076                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2077                         "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2078                                  AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2079                                  AFMT_U8));
2080                 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2081                                 AFMT_U8, (int *) arg);
2082
2083         case SNDCTL_DSP_SETFMT:
2084                 if (get_user(val, (int *) arg))
2085                         return -EFAULT;
2086                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2087                          "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2088                                  val));
2089                 if (val != AFMT_QUERY) {
2090                         if (file->f_mode & FMODE_READ) {
2091                                 stop_adc(s);
2092                                 s->dma_adc.ready = 0;
2093                                 if (val != AFMT_S16_LE
2094                                     && val != AFMT_U16_LE && val != AFMT_S8
2095                                     && val != AFMT_U8)
2096                                         val = AFMT_U8;
2097                                 s->prop_adc.fmt = val;
2098                                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2099                         }
2100                         if (file->f_mode & FMODE_WRITE) {
2101                                 stop_dac(s);
2102                                 s->dma_dac.ready = 0;
2103                                 if (val != AFMT_S16_LE
2104                                     && val != AFMT_U16_LE && val != AFMT_S8
2105                                     && val != AFMT_U8)
2106                                         val = AFMT_U8;
2107                                 s->prop_dac.fmt = val;
2108                                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2109                         }
2110                 } else {
2111                         if (file->f_mode & FMODE_WRITE)
2112                                 val = s->prop_dac.fmt_original;
2113                         else if (file->f_mode & FMODE_READ)
2114                                 val = s->prop_adc.fmt_original;
2115                 }
2116                 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2117                   "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2118                         val));
2119                 return put_user(val, (int *) arg);
2120
2121         case SNDCTL_DSP_POST:
2122                 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2123                          "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2124                 return 0;
2125
2126         case SNDCTL_DSP_GETTRIGGER:
2127                 val = 0;
2128                 if (file->f_mode & s->ena & FMODE_READ)
2129                         val |= PCM_ENABLE_INPUT;
2130                 if (file->f_mode & s->ena & FMODE_WRITE)
2131                         val |= PCM_ENABLE_OUTPUT;
2132                 return put_user(val, (int *) arg);
2133
2134         case SNDCTL_DSP_SETTRIGGER:
2135                 if (get_user(val, (int *) arg))
2136                         return -EFAULT;
2137                 if (file->f_mode & FMODE_READ) {
2138                         if (val & PCM_ENABLE_INPUT) {
2139                                 if (!s->dma_adc.ready
2140                                     && (ret = prog_dmabuf_adc(s)))
2141                                         return ret;
2142                                 start_adc(s);
2143                         } else
2144                                 stop_adc(s);
2145                 }
2146                 if (file->f_mode & FMODE_WRITE) {
2147                         if (val & PCM_ENABLE_OUTPUT) {
2148                                 if (!s->dma_dac.ready
2149                                     && (ret = prog_dmabuf_dac(s)))
2150                                         return ret;
2151                                 start_dac(s);
2152                         } else
2153                                 stop_dac(s);
2154                 }
2155                 return 0;
2156
2157         case SNDCTL_DSP_GETOSPACE:
2158                 if (!(file->f_mode & FMODE_WRITE))
2159                         return -EINVAL;
2160                 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2161                         return val;
2162                 spin_lock_irqsave(&s->lock, flags);
2163                 cs4297a_update_ptr(s,CS_FALSE);
2164                 abinfo.fragsize = s->dma_dac.fragsize;
2165                 if (s->dma_dac.mapped)
2166                         abinfo.bytes = s->dma_dac.sbufsz;
2167                 else
2168                         abinfo.bytes =
2169                             s->dma_dac.sbufsz - s->dma_dac.count;
2170                 abinfo.fragstotal = s->dma_dac.numfrag;
2171                 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2172                 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2173                         "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2174                                 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2175                                 abinfo.fragments));
2176                 spin_unlock_irqrestore(&s->lock, flags);
2177                 return copy_to_user((void *) arg, &abinfo,
2178                                     sizeof(abinfo)) ? -EFAULT : 0;
2179
2180         case SNDCTL_DSP_GETISPACE:
2181                 if (!(file->f_mode & FMODE_READ))
2182                         return -EINVAL;
2183                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2184                         return val;
2185                 spin_lock_irqsave(&s->lock, flags);
2186                 cs4297a_update_ptr(s,CS_FALSE);
2187                 if (s->conversion) {
2188                         abinfo.fragsize = s->dma_adc.fragsize / 2;
2189                         abinfo.bytes = s->dma_adc.count / 2;
2190                         abinfo.fragstotal = s->dma_adc.numfrag;
2191                         abinfo.fragments =
2192                             abinfo.bytes >> (s->dma_adc.fragshift - 1);
2193                 } else {
2194                         abinfo.fragsize = s->dma_adc.fragsize;
2195                         abinfo.bytes = s->dma_adc.count;
2196                         abinfo.fragstotal = s->dma_adc.numfrag;
2197                         abinfo.fragments =
2198                             abinfo.bytes >> s->dma_adc.fragshift;
2199                 }
2200                 spin_unlock_irqrestore(&s->lock, flags);
2201                 return copy_to_user((void *) arg, &abinfo,
2202                                     sizeof(abinfo)) ? -EFAULT : 0;
2203
2204         case SNDCTL_DSP_NONBLOCK:
2205                 file->f_flags |= O_NONBLOCK;
2206                 return 0;
2207
2208         case SNDCTL_DSP_GETODELAY:
2209                 if (!(file->f_mode & FMODE_WRITE))
2210                         return -EINVAL;
2211                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2212                         return 0;
2213                 spin_lock_irqsave(&s->lock, flags);
2214                 cs4297a_update_ptr(s,CS_FALSE);
2215                 val = s->dma_dac.count;
2216                 spin_unlock_irqrestore(&s->lock, flags);
2217                 return put_user(val, (int *) arg);
2218
2219         case SNDCTL_DSP_GETIPTR:
2220                 if (!(file->f_mode & FMODE_READ))
2221                         return -EINVAL;
2222                 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2223                         return 0;
2224                 spin_lock_irqsave(&s->lock, flags);
2225                 cs4297a_update_ptr(s,CS_FALSE);
2226                 cinfo.bytes = s->dma_adc.total_bytes;
2227                 if (s->dma_adc.mapped) {
2228                         cinfo.blocks =
2229                             (cinfo.bytes >> s->dma_adc.fragshift) -
2230                             s->dma_adc.blocks;
2231                         s->dma_adc.blocks =
2232                             cinfo.bytes >> s->dma_adc.fragshift;
2233                 } else {
2234                         if (s->conversion) {
2235                                 cinfo.blocks =
2236                                     s->dma_adc.count /
2237                                     2 >> (s->dma_adc.fragshift - 1);
2238                         } else
2239                                 cinfo.blocks =
2240                                     s->dma_adc.count >> s->dma_adc.
2241                                     fragshift;
2242                 }
2243                 if (s->conversion)
2244                         cinfo.ptr = s->dma_adc.hwptr / 2;
2245                 else
2246                         cinfo.ptr = s->dma_adc.hwptr;
2247                 if (s->dma_adc.mapped)
2248                         s->dma_adc.count &= s->dma_adc.fragsize - 1;
2249                 spin_unlock_irqrestore(&s->lock, flags);
2250                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2251
2252         case SNDCTL_DSP_GETOPTR:
2253                 if (!(file->f_mode & FMODE_WRITE))
2254                         return -EINVAL;
2255                 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2256                         return 0;
2257                 spin_lock_irqsave(&s->lock, flags);
2258                 cs4297a_update_ptr(s,CS_FALSE);
2259                 cinfo.bytes = s->dma_dac.total_bytes;
2260                 if (s->dma_dac.mapped) {
2261                         cinfo.blocks =
2262                             (cinfo.bytes >> s->dma_dac.fragshift) -
2263                             s->dma_dac.blocks;
2264                         s->dma_dac.blocks =
2265                             cinfo.bytes >> s->dma_dac.fragshift;
2266                 } else {
2267                         cinfo.blocks =
2268                             s->dma_dac.count >> s->dma_dac.fragshift;
2269                 }
2270                 cinfo.ptr = s->dma_dac.hwptr;
2271                 if (s->dma_dac.mapped)
2272                         s->dma_dac.count &= s->dma_dac.fragsize - 1;
2273                 spin_unlock_irqrestore(&s->lock, flags);
2274                 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2275
2276         case SNDCTL_DSP_GETBLKSIZE:
2277                 if (file->f_mode & FMODE_WRITE) {
2278                         if ((val = prog_dmabuf_dac(s)))
2279                                 return val;
2280                         return put_user(s->dma_dac.fragsize, (int *) arg);
2281                 }
2282                 if ((val = prog_dmabuf_adc(s)))
2283                         return val;
2284                 if (s->conversion)
2285                         return put_user(s->dma_adc.fragsize / 2,
2286                                         (int *) arg);
2287                 else
2288                         return put_user(s->dma_adc.fragsize, (int *) arg);
2289
2290         case SNDCTL_DSP_SETFRAGMENT:
2291                 if (get_user(val, (int *) arg))
2292                         return -EFAULT;
2293                 return 0;       // Say OK, but do nothing.
2294
2295         case SNDCTL_DSP_SUBDIVIDE:
2296                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2297                     || (file->f_mode & FMODE_WRITE
2298                         && s->dma_dac.subdivision)) return -EINVAL;
2299                 if (get_user(val, (int *) arg))
2300                         return -EFAULT;
2301                 if (val != 1 && val != 2 && val != 4)
2302                         return -EINVAL;
2303                 if (file->f_mode & FMODE_READ)
2304                         s->dma_adc.subdivision = val;
2305                 else if (file->f_mode & FMODE_WRITE)
2306                         s->dma_dac.subdivision = val;
2307                 return 0;
2308
2309         case SOUND_PCM_READ_RATE:
2310                 if (file->f_mode & FMODE_READ)
2311                         return put_user(s->prop_adc.rate, (int *) arg);
2312                 else if (file->f_mode & FMODE_WRITE)
2313                         return put_user(s->prop_dac.rate, (int *) arg);
2314
2315         case SOUND_PCM_READ_CHANNELS:
2316                 if (file->f_mode & FMODE_READ)
2317                         return put_user(s->prop_adc.channels, (int *) arg);
2318                 else if (file->f_mode & FMODE_WRITE)
2319                         return put_user(s->prop_dac.channels, (int *) arg);
2320
2321         case SOUND_PCM_READ_BITS:
2322                 if (file->f_mode & FMODE_READ)
2323                         return
2324                             put_user(
2325                                      (s->prop_adc.
2326                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2327                                      (int *) arg);
2328                 else if (file->f_mode & FMODE_WRITE)
2329                         return
2330                             put_user(
2331                                      (s->prop_dac.
2332                                       fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2333                                      (int *) arg);
2334
2335         case SOUND_PCM_WRITE_FILTER:
2336         case SNDCTL_DSP_SETSYNCRO:
2337         case SOUND_PCM_READ_FILTER:
2338                 return -EINVAL;
2339         }
2340         return mixer_ioctl(s, cmd, arg);
2341 }
2342
2343
2344 static int cs4297a_release(struct inode *inode, struct file *file)
2345 {
2346         struct cs4297a_state *s =
2347             (struct cs4297a_state *) file->private_data;
2348
2349         CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2350                  "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2351                          (unsigned) inode, (unsigned) file, file->f_mode));
2352         VALIDATE_STATE(s);
2353
2354         if (file->f_mode & FMODE_WRITE) {
2355                 drain_dac(s, file->f_flags & O_NONBLOCK);
2356                 mutex_lock(&s->open_sem_dac);
2357                 stop_dac(s);
2358                 dealloc_dmabuf(s, &s->dma_dac);
2359                 s->open_mode &= ~FMODE_WRITE;
2360                 mutex_unlock(&s->open_sem_dac);
2361                 wake_up(&s->open_wait_dac);
2362         }
2363         if (file->f_mode & FMODE_READ) {
2364                 drain_adc(s, file->f_flags & O_NONBLOCK);
2365                 mutex_lock(&s->open_sem_adc);
2366                 stop_adc(s);
2367                 dealloc_dmabuf(s, &s->dma_adc);
2368                 s->open_mode &= ~FMODE_READ;
2369                 mutex_unlock(&s->open_sem_adc);
2370                 wake_up(&s->open_wait_adc);
2371         }
2372         return 0;
2373 }
2374
2375 static int cs4297a_open(struct inode *inode, struct file *file)
2376 {
2377         int minor = iminor(inode);
2378         struct cs4297a_state *s=NULL;
2379         struct list_head *entry;
2380
2381         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2382                 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2383                         (unsigned) inode, (unsigned) file, file->f_mode));
2384         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2385                 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2386
2387         list_for_each(entry, &cs4297a_devs)
2388         {
2389                 s = list_entry(entry, struct cs4297a_state, list);
2390
2391                 if (!((s->dev_audio ^ minor) & ~0xf))
2392                         break;
2393         }
2394         if (entry == &cs4297a_devs)
2395                 return -ENODEV;
2396         if (!s) {
2397                 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2398                         "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2399                 return -ENODEV;
2400         }
2401         VALIDATE_STATE(s);
2402         file->private_data = s;
2403
2404         // wait for device to become free
2405         if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2406                 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2407                          "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2408                 return -ENODEV;
2409         }
2410         if (file->f_mode & FMODE_WRITE) {
2411                 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2412                         printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2413                         while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2414                                 ;
2415                 }
2416
2417                 mutex_lock(&s->open_sem_dac);
2418                 while (s->open_mode & FMODE_WRITE) {
2419                         if (file->f_flags & O_NONBLOCK) {
2420                                 mutex_unlock(&s->open_sem_dac);
2421                                 return -EBUSY;
2422                         }
2423                         mutex_unlock(&s->open_sem_dac);
2424                         interruptible_sleep_on(&s->open_wait_dac);
2425
2426                         if (signal_pending(current)) {
2427                                 printk("open - sig pending\n");
2428                                 return -ERESTARTSYS;
2429                         }
2430                         mutex_lock(&s->open_sem_dac);
2431                 }
2432         }
2433         if (file->f_mode & FMODE_READ) {
2434                 mutex_lock(&s->open_sem_adc);
2435                 while (s->open_mode & FMODE_READ) {
2436                         if (file->f_flags & O_NONBLOCK) {
2437                                 mutex_unlock(&s->open_sem_adc);
2438                                 return -EBUSY;
2439                         }
2440                         mutex_unlock(&s->open_sem_adc);
2441                         interruptible_sleep_on(&s->open_wait_adc);
2442
2443                         if (signal_pending(current)) {
2444                                 printk("open - sig pending\n");
2445                                 return -ERESTARTSYS;
2446                         }
2447                         mutex_lock(&s->open_sem_adc);
2448                 }
2449         }
2450         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2451         if (file->f_mode & FMODE_READ) {
2452                 s->prop_adc.fmt = AFMT_S16_BE;
2453                 s->prop_adc.fmt_original = s->prop_adc.fmt;
2454                 s->prop_adc.channels = 2;
2455                 s->prop_adc.rate = 48000;
2456                 s->conversion = 0;
2457                 s->ena &= ~FMODE_READ;
2458                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2459                     s->dma_adc.subdivision = 0;
2460                 mutex_unlock(&s->open_sem_adc);
2461
2462                 if (prog_dmabuf_adc(s)) {
2463                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2464                                 "cs4297a: adc Program dmabufs failed.\n"));
2465                         cs4297a_release(inode, file);
2466                         return -ENOMEM;
2467                 }
2468         }
2469         if (file->f_mode & FMODE_WRITE) {
2470                 s->prop_dac.fmt = AFMT_S16_BE;
2471                 s->prop_dac.fmt_original = s->prop_dac.fmt;
2472                 s->prop_dac.channels = 2;
2473                 s->prop_dac.rate = 48000;
2474                 s->conversion = 0;
2475                 s->ena &= ~FMODE_WRITE;
2476                 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2477                     s->dma_dac.subdivision = 0;
2478                 mutex_unlock(&s->open_sem_dac);
2479
2480                 if (prog_dmabuf_dac(s)) {
2481                         CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2482                                 "cs4297a: dac Program dmabufs failed.\n"));
2483                         cs4297a_release(inode, file);
2484                         return -ENOMEM;
2485                 }
2486         }
2487         CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2488                   printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2489         return nonseekable_open(inode, file);
2490 }
2491
2492
2493 // ******************************************************************************************
2494 //   Wave (audio) file operations struct.
2495 // ******************************************************************************************
2496 static /*const */ struct file_operations cs4297a_audio_fops = {
2497         .owner          = THIS_MODULE,
2498         .llseek         = no_llseek,
2499         .read           = cs4297a_read,
2500         .write          = cs4297a_write,
2501         .poll           = cs4297a_poll,
2502         .ioctl          = cs4297a_ioctl,
2503         .mmap           = cs4297a_mmap,
2504         .open           = cs4297a_open,
2505         .release        = cs4297a_release,
2506 };
2507
2508 static void cs4297a_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2509 {
2510         struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2511         u32 status;
2512
2513         status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2514
2515         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2516                  "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2517
2518 #if 0
2519         /* XXXKW what check *should* be done here? */
2520         if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2521                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2522                 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2523                 return;
2524         }
2525 #endif
2526
2527         if (status & M_SYNCSER_RX_SYNC_ERR) {
2528                 status = __raw_readq(SS_CSR(R_SER_STATUS));
2529                 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2530                 return;
2531         }
2532
2533         if (status & M_SYNCSER_RX_OVERRUN) {
2534                 int newptr, i;
2535                 s->stats.rx_ovrrn++;
2536                 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2537
2538                 /* Fix things up: get the receive descriptor pool
2539                    clean and give them back to the hardware */
2540                 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2541                         ;
2542                 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2543                                      s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2544                 for (i=0; i<DMA_DESCR; i++) {
2545                         s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2546                 }
2547                 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2548                 s->dma_adc.count = 0;
2549                 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2550                 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2551         }
2552
2553         spin_lock(&s->lock);
2554         cs4297a_update_ptr(s,CS_TRUE);
2555         spin_unlock(&s->lock);
2556
2557         CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2558                   "cs4297a: cs4297a_interrupt()-\n"));
2559 }
2560
2561 #if 0
2562 static struct initvol {
2563         int mixch;
2564         int vol;
2565 } initvol[] __initdata = {
2566
2567         {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2568         {SOUND_MIXER_WRITE_PCM, 0x4040},
2569         {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2570         {SOUND_MIXER_WRITE_CD, 0x4040},
2571         {SOUND_MIXER_WRITE_LINE, 0x4040},
2572         {SOUND_MIXER_WRITE_LINE1, 0x4040},
2573         {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2574         {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2575         {SOUND_MIXER_WRITE_MIC, 0x0000}
2576 };
2577 #endif
2578
2579 static int __init cs4297a_init(void)
2580 {
2581         struct cs4297a_state *s;
2582         u32 pwr, id;
2583         mm_segment_t fs;
2584         int rval;
2585 #ifndef CONFIG_BCM_CS4297A_CSWARM
2586         u64 cfg;
2587         int mdio_val;
2588 #endif
2589
2590         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2591                 "cs4297a: cs4297a_init_module()+ \n"));
2592
2593 #ifndef CONFIG_BCM_CS4297A_CSWARM
2594         mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2595                 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2596
2597         /* Check syscfg for synchronous serial on port 1 */
2598         cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2599         if (!(cfg & M_SYS_SER1_ENABLE)) {
2600                 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2601                 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2602                 if (!(cfg & M_SYS_SER1_ENABLE)) {
2603                   printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2604                   return -1;
2605                 }
2606
2607                 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2608
2609                 /* Force the codec (on SWARM) to reset by clearing
2610                    GENO, preserving MDIO (no effect on CSWARM) */
2611                 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2612                 udelay(10);
2613         }
2614
2615         /* Now set GENO */
2616         __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2617         /* Give the codec some time to finish resetting (start the bit clock) */
2618         udelay(100);
2619 #endif
2620
2621         if (!(s = kmalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2622                 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2623                       "cs4297a: probe() no memory for state struct.\n"));
2624                 return -1;
2625         }
2626         memset(s, 0, sizeof(struct cs4297a_state));
2627         s->magic = CS4297a_MAGIC;
2628         init_waitqueue_head(&s->dma_adc.wait);
2629         init_waitqueue_head(&s->dma_dac.wait);
2630         init_waitqueue_head(&s->dma_adc.reg_wait);
2631         init_waitqueue_head(&s->dma_dac.reg_wait);
2632         init_waitqueue_head(&s->open_wait);
2633         init_waitqueue_head(&s->open_wait_adc);
2634         init_waitqueue_head(&s->open_wait_dac);
2635         mutex_init(&s->open_sem_adc);
2636         mutex_init(&s->open_sem_dac);
2637         spin_lock_init(&s->lock);
2638
2639         s->irq = K_INT_SER_1;
2640
2641         if (request_irq
2642             (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2643                 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2644                           printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2645                 goto err_irq;
2646         }
2647         if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2648             0) {
2649                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2650                          "cs4297a: probe() register_sound_dsp() failed.\n"));
2651                 goto err_dev1;
2652         }
2653         if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2654             0) {
2655                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2656                          "cs4297a: probe() register_sound_mixer() failed.\n"));
2657                 goto err_dev2;
2658         }
2659
2660         if (ser_init(s) || dma_init(s)) {
2661                 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2662                          "cs4297a: ser_init failed.\n"));
2663                 goto err_dev3;
2664         }
2665
2666         do {
2667                 udelay(4000);
2668                 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2669         } while (!rval && (pwr != 0xf));
2670
2671         if (!rval) {
2672                 char *sb1250_duart_present;
2673
2674                 fs = get_fs();
2675                 set_fs(KERNEL_DS);
2676 #if 0
2677                 val = SOUND_MASK_LINE;
2678                 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2679                 for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
2680                         val = initvol[i].vol;
2681                         mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2682                 }
2683 //                cs4297a_write_ac97(s, 0x18, 0x0808);
2684 #else
2685                 //                cs4297a_write_ac97(s, 0x5e, 0x180);
2686                 cs4297a_write_ac97(s, 0x02, 0x0808);
2687                 cs4297a_write_ac97(s, 0x18, 0x0808);
2688 #endif
2689                 set_fs(fs);
2690
2691                 list_add(&s->list, &cs4297a_devs);
2692
2693                 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2694
2695                 sb1250_duart_present = symbol_get(sb1250_duart_present);
2696                 if (sb1250_duart_present)
2697                         sb1250_duart_present[1] = 0;
2698
2699                 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2700
2701                 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2702                           printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2703
2704                 return 0;
2705         }
2706
2707  err_dev3:
2708         unregister_sound_mixer(s->dev_mixer);
2709  err_dev2:
2710         unregister_sound_dsp(s->dev_audio);
2711  err_dev1:
2712         free_irq(s->irq, s);
2713  err_irq:
2714         kfree(s);
2715
2716         printk(KERN_INFO "cs4297a: initialization failed\n");
2717
2718         return -1;
2719 }
2720
2721 static void __exit cs4297a_cleanup(void)
2722 {
2723         /*
2724           XXXKW
2725            disable_irq, free_irq
2726            drain DMA queue
2727            disable DMA
2728            disable TX/RX
2729            free memory
2730         */
2731         CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2732                   printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2733 }
2734
2735 // ---------------------------------------------------------------------
2736
2737 MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2738 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2739
2740 // ---------------------------------------------------------------------
2741
2742 module_init(cs4297a_init);
2743 module_exit(cs4297a_cleanup);