2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count;
60 u8 move_in_progress : 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
83 static int assign_irq_vector(int irq, cpumask_t mask);
85 int first_system_vector = 0xfe;
87 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
89 #define __apicdebuginit __init
91 int sis_apic_bug; /* not actually supported, dummy for compile */
93 static int no_timer_check;
95 static int disable_timer_pin_1 __initdata;
97 static bool mask_ioapic_irq_2 __initdata;
99 void __init force_mask_ioapic_irq_2(void)
101 mask_ioapic_irq_2 = true;
104 int timer_through_8259 __initdata;
106 /* Where if anywhere is the i8259 connect in external int mode */
107 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
109 static DEFINE_SPINLOCK(ioapic_lock);
110 DEFINE_SPINLOCK(vector_lock);
113 * # of IRQ routing registers
115 int nr_ioapic_registers[MAX_IO_APICS];
117 /* I/O APIC entries */
118 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
121 /* MP IRQ source entries */
122 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
124 /* # of MP IRQ source entries */
127 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
130 * Rough estimation of how many shared IRQs there are, can
131 * be changed anytime.
133 #define MAX_PLUS_SHARED_IRQS NR_IRQS
134 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
137 * This is performance-critical, we want to do it O(1)
139 * the indexing order of this array favors 1:1 mappings
140 * between pins and IRQs.
143 static struct irq_pin_list {
144 short apic, pin, next;
145 } irq_2_pin[PIN_MAP_SIZE];
149 unsigned int unused[3];
153 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
155 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
156 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
159 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
161 struct io_apic __iomem *io_apic = io_apic_base(apic);
162 writel(reg, &io_apic->index);
163 return readl(&io_apic->data);
166 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
168 struct io_apic __iomem *io_apic = io_apic_base(apic);
169 writel(reg, &io_apic->index);
170 writel(value, &io_apic->data);
174 * Re-write a value: to be used for read-modify-write
175 * cycles where the read already set up the index register.
177 static inline void io_apic_modify(unsigned int apic, unsigned int value)
179 struct io_apic __iomem *io_apic = io_apic_base(apic);
180 writel(value, &io_apic->data);
183 static bool io_apic_level_ack_pending(unsigned int irq)
185 struct irq_pin_list *entry;
188 spin_lock_irqsave(&ioapic_lock, flags);
189 entry = irq_2_pin + irq;
197 reg = io_apic_read(entry->apic, 0x10 + pin*2);
198 /* Is the remote IRR bit set? */
199 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
200 spin_unlock_irqrestore(&ioapic_lock, flags);
205 entry = irq_2_pin + entry->next;
207 spin_unlock_irqrestore(&ioapic_lock, flags);
213 * Synchronize the IO-APIC and the CPU by doing
214 * a dummy read from the IO-APIC
216 static inline void io_apic_sync(unsigned int apic)
218 struct io_apic __iomem *io_apic = io_apic_base(apic);
219 readl(&io_apic->data);
222 #define __DO_ACTION(R, ACTION, FINAL) \
226 struct irq_pin_list *entry = irq_2_pin + irq; \
228 BUG_ON(irq >= NR_IRQS); \
234 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
236 io_apic_modify(entry->apic, reg); \
240 entry = irq_2_pin + entry->next; \
245 struct { u32 w1, w2; };
246 struct IO_APIC_route_entry entry;
249 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
251 union entry_union eu;
253 spin_lock_irqsave(&ioapic_lock, flags);
254 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
255 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
256 spin_unlock_irqrestore(&ioapic_lock, flags);
261 * When we write a new IO APIC routing entry, we need to write the high
262 * word first! If the mask bit in the low word is clear, we will enable
263 * the interrupt, and we need to make sure the entry is fully populated
264 * before that happens.
267 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
269 union entry_union eu;
271 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
272 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
275 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
278 spin_lock_irqsave(&ioapic_lock, flags);
279 __ioapic_write_entry(apic, pin, e);
280 spin_unlock_irqrestore(&ioapic_lock, flags);
284 * When we mask an IO APIC routing entry, we need to write the low
285 * word first, in order to set the mask bit before we change the
288 static void ioapic_mask_entry(int apic, int pin)
291 union entry_union eu = { .entry.mask = 1 };
293 spin_lock_irqsave(&ioapic_lock, flags);
294 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
295 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
296 spin_unlock_irqrestore(&ioapic_lock, flags);
300 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
303 struct irq_pin_list *entry = irq_2_pin + irq;
305 BUG_ON(irq >= NR_IRQS);
312 io_apic_write(apic, 0x11 + pin*2, dest);
313 reg = io_apic_read(apic, 0x10 + pin*2);
314 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
316 io_apic_modify(apic, reg);
319 entry = irq_2_pin + entry->next;
323 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
325 struct irq_cfg *cfg = irq_cfg + irq;
330 cpus_and(tmp, mask, cpu_online_map);
334 if (assign_irq_vector(irq, mask))
337 cpus_and(tmp, cfg->domain, mask);
338 dest = cpu_mask_to_apicid(tmp);
341 * Only the high 8 bits are valid.
343 dest = SET_APIC_LOGICAL_ID(dest);
345 spin_lock_irqsave(&ioapic_lock, flags);
346 __target_IO_APIC_irq(irq, dest, cfg->vector);
347 irq_desc[irq].affinity = mask;
348 spin_unlock_irqrestore(&ioapic_lock, flags);
353 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
354 * shared ISA-space IRQs, so we have to support them. We are super
355 * fast in the common case, and fast for shared ISA-space IRQs.
357 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
359 static int first_free_entry = NR_IRQS;
360 struct irq_pin_list *entry = irq_2_pin + irq;
362 BUG_ON(irq >= NR_IRQS);
364 entry = irq_2_pin + entry->next;
366 if (entry->pin != -1) {
367 entry->next = first_free_entry;
368 entry = irq_2_pin + entry->next;
369 if (++first_free_entry >= PIN_MAP_SIZE)
370 panic("io_apic.c: ran out of irq_2_pin entries!");
377 * Reroute an IRQ to a different pin.
379 static void __init replace_pin_at_irq(unsigned int irq,
380 int oldapic, int oldpin,
381 int newapic, int newpin)
383 struct irq_pin_list *entry = irq_2_pin + irq;
386 if (entry->apic == oldapic && entry->pin == oldpin) {
387 entry->apic = newapic;
392 entry = irq_2_pin + entry->next;
397 #define DO_ACTION(name,R,ACTION, FINAL) \
399 static void name##_IO_APIC_irq (unsigned int irq) \
400 __DO_ACTION(R, ACTION, FINAL)
403 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
406 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
408 static void mask_IO_APIC_irq (unsigned int irq)
412 spin_lock_irqsave(&ioapic_lock, flags);
413 __mask_IO_APIC_irq(irq);
414 spin_unlock_irqrestore(&ioapic_lock, flags);
417 static void unmask_IO_APIC_irq (unsigned int irq)
421 spin_lock_irqsave(&ioapic_lock, flags);
422 __unmask_IO_APIC_irq(irq);
423 spin_unlock_irqrestore(&ioapic_lock, flags);
426 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
428 struct IO_APIC_route_entry entry;
430 /* Check delivery_mode to be sure we're not clearing an SMI pin */
431 entry = ioapic_read_entry(apic, pin);
432 if (entry.delivery_mode == dest_SMI)
435 * Disable it in the IO-APIC irq-routing table:
437 ioapic_mask_entry(apic, pin);
440 static void clear_IO_APIC (void)
444 for (apic = 0; apic < nr_ioapics; apic++)
445 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
446 clear_IO_APIC_pin(apic, pin);
449 int skip_ioapic_setup;
452 static int __init parse_noapic(char *str)
454 disable_ioapic_setup();
457 early_param("noapic", parse_noapic);
459 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
460 static int __init disable_timer_pin_setup(char *arg)
462 disable_timer_pin_1 = 1;
465 __setup("disable_timer_pin_1", disable_timer_pin_setup);
469 * Find the IRQ entry number of a certain pin.
471 static int find_irq_entry(int apic, int pin, int type)
475 for (i = 0; i < mp_irq_entries; i++)
476 if (mp_irqs[i].mp_irqtype == type &&
477 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
478 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
479 mp_irqs[i].mp_dstirq == pin)
486 * Find the pin to which IRQ[irq] (ISA) is connected
488 static int __init find_isa_irq_pin(int irq, int type)
492 for (i = 0; i < mp_irq_entries; i++) {
493 int lbus = mp_irqs[i].mp_srcbus;
495 if (test_bit(lbus, mp_bus_not_pci) &&
496 (mp_irqs[i].mp_irqtype == type) &&
497 (mp_irqs[i].mp_srcbusirq == irq))
499 return mp_irqs[i].mp_dstirq;
504 static int __init find_isa_irq_apic(int irq, int type)
508 for (i = 0; i < mp_irq_entries; i++) {
509 int lbus = mp_irqs[i].mp_srcbus;
511 if (test_bit(lbus, mp_bus_not_pci) &&
512 (mp_irqs[i].mp_irqtype == type) &&
513 (mp_irqs[i].mp_srcbusirq == irq))
516 if (i < mp_irq_entries) {
518 for(apic = 0; apic < nr_ioapics; apic++) {
519 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
528 * Find a specific PCI IRQ entry.
529 * Not an __init, possibly needed by modules
531 static int pin_2_irq(int idx, int apic, int pin);
533 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
535 int apic, i, best_guess = -1;
537 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
539 if (test_bit(bus, mp_bus_not_pci)) {
540 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
543 for (i = 0; i < mp_irq_entries; i++) {
544 int lbus = mp_irqs[i].mp_srcbus;
546 for (apic = 0; apic < nr_ioapics; apic++)
547 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
548 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
551 if (!test_bit(lbus, mp_bus_not_pci) &&
552 !mp_irqs[i].mp_irqtype &&
554 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
555 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
557 if (!(apic || IO_APIC_IRQ(irq)))
560 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
563 * Use the first all-but-pin matching entry as a
564 * best-guess fuzzy result for broken mptables.
570 BUG_ON(best_guess >= NR_IRQS);
574 /* ISA interrupts are always polarity zero edge triggered,
575 * when listed as conforming in the MP table. */
577 #define default_ISA_trigger(idx) (0)
578 #define default_ISA_polarity(idx) (0)
580 /* PCI interrupts are always polarity one level triggered,
581 * when listed as conforming in the MP table. */
583 #define default_PCI_trigger(idx) (1)
584 #define default_PCI_polarity(idx) (1)
586 static int MPBIOS_polarity(int idx)
588 int bus = mp_irqs[idx].mp_srcbus;
592 * Determine IRQ line polarity (high active or low active):
594 switch (mp_irqs[idx].mp_irqflag & 3)
596 case 0: /* conforms, ie. bus-type dependent polarity */
597 if (test_bit(bus, mp_bus_not_pci))
598 polarity = default_ISA_polarity(idx);
600 polarity = default_PCI_polarity(idx);
602 case 1: /* high active */
607 case 2: /* reserved */
609 printk(KERN_WARNING "broken BIOS!!\n");
613 case 3: /* low active */
618 default: /* invalid */
620 printk(KERN_WARNING "broken BIOS!!\n");
628 static int MPBIOS_trigger(int idx)
630 int bus = mp_irqs[idx].mp_srcbus;
634 * Determine IRQ trigger mode (edge or level sensitive):
636 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
638 case 0: /* conforms, ie. bus-type dependent */
639 if (test_bit(bus, mp_bus_not_pci))
640 trigger = default_ISA_trigger(idx);
642 trigger = default_PCI_trigger(idx);
649 case 2: /* reserved */
651 printk(KERN_WARNING "broken BIOS!!\n");
660 default: /* invalid */
662 printk(KERN_WARNING "broken BIOS!!\n");
670 static inline int irq_polarity(int idx)
672 return MPBIOS_polarity(idx);
675 static inline int irq_trigger(int idx)
677 return MPBIOS_trigger(idx);
680 static int pin_2_irq(int idx, int apic, int pin)
683 int bus = mp_irqs[idx].mp_srcbus;
686 * Debugging check, we are in big trouble if this message pops up!
688 if (mp_irqs[idx].mp_dstirq != pin)
689 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
691 if (test_bit(bus, mp_bus_not_pci)) {
692 irq = mp_irqs[idx].mp_srcbusirq;
695 * PCI IRQs are mapped in order
699 irq += nr_ioapic_registers[i++];
702 BUG_ON(irq >= NR_IRQS);
706 static int __assign_irq_vector(int irq, cpumask_t mask)
709 * NOTE! The local APIC isn't very good at handling
710 * multiple interrupts at the same interrupt level.
711 * As the interrupt level is determined by taking the
712 * vector number and shifting that right by 4, we
713 * want to spread these out a bit so that they don't
714 * all fall in the same interrupt level.
716 * Also, we've got to be careful not to trash gate
717 * 0x80, because int 0x80 is hm, kind of importantish. ;)
719 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
720 unsigned int old_vector;
724 BUG_ON((unsigned)irq >= NR_IRQS);
727 /* Only try and allocate irqs on cpus that are present */
728 cpus_and(mask, mask, cpu_online_map);
730 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
733 old_vector = cfg->vector;
736 cpus_and(tmp, cfg->domain, mask);
737 if (!cpus_empty(tmp))
741 for_each_cpu_mask(cpu, mask) {
742 cpumask_t domain, new_mask;
746 domain = vector_allocation_domain(cpu);
747 cpus_and(new_mask, domain, cpu_online_map);
749 vector = current_vector;
750 offset = current_offset;
753 if (vector >= first_system_vector) {
754 /* If we run out of vectors on large boxen, must share them. */
755 offset = (offset + 1) % 8;
756 vector = FIRST_DEVICE_VECTOR + offset;
758 if (unlikely(current_vector == vector))
760 if (vector == IA32_SYSCALL_VECTOR)
762 for_each_cpu_mask(new_cpu, new_mask)
763 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
766 current_vector = vector;
767 current_offset = offset;
769 cfg->move_in_progress = 1;
770 cfg->old_domain = cfg->domain;
772 for_each_cpu_mask(new_cpu, new_mask)
773 per_cpu(vector_irq, new_cpu)[vector] = irq;
774 cfg->vector = vector;
775 cfg->domain = domain;
781 static int assign_irq_vector(int irq, cpumask_t mask)
786 spin_lock_irqsave(&vector_lock, flags);
787 err = __assign_irq_vector(irq, mask);
788 spin_unlock_irqrestore(&vector_lock, flags);
792 static void __clear_irq_vector(int irq)
798 BUG_ON((unsigned)irq >= NR_IRQS);
800 BUG_ON(!cfg->vector);
802 vector = cfg->vector;
803 cpus_and(mask, cfg->domain, cpu_online_map);
804 for_each_cpu_mask(cpu, mask)
805 per_cpu(vector_irq, cpu)[vector] = -1;
808 cpus_clear(cfg->domain);
811 static void __setup_vector_irq(int cpu)
813 /* Initialize vector_irq on a new cpu */
814 /* This function must be called with vector_lock held */
817 /* Mark the inuse vectors */
818 for (irq = 0; irq < NR_IRQS; ++irq) {
819 if (!cpu_isset(cpu, irq_cfg[irq].domain))
821 vector = irq_cfg[irq].vector;
822 per_cpu(vector_irq, cpu)[vector] = irq;
824 /* Mark the free vectors */
825 for (vector = 0; vector < NR_VECTORS; ++vector) {
826 irq = per_cpu(vector_irq, cpu)[vector];
829 if (!cpu_isset(cpu, irq_cfg[irq].domain))
830 per_cpu(vector_irq, cpu)[vector] = -1;
834 void setup_vector_irq(int cpu)
836 spin_lock(&vector_lock);
837 __setup_vector_irq(smp_processor_id());
838 spin_unlock(&vector_lock);
842 static struct irq_chip ioapic_chip;
844 static void ioapic_register_intr(int irq, unsigned long trigger)
847 irq_desc[irq].status |= IRQ_LEVEL;
848 set_irq_chip_and_handler_name(irq, &ioapic_chip,
849 handle_fasteoi_irq, "fasteoi");
851 irq_desc[irq].status &= ~IRQ_LEVEL;
852 set_irq_chip_and_handler_name(irq, &ioapic_chip,
853 handle_edge_irq, "edge");
857 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
858 int trigger, int polarity)
860 struct irq_cfg *cfg = irq_cfg + irq;
861 struct IO_APIC_route_entry entry;
864 if (!IO_APIC_IRQ(irq))
868 if (assign_irq_vector(irq, mask))
871 cpus_and(mask, cfg->domain, mask);
873 apic_printk(APIC_VERBOSE,KERN_DEBUG
874 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
875 "IRQ %d Mode:%i Active:%i)\n",
876 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
877 irq, trigger, polarity);
880 * add it to the IO-APIC irq-routing table:
882 memset(&entry,0,sizeof(entry));
884 entry.delivery_mode = INT_DELIVERY_MODE;
885 entry.dest_mode = INT_DEST_MODE;
886 entry.dest = cpu_mask_to_apicid(mask);
887 entry.mask = 0; /* enable IRQ */
888 entry.trigger = trigger;
889 entry.polarity = polarity;
890 entry.vector = cfg->vector;
892 /* Mask level triggered irqs.
893 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
898 ioapic_register_intr(irq, trigger);
900 disable_8259A_irq(irq);
902 ioapic_write_entry(apic, pin, entry);
905 static void __init setup_IO_APIC_irqs(void)
907 int apic, pin, idx, irq, first_notcon = 1;
909 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
911 for (apic = 0; apic < nr_ioapics; apic++) {
912 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
914 idx = find_irq_entry(apic,pin,mp_INT);
917 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
920 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
924 apic_printk(APIC_VERBOSE, " not connected.\n");
928 irq = pin_2_irq(idx, apic, pin);
929 add_pin_to_irq(irq, apic, pin);
931 setup_IO_APIC_irq(apic, pin, irq,
932 irq_trigger(idx), irq_polarity(idx));
937 apic_printk(APIC_VERBOSE, " not connected.\n");
941 * Set up the timer pin, possibly with the 8259A-master behind.
943 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
946 struct IO_APIC_route_entry entry;
948 memset(&entry, 0, sizeof(entry));
951 * We use logical delivery to get the timer IRQ
954 entry.dest_mode = INT_DEST_MODE;
955 entry.mask = 1; /* mask IRQ now */
956 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
957 entry.delivery_mode = INT_DELIVERY_MODE;
960 entry.vector = vector;
963 * The timer IRQ doesn't have to know that behind the
964 * scene we may have a 8259A-master in AEOI mode ...
966 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
969 * Add it to the IO-APIC irq-routing table:
971 ioapic_write_entry(apic, pin, entry);
974 void __apicdebuginit print_IO_APIC(void)
977 union IO_APIC_reg_00 reg_00;
978 union IO_APIC_reg_01 reg_01;
979 union IO_APIC_reg_02 reg_02;
982 if (apic_verbosity == APIC_QUIET)
985 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
986 for (i = 0; i < nr_ioapics; i++)
987 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
988 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
991 * We are a bit conservative about what we expect. We have to
992 * know about every hardware change ASAP.
994 printk(KERN_INFO "testing the IO APIC.......................\n");
996 for (apic = 0; apic < nr_ioapics; apic++) {
998 spin_lock_irqsave(&ioapic_lock, flags);
999 reg_00.raw = io_apic_read(apic, 0);
1000 reg_01.raw = io_apic_read(apic, 1);
1001 if (reg_01.bits.version >= 0x10)
1002 reg_02.raw = io_apic_read(apic, 2);
1003 spin_unlock_irqrestore(&ioapic_lock, flags);
1006 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1007 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1008 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1010 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1011 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1013 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1014 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1016 if (reg_01.bits.version >= 0x10) {
1017 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1018 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1021 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1023 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1024 " Stat Dmod Deli Vect: \n");
1026 for (i = 0; i <= reg_01.bits.entries; i++) {
1027 struct IO_APIC_route_entry entry;
1029 entry = ioapic_read_entry(apic, i);
1031 printk(KERN_DEBUG " %02x %03X ",
1036 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1041 entry.delivery_status,
1043 entry.delivery_mode,
1048 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1049 for (i = 0; i < NR_IRQS; i++) {
1050 struct irq_pin_list *entry = irq_2_pin + i;
1053 printk(KERN_DEBUG "IRQ%d ", i);
1055 printk("-> %d:%d", entry->apic, entry->pin);
1058 entry = irq_2_pin + entry->next;
1063 printk(KERN_INFO ".................................... done.\n");
1070 static __apicdebuginit void print_APIC_bitfield (int base)
1075 if (apic_verbosity == APIC_QUIET)
1078 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1079 for (i = 0; i < 8; i++) {
1080 v = apic_read(base + i*0x10);
1081 for (j = 0; j < 32; j++) {
1091 void __apicdebuginit print_local_APIC(void * dummy)
1093 unsigned int v, ver, maxlvt;
1095 if (apic_verbosity == APIC_QUIET)
1098 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1099 smp_processor_id(), hard_smp_processor_id());
1100 v = apic_read(APIC_ID);
1101 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1102 v = apic_read(APIC_LVR);
1103 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1104 ver = GET_APIC_VERSION(v);
1105 maxlvt = lapic_get_maxlvt();
1107 v = apic_read(APIC_TASKPRI);
1108 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1110 v = apic_read(APIC_ARBPRI);
1111 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1112 v & APIC_ARBPRI_MASK);
1113 v = apic_read(APIC_PROCPRI);
1114 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1116 v = apic_read(APIC_EOI);
1117 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1118 v = apic_read(APIC_RRR);
1119 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1120 v = apic_read(APIC_LDR);
1121 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1122 v = apic_read(APIC_DFR);
1123 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1124 v = apic_read(APIC_SPIV);
1125 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1127 printk(KERN_DEBUG "... APIC ISR field:\n");
1128 print_APIC_bitfield(APIC_ISR);
1129 printk(KERN_DEBUG "... APIC TMR field:\n");
1130 print_APIC_bitfield(APIC_TMR);
1131 printk(KERN_DEBUG "... APIC IRR field:\n");
1132 print_APIC_bitfield(APIC_IRR);
1134 v = apic_read(APIC_ESR);
1135 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1137 v = apic_read(APIC_ICR);
1138 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1139 v = apic_read(APIC_ICR2);
1140 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1142 v = apic_read(APIC_LVTT);
1143 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1145 if (maxlvt > 3) { /* PC is LVT#4. */
1146 v = apic_read(APIC_LVTPC);
1147 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1149 v = apic_read(APIC_LVT0);
1150 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1151 v = apic_read(APIC_LVT1);
1152 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1154 if (maxlvt > 2) { /* ERR is LVT#3. */
1155 v = apic_read(APIC_LVTERR);
1156 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1159 v = apic_read(APIC_TMICT);
1160 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1161 v = apic_read(APIC_TMCCT);
1162 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1163 v = apic_read(APIC_TDCR);
1164 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1168 void print_all_local_APICs (void)
1170 on_each_cpu(print_local_APIC, NULL, 1, 1);
1173 void __apicdebuginit print_PIC(void)
1176 unsigned long flags;
1178 if (apic_verbosity == APIC_QUIET)
1181 printk(KERN_DEBUG "\nprinting PIC contents\n");
1183 spin_lock_irqsave(&i8259A_lock, flags);
1185 v = inb(0xa1) << 8 | inb(0x21);
1186 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1188 v = inb(0xa0) << 8 | inb(0x20);
1189 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1193 v = inb(0xa0) << 8 | inb(0x20);
1197 spin_unlock_irqrestore(&i8259A_lock, flags);
1199 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1201 v = inb(0x4d1) << 8 | inb(0x4d0);
1202 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1207 void __init enable_IO_APIC(void)
1209 union IO_APIC_reg_01 reg_01;
1210 int i8259_apic, i8259_pin;
1212 unsigned long flags;
1214 for (i = 0; i < PIN_MAP_SIZE; i++) {
1215 irq_2_pin[i].pin = -1;
1216 irq_2_pin[i].next = 0;
1220 * The number of IO-APIC IRQ registers (== #pins):
1222 for (apic = 0; apic < nr_ioapics; apic++) {
1223 spin_lock_irqsave(&ioapic_lock, flags);
1224 reg_01.raw = io_apic_read(apic, 1);
1225 spin_unlock_irqrestore(&ioapic_lock, flags);
1226 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1228 for(apic = 0; apic < nr_ioapics; apic++) {
1230 /* See if any of the pins is in ExtINT mode */
1231 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1232 struct IO_APIC_route_entry entry;
1233 entry = ioapic_read_entry(apic, pin);
1235 /* If the interrupt line is enabled and in ExtInt mode
1236 * I have found the pin where the i8259 is connected.
1238 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1239 ioapic_i8259.apic = apic;
1240 ioapic_i8259.pin = pin;
1246 /* Look to see what if the MP table has reported the ExtINT */
1247 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1248 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1249 /* Trust the MP table if nothing is setup in the hardware */
1250 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1251 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1252 ioapic_i8259.pin = i8259_pin;
1253 ioapic_i8259.apic = i8259_apic;
1255 /* Complain if the MP table and the hardware disagree */
1256 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1257 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1259 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1263 * Do not trust the IO-APIC being empty at bootup
1269 * Not an __init, needed by the reboot code
1271 void disable_IO_APIC(void)
1274 * Clear the IO-APIC before rebooting:
1279 * If the i8259 is routed through an IOAPIC
1280 * Put that IOAPIC in virtual wire mode
1281 * so legacy interrupts can be delivered.
1283 if (ioapic_i8259.pin != -1) {
1284 struct IO_APIC_route_entry entry;
1286 memset(&entry, 0, sizeof(entry));
1287 entry.mask = 0; /* Enabled */
1288 entry.trigger = 0; /* Edge */
1290 entry.polarity = 0; /* High */
1291 entry.delivery_status = 0;
1292 entry.dest_mode = 0; /* Physical */
1293 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1295 entry.dest = GET_APIC_ID(read_apic_id());
1298 * Add it to the IO-APIC irq-routing table:
1300 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1303 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1307 * There is a nasty bug in some older SMP boards, their mptable lies
1308 * about the timer IRQ. We do the following to work around the situation:
1310 * - timer IRQ defaults to IO-APIC IRQ
1311 * - if this function detects that timer IRQs are defunct, then we fall
1312 * back to ISA timer IRQs
1314 static int __init timer_irq_works(void)
1316 unsigned long t1 = jiffies;
1317 unsigned long flags;
1319 local_save_flags(flags);
1321 /* Let ten ticks pass... */
1322 mdelay((10 * 1000) / HZ);
1323 local_irq_restore(flags);
1326 * Expect a few ticks at least, to be sure some possible
1327 * glue logic does not lock up after one or two first
1328 * ticks in a non-ExtINT mode. Also the local APIC
1329 * might have cached one ExtINT interrupt. Finally, at
1330 * least one tick may be lost due to delays.
1334 if (time_after(jiffies, t1 + 4))
1340 * In the SMP+IOAPIC case it might happen that there are an unspecified
1341 * number of pending IRQ events unhandled. These cases are very rare,
1342 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1343 * better to do it this way as thus we do not have to be aware of
1344 * 'pending' interrupts in the IRQ path, except at this point.
1347 * Edge triggered needs to resend any interrupt
1348 * that was delayed but this is now handled in the device
1353 * Starting up a edge-triggered IO-APIC interrupt is
1354 * nasty - we need to make sure that we get the edge.
1355 * If it is already asserted for some reason, we need
1356 * return 1 to indicate that is was pending.
1358 * This is not complete - we should be able to fake
1359 * an edge even if it isn't on the 8259A...
1362 static unsigned int startup_ioapic_irq(unsigned int irq)
1364 int was_pending = 0;
1365 unsigned long flags;
1367 spin_lock_irqsave(&ioapic_lock, flags);
1369 disable_8259A_irq(irq);
1370 if (i8259A_irq_pending(irq))
1373 __unmask_IO_APIC_irq(irq);
1374 spin_unlock_irqrestore(&ioapic_lock, flags);
1379 static int ioapic_retrigger_irq(unsigned int irq)
1381 struct irq_cfg *cfg = &irq_cfg[irq];
1383 unsigned long flags;
1385 spin_lock_irqsave(&vector_lock, flags);
1386 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1387 send_IPI_mask(mask, cfg->vector);
1388 spin_unlock_irqrestore(&vector_lock, flags);
1394 * Level and edge triggered IO-APIC interrupts need different handling,
1395 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1396 * handled with the level-triggered descriptor, but that one has slightly
1397 * more overhead. Level-triggered interrupts cannot be handled with the
1398 * edge-triggered handler, without risking IRQ storms and other ugly
1403 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1405 unsigned vector, me;
1410 me = smp_processor_id();
1411 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1413 struct irq_desc *desc;
1414 struct irq_cfg *cfg;
1415 irq = __get_cpu_var(vector_irq)[vector];
1419 desc = irq_desc + irq;
1420 cfg = irq_cfg + irq;
1421 spin_lock(&desc->lock);
1422 if (!cfg->move_cleanup_count)
1425 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1428 __get_cpu_var(vector_irq)[vector] = -1;
1429 cfg->move_cleanup_count--;
1431 spin_unlock(&desc->lock);
1437 static void irq_complete_move(unsigned int irq)
1439 struct irq_cfg *cfg = irq_cfg + irq;
1440 unsigned vector, me;
1442 if (likely(!cfg->move_in_progress))
1445 vector = ~get_irq_regs()->orig_ax;
1446 me = smp_processor_id();
1447 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1448 cpumask_t cleanup_mask;
1450 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1451 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1452 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1453 cfg->move_in_progress = 0;
1457 static inline void irq_complete_move(unsigned int irq) {}
1460 static void ack_apic_edge(unsigned int irq)
1462 irq_complete_move(irq);
1463 move_native_irq(irq);
1467 static void ack_apic_level(unsigned int irq)
1469 int do_unmask_irq = 0;
1471 irq_complete_move(irq);
1472 #ifdef CONFIG_GENERIC_PENDING_IRQ
1473 /* If we are moving the irq we need to mask it */
1474 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1476 mask_IO_APIC_irq(irq);
1481 * We must acknowledge the irq before we move it or the acknowledge will
1482 * not propagate properly.
1486 /* Now we can move and renable the irq */
1487 if (unlikely(do_unmask_irq)) {
1488 /* Only migrate the irq if the ack has been received.
1490 * On rare occasions the broadcast level triggered ack gets
1491 * delayed going to ioapics, and if we reprogram the
1492 * vector while Remote IRR is still set the irq will never
1495 * To prevent this scenario we read the Remote IRR bit
1496 * of the ioapic. This has two effects.
1497 * - On any sane system the read of the ioapic will
1498 * flush writes (and acks) going to the ioapic from
1500 * - We get to see if the ACK has actually been delivered.
1502 * Based on failed experiments of reprogramming the
1503 * ioapic entry from outside of irq context starting
1504 * with masking the ioapic entry and then polling until
1505 * Remote IRR was clear before reprogramming the
1506 * ioapic I don't trust the Remote IRR bit to be
1507 * completey accurate.
1509 * However there appears to be no other way to plug
1510 * this race, so if the Remote IRR bit is not
1511 * accurate and is causing problems then it is a hardware bug
1512 * and you can go talk to the chipset vendor about it.
1514 if (!io_apic_level_ack_pending(irq))
1515 move_masked_irq(irq);
1516 unmask_IO_APIC_irq(irq);
1520 static struct irq_chip ioapic_chip __read_mostly = {
1522 .startup = startup_ioapic_irq,
1523 .mask = mask_IO_APIC_irq,
1524 .unmask = unmask_IO_APIC_irq,
1525 .ack = ack_apic_edge,
1526 .eoi = ack_apic_level,
1528 .set_affinity = set_ioapic_affinity_irq,
1530 .retrigger = ioapic_retrigger_irq,
1533 static inline void init_IO_APIC_traps(void)
1538 * NOTE! The local APIC isn't very good at handling
1539 * multiple interrupts at the same interrupt level.
1540 * As the interrupt level is determined by taking the
1541 * vector number and shifting that right by 4, we
1542 * want to spread these out a bit so that they don't
1543 * all fall in the same interrupt level.
1545 * Also, we've got to be careful not to trash gate
1546 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1548 for (irq = 0; irq < NR_IRQS ; irq++) {
1549 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1551 * Hmm.. We don't have an entry for this,
1552 * so default to an old-fashioned 8259
1553 * interrupt if we can..
1556 make_8259A_irq(irq);
1558 /* Strange. Oh, well.. */
1559 irq_desc[irq].chip = &no_irq_chip;
1564 static void unmask_lapic_irq(unsigned int irq)
1568 v = apic_read(APIC_LVT0);
1569 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1572 static void mask_lapic_irq(unsigned int irq)
1576 v = apic_read(APIC_LVT0);
1577 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1580 static void ack_lapic_irq (unsigned int irq)
1585 static struct irq_chip lapic_chip __read_mostly = {
1586 .name = "local-APIC",
1587 .mask = mask_lapic_irq,
1588 .unmask = unmask_lapic_irq,
1589 .ack = ack_lapic_irq,
1592 static void lapic_register_intr(int irq)
1594 irq_desc[irq].status &= ~IRQ_LEVEL;
1595 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1599 static void __init setup_nmi(void)
1602 * Dirty trick to enable the NMI watchdog ...
1603 * We put the 8259A master into AEOI mode and
1604 * unmask on all local APICs LVT0 as NMI.
1606 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1607 * is from Maciej W. Rozycki - so we do not have to EOI from
1608 * the NMI handler or the timer interrupt.
1610 printk(KERN_INFO "activating NMI Watchdog ...");
1612 enable_NMI_through_LVT0();
1618 * This looks a bit hackish but it's about the only one way of sending
1619 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1620 * not support the ExtINT mode, unfortunately. We need to send these
1621 * cycles as some i82489DX-based boards have glue logic that keeps the
1622 * 8259A interrupt line asserted until INTA. --macro
1624 static inline void __init unlock_ExtINT_logic(void)
1627 struct IO_APIC_route_entry entry0, entry1;
1628 unsigned char save_control, save_freq_select;
1630 pin = find_isa_irq_pin(8, mp_INT);
1631 apic = find_isa_irq_apic(8, mp_INT);
1635 entry0 = ioapic_read_entry(apic, pin);
1637 clear_IO_APIC_pin(apic, pin);
1639 memset(&entry1, 0, sizeof(entry1));
1641 entry1.dest_mode = 0; /* physical delivery */
1642 entry1.mask = 0; /* unmask IRQ now */
1643 entry1.dest = hard_smp_processor_id();
1644 entry1.delivery_mode = dest_ExtINT;
1645 entry1.polarity = entry0.polarity;
1649 ioapic_write_entry(apic, pin, entry1);
1651 save_control = CMOS_READ(RTC_CONTROL);
1652 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1653 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1655 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1660 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1664 CMOS_WRITE(save_control, RTC_CONTROL);
1665 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1666 clear_IO_APIC_pin(apic, pin);
1668 ioapic_write_entry(apic, pin, entry0);
1672 * This code may look a bit paranoid, but it's supposed to cooperate with
1673 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1674 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1675 * fanatically on his truly buggy board.
1677 * FIXME: really need to revamp this for modern platforms only.
1679 static inline void __init check_timer(void)
1681 struct irq_cfg *cfg = irq_cfg + 0;
1682 int apic1, pin1, apic2, pin2;
1683 unsigned long flags;
1686 local_irq_save(flags);
1689 * get/set the timer IRQ vector:
1691 disable_8259A_irq(0);
1692 assign_irq_vector(0, TARGET_CPUS);
1695 * As IRQ0 is to be enabled in the 8259A, the virtual
1696 * wire has to be disabled in the local APIC.
1698 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1701 pin1 = find_isa_irq_pin(0, mp_INT);
1702 apic1 = find_isa_irq_apic(0, mp_INT);
1703 pin2 = ioapic_i8259.pin;
1704 apic2 = ioapic_i8259.apic;
1706 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1707 cfg->vector, apic1, pin1, apic2, pin2);
1709 if (mask_ioapic_irq_2)
1710 mask_IO_APIC_irq(2);
1713 * Some BIOS writers are clueless and report the ExtINTA
1714 * I/O APIC input from the cascaded 8259A as the timer
1715 * interrupt input. So just in case, if only one pin
1716 * was found above, try it both directly and through the
1723 } else if (pin2 == -1) {
1730 * Ok, does IRQ0 through the IOAPIC work?
1733 add_pin_to_irq(0, apic1, pin1);
1734 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1736 unmask_IO_APIC_irq(0);
1737 if (!no_timer_check && timer_irq_works()) {
1738 if (nmi_watchdog == NMI_IO_APIC) {
1740 enable_8259A_irq(0);
1742 if (disable_timer_pin_1 > 0)
1743 clear_IO_APIC_pin(0, pin1);
1746 clear_IO_APIC_pin(apic1, pin1);
1748 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1749 "8254 timer not connected to IO-APIC\n");
1751 apic_printk(APIC_VERBOSE,KERN_INFO
1752 "...trying to set up timer (IRQ0) "
1753 "through the 8259A ... ");
1754 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1757 * legacy devices should be connected to IO APIC #0
1759 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1760 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1761 unmask_IO_APIC_irq(0);
1762 enable_8259A_irq(0);
1763 if (timer_irq_works()) {
1764 apic_printk(APIC_VERBOSE," works.\n");
1765 timer_through_8259 = 1;
1766 if (nmi_watchdog == NMI_IO_APIC) {
1767 disable_8259A_irq(0);
1769 enable_8259A_irq(0);
1774 * Cleanup, just in case ...
1776 disable_8259A_irq(0);
1777 clear_IO_APIC_pin(apic2, pin2);
1778 apic_printk(APIC_VERBOSE," failed.\n");
1781 if (nmi_watchdog == NMI_IO_APIC) {
1782 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1783 nmi_watchdog = NMI_NONE;
1786 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1788 lapic_register_intr(0);
1789 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1790 enable_8259A_irq(0);
1792 if (timer_irq_works()) {
1793 apic_printk(APIC_VERBOSE," works.\n");
1796 disable_8259A_irq(0);
1797 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1798 apic_printk(APIC_VERBOSE," failed.\n");
1800 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1804 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1806 unlock_ExtINT_logic();
1808 if (timer_irq_works()) {
1809 apic_printk(APIC_VERBOSE," works.\n");
1812 apic_printk(APIC_VERBOSE," failed :(.\n");
1813 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1815 local_irq_restore(flags);
1818 static int __init notimercheck(char *s)
1823 __setup("no_timer_check", notimercheck);
1826 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
1827 * to devices. However there may be an I/O APIC pin available for
1828 * this interrupt regardless. The pin may be left unconnected, but
1829 * typically it will be reused as an ExtINT cascade interrupt for
1830 * the master 8259A. In the MPS case such a pin will normally be
1831 * reported as an ExtINT interrupt in the MP table. With ACPI
1832 * there is no provision for ExtINT interrupts, and in the absence
1833 * of an override it would be treated as an ordinary ISA I/O APIC
1834 * interrupt, that is edge-triggered and unmasked by default. We
1835 * used to do this, but it caused problems on some systems because
1836 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
1837 * the same ExtINT cascade interrupt to drive the local APIC of the
1838 * bootstrap processor. Therefore we refrain from routing IRQ2 to
1839 * the I/O APIC in all cases now. No actual device should request
1840 * it anyway. --macro
1842 #define PIC_IRQS (1<<2)
1844 void __init setup_IO_APIC(void)
1848 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1851 io_apic_irqs = ~PIC_IRQS;
1853 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1856 setup_IO_APIC_irqs();
1857 init_IO_APIC_traps();
1863 struct sysfs_ioapic_data {
1864 struct sys_device dev;
1865 struct IO_APIC_route_entry entry[0];
1867 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1869 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1871 struct IO_APIC_route_entry *entry;
1872 struct sysfs_ioapic_data *data;
1875 data = container_of(dev, struct sysfs_ioapic_data, dev);
1876 entry = data->entry;
1877 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1878 *entry = ioapic_read_entry(dev->id, i);
1883 static int ioapic_resume(struct sys_device *dev)
1885 struct IO_APIC_route_entry *entry;
1886 struct sysfs_ioapic_data *data;
1887 unsigned long flags;
1888 union IO_APIC_reg_00 reg_00;
1891 data = container_of(dev, struct sysfs_ioapic_data, dev);
1892 entry = data->entry;
1894 spin_lock_irqsave(&ioapic_lock, flags);
1895 reg_00.raw = io_apic_read(dev->id, 0);
1896 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
1897 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1898 io_apic_write(dev->id, 0, reg_00.raw);
1900 spin_unlock_irqrestore(&ioapic_lock, flags);
1901 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1902 ioapic_write_entry(dev->id, i, entry[i]);
1907 static struct sysdev_class ioapic_sysdev_class = {
1909 .suspend = ioapic_suspend,
1910 .resume = ioapic_resume,
1913 static int __init ioapic_init_sysfs(void)
1915 struct sys_device * dev;
1918 error = sysdev_class_register(&ioapic_sysdev_class);
1922 for (i = 0; i < nr_ioapics; i++ ) {
1923 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1924 * sizeof(struct IO_APIC_route_entry);
1925 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1926 if (!mp_ioapic_data[i]) {
1927 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1930 dev = &mp_ioapic_data[i]->dev;
1932 dev->cls = &ioapic_sysdev_class;
1933 error = sysdev_register(dev);
1935 kfree(mp_ioapic_data[i]);
1936 mp_ioapic_data[i] = NULL;
1937 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1945 device_initcall(ioapic_init_sysfs);
1948 * Dynamic irq allocate and deallocation
1950 int create_irq(void)
1952 /* Allocate an unused irq */
1955 unsigned long flags;
1958 spin_lock_irqsave(&vector_lock, flags);
1959 for (new = (NR_IRQS - 1); new >= 0; new--) {
1960 if (platform_legacy_irq(new))
1962 if (irq_cfg[new].vector != 0)
1964 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1968 spin_unlock_irqrestore(&vector_lock, flags);
1971 dynamic_irq_init(irq);
1976 void destroy_irq(unsigned int irq)
1978 unsigned long flags;
1980 dynamic_irq_cleanup(irq);
1982 spin_lock_irqsave(&vector_lock, flags);
1983 __clear_irq_vector(irq);
1984 spin_unlock_irqrestore(&vector_lock, flags);
1988 * MSI message composition
1990 #ifdef CONFIG_PCI_MSI
1991 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1993 struct irq_cfg *cfg = irq_cfg + irq;
1999 err = assign_irq_vector(irq, tmp);
2001 cpus_and(tmp, cfg->domain, tmp);
2002 dest = cpu_mask_to_apicid(tmp);
2004 msg->address_hi = MSI_ADDR_BASE_HI;
2007 ((INT_DEST_MODE == 0) ?
2008 MSI_ADDR_DEST_MODE_PHYSICAL:
2009 MSI_ADDR_DEST_MODE_LOGICAL) |
2010 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2011 MSI_ADDR_REDIRECTION_CPU:
2012 MSI_ADDR_REDIRECTION_LOWPRI) |
2013 MSI_ADDR_DEST_ID(dest);
2016 MSI_DATA_TRIGGER_EDGE |
2017 MSI_DATA_LEVEL_ASSERT |
2018 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2019 MSI_DATA_DELIVERY_FIXED:
2020 MSI_DATA_DELIVERY_LOWPRI) |
2021 MSI_DATA_VECTOR(cfg->vector);
2027 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2029 struct irq_cfg *cfg = irq_cfg + irq;
2034 cpus_and(tmp, mask, cpu_online_map);
2035 if (cpus_empty(tmp))
2038 if (assign_irq_vector(irq, mask))
2041 cpus_and(tmp, cfg->domain, mask);
2042 dest = cpu_mask_to_apicid(tmp);
2044 read_msi_msg(irq, &msg);
2046 msg.data &= ~MSI_DATA_VECTOR_MASK;
2047 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2048 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2049 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2051 write_msi_msg(irq, &msg);
2052 irq_desc[irq].affinity = mask;
2054 #endif /* CONFIG_SMP */
2057 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2058 * which implement the MSI or MSI-X Capability Structure.
2060 static struct irq_chip msi_chip = {
2062 .unmask = unmask_msi_irq,
2063 .mask = mask_msi_irq,
2064 .ack = ack_apic_edge,
2066 .set_affinity = set_msi_irq_affinity,
2068 .retrigger = ioapic_retrigger_irq,
2071 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2079 ret = msi_compose_msg(dev, irq, &msg);
2085 set_irq_msi(irq, desc);
2086 write_msi_msg(irq, &msg);
2088 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2093 void arch_teardown_msi_irq(unsigned int irq)
2100 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2102 struct irq_cfg *cfg = irq_cfg + irq;
2107 cpus_and(tmp, mask, cpu_online_map);
2108 if (cpus_empty(tmp))
2111 if (assign_irq_vector(irq, mask))
2114 cpus_and(tmp, cfg->domain, mask);
2115 dest = cpu_mask_to_apicid(tmp);
2117 dmar_msi_read(irq, &msg);
2119 msg.data &= ~MSI_DATA_VECTOR_MASK;
2120 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2121 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2122 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2124 dmar_msi_write(irq, &msg);
2125 irq_desc[irq].affinity = mask;
2127 #endif /* CONFIG_SMP */
2129 struct irq_chip dmar_msi_type = {
2131 .unmask = dmar_msi_unmask,
2132 .mask = dmar_msi_mask,
2133 .ack = ack_apic_edge,
2135 .set_affinity = dmar_msi_set_affinity,
2137 .retrigger = ioapic_retrigger_irq,
2140 int arch_setup_dmar_msi(unsigned int irq)
2145 ret = msi_compose_msg(NULL, irq, &msg);
2148 dmar_msi_write(irq, &msg);
2149 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2155 #endif /* CONFIG_PCI_MSI */
2157 * Hypertransport interrupt support
2159 #ifdef CONFIG_HT_IRQ
2163 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2165 struct ht_irq_msg msg;
2166 fetch_ht_irq_msg(irq, &msg);
2168 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2169 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2171 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2172 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2174 write_ht_irq_msg(irq, &msg);
2177 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2179 struct irq_cfg *cfg = irq_cfg + irq;
2183 cpus_and(tmp, mask, cpu_online_map);
2184 if (cpus_empty(tmp))
2187 if (assign_irq_vector(irq, mask))
2190 cpus_and(tmp, cfg->domain, mask);
2191 dest = cpu_mask_to_apicid(tmp);
2193 target_ht_irq(irq, dest, cfg->vector);
2194 irq_desc[irq].affinity = mask;
2198 static struct irq_chip ht_irq_chip = {
2200 .mask = mask_ht_irq,
2201 .unmask = unmask_ht_irq,
2202 .ack = ack_apic_edge,
2204 .set_affinity = set_ht_irq_affinity,
2206 .retrigger = ioapic_retrigger_irq,
2209 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2211 struct irq_cfg *cfg = irq_cfg + irq;
2216 err = assign_irq_vector(irq, tmp);
2218 struct ht_irq_msg msg;
2221 cpus_and(tmp, cfg->domain, tmp);
2222 dest = cpu_mask_to_apicid(tmp);
2224 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2228 HT_IRQ_LOW_DEST_ID(dest) |
2229 HT_IRQ_LOW_VECTOR(cfg->vector) |
2230 ((INT_DEST_MODE == 0) ?
2231 HT_IRQ_LOW_DM_PHYSICAL :
2232 HT_IRQ_LOW_DM_LOGICAL) |
2233 HT_IRQ_LOW_RQEOI_EDGE |
2234 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2235 HT_IRQ_LOW_MT_FIXED :
2236 HT_IRQ_LOW_MT_ARBITRATED) |
2237 HT_IRQ_LOW_IRQ_MASKED;
2239 write_ht_irq_msg(irq, &msg);
2241 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2242 handle_edge_irq, "edge");
2246 #endif /* CONFIG_HT_IRQ */
2248 /* --------------------------------------------------------------------------
2249 ACPI-based IOAPIC Configuration
2250 -------------------------------------------------------------------------- */
2254 #define IO_APIC_MAX_ID 0xFE
2256 int __init io_apic_get_redir_entries (int ioapic)
2258 union IO_APIC_reg_01 reg_01;
2259 unsigned long flags;
2261 spin_lock_irqsave(&ioapic_lock, flags);
2262 reg_01.raw = io_apic_read(ioapic, 1);
2263 spin_unlock_irqrestore(&ioapic_lock, flags);
2265 return reg_01.bits.entries;
2269 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2271 if (!IO_APIC_IRQ(irq)) {
2272 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2278 * IRQs < 16 are already in the irq_2_pin[] map
2281 add_pin_to_irq(irq, ioapic, pin);
2283 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2289 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2293 if (skip_ioapic_setup)
2296 for (i = 0; i < mp_irq_entries; i++)
2297 if (mp_irqs[i].mp_irqtype == mp_INT &&
2298 mp_irqs[i].mp_srcbusirq == bus_irq)
2300 if (i >= mp_irq_entries)
2303 *trigger = irq_trigger(i);
2304 *polarity = irq_polarity(i);
2308 #endif /* CONFIG_ACPI */
2311 * This function currently is only a helper for the i386 smp boot process where
2312 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2313 * so mask in all cases should simply be TARGET_CPUS
2316 void __init setup_ioapic_dest(void)
2318 int pin, ioapic, irq, irq_entry;
2320 if (skip_ioapic_setup == 1)
2323 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2324 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2325 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2326 if (irq_entry == -1)
2328 irq = pin_2_irq(irq_entry, ioapic, pin);
2330 /* setup_IO_APIC_irqs could fail to get vector for some device
2331 * when you have too many devices, because at that time only boot
2334 if (!irq_cfg[irq].vector)
2335 setup_IO_APIC_irq(ioapic, pin, irq,
2336 irq_trigger(irq_entry),
2337 irq_polarity(irq_entry));
2339 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2346 #define IOAPIC_RESOURCE_NAME_SIZE 11
2348 static struct resource *ioapic_resources;
2350 static struct resource * __init ioapic_setup_resources(void)
2353 struct resource *res;
2357 if (nr_ioapics <= 0)
2360 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2363 mem = alloc_bootmem(n);
2367 mem += sizeof(struct resource) * nr_ioapics;
2369 for (i = 0; i < nr_ioapics; i++) {
2371 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2372 sprintf(mem, "IOAPIC %u", i);
2373 mem += IOAPIC_RESOURCE_NAME_SIZE;
2377 ioapic_resources = res;
2382 void __init ioapic_init_mappings(void)
2384 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2385 struct resource *ioapic_res;
2388 ioapic_res = ioapic_setup_resources();
2389 for (i = 0; i < nr_ioapics; i++) {
2390 if (smp_found_config) {
2391 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2393 ioapic_phys = (unsigned long)
2394 alloc_bootmem_pages(PAGE_SIZE);
2395 ioapic_phys = __pa(ioapic_phys);
2397 set_fixmap_nocache(idx, ioapic_phys);
2398 apic_printk(APIC_VERBOSE,
2399 "mapped IOAPIC to %016lx (%016lx)\n",
2400 __fix_to_virt(idx), ioapic_phys);
2403 if (ioapic_res != NULL) {
2404 ioapic_res->start = ioapic_phys;
2405 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2411 static int __init ioapic_insert_resources(void)
2414 struct resource *r = ioapic_resources;
2418 "IO APIC resources could be not be allocated.\n");
2422 for (i = 0; i < nr_ioapics; i++) {
2423 insert_resource(&iomem_resource, r);
2430 /* Insert the IO APIC resources after PCI initialization has occured to handle
2431 * IO APICS that are mapped in on a BAR in PCI space. */
2432 late_initcall(ioapic_insert_resources);