2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
15 * it to save wrong values... Be aware!
17 #include <linux/config.h>
19 #include <asm/memory.h>
21 #include <asm/vfpmacros.h>
22 #include <asm/arch/entry-macro.S>
23 #include <asm/thread_notify.h>
25 #include "entry-header.S"
28 * Interrupt handling. Preserves r7, r8, r9
31 1: get_irqnr_and_base r0, r6, r5, lr
34 @ routine called with r0 = irq number, r1 = struct pt_regs *
43 * this macro assumes that irqstat (r6) and base (r5) are
44 * preserved from get_irqnr_and_base above
46 test_for_ipi r0, r6, r5, lr
51 #ifdef CONFIG_LOCAL_TIMERS
52 test_for_ltirq r0, r6, r5, lr
62 * Invalid mode handlers
64 .macro inv_entry, reason
65 sub sp, sp, #S_FRAME_SIZE
71 inv_entry BAD_PREFETCH
83 inv_entry BAD_UNDEFINSTR
86 @ XXX fall through to common_invalid
90 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
96 add r0, sp, #S_PC @ here for interlock avoidance
97 mov r7, #-1 @ "" "" "" ""
98 str r4, [sp] @ save preserved r0
99 stmia r0, {r5 - r7} @ lr_<exception>,
100 @ cpsr_<exception>, "old_r0"
110 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
111 #define SPFIX(code...) code
113 #define SPFIX(code...)
117 sub sp, sp, #S_FRAME_SIZE
119 SPFIX( bicne sp, sp, #4 )
123 add r5, sp, #S_SP @ here for interlock avoidance
124 mov r4, #-1 @ "" "" "" ""
125 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
126 SPFIX( addne r0, r0, #4 )
127 str r1, [sp] @ save the "real" r0 copied
128 @ from the exception stack
133 @ We are now ready to fill in the remaining blanks on the stack:
137 @ r2 - lr_<exception>, already fixed up for correct return/restart
138 @ r3 - spsr_<exception>
139 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
149 @ get ready to re-enable interrupts if appropriate
153 biceq r9, r9, #PSR_I_BIT
156 @ Call the processor-specific abort handler:
158 @ r2 - aborted context pc
159 @ r3 - aborted context cpsr
161 @ The abort handler must return the aborted address in r0, and
162 @ the fault status register in r1. r9 must be preserved.
173 @ set desired IRQ state, then call main handler
180 @ IRQs off again before pulling preserved data off the stack
185 @ restore SPSR and restart the instruction
189 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
195 #ifdef CONFIG_PREEMPT
197 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
198 add r7, r8, #1 @ increment it
199 str r7, [tsk, #TI_PREEMPT]
203 #ifdef CONFIG_PREEMPT
204 ldr r0, [tsk, #TI_FLAGS] @ get flags
205 tst r0, #_TIF_NEED_RESCHED
208 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
209 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
211 strne r0, [r0, -r0] @ bug()
213 ldr r0, [sp, #S_PSR] @ irqs are already disabled
215 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
219 #ifdef CONFIG_PREEMPT
221 teq r8, #0 @ was preempt count = 0
222 ldreq r6, .LCirq_stat
224 ldr r0, [r6, #4] @ local_irq_count
225 ldr r1, [r6, #8] @ local_bh_count
228 mov r7, #0 @ preempt_schedule_irq
229 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
230 1: bl preempt_schedule_irq @ irq en/disable is done inside
231 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
232 tst r0, #_TIF_NEED_RESCHED
233 beq preempt_return @ go again
242 @ call emulation code, which returns using r9 if it has emulated
243 @ the instruction, or the more conventional lr if we are to treat
244 @ this as a real undefined instruction
252 mov r0, sp @ struct pt_regs *regs
256 @ IRQs off again before pulling preserved data off the stack
261 @ restore SPSR and restart the instruction
263 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
265 ldmia sp, {r0 - pc}^ @ Restore SVC registers
272 @ re-enable interrupts if appropriate
276 biceq r9, r9, #PSR_I_BIT
280 @ set args, then call main handler
282 @ r0 - address of faulting instruction
283 @ r1 - pointer to registers on stack
285 mov r0, r2 @ address (pc)
287 bl do_PrefetchAbort @ call abort handler
290 @ IRQs off again before pulling preserved data off the stack
295 @ restore SPSR and restart the instruction
299 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
310 #ifdef CONFIG_PREEMPT
318 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
321 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
322 #error "sizeof(struct pt_regs) must be a multiple of 8"
326 sub sp, sp, #S_FRAME_SIZE
330 add r0, sp, #S_PC @ here for interlock avoidance
331 mov r4, #-1 @ "" "" "" ""
333 str r1, [sp] @ save the "real" r0 copied
334 @ from the exception stack
336 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
338 #warning "NPTL on non MMU needs fixing"
340 @ make sure our user space atomic helper is aborted
342 bichs r3, r3, #PSR_Z_BIT
347 @ We are now ready to fill in the remaining blanks on the stack:
349 @ r2 - lr_<exception>, already fixed up for correct return/restart
350 @ r3 - spsr_<exception>
351 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
353 @ Also, separately save sp_usr and lr_usr
359 @ Enable the alignment trap while in kernel mode
364 @ Clear FP to mark the first stack frame
374 @ Call the processor-specific abort handler:
376 @ r2 - aborted context pc
377 @ r3 - aborted context cpsr
379 @ The abort handler must return the aborted address in r0, and
380 @ the fault status register in r1.
391 @ IRQs on, then call the main handler
395 adr lr, ret_from_exception
403 #ifdef CONFIG_PREEMPT
404 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
405 add r7, r8, #1 @ increment it
406 str r7, [tsk, #TI_PREEMPT]
410 #ifdef CONFIG_PREEMPT
411 ldr r0, [tsk, #TI_PREEMPT]
412 str r8, [tsk, #TI_PREEMPT]
426 tst r3, #PSR_T_BIT @ Thumb mode?
427 bne fpundefinstr @ ignore FP
431 @ fall through to the emulation code, which returns using r9 if
432 @ it has emulated the instruction, or the more conventional lr
433 @ if we are to treat this as a real undefined instruction
438 adr r9, ret_from_exception
441 @ fallthrough to call_fpe
445 * The out of line fixup for the ldrt above.
447 .section .fixup, "ax"
450 .section __ex_table,"a"
455 * Check whether the instruction is a co-processor instruction.
456 * If yes, we need to call the relevant co-processor handler.
458 * Note that we don't do a full check here for the co-processor
459 * instructions; all instructions with bit 27 set are well
460 * defined. The only instructions that should fault are the
461 * co-processor instructions. However, we have to watch out
462 * for the ARM6/ARM7 SWI bug.
464 * Emulators may wish to make use of the following registers:
465 * r0 = instruction opcode.
467 * r10 = this threads thread_info structure.
470 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
471 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
472 and r8, r0, #0x0f000000 @ mask out op-code bits
473 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
476 get_thread_info r10 @ get current thread
477 and r8, r0, #0x00000f00 @ mask out CP number
479 add r6, r10, #TI_USED_CP
480 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
482 @ Test if we need to give access to iWMMXt coprocessors
483 ldr r5, [r10, #TI_FLAGS]
484 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
485 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
486 bcs iwmmxt_task_enable
488 add pc, pc, r8, lsr #6
492 b do_fpe @ CP#1 (FPE)
493 b do_fpe @ CP#2 (FPE)
496 b crunch_task_enable @ CP#4 (MaverickCrunch)
497 b crunch_task_enable @ CP#5 (MaverickCrunch)
498 b crunch_task_enable @ CP#6 (MaverickCrunch)
508 b do_vfp @ CP#10 (VFP)
509 b do_vfp @ CP#11 (VFP)
511 mov pc, lr @ CP#10 (VFP)
512 mov pc, lr @ CP#11 (VFP)
516 mov pc, lr @ CP#14 (Debug)
517 mov pc, lr @ CP#15 (Control)
522 add r10, r10, #TI_FPSTATE @ r10 = workspace
523 ldr pc, [r4] @ Call FP module USR entry point
526 * The FP module is called with these registers set:
529 * r9 = normal "successful" return address
531 * lr = unrecognised FP instruction return address
541 adr lr, ret_from_exception
548 enable_irq @ Enable interrupts
549 mov r0, r2 @ address (pc)
551 bl do_PrefetchAbort @ call abort handler
554 * This is the return code to user mode for abort handlers
556 ENTRY(ret_from_exception)
562 * Register switch for ARMv3 and ARMv4 processors
563 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
564 * previous and next are guaranteed not to be the same.
567 add ip, r1, #TI_CPU_SAVE
568 ldr r3, [r2, #TI_TP_VALUE]
569 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
571 ldr r6, [r2, #TI_CPU_DOMAIN]
573 #if __LINUX_ARM_ARCH__ >= 6
574 #ifdef CONFIG_CPU_32v6K
577 strex r5, r4, [ip] @ Clear exclusive monitor
580 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
584 #if defined(CONFIG_HAS_TLS_REG)
585 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
586 #elif !defined(CONFIG_TLS_REG_EMUL)
588 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
591 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
593 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
594 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
599 add r4, r2, #TI_CPU_SAVE
600 ldr r0, =thread_notify_head
601 mov r1, #THREAD_NOTIFY_SWITCH
602 bl atomic_notifier_call_chain
604 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
611 * These are segment of kernel provided user code reachable from user space
612 * at a fixed address in kernel memory. This is used to provide user space
613 * with some operations which require kernel help because of unimplemented
614 * native feature and/or instructions in many ARM CPUs. The idea is for
615 * this code to be executed directly in user mode for best efficiency but
616 * which is too intimate with the kernel counter part to be left to user
617 * libraries. In fact this code might even differ from one CPU to another
618 * depending on the available instruction set and restrictions like on
619 * SMP systems. In other words, the kernel reserves the right to change
620 * this code as needed without warning. Only the entry points and their
621 * results are guaranteed to be stable.
623 * Each segment is 32-byte aligned and will be moved to the top of the high
624 * vector page. New segments (if ever needed) must be added in front of
625 * existing ones. This mechanism should be used only for things that are
626 * really small and justified, and not be abused freely.
628 * User space is expected to implement those things inline when optimizing
629 * for a processor that has the necessary native support, but only if such
630 * resulting binaries are already to be incompatible with earlier ARM
631 * processors due to the use of unsupported instructions other than what
632 * is provided here. In other words don't make binaries unable to run on
633 * earlier processors just for the sake of not using these kernel helpers
634 * if your compiled code is not going to use the new instructions for other
639 .globl __kuser_helper_start
640 __kuser_helper_start:
643 * Reference prototype:
645 * void __kernel_memory_barrier(void)
649 * lr = return address
657 * the Z flag might be lost
659 * Definition and user space usage example:
661 * typedef void (__kernel_dmb_t)(void);
662 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
664 * Apply any needed memory barrier to preserve consistency with data modified
665 * manually and __kuser_cmpxchg usage.
667 * This could be used as follows:
669 * #define __kernel_dmb() \
670 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
671 * : : : "r0", "lr","cc" )
674 __kuser_memory_barrier: @ 0xffff0fa0
676 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
677 mcr p15, 0, r0, c7, c10, 5 @ dmb
684 * Reference prototype:
686 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
693 * lr = return address
697 * r0 = returned value (zero or non-zero)
698 * C flag = set if r0 == 0, clear if r0 != 0
704 * Definition and user space usage example:
706 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
707 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
709 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
710 * Return zero if *ptr was changed or non-zero if no exchange happened.
711 * The C flag is also set if *ptr was changed to allow for assembly
712 * optimization in the calling code.
716 * - This routine already includes memory barriers as needed.
718 * - A failure might be transient, i.e. it is possible, although unlikely,
719 * that "failure" be returned even if *ptr == oldval.
721 * For example, a user space atomic_add implementation could look like this:
723 * #define atomic_add(ptr, val) \
724 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
725 * register unsigned int __result asm("r1"); \
727 * "1: @ atomic_add\n\t" \
728 * "ldr r0, [r2]\n\t" \
729 * "mov r3, #0xffff0fff\n\t" \
730 * "add lr, pc, #4\n\t" \
731 * "add r1, r0, %2\n\t" \
732 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
734 * : "=&r" (__result) \
735 * : "r" (__ptr), "rIL" (val) \
736 * : "r0","r3","ip","lr","cc","memory" ); \
740 __kuser_cmpxchg: @ 0xffff0fc0
742 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
745 * Poor you. No fast solution possible...
746 * The kernel itself must perform the operation.
747 * A special ghost syscall is used for that (see traps.c).
750 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
755 #elif __LINUX_ARM_ARCH__ < 6
758 * Theory of operation:
760 * We set the Z flag before loading oldval. If ever an exception
761 * occurs we can not be sure the loaded value will still be the same
762 * when the exception returns, therefore the user exception handler
763 * will clear the Z flag whenever the interrupted user code was
764 * actually from the kernel address space (see the usr_entry macro).
766 * The post-increment on the str is used to prevent a race with an
767 * exception happening just after the str instruction which would
768 * clear the Z flag although the exchange was done.
771 teq ip, ip @ set Z flag
772 ldr ip, [r2] @ load current val
773 add r3, r2, #1 @ prepare store ptr
774 teqeq ip, r0 @ compare with oldval if still allowed
775 streq r1, [r3, #-1]! @ store newval if still allowed
776 subs r0, r2, r3 @ if r2 == r3 the str occured
778 #warning "NPTL on non MMU needs fixing"
787 mcr p15, 0, r0, c7, c10, 5 @ dmb
794 mcr p15, 0, r0, c7, c10, 5 @ dmb
803 * Reference prototype:
805 * int __kernel_get_tls(void)
809 * lr = return address
817 * the Z flag might be lost
819 * Definition and user space usage example:
821 * typedef int (__kernel_get_tls_t)(void);
822 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
824 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
826 * This could be used as follows:
828 * #define __kernel_get_tls() \
829 * ({ register unsigned int __val asm("r0"); \
830 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
831 * : "=r" (__val) : : "lr","cc" ); \
835 __kuser_get_tls: @ 0xffff0fe0
837 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
839 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
844 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
850 .word 0 @ pad up to __kuser_helper_version
854 * Reference declaration:
856 * extern unsigned int __kernel_helper_version;
858 * Definition and user space usage example:
860 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
862 * User space may read this to determine the curent number of helpers
866 __kuser_helper_version: @ 0xffff0ffc
867 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
869 .globl __kuser_helper_end
876 * This code is copied to 0xffff0200 so we can use branches in the
877 * vectors, rather than ldr's. Note that this code must not
878 * exceed 0x300 bytes.
880 * Common stub entry macro:
881 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
883 * SP points to a minimal amount of processor-private memory, the address
884 * of which is copied into r0 for the mode specific abort handler.
886 .macro vector_stub, name, mode, correction=0
891 sub lr, lr, #\correction
895 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
898 stmia sp, {r0, lr} @ save r0, lr
900 str lr, [sp, #8] @ save spsr
903 @ Prepare for SVC32 mode. IRQs remain disabled.
906 eor r0, r0, #(\mode ^ SVC_MODE)
910 @ the branch table must immediately follow this code
914 ldr lr, [pc, lr, lsl #2]
915 movs pc, lr @ branch to handler in SVC mode
921 * Interrupt dispatcher
923 vector_stub irq, IRQ_MODE, 4
925 .long __irq_usr @ 0 (USR_26 / USR_32)
926 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
927 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
928 .long __irq_svc @ 3 (SVC_26 / SVC_32)
929 .long __irq_invalid @ 4
930 .long __irq_invalid @ 5
931 .long __irq_invalid @ 6
932 .long __irq_invalid @ 7
933 .long __irq_invalid @ 8
934 .long __irq_invalid @ 9
935 .long __irq_invalid @ a
936 .long __irq_invalid @ b
937 .long __irq_invalid @ c
938 .long __irq_invalid @ d
939 .long __irq_invalid @ e
940 .long __irq_invalid @ f
943 * Data abort dispatcher
944 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
946 vector_stub dabt, ABT_MODE, 8
948 .long __dabt_usr @ 0 (USR_26 / USR_32)
949 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
950 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
951 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
952 .long __dabt_invalid @ 4
953 .long __dabt_invalid @ 5
954 .long __dabt_invalid @ 6
955 .long __dabt_invalid @ 7
956 .long __dabt_invalid @ 8
957 .long __dabt_invalid @ 9
958 .long __dabt_invalid @ a
959 .long __dabt_invalid @ b
960 .long __dabt_invalid @ c
961 .long __dabt_invalid @ d
962 .long __dabt_invalid @ e
963 .long __dabt_invalid @ f
966 * Prefetch abort dispatcher
967 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
969 vector_stub pabt, ABT_MODE, 4
971 .long __pabt_usr @ 0 (USR_26 / USR_32)
972 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
973 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
974 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
975 .long __pabt_invalid @ 4
976 .long __pabt_invalid @ 5
977 .long __pabt_invalid @ 6
978 .long __pabt_invalid @ 7
979 .long __pabt_invalid @ 8
980 .long __pabt_invalid @ 9
981 .long __pabt_invalid @ a
982 .long __pabt_invalid @ b
983 .long __pabt_invalid @ c
984 .long __pabt_invalid @ d
985 .long __pabt_invalid @ e
986 .long __pabt_invalid @ f
989 * Undef instr entry dispatcher
990 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
992 vector_stub und, UND_MODE
994 .long __und_usr @ 0 (USR_26 / USR_32)
995 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
996 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
997 .long __und_svc @ 3 (SVC_26 / SVC_32)
998 .long __und_invalid @ 4
999 .long __und_invalid @ 5
1000 .long __und_invalid @ 6
1001 .long __und_invalid @ 7
1002 .long __und_invalid @ 8
1003 .long __und_invalid @ 9
1004 .long __und_invalid @ a
1005 .long __und_invalid @ b
1006 .long __und_invalid @ c
1007 .long __und_invalid @ d
1008 .long __und_invalid @ e
1009 .long __und_invalid @ f
1013 /*=============================================================================
1015 *-----------------------------------------------------------------------------
1016 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1017 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1018 * Basically to switch modes, we *HAVE* to clobber one register... brain
1019 * damage alert! I don't think that we can execute any code in here in any
1020 * other mode than FIQ... Ok you can switch to another mode, but you can't
1021 * get out of that mode without clobbering one register.
1027 /*=============================================================================
1028 * Address exception handler
1029 *-----------------------------------------------------------------------------
1030 * These aren't too critical.
1031 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1038 * We group all the following data together to optimise
1039 * for CPUs with separate I & D caches.
1049 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1051 .globl __vectors_start
1054 b vector_und + stubs_offset
1055 ldr pc, .LCvswi + stubs_offset
1056 b vector_pabt + stubs_offset
1057 b vector_dabt + stubs_offset
1058 b vector_addrexcptn + stubs_offset
1059 b vector_irq + stubs_offset
1060 b vector_fiq + stubs_offset
1062 .globl __vectors_end
1068 .globl cr_no_alignment
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