2 * Cache flushing routines.
4 * Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * 05/28/05 Zoltan Menyhart Dynamic stride size
10 #include <asm/asmmacro.h>
14 * flush_icache_range(start,end)
16 * Make i-cache(s) coherent with d-caches.
18 * Must deal with range from start to end-1 but nothing else (need to
19 * be careful not to touch addresses that may be unmapped).
21 * Note: "in0" and "in1" are preserved for debugging purposes.
23 GLOBAL_ENTRY(flush_icache_range)
26 alloc r2=ar.pfs,2,0,0,0
27 movl r3=ia64_i_cache_stride_shift
30 ld8 r20=[r3] // r20: stride shift
31 sub r22=in1,r0,1 // last byte address
33 shr.u r23=in0,r20 // start / (stride size)
34 shr.u r22=r22,r20 // (last byte address) / (stride size)
35 shl r21=r21,r20 // r21: stride size of the i-cache(s)
37 sub r8=r22,r23 // number of strides - 1
38 shl r24=r23,r20 // r24: addresses for "fc.i" =
39 // "start" rounded down to stride boundary
41 mov r3=ar.lc // save ar.lc
48 * 32 byte aligned loop, even number of (actually 2) bundles
50 .Loop: fc.i r24 // issuable on M0 only
51 add r24=r21,r24 // we flush "stride size" bytes per iteration
53 br.cloop.sptk.few .Loop
59 mov ar.lc=r3 // restore ar.lc
61 END(flush_icache_range)