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   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 #include <mach/board.h>
  34 #include <mach/mmc.h>
  35 #include <mach/gpio.h>
  36 #include <mach/dma.h>
  37 #include <mach/mux.h>
  38 #include <mach/fpga.h>
  39
  40 #define OMAP_MMC_REG_CMD        0x00
  41 #define OMAP_MMC_REG_ARGL       0x04
  42 #define OMAP_MMC_REG_ARGH       0x08
  43 #define OMAP_MMC_REG_CON        0x0c
  44 #define OMAP_MMC_REG_STAT       0x10
  45 #define OMAP_MMC_REG_IE         0x14
  46 #define OMAP_MMC_REG_CTO        0x18
  47 #define OMAP_MMC_REG_DTO        0x1c
  48 #define OMAP_MMC_REG_DATA       0x20
  49 #define OMAP_MMC_REG_BLEN       0x24
  50 #define OMAP_MMC_REG_NBLK       0x28
  51 #define OMAP_MMC_REG_BUF        0x2c
  52 #define OMAP_MMC_REG_SDIO       0x34
  53 #define OMAP_MMC_REG_REV        0x3c
  54 #define OMAP_MMC_REG_RSP0       0x40
  55 #define OMAP_MMC_REG_RSP1       0x44
  56 #define OMAP_MMC_REG_RSP2       0x48
  57 #define OMAP_MMC_REG_RSP3       0x4c
  58 #define OMAP_MMC_REG_RSP4       0x50
  59 #define OMAP_MMC_REG_RSP5       0x54
  60 #define OMAP_MMC_REG_RSP6       0x58
  61 #define OMAP_MMC_REG_RSP7       0x5c
  62 #define OMAP_MMC_REG_IOSR       0x60
  63 #define OMAP_MMC_REG_SYSC       0x64
  64 #define OMAP_MMC_REG_SYSS       0x68
  65
  66 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  67 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  68 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  69 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  70 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  71 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  72 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  73 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  74 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  75 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  76 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  77 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  78 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  79
  80 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  81 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  82
  83 /*
  84  * Command types
  85  */
  86 #define OMAP_MMC_CMDTYPE_BC     0
  87 #define OMAP_MMC_CMDTYPE_BCR    1
  88 #define OMAP_MMC_CMDTYPE_AC     2
  89 #define OMAP_MMC_CMDTYPE_ADTC   3
  90
  91
  92 #define DRIVER_NAME "mmci-omap"
  93
  94 /* Specifies how often in millisecs to poll for card status changes
  95  * when the cover switch is open */
  96 #define OMAP_MMC_COVER_POLL_DELAY       500
  97
  98 struct mmc_omap_host;
  99
 100 struct mmc_omap_slot {
 101         int                     id;
 102         unsigned int            vdd;
 103         u16                     saved_con;
 104         u16                     bus_mode;
 105         unsigned int            fclk_freq;
 106         unsigned                powered:1;
 107
 108         struct tasklet_struct   cover_tasklet;
 109         struct timer_list       cover_timer;
 110         unsigned                cover_open;
 111
 112         struct mmc_request      *mrq;
 113         struct mmc_omap_host    *host;
 114         struct mmc_host         *mmc;
 115         struct omap_mmc_slot_data *pdata;
 116 };
 117
 118 struct mmc_omap_host {
 119         int                     initialized;
 120         int                     suspended;
 121         struct mmc_request *    mrq;
 122         struct mmc_command *    cmd;
 123         struct mmc_data *       data;
 124         struct mmc_host *       mmc;
 125         struct device *         dev;
 126         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 127         struct clk *            iclk;
 128         struct clk *            fclk;
 129         struct resource         *mem_res;
 130         void __iomem            *virt_base;
 131         unsigned int            phys_base;
 132         int                     irq;
 133         unsigned char           bus_mode;
 134         unsigned char           hw_bus_mode;
 135
 136         struct work_struct      cmd_abort_work;
 137         unsigned                abort:1;
 138         struct timer_list       cmd_abort_timer;
 139
 140         struct work_struct      slot_release_work;
 141         struct mmc_omap_slot    *next_slot;
 142         struct work_struct      send_stop_work;
 143         struct mmc_data         *stop_data;
 144
 145         unsigned int            sg_len;
 146         int                     sg_idx;
 147         u16 *                   buffer;
 148         u32                     buffer_bytes_left;
 149         u32                     total_bytes_left;
 150
 151         unsigned                use_dma:1;
 152         unsigned                brs_received:1, dma_done:1;
 153         unsigned                dma_is_read:1;
 154         unsigned                dma_in_use:1;
 155         int                     dma_ch;
 156         spinlock_t              dma_lock;
 157         struct timer_list       dma_timer;
 158         unsigned                dma_len;
 159
 160         short                   power_pin;
 161
 162         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 163         struct mmc_omap_slot    *current_slot;
 164         spinlock_t              slot_lock;
 165         wait_queue_head_t       slot_wq;
 166         int                     nr_slots;
 167
 168         struct timer_list       clk_timer;
 169         spinlock_t              clk_lock;     /* for changing enabled state */
 170         unsigned int            fclk_enabled:1;
 171
 172         struct omap_mmc_platform_data *pdata;
 173 };
 174
 175 void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 176 {
 177         unsigned long tick_ns;
 178
 179         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 180                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
 181                 ndelay(8 * tick_ns);
 182         }
 183 }
 184
 185 void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 186 {
 187         unsigned long flags;
 188
 189         spin_lock_irqsave(&host->clk_lock, flags);
 190         if (host->fclk_enabled != enable) {
 191                 host->fclk_enabled = enable;
 192                 if (enable)
 193                         clk_enable(host->fclk);
 194                 else
 195                         clk_disable(host->fclk);
 196         }
 197         spin_unlock_irqrestore(&host->clk_lock, flags);
 198 }
 199
 200 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 201 {
 202         struct mmc_omap_host *host = slot->host;
 203         unsigned long flags;
 204
 205         if (claimed)
 206                 goto no_claim;
 207         spin_lock_irqsave(&host->slot_lock, flags);
 208         while (host->mmc != NULL) {
 209                 spin_unlock_irqrestore(&host->slot_lock, flags);
 210                 wait_event(host->slot_wq, host->mmc == NULL);
 211                 spin_lock_irqsave(&host->slot_lock, flags);
 212         }
 213         host->mmc = slot->mmc;
 214         spin_unlock_irqrestore(&host->slot_lock, flags);
 215 no_claim:
 216         del_timer(&host->clk_timer);
 217         if (host->current_slot != slot || !claimed)
 218                 mmc_omap_fclk_offdelay(host->current_slot);
 219
 220         if (host->current_slot != slot) {
 221                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 222                 if (host->pdata->switch_slot != NULL)
 223                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 224                 host->current_slot = slot;
 225         }
 226
 227         if (claimed) {
 228                 mmc_omap_fclk_enable(host, 1);
 229
 230                 /* Doing the dummy read here seems to work around some bug
 231                  * at least in OMAP24xx silicon where the command would not
 232                  * start after writing the CMD register. Sigh. */
 233                 OMAP_MMC_READ(host, CON);
 234
 235                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
 236         } else
 237                 mmc_omap_fclk_enable(host, 0);
 238 }
 239
 240 static void mmc_omap_start_request(struct mmc_omap_host *host,
 241                                    struct mmc_request *req);
 242
 243 static void mmc_omap_slot_release_work(struct work_struct *work)
 244 {
 245         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 246                                                   slot_release_work);
 247         struct mmc_omap_slot *next_slot = host->next_slot;
 248         struct mmc_request *rq;
 249
 250         host->next_slot = NULL;
 251         mmc_omap_select_slot(next_slot, 1);
 252
 253         rq = next_slot->mrq;
 254         next_slot->mrq = NULL;
 255         mmc_omap_start_request(host, rq);
 256 }
 257
 258 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 259 {
 260         struct mmc_omap_host *host = slot->host;
 261         unsigned long flags;
 262         int i;
 263
 264         BUG_ON(slot == NULL || host->mmc == NULL);
 265
 266         if (clk_enabled)
 267                 /* Keeps clock running for at least 8 cycles on valid freq */
 268                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
 269         else {
 270                 del_timer(&host->clk_timer);
 271                 mmc_omap_fclk_offdelay(slot);
 272                 mmc_omap_fclk_enable(host, 0);
 273         }
 274
 275         spin_lock_irqsave(&host->slot_lock, flags);
 276         /* Check for any pending requests */
 277         for (i = 0; i < host->nr_slots; i++) {
 278                 struct mmc_omap_slot *new_slot;
 279
 280                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 281                         continue;
 282
 283                 BUG_ON(host->next_slot != NULL);
 284                 new_slot = host->slots[i];
 285                 /* The current slot should not have a request in queue */
 286                 BUG_ON(new_slot == host->current_slot);
 287
 288                 host->next_slot = new_slot;
 289                 host->mmc = new_slot->mmc;
 290                 spin_unlock_irqrestore(&host->slot_lock, flags);
 291                 schedule_work(&host->slot_release_work);
 292                 return;
 293         }
 294
 295         host->mmc = NULL;
 296         wake_up(&host->slot_wq);
 297         spin_unlock_irqrestore(&host->slot_lock, flags);
 298 }
 299
 300 static inline
 301 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 302 {
 303         if (slot->pdata->get_cover_state)
 304                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 305                                                     slot->id);
 306         return 0;
 307 }
 308
 309 static ssize_t
 310 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 311                            char *buf)
 312 {
 313         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 314         struct mmc_omap_slot *slot = mmc_priv(mmc);
 315
 316         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 317                        "closed");
 318 }
 319
 320 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 321
 322 static ssize_t
 323 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 324                         char *buf)
 325 {
 326         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 327         struct mmc_omap_slot *slot = mmc_priv(mmc);
 328
 329         return sprintf(buf, "%s\n", slot->pdata->name);
 330 }
 331
 332 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 333
 334 static void
 335 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 336 {
 337         u32 cmdreg;
 338         u32 resptype;
 339         u32 cmdtype;
 340
 341         host->cmd = cmd;
 342
 343         resptype = 0;
 344         cmdtype = 0;
 345
 346         /* Our hardware needs to know exact type */
 347         switch (mmc_resp_type(cmd)) {
 348         case MMC_RSP_NONE:
 349                 break;
 350         case MMC_RSP_R1:
 351         case MMC_RSP_R1B:
 352                 /* resp 1, 1b, 6, 7 */
 353                 resptype = 1;
 354                 break;
 355         case MMC_RSP_R2:
 356                 resptype = 2;
 357                 break;
 358         case MMC_RSP_R3:
 359                 resptype = 3;
 360                 break;
 361         default:
 362                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 363                 break;
 364         }
 365
 366         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 367                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 368         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 369                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 370         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 371                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 372         } else {
 373                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 374         }
 375
 376         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 377
 378         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 379                 cmdreg |= 1 << 6;
 380
 381         if (cmd->flags & MMC_RSP_BUSY)
 382                 cmdreg |= 1 << 11;
 383
 384         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 385                 cmdreg |= 1 << 15;
 386
 387         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 388
 389         OMAP_MMC_WRITE(host, CTO, 200);
 390         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 391         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 392         OMAP_MMC_WRITE(host, IE,
 393                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 394                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 395                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 396                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 397                        OMAP_MMC_STAT_END_OF_DATA);
 398         OMAP_MMC_WRITE(host, CMD, cmdreg);
 399 }
 400
 401 static void
 402 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 403                      int abort)
 404 {
 405         enum dma_data_direction dma_data_dir;
 406
 407         BUG_ON(host->dma_ch < 0);
 408         if (data->error)
 409                 omap_stop_dma(host->dma_ch);
 410         /* Release DMA channel lazily */
 411         mod_timer(&host->dma_timer, jiffies + HZ);
 412         if (data->flags & MMC_DATA_WRITE)
 413                 dma_data_dir = DMA_TO_DEVICE;
 414         else
 415                 dma_data_dir = DMA_FROM_DEVICE;
 416         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 417                      dma_data_dir);
 418 }
 419
 420 static void mmc_omap_send_stop_work(struct work_struct *work)
 421 {
 422         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 423                                                   send_stop_work);
 424         struct mmc_omap_slot *slot = host->current_slot;
 425         struct mmc_data *data = host->stop_data;
 426         unsigned long tick_ns;
 427
 428         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 429         ndelay(8*tick_ns);
 430
 431         mmc_omap_start_command(host, data->stop);
 432 }
 433
 434 static void
 435 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 436 {
 437         if (host->dma_in_use)
 438                 mmc_omap_release_dma(host, data, data->error);
 439
 440         host->data = NULL;
 441         host->sg_len = 0;
 442
 443         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 444          * dozens of requests until the card finishes writing data.
 445          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 446          */
 447
 448         if (!data->stop) {
 449                 struct mmc_host *mmc;
 450
 451                 host->mrq = NULL;
 452                 mmc = host->mmc;
 453                 mmc_omap_release_slot(host->current_slot, 1);
 454                 mmc_request_done(mmc, data->mrq);
 455                 return;
 456         }
 457
 458         host->stop_data = data;
 459         schedule_work(&host->send_stop_work);
 460 }
 461
 462 static void
 463 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 464 {
 465         struct mmc_omap_slot *slot = host->current_slot;
 466         unsigned int restarts, passes, timeout;
 467         u16 stat = 0;
 468
 469         /* Sending abort takes 80 clocks. Have some extra and round up */
 470         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 471         restarts = 0;
 472         while (restarts < maxloops) {
 473                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 474                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 475
 476                 passes = 0;
 477                 while (passes < timeout) {
 478                         stat = OMAP_MMC_READ(host, STAT);
 479                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 480                                 goto out;
 481                         udelay(1);
 482                         passes++;
 483                 }
 484
 485                 restarts++;
 486         }
 487 out:
 488         OMAP_MMC_WRITE(host, STAT, stat);
 489 }
 490
 491 static void
 492 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 493 {
 494         if (host->dma_in_use)
 495                 mmc_omap_release_dma(host, data, 1);
 496
 497         host->data = NULL;
 498         host->sg_len = 0;
 499
 500         mmc_omap_send_abort(host, 10000);
 501 }
 502
 503 static void
 504 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 505 {
 506         unsigned long flags;
 507         int done;
 508
 509         if (!host->dma_in_use) {
 510                 mmc_omap_xfer_done(host, data);
 511                 return;
 512         }
 513         done = 0;
 514         spin_lock_irqsave(&host->dma_lock, flags);
 515         if (host->dma_done)
 516                 done = 1;
 517         else
 518                 host->brs_received = 1;
 519         spin_unlock_irqrestore(&host->dma_lock, flags);
 520         if (done)
 521                 mmc_omap_xfer_done(host, data);
 522 }
 523
 524 static void
 525 mmc_omap_dma_timer(unsigned long data)
 526 {
 527         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 528
 529         BUG_ON(host->dma_ch < 0);
 530         omap_free_dma(host->dma_ch);
 531         host->dma_ch = -1;
 532 }
 533
 534 static void
 535 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 536 {
 537         unsigned long flags;
 538         int done;
 539
 540         done = 0;
 541         spin_lock_irqsave(&host->dma_lock, flags);
 542         if (host->brs_received)
 543                 done = 1;
 544         else
 545                 host->dma_done = 1;
 546         spin_unlock_irqrestore(&host->dma_lock, flags);
 547         if (done)
 548                 mmc_omap_xfer_done(host, data);
 549 }
 550
 551 static void
 552 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 553 {
 554         host->cmd = NULL;
 555
 556         del_timer(&host->cmd_abort_timer);
 557
 558         if (cmd->flags & MMC_RSP_PRESENT) {
 559                 if (cmd->flags & MMC_RSP_136) {
 560                         /* response type 2 */
 561                         cmd->resp[3] =
 562                                 OMAP_MMC_READ(host, RSP0) |
 563                                 (OMAP_MMC_READ(host, RSP1) << 16);
 564                         cmd->resp[2] =
 565                                 OMAP_MMC_READ(host, RSP2) |
 566                                 (OMAP_MMC_READ(host, RSP3) << 16);
 567                         cmd->resp[1] =
 568                                 OMAP_MMC_READ(host, RSP4) |
 569                                 (OMAP_MMC_READ(host, RSP5) << 16);
 570                         cmd->resp[0] =
 571                                 OMAP_MMC_READ(host, RSP6) |
 572                                 (OMAP_MMC_READ(host, RSP7) << 16);
 573                 } else {
 574                         /* response types 1, 1b, 3, 4, 5, 6 */
 575                         cmd->resp[0] =
 576                                 OMAP_MMC_READ(host, RSP6) |
 577                                 (OMAP_MMC_READ(host, RSP7) << 16);
 578                 }
 579         }
 580
 581         if (host->data == NULL || cmd->error) {
 582                 struct mmc_host *mmc;
 583
 584                 if (host->data != NULL)
 585                         mmc_omap_abort_xfer(host, host->data);
 586                 host->mrq = NULL;
 587                 mmc = host->mmc;
 588                 mmc_omap_release_slot(host->current_slot, 1);
 589                 mmc_request_done(mmc, cmd->mrq);
 590         }
 591 }
 592
 593 /*
 594  * Abort stuck command. Can occur when card is removed while it is being
 595  * read.
 596  */
 597 static void mmc_omap_abort_command(struct work_struct *work)
 598 {
 599         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 600                                                   cmd_abort_work);
 601         BUG_ON(!host->cmd);
 602
 603         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 604                 host->cmd->opcode);
 605
 606         if (host->cmd->error == 0)
 607                 host->cmd->error = -ETIMEDOUT;
 608
 609         if (host->data == NULL) {
 610                 struct mmc_command *cmd;
 611                 struct mmc_host    *mmc;
 612
 613                 cmd = host->cmd;
 614                 host->cmd = NULL;
 615                 mmc_omap_send_abort(host, 10000);
 616
 617                 host->mrq = NULL;
 618                 mmc = host->mmc;
 619                 mmc_omap_release_slot(host->current_slot, 1);
 620                 mmc_request_done(mmc, cmd->mrq);
 621         } else
 622                 mmc_omap_cmd_done(host, host->cmd);
 623
 624         host->abort = 0;
 625         enable_irq(host->irq);
 626 }
 627
 628 static void
 629 mmc_omap_cmd_timer(unsigned long data)
 630 {
 631         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 632         unsigned long flags;
 633
 634         spin_lock_irqsave(&host->slot_lock, flags);
 635         if (host->cmd != NULL && !host->abort) {
 636                 OMAP_MMC_WRITE(host, IE, 0);
 637                 disable_irq(host->irq);
 638                 host->abort = 1;
 639                 schedule_work(&host->cmd_abort_work);
 640         }
 641         spin_unlock_irqrestore(&host->slot_lock, flags);
 642 }
 643
 644 /* PIO only */
 645 static void
 646 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 647 {
 648         struct scatterlist *sg;
 649
 650         sg = host->data->sg + host->sg_idx;
 651         host->buffer_bytes_left = sg->length;
 652         host->buffer = sg_virt(sg);
 653         if (host->buffer_bytes_left > host->total_bytes_left)
 654                 host->buffer_bytes_left = host->total_bytes_left;
 655 }
 656
 657 static void
 658 mmc_omap_clk_timer(unsigned long data)
 659 {
 660         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 661
 662         mmc_omap_fclk_enable(host, 0);
 663 }
 664
 665 /* PIO only */
 666 static void
 667 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 668 {
 669         int n;
 670
 671         if (host->buffer_bytes_left == 0) {
 672                 host->sg_idx++;
 673                 BUG_ON(host->sg_idx == host->sg_len);
 674                 mmc_omap_sg_to_buf(host);
 675         }
 676         n = 64;
 677         if (n > host->buffer_bytes_left)
 678                 n = host->buffer_bytes_left;
 679         host->buffer_bytes_left -= n;
 680         host->total_bytes_left -= n;
 681         host->data->bytes_xfered += n;
 682
 683         if (write) {
 684                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 685         } else {
 686                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 687         }
 688 }
 689
 690 static inline void mmc_omap_report_irq(u16 status)
 691 {
 692         static const char *mmc_omap_status_bits[] = {
 693                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 694                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 695         };
 696         int i, c = 0;
 697
 698         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 699                 if (status & (1 << i)) {
 700                         if (c)
 701                                 printk(" ");
 702                         printk("%s", mmc_omap_status_bits[i]);
 703                         c++;
 704                 }
 705 }
 706
 707 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 708 {
 709         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 710         u16 status;
 711         int end_command;
 712         int end_transfer;
 713         int transfer_error, cmd_error;
 714
 715         if (host->cmd == NULL && host->data == NULL) {
 716                 status = OMAP_MMC_READ(host, STAT);
 717                 dev_info(mmc_dev(host->slots[0]->mmc),
 718                          "Spurious IRQ 0x%04x\n", status);
 719                 if (status != 0) {
 720                         OMAP_MMC_WRITE(host, STAT, status);
 721                         OMAP_MMC_WRITE(host, IE, 0);
 722                 }
 723                 return IRQ_HANDLED;
 724         }
 725
 726         end_command = 0;
 727         end_transfer = 0;
 728         transfer_error = 0;
 729         cmd_error = 0;
 730
 731         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 732                 int cmd;
 733
 734                 OMAP_MMC_WRITE(host, STAT, status);
 735                 if (host->cmd != NULL)
 736                         cmd = host->cmd->opcode;
 737                 else
 738                         cmd = -1;
 739 #ifdef CONFIG_MMC_DEBUG
 740                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 741                         status, cmd);
 742                 mmc_omap_report_irq(status);
 743                 printk("\n");
 744 #endif
 745                 if (host->total_bytes_left) {
 746                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 747                             (status & OMAP_MMC_STAT_END_OF_DATA))
 748                                 mmc_omap_xfer_data(host, 0);
 749                         if (status & OMAP_MMC_STAT_A_EMPTY)
 750                                 mmc_omap_xfer_data(host, 1);
 751                 }
 752
 753                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 754                         end_transfer = 1;
 755
 756                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 757                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 758                                 cmd);
 759                         if (host->data) {
 760                                 host->data->error = -ETIMEDOUT;
 761                                 transfer_error = 1;
 762                         }
 763                 }
 764
 765                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 766                         if (host->data) {
 767                                 host->data->error = -EILSEQ;
 768                                 dev_dbg(mmc_dev(host->mmc),
 769                                          "data CRC error, bytes left %d\n",
 770                                         host->total_bytes_left);
 771                                 transfer_error = 1;
 772                         } else {
 773                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 774                         }
 775                 }
 776
 777                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 778                         /* Timeouts are routine with some commands */
 779                         if (host->cmd) {
 780                                 struct mmc_omap_slot *slot =
 781                                         host->current_slot;
 782                                 if (slot == NULL ||
 783                                     !mmc_omap_cover_is_open(slot))
 784                                         dev_err(mmc_dev(host->mmc),
 785                                                 "command timeout (CMD%d)\n",
 786                                                 cmd);
 787                                 host->cmd->error = -ETIMEDOUT;
 788                                 end_command = 1;
 789                                 cmd_error = 1;
 790                         }
 791                 }
 792
 793                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 794                         if (host->cmd) {
 795                                 dev_err(mmc_dev(host->mmc),
 796                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 797                                         cmd, host->cmd->arg);
 798                                 host->cmd->error = -EILSEQ;
 799                                 end_command = 1;
 800                                 cmd_error = 1;
 801                         } else
 802                                 dev_err(mmc_dev(host->mmc),
 803                                         "command CRC error without cmd?\n");
 804                 }
 805
 806                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 807                         dev_dbg(mmc_dev(host->mmc),
 808                                 "ignoring card status error (CMD%d)\n",
 809                                 cmd);
 810                         end_command = 1;
 811                 }
 812
 813                 /*
 814                  * NOTE: On 1610 the END_OF_CMD may come too early when
 815                  * starting a write
 816                  */
 817                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 818                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 819                         end_command = 1;
 820                 }
 821         }
 822
 823         if (cmd_error && host->data) {
 824                 del_timer(&host->cmd_abort_timer);
 825                 host->abort = 1;
 826                 OMAP_MMC_WRITE(host, IE, 0);
 827                 disable_irq(host->irq);
 828                 schedule_work(&host->cmd_abort_work);
 829                 return IRQ_HANDLED;
 830         }
 831
 832         if (end_command)
 833                 mmc_omap_cmd_done(host, host->cmd);
 834         if (host->data != NULL) {
 835                 if (transfer_error)
 836                         mmc_omap_xfer_done(host, host->data);
 837                 else if (end_transfer)
 838                         mmc_omap_end_of_data(host, host->data);
 839         }
 840
 841         return IRQ_HANDLED;
 842 }
 843
 844 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 845 {
 846         int cover_open;
 847         struct mmc_omap_host *host = dev_get_drvdata(dev);
 848         struct mmc_omap_slot *slot = host->slots[num];
 849
 850         BUG_ON(num >= host->nr_slots);
 851
 852         /* Other subsystems can call in here before we're initialised. */
 853         if (host->nr_slots == 0 || !host->slots[num])
 854                 return;
 855
 856         cover_open = mmc_omap_cover_is_open(slot);
 857         if (cover_open != slot->cover_open) {
 858                 slot->cover_open = cover_open;
 859                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 860         }
 861
 862         tasklet_hi_schedule(&slot->cover_tasklet);
 863 }
 864
 865 static void mmc_omap_cover_timer(unsigned long arg)
 866 {
 867         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 868         tasklet_schedule(&slot->cover_tasklet);
 869 }
 870
 871 static void mmc_omap_cover_handler(unsigned long param)
 872 {
 873         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 874         int cover_open = mmc_omap_cover_is_open(slot);
 875
 876         mmc_detect_change(slot->mmc, 0);
 877         if (!cover_open)
 878                 return;
 879
 880         /*
 881          * If no card is inserted, we postpone polling until
 882          * the cover has been closed.
 883          */
 884         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 885                 return;
 886
 887         mod_timer(&slot->cover_timer,
 888                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 889 }
 890
 891 /* Prepare to transfer the next segment of a scatterlist */
 892 static void
 893 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 894 {
 895         int dma_ch = host->dma_ch;
 896         unsigned long data_addr;
 897         u16 buf, frame;
 898         u32 count;
 899         struct scatterlist *sg = &data->sg[host->sg_idx];
 900         int src_port = 0;
 901         int dst_port = 0;
 902         int sync_dev = 0;
 903
 904         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 905         frame = data->blksz;
 906         count = sg_dma_len(sg);
 907
 908         if ((data->blocks == 1) && (count > data->blksz))
 909                 count = frame;
 910
 911         host->dma_len = count;
 912
 913         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 914          * Use 16 or 32 word frames when the blocksize is at least that large.
 915          * Blocksize is usually 512 bytes; but not for some SD reads.
 916          */
 917         if (cpu_is_omap15xx() && frame > 32)
 918                 frame = 32;
 919         else if (frame > 64)
 920                 frame = 64;
 921         count /= frame;
 922         frame >>= 1;
 923
 924         if (!(data->flags & MMC_DATA_WRITE)) {
 925                 buf = 0x800f | ((frame - 1) << 8);
 926
 927                 if (cpu_class_is_omap1()) {
 928                         src_port = OMAP_DMA_PORT_TIPB;
 929                         dst_port = OMAP_DMA_PORT_EMIFF;
 930                 }
 931                 if (cpu_is_omap24xx())
 932                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 933
 934                 omap_set_dma_src_params(dma_ch, src_port,
 935                                         OMAP_DMA_AMODE_CONSTANT,
 936                                         data_addr, 0, 0);
 937                 omap_set_dma_dest_params(dma_ch, dst_port,
 938                                          OMAP_DMA_AMODE_POST_INC,
 939                                          sg_dma_address(sg), 0, 0);
 940                 omap_set_dma_dest_data_pack(dma_ch, 1);
 941                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 942         } else {
 943                 buf = 0x0f80 | ((frame - 1) << 0);
 944
 945                 if (cpu_class_is_omap1()) {
 946                         src_port = OMAP_DMA_PORT_EMIFF;
 947                         dst_port = OMAP_DMA_PORT_TIPB;
 948                 }
 949                 if (cpu_is_omap24xx())
 950                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 951
 952                 omap_set_dma_dest_params(dma_ch, dst_port,
 953                                          OMAP_DMA_AMODE_CONSTANT,
 954                                          data_addr, 0, 0);
 955                 omap_set_dma_src_params(dma_ch, src_port,
 956                                         OMAP_DMA_AMODE_POST_INC,
 957                                         sg_dma_address(sg), 0, 0);
 958                 omap_set_dma_src_data_pack(dma_ch, 1);
 959                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 960         }
 961
 962         /* Max limit for DMA frame count is 0xffff */
 963         BUG_ON(count > 0xffff);
 964
 965         OMAP_MMC_WRITE(host, BUF, buf);
 966         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 967                                      frame, count, OMAP_DMA_SYNC_FRAME,
 968                                      sync_dev, 0);
 969 }
 970
 971 /* A scatterlist segment completed */
 972 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 973 {
 974         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 975         struct mmc_data *mmcdat = host->data;
 976
 977         if (unlikely(host->dma_ch < 0)) {
 978                 dev_err(mmc_dev(host->mmc),
 979                         "DMA callback while DMA not enabled\n");
 980                 return;
 981         }
 982         /* FIXME: We really should do something to _handle_ the errors */
 983         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 984                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 985                 return;
 986         }
 987         if (ch_status & OMAP_DMA_DROP_IRQ) {
 988                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 989                 return;
 990         }
 991         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 992                 return;
 993         }
 994         mmcdat->bytes_xfered += host->dma_len;
 995         host->sg_idx++;
 996         if (host->sg_idx < host->sg_len) {
 997                 mmc_omap_prepare_dma(host, host->data);
 998                 omap_start_dma(host->dma_ch);
 999         } else
1000                 mmc_omap_dma_done(host, host->data);
1001 }
1002
1003 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
1004 {
1005         const char *dma_dev_name;
1006         int sync_dev, dma_ch, is_read, r;
1007
1008         is_read = !(data->flags & MMC_DATA_WRITE);
1009         del_timer_sync(&host->dma_timer);
1010         if (host->dma_ch >= 0) {
1011                 if (is_read == host->dma_is_read)
1012                         return 0;
1013                 omap_free_dma(host->dma_ch);
1014                 host->dma_ch = -1;
1015         }
1016
1017         if (is_read) {
1018                 if (host->id == 1) {
1019                         sync_dev = OMAP_DMA_MMC_RX;
1020                         dma_dev_name = "MMC1 read";
1021                 } else {
1022                         sync_dev = OMAP_DMA_MMC2_RX;
1023                         dma_dev_name = "MMC2 read";
1024                 }
1025         } else {
1026                 if (host->id == 1) {
1027                         sync_dev = OMAP_DMA_MMC_TX;
1028                         dma_dev_name = "MMC1 write";
1029                 } else {
1030                         sync_dev = OMAP_DMA_MMC2_TX;
1031                         dma_dev_name = "MMC2 write";
1032                 }
1033         }
1034         r = omap_request_dma(sync_dev, dma_dev_name, mmc_omap_dma_cb,
1035                              host, &dma_ch);
1036         if (r != 0) {
1037                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
1038                 return r;
1039         }
1040         host->dma_ch = dma_ch;
1041         host->dma_is_read = is_read;
1042
1043         return 0;
1044 }
1045
1046 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1047 {
1048         u16 reg;
1049
1050         reg = OMAP_MMC_READ(host, SDIO);
1051         reg &= ~(1 << 5);
1052         OMAP_MMC_WRITE(host, SDIO, reg);
1053         /* Set maximum timeout */
1054         OMAP_MMC_WRITE(host, CTO, 0xff);
1055 }
1056
1057 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1058 {
1059         unsigned int timeout, cycle_ns;
1060         u16 reg;
1061
1062         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
1063         timeout = req->data->timeout_ns / cycle_ns;
1064         timeout += req->data->timeout_clks;
1065
1066         /* Check if we need to use timeout multiplier register */
1067         reg = OMAP_MMC_READ(host, SDIO);
1068         if (timeout > 0xffff) {
1069                 reg |= (1 << 5);
1070                 timeout /= 1024;
1071         } else
1072                 reg &= ~(1 << 5);
1073         OMAP_MMC_WRITE(host, SDIO, reg);
1074         OMAP_MMC_WRITE(host, DTO, timeout);
1075 }
1076
1077 static void
1078 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1079 {
1080         struct mmc_data *data = req->data;
1081         int i, use_dma, block_size;
1082         unsigned sg_len;
1083
1084         host->data = data;
1085         if (data == NULL) {
1086                 OMAP_MMC_WRITE(host, BLEN, 0);
1087                 OMAP_MMC_WRITE(host, NBLK, 0);
1088                 OMAP_MMC_WRITE(host, BUF, 0);
1089                 host->dma_in_use = 0;
1090                 set_cmd_timeout(host, req);
1091                 return;
1092         }
1093
1094         block_size = data->blksz;
1095
1096         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1097         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1098         set_data_timeout(host, req);
1099
1100         /* cope with calling layer confusion; it issues "single
1101          * block" writes using multi-block scatterlists.
1102          */
1103         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1104
1105         /* Only do DMA for entire blocks */
1106         use_dma = host->use_dma;
1107         if (use_dma) {
1108                 for (i = 0; i < sg_len; i++) {
1109                         if ((data->sg[i].length % block_size) != 0) {
1110                                 use_dma = 0;
1111                                 break;
1112                         }
1113                 }
1114         }
1115
1116         host->sg_idx = 0;
1117         if (use_dma) {
1118                 if (mmc_omap_get_dma_channel(host, data) == 0) {
1119                         enum dma_data_direction dma_data_dir;
1120
1121                         if (data->flags & MMC_DATA_WRITE)
1122                                 dma_data_dir = DMA_TO_DEVICE;
1123                         else
1124                                 dma_data_dir = DMA_FROM_DEVICE;
1125
1126                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1127                                                 sg_len, dma_data_dir);
1128                         host->total_bytes_left = 0;
1129                         mmc_omap_prepare_dma(host, req->data);
1130                         host->brs_received = 0;
1131                         host->dma_done = 0;
1132                         host->dma_in_use = 1;
1133                 } else
1134                         use_dma = 0;
1135         }
1136
1137         /* Revert to PIO? */
1138         if (!use_dma) {
1139                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1140                 host->total_bytes_left = data->blocks * block_size;
1141                 host->sg_len = sg_len;
1142                 mmc_omap_sg_to_buf(host);
1143                 host->dma_in_use = 0;
1144         }
1145 }
1146
1147 static void mmc_omap_start_request(struct mmc_omap_host *host,
1148                                    struct mmc_request *req)
1149 {
1150         BUG_ON(host->mrq != NULL);
1151
1152         host->mrq = req;
1153
1154         /* only touch fifo AFTER the controller readies it */
1155         mmc_omap_prepare_data(host, req);
1156         mmc_omap_start_command(host, req->cmd);
1157         if (host->dma_in_use)
1158                 omap_start_dma(host->dma_ch);
1159         BUG_ON(irqs_disabled());
1160 }
1161
1162 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1163 {
1164         struct mmc_omap_slot *slot = mmc_priv(mmc);
1165         struct mmc_omap_host *host = slot->host;
1166         unsigned long flags;
1167
1168         spin_lock_irqsave(&host->slot_lock, flags);
1169         if (host->mmc != NULL) {
1170                 BUG_ON(slot->mrq != NULL);
1171                 slot->mrq = req;
1172                 spin_unlock_irqrestore(&host->slot_lock, flags);
1173                 return;
1174         } else
1175                 host->mmc = mmc;
1176         spin_unlock_irqrestore(&host->slot_lock, flags);
1177         mmc_omap_select_slot(slot, 1);
1178         mmc_omap_start_request(host, req);
1179 }
1180
1181 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1182                                 int vdd)
1183 {
1184         struct mmc_omap_host *host;
1185
1186         host = slot->host;
1187
1188         if (slot->pdata->set_power != NULL)
1189                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1190                                         vdd);
1191
1192         if (cpu_is_omap24xx()) {
1193                 u16 w;
1194
1195                 if (power_on) {
1196                         w = OMAP_MMC_READ(host, CON);
1197                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1198                 } else {
1199                         w = OMAP_MMC_READ(host, CON);
1200                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1201                 }
1202         }
1203 }
1204
1205 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1206 {
1207         struct mmc_omap_slot *slot = mmc_priv(mmc);
1208         struct mmc_omap_host *host = slot->host;
1209         int func_clk_rate = clk_get_rate(host->fclk);
1210         int dsor;
1211
1212         if (ios->clock == 0)
1213                 return 0;
1214
1215         dsor = func_clk_rate / ios->clock;
1216         if (dsor < 1)
1217                 dsor = 1;
1218
1219         if (func_clk_rate / dsor > ios->clock)
1220                 dsor++;
1221
1222         if (dsor > 250)
1223                 dsor = 250;
1224
1225         slot->fclk_freq = func_clk_rate / dsor;
1226
1227         if (ios->bus_width == MMC_BUS_WIDTH_4)
1228                 dsor |= 1 << 15;
1229
1230         return dsor;
1231 }
1232
1233 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1234 {
1235         struct mmc_omap_slot *slot = mmc_priv(mmc);
1236         struct mmc_omap_host *host = slot->host;
1237         int i, dsor;
1238         int clk_enabled;
1239
1240         mmc_omap_select_slot(slot, 0);
1241
1242         dsor = mmc_omap_calc_divisor(mmc, ios);
1243
1244         if (ios->vdd != slot->vdd)
1245                 slot->vdd = ios->vdd;
1246
1247         clk_enabled = 0;
1248         switch (ios->power_mode) {
1249         case MMC_POWER_OFF:
1250                 mmc_omap_set_power(slot, 0, ios->vdd);
1251                 break;
1252         case MMC_POWER_UP:
1253                 /* Cannot touch dsor yet, just power up MMC */
1254                 mmc_omap_set_power(slot, 1, ios->vdd);
1255                 goto exit;
1256         case MMC_POWER_ON:
1257                 mmc_omap_fclk_enable(host, 1);
1258                 clk_enabled = 1;
1259                 dsor |= 1 << 11;
1260                 break;
1261         }
1262
1263         if (slot->bus_mode != ios->bus_mode) {
1264                 if (slot->pdata->set_bus_mode != NULL)
1265                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1266                                                   ios->bus_mode);
1267                 slot->bus_mode = ios->bus_mode;
1268         }
1269
1270         /* On insanely high arm_per frequencies something sometimes
1271          * goes somehow out of sync, and the POW bit is not being set,
1272          * which results in the while loop below getting stuck.
1273          * Writing to the CON register twice seems to do the trick. */
1274         for (i = 0; i < 2; i++)
1275                 OMAP_MMC_WRITE(host, CON, dsor);
1276         slot->saved_con = dsor;
1277         if (ios->power_mode == MMC_POWER_ON) {
1278                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1279                 int usecs = 250;
1280
1281                 /* Send clock cycles, poll completion */
1282                 OMAP_MMC_WRITE(host, IE, 0);
1283                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1284                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1285                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1286                         udelay(1);
1287                         usecs--;
1288                 }
1289                 OMAP_MMC_WRITE(host, STAT, 1);
1290         }
1291
1292 exit:
1293         mmc_omap_release_slot(slot, clk_enabled);
1294 }
1295
1296 static const struct mmc_host_ops mmc_omap_ops = {
1297         .request        = mmc_omap_request,
1298         .set_ios        = mmc_omap_set_ios,
1299 };
1300
1301 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1302 {
1303         struct mmc_omap_slot *slot = NULL;
1304         struct mmc_host *mmc;
1305         int r;
1306
1307         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1308         if (mmc == NULL)
1309                 return -ENOMEM;
1310
1311         slot = mmc_priv(mmc);
1312         slot->host = host;
1313         slot->mmc = mmc;
1314         slot->id = id;
1315         slot->pdata = &host->pdata->slots[id];
1316
1317         host->slots[id] = slot;
1318
1319         mmc->caps = 0;
1320         if (host->pdata->conf.wire4)
1321                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1322
1323         mmc->ops = &mmc_omap_ops;
1324         mmc->f_min = 400000;
1325
1326         if (cpu_class_is_omap2())
1327                 mmc->f_max = 48000000;
1328         else
1329                 mmc->f_max = 24000000;
1330         if (host->pdata->max_freq)
1331                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1332         mmc->ocr_avail = slot->pdata->ocr_mask;
1333
1334         /* Use scatterlist DMA to reduce per-transfer costs.
1335          * NOTE max_seg_size assumption that small blocks aren't
1336          * normally used (except e.g. for reading SD registers).
1337          */
1338         mmc->max_phys_segs = 32;
1339         mmc->max_hw_segs = 32;
1340         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1341         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1342         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1343         mmc->max_seg_size = mmc->max_req_size;
1344
1345         r = mmc_add_host(mmc);
1346         if (r < 0)
1347                 goto err_remove_host;
1348
1349         if (slot->pdata->name != NULL) {
1350                 r = device_create_file(&mmc->class_dev,
1351                                         &dev_attr_slot_name);
1352                 if (r < 0)
1353                         goto err_remove_host;
1354         }
1355
1356         if (slot->pdata->get_cover_state != NULL) {
1357                 r = device_create_file(&mmc->class_dev,
1358                                         &dev_attr_cover_switch);
1359                 if (r < 0)
1360                         goto err_remove_slot_name;
1361
1362                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1363                             (unsigned long)slot);
1364                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1365                              (unsigned long)slot);
1366                 tasklet_schedule(&slot->cover_tasklet);
1367         }
1368
1369         return 0;
1370
1371 err_remove_slot_name:
1372         if (slot->pdata->name != NULL)
1373                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1374 err_remove_host:
1375         mmc_remove_host(mmc);
1376         mmc_free_host(mmc);
1377         return r;
1378 }
1379
1380 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1381 {
1382         struct mmc_host *mmc = slot->mmc;
1383
1384         if (slot->pdata->name != NULL)
1385                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1386         if (slot->pdata->get_cover_state != NULL)
1387                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1388
1389         tasklet_kill(&slot->cover_tasklet);
1390         del_timer_sync(&slot->cover_timer);
1391         flush_scheduled_work();
1392
1393         mmc_remove_host(mmc);
1394         mmc_free_host(mmc);
1395 }
1396
1397 static int __init mmc_omap_probe(struct platform_device *pdev)
1398 {
1399         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1400         struct mmc_omap_host *host = NULL;
1401         struct resource *res;
1402         int i, ret = 0;
1403         int irq;
1404
1405         if (pdata == NULL) {
1406                 dev_err(&pdev->dev, "platform data missing\n");
1407                 return -ENXIO;
1408         }
1409         if (pdata->nr_slots == 0) {
1410                 dev_err(&pdev->dev, "no slots\n");
1411                 return -ENXIO;
1412         }
1413
1414         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1415         irq = platform_get_irq(pdev, 0);
1416         if (res == NULL || irq < 0)
1417                 return -ENXIO;
1418
1419         res = request_mem_region(res->start, res->end - res->start + 1,
1420                                  pdev->name);
1421         if (res == NULL)
1422                 return -EBUSY;
1423
1424         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1425         if (host == NULL) {
1426                 ret = -ENOMEM;
1427                 goto err_free_mem_region;
1428         }
1429
1430         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1431         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1432
1433         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1434         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1435                     (unsigned long) host);
1436
1437         spin_lock_init(&host->clk_lock);
1438         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1439
1440         spin_lock_init(&host->dma_lock);
1441         setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1442         spin_lock_init(&host->slot_lock);
1443         init_waitqueue_head(&host->slot_wq);
1444
1445         host->pdata = pdata;
1446         host->dev = &pdev->dev;
1447         platform_set_drvdata(pdev, host);
1448
1449         host->id = pdev->id;
1450         host->mem_res = res;
1451         host->irq = irq;
1452
1453         host->use_dma = 1;
1454         host->dma_ch = -1;
1455
1456         host->irq = irq;
1457         host->phys_base = host->mem_res->start;
1458         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1459
1460         if (cpu_is_omap24xx()) {
1461                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1462                 if (IS_ERR(host->iclk))
1463                         goto err_free_mmc_host;
1464                 clk_enable(host->iclk);
1465         }
1466
1467         if (!cpu_is_omap24xx())
1468                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1469         else
1470                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1471
1472         if (IS_ERR(host->fclk)) {
1473                 ret = PTR_ERR(host->fclk);
1474                 goto err_free_iclk;
1475         }
1476
1477         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1478         if (ret)
1479                 goto err_free_fclk;
1480
1481         if (pdata->init != NULL) {
1482                 ret = pdata->init(&pdev->dev);
1483                 if (ret < 0)
1484                         goto err_free_irq;
1485         }
1486
1487         host->nr_slots = pdata->nr_slots;
1488         for (i = 0; i < pdata->nr_slots; i++) {
1489                 ret = mmc_omap_new_slot(host, i);
1490                 if (ret < 0) {
1491                         while (--i >= 0)
1492                                 mmc_omap_remove_slot(host->slots[i]);
1493
1494                         goto err_plat_cleanup;
1495                 }
1496         }
1497
1498         return 0;
1499
1500 err_plat_cleanup:
1501         if (pdata->cleanup)
1502                 pdata->cleanup(&pdev->dev);
1503 err_free_irq:
1504         free_irq(host->irq, host);
1505 err_free_fclk:
1506         clk_put(host->fclk);
1507 err_free_iclk:
1508         if (host->iclk != NULL) {
1509                 clk_disable(host->iclk);
1510                 clk_put(host->iclk);
1511         }
1512 err_free_mmc_host:
1513         kfree(host);
1514 err_free_mem_region:
1515         release_mem_region(res->start, res->end - res->start + 1);
1516         return ret;
1517 }
1518
1519 static int mmc_omap_remove(struct platform_device *pdev)
1520 {
1521         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1522         int i;
1523
1524         platform_set_drvdata(pdev, NULL);
1525
1526         BUG_ON(host == NULL);
1527
1528         for (i = 0; i < host->nr_slots; i++)
1529                 mmc_omap_remove_slot(host->slots[i]);
1530
1531         if (host->pdata->cleanup)
1532                 host->pdata->cleanup(&pdev->dev);
1533
1534         if (host->iclk && !IS_ERR(host->iclk))
1535                 clk_put(host->iclk);
1536         if (host->fclk && !IS_ERR(host->fclk))
1537                 clk_put(host->fclk);
1538
1539         release_mem_region(pdev->resource[0].start,
1540                            pdev->resource[0].end - pdev->resource[0].start + 1);
1541
1542         kfree(host);
1543
1544         return 0;
1545 }
1546
1547 #ifdef CONFIG_PM
1548 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1549 {
1550         int i, ret = 0;
1551         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1552
1553         if (host == NULL || host->suspended)
1554                 return 0;
1555
1556         for (i = 0; i < host->nr_slots; i++) {
1557                 struct mmc_omap_slot *slot;
1558
1559                 slot = host->slots[i];
1560                 ret = mmc_suspend_host(slot->mmc, mesg);
1561                 if (ret < 0) {
1562                         while (--i >= 0) {
1563                                 slot = host->slots[i];
1564                                 mmc_resume_host(slot->mmc);
1565                         }
1566                         return ret;
1567                 }
1568         }
1569         host->suspended = 1;
1570         return 0;
1571 }
1572
1573 static int mmc_omap_resume(struct platform_device *pdev)
1574 {
1575         int i, ret = 0;
1576         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1577
1578         if (host == NULL || !host->suspended)
1579                 return 0;
1580
1581         for (i = 0; i < host->nr_slots; i++) {
1582                 struct mmc_omap_slot *slot;
1583                 slot = host->slots[i];
1584                 ret = mmc_resume_host(slot->mmc);
1585                 if (ret < 0)
1586                         return ret;
1587
1588                 host->suspended = 0;
1589         }
1590         return 0;
1591 }
1592 #else
1593 #define mmc_omap_suspend        NULL
1594 #define mmc_omap_resume         NULL
1595 #endif
1596
1597 static struct platform_driver mmc_omap_driver = {
1598         .probe          = mmc_omap_probe,
1599         .remove         = mmc_omap_remove,
1600         .suspend        = mmc_omap_suspend,
1601         .resume         = mmc_omap_resume,
1602         .driver         = {
1603                 .name   = DRIVER_NAME,
1604                 .owner  = THIS_MODULE,
1605         },
1606 };
1607
1608 static int __init mmc_omap_init(void)
1609 {
1610         return platform_driver_register(&mmc_omap_driver);
1611 }
1612
1613 static void __exit mmc_omap_exit(void)
1614 {
1615         platform_driver_unregister(&mmc_omap_driver);
1616 }
1617
1618 module_init(mmc_omap_init);
1619 module_exit(mmc_omap_exit);
1620
1621 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1622 MODULE_LICENSE("GPL");
1623 MODULE_ALIAS("platform:" DRIVER_NAME);
1624 MODULE_AUTHOR("Juha Yrjölä");