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   1 /* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
   2  *
   3  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 MMC/SDIO register definitions
  11 */
  12
  13 #ifndef __ASM_ARM_REGS_SDI
  14 #define __ASM_ARM_REGS_SDI "regs-sdi.h"
  15
  16 #define S3C2410_SDICON                (0x00)
  17 #define S3C2410_SDIPRE                (0x04)
  18 #define S3C2410_SDICMDARG             (0x08)
  19 #define S3C2410_SDICMDCON             (0x0C)
  20 #define S3C2410_SDICMDSTAT            (0x10)
  21 #define S3C2410_SDIRSP0               (0x14)
  22 #define S3C2410_SDIRSP1               (0x18)
  23 #define S3C2410_SDIRSP2               (0x1C)
  24 #define S3C2410_SDIRSP3               (0x20)
  25 #define S3C2410_SDITIMER              (0x24)
  26 #define S3C2410_SDIBSIZE              (0x28)
  27 #define S3C2410_SDIDCON               (0x2C)
  28 #define S3C2410_SDIDCNT               (0x30)
  29 #define S3C2410_SDIDSTA               (0x34)
  30 #define S3C2410_SDIFSTA               (0x38)
  31
  32 #define S3C2410_SDIDATA               (0x3C)
  33 #define S3C2410_SDIIMSK               (0x40)
  34
  35 #define S3C2440_SDIDATA               (0x40)
  36 #define S3C2440_SDIIMSK               (0x3C)
  37
  38 #define S3C2440_SDICON_SDRESET        (1<<8)
  39 #define S3C2440_SDICON_MMCCLOCK       (1<<5)
  40 #define S3C2410_SDICON_BYTEORDER      (1<<4)
  41 #define S3C2410_SDICON_SDIOIRQ        (1<<3)
  42 #define S3C2410_SDICON_RWAITEN        (1<<2)
  43 #define S3C2410_SDICON_FIFORESET      (1<<1)
  44 #define S3C2410_SDICON_CLOCKTYPE      (1<<0)
  45
  46 #define S3C2410_SDICMDCON_ABORT       (1<<12)
  47 #define S3C2410_SDICMDCON_WITHDATA    (1<<11)
  48 #define S3C2410_SDICMDCON_LONGRSP     (1<<10)
  49 #define S3C2410_SDICMDCON_WAITRSP     (1<<9)
  50 #define S3C2410_SDICMDCON_CMDSTART    (1<<8)
  51 #define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
  52 #define S3C2410_SDICMDCON_INDEX       (0x3f)
  53
  54 #define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
  55 #define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
  56 #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
  57 #define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
  58 #define S3C2410_SDICMDSTAT_XFERING    (1<<8)
  59 #define S3C2410_SDICMDSTAT_INDEX      (0xff)
  60
  61 #define S3C2440_SDIDCON_DS_BYTE       (0<<22)
  62 #define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
  63 #define S3C2440_SDIDCON_DS_WORD       (2<<22)
  64 #define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
  65 #define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
  66 #define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
  67 #define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
  68 #define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
  69 #define S3C2410_SDIDCON_WIDEBUS       (1<<16)
  70 #define S3C2410_SDIDCON_DMAEN         (1<<15)
  71 #define S3C2410_SDIDCON_STOP          (1<<14)
  72 #define S3C2440_SDIDCON_DATSTART      (1<<14)
  73 #define S3C2410_SDIDCON_DATMODE       (3<<12)
  74 #define S3C2410_SDIDCON_BLKNUM        (0x7ff)
  75
  76 /* constants for S3C2410_SDIDCON_DATMODE */
  77 #define S3C2410_SDIDCON_XFER_READY    (0<<12)
  78 #define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
  79 #define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
  80 #define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
  81
  82 #define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
  83 #define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
  84
  85 #define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
  86 #define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
  87 #define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
  88 #define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
  89 #define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
  90 #define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
  91 #define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
  92 #define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
  93 #define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
  94 #define S3C2410_SDIDSTA_TXDATAON      (1<<1)
  95 #define S3C2410_SDIDSTA_RXDATAON      (1<<0)
  96
  97 #define S3C2440_SDIFSTA_FIFORESET      (1<<16)
  98 #define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
  99 #define S3C2410_SDIFSTA_TFDET          (1<<13)
 100 #define S3C2410_SDIFSTA_RFDET          (1<<12)
 101 #define S3C2410_SDIFSTA_TFHALF         (1<<11)
 102 #define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
 103 #define S3C2410_SDIFSTA_RFLAST         (1<<9)
 104 #define S3C2410_SDIFSTA_RFFULL         (1<<8)
 105 #define S3C2410_SDIFSTA_RFHALF         (1<<7)
 106 #define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
 107
 108 #define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
 109 #define S3C2410_SDIIMSK_CMDSENT        (1<<16)
 110 #define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
 111 #define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
 112 #define S3C2410_SDIIMSK_READWAIT       (1<<13)
 113 #define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
 114 #define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
 115 #define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
 116 #define S3C2410_SDIIMSK_DATACRC        (1<<9)
 117 #define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
 118 #define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
 119 #define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
 120 #define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
 121 #define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
 122 #define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
 123 #define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
 124 #define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
 125 #define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
 126
 127 #endif /* __ASM_ARM_REGS_SDI */