git.oblomov.eu Git - linux-2.6/blob - drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 static int radeon_do_cleanup_cp( drm_device_t *dev );
  40
  41 /* CP microcode (from ATI) */
  42 static u32 R200_cp_microcode[][2] = {
  43         { 0x21007000, 0000000000 },
  44         { 0x20007000, 0000000000 },
  45         { 0x000000ab, 0x00000004 },
  46         { 0x000000af, 0x00000004 },
  47         { 0x66544a49, 0000000000 },
  48         { 0x49494174, 0000000000 },
  49         { 0x54517d83, 0000000000 },
  50         { 0x498d8b64, 0000000000 },
  51         { 0x49494949, 0000000000 },
  52         { 0x49da493c, 0000000000 },
  53         { 0x49989898, 0000000000 },
  54         { 0xd34949d5, 0000000000 },
  55         { 0x9dc90e11, 0000000000 },
  56         { 0xce9b9b9b, 0000000000 },
  57         { 0x000f0000, 0x00000016 },
  58         { 0x352e232c, 0000000000 },
  59         { 0x00000013, 0x00000004 },
  60         { 0x000f0000, 0x00000016 },
  61         { 0x352e272c, 0000000000 },
  62         { 0x000f0001, 0x00000016 },
  63         { 0x3239362f, 0000000000 },
  64         { 0x000077ef, 0x00000002 },
  65         { 0x00061000, 0x00000002 },
  66         { 0x00000020, 0x0000001a },
  67         { 0x00004000, 0x0000001e },
  68         { 0x00061000, 0x00000002 },
  69         { 0x00000020, 0x0000001a },
  70         { 0x00004000, 0x0000001e },
  71         { 0x00061000, 0x00000002 },
  72         { 0x00000020, 0x0000001a },
  73         { 0x00004000, 0x0000001e },
  74         { 0x00000016, 0x00000004 },
  75         { 0x0003802a, 0x00000002 },
  76         { 0x040067e0, 0x00000002 },
  77         { 0x00000016, 0x00000004 },
  78         { 0x000077e0, 0x00000002 },
  79         { 0x00065000, 0x00000002 },
  80         { 0x000037e1, 0x00000002 },
  81         { 0x040067e1, 0x00000006 },
  82         { 0x000077e0, 0x00000002 },
  83         { 0x000077e1, 0x00000002 },
  84         { 0x000077e1, 0x00000006 },
  85         { 0xffffffff, 0000000000 },
  86         { 0x10000000, 0000000000 },
  87         { 0x0003802a, 0x00000002 },
  88         { 0x040067e0, 0x00000006 },
  89         { 0x00007675, 0x00000002 },
  90         { 0x00007676, 0x00000002 },
  91         { 0x00007677, 0x00000002 },
  92         { 0x00007678, 0x00000006 },
  93         { 0x0003802b, 0x00000002 },
  94         { 0x04002676, 0x00000002 },
  95         { 0x00007677, 0x00000002 },
  96         { 0x00007678, 0x00000006 },
  97         { 0x0000002e, 0x00000018 },
  98         { 0x0000002e, 0x00000018 },
  99         { 0000000000, 0x00000006 },
 100         { 0x0000002f, 0x00000018 },
 101         { 0x0000002f, 0x00000018 },
 102         { 0000000000, 0x00000006 },
 103         { 0x01605000, 0x00000002 },
 104         { 0x00065000, 0x00000002 },
 105         { 0x00098000, 0x00000002 },
 106         { 0x00061000, 0x00000002 },
 107         { 0x64c0603d, 0x00000004 },
 108         { 0x00080000, 0x00000016 },
 109         { 0000000000, 0000000000 },
 110         { 0x0400251d, 0x00000002 },
 111         { 0x00007580, 0x00000002 },
 112         { 0x00067581, 0x00000002 },
 113         { 0x04002580, 0x00000002 },
 114         { 0x00067581, 0x00000002 },
 115         { 0x00000046, 0x00000004 },
 116         { 0x00005000, 0000000000 },
 117         { 0x00061000, 0x00000002 },
 118         { 0x0000750e, 0x00000002 },
 119         { 0x00019000, 0x00000002 },
 120         { 0x00011055, 0x00000014 },
 121         { 0x00000055, 0x00000012 },
 122         { 0x0400250f, 0x00000002 },
 123         { 0x0000504a, 0x00000004 },
 124         { 0x00007565, 0x00000002 },
 125         { 0x00007566, 0x00000002 },
 126         { 0x00000051, 0x00000004 },
 127         { 0x01e655b4, 0x00000002 },
 128         { 0x4401b0dc, 0x00000002 },
 129         { 0x01c110dc, 0x00000002 },
 130         { 0x2666705d, 0x00000018 },
 131         { 0x040c2565, 0x00000002 },
 132         { 0x0000005d, 0x00000018 },
 133         { 0x04002564, 0x00000002 },
 134         { 0x00007566, 0x00000002 },
 135         { 0x00000054, 0x00000004 },
 136         { 0x00401060, 0x00000008 },
 137         { 0x00101000, 0x00000002 },
 138         { 0x000d80ff, 0x00000002 },
 139         { 0x00800063, 0x00000008 },
 140         { 0x000f9000, 0x00000002 },
 141         { 0x000e00ff, 0x00000002 },
 142         { 0000000000, 0x00000006 },
 143         { 0x00000080, 0x00000018 },
 144         { 0x00000054, 0x00000004 },
 145         { 0x00007576, 0x00000002 },
 146         { 0x00065000, 0x00000002 },
 147         { 0x00009000, 0x00000002 },
 148         { 0x00041000, 0x00000002 },
 149         { 0x0c00350e, 0x00000002 },
 150         { 0x00049000, 0x00000002 },
 151         { 0x00051000, 0x00000002 },
 152         { 0x01e785f8, 0x00000002 },
 153         { 0x00200000, 0x00000002 },
 154         { 0x00600073, 0x0000000c },
 155         { 0x00007563, 0x00000002 },
 156         { 0x006075f0, 0x00000021 },
 157         { 0x20007068, 0x00000004 },
 158         { 0x00005068, 0x00000004 },
 159         { 0x00007576, 0x00000002 },
 160         { 0x00007577, 0x00000002 },
 161         { 0x0000750e, 0x00000002 },
 162         { 0x0000750f, 0x00000002 },
 163         { 0x00a05000, 0x00000002 },
 164         { 0x00600076, 0x0000000c },
 165         { 0x006075f0, 0x00000021 },
 166         { 0x000075f8, 0x00000002 },
 167         { 0x00000076, 0x00000004 },
 168         { 0x000a750e, 0x00000002 },
 169         { 0x0020750f, 0x00000002 },
 170         { 0x00600079, 0x00000004 },
 171         { 0x00007570, 0x00000002 },
 172         { 0x00007571, 0x00000002 },
 173         { 0x00007572, 0x00000006 },
 174         { 0x00005000, 0x00000002 },
 175         { 0x00a05000, 0x00000002 },
 176         { 0x00007568, 0x00000002 },
 177         { 0x00061000, 0x00000002 },
 178         { 0x00000084, 0x0000000c },
 179         { 0x00058000, 0x00000002 },
 180         { 0x0c607562, 0x00000002 },
 181         { 0x00000086, 0x00000004 },
 182         { 0x00600085, 0x00000004 },
 183         { 0x400070dd, 0000000000 },
 184         { 0x000380dd, 0x00000002 },
 185         { 0x00000093, 0x0000001c },
 186         { 0x00065095, 0x00000018 },
 187         { 0x040025bb, 0x00000002 },
 188         { 0x00061096, 0x00000018 },
 189         { 0x040075bc, 0000000000 },
 190         { 0x000075bb, 0x00000002 },
 191         { 0x000075bc, 0000000000 },
 192         { 0x00090000, 0x00000006 },
 193         { 0x00090000, 0x00000002 },
 194         { 0x000d8002, 0x00000006 },
 195         { 0x00005000, 0x00000002 },
 196         { 0x00007821, 0x00000002 },
 197         { 0x00007800, 0000000000 },
 198         { 0x00007821, 0x00000002 },
 199         { 0x00007800, 0000000000 },
 200         { 0x01665000, 0x00000002 },
 201         { 0x000a0000, 0x00000002 },
 202         { 0x000671cc, 0x00000002 },
 203         { 0x0286f1cd, 0x00000002 },
 204         { 0x000000a3, 0x00000010 },
 205         { 0x21007000, 0000000000 },
 206         { 0x000000aa, 0x0000001c },
 207         { 0x00065000, 0x00000002 },
 208         { 0x000a0000, 0x00000002 },
 209         { 0x00061000, 0x00000002 },
 210         { 0x000b0000, 0x00000002 },
 211         { 0x38067000, 0x00000002 },
 212         { 0x000a00a6, 0x00000004 },
 213         { 0x20007000, 0000000000 },
 214         { 0x01200000, 0x00000002 },
 215         { 0x20077000, 0x00000002 },
 216         { 0x01200000, 0x00000002 },
 217         { 0x20007000, 0000000000 },
 218         { 0x00061000, 0x00000002 },
 219         { 0x0120751b, 0x00000002 },
 220         { 0x8040750a, 0x00000002 },
 221         { 0x8040750b, 0x00000002 },
 222         { 0x00110000, 0x00000002 },
 223         { 0x000380dd, 0x00000002 },
 224         { 0x000000bd, 0x0000001c },
 225         { 0x00061096, 0x00000018 },
 226         { 0x844075bd, 0x00000002 },
 227         { 0x00061095, 0x00000018 },
 228         { 0x840075bb, 0x00000002 },
 229         { 0x00061096, 0x00000018 },
 230         { 0x844075bc, 0x00000002 },
 231         { 0x000000c0, 0x00000004 },
 232         { 0x804075bd, 0x00000002 },
 233         { 0x800075bb, 0x00000002 },
 234         { 0x804075bc, 0x00000002 },
 235         { 0x00108000, 0x00000002 },
 236         { 0x01400000, 0x00000002 },
 237         { 0x006000c4, 0x0000000c },
 238         { 0x20c07000, 0x00000020 },
 239         { 0x000000c6, 0x00000012 },
 240         { 0x00800000, 0x00000006 },
 241         { 0x0080751d, 0x00000006 },
 242         { 0x000025bb, 0x00000002 },
 243         { 0x000040c0, 0x00000004 },
 244         { 0x0000775c, 0x00000002 },
 245         { 0x00a05000, 0x00000002 },
 246         { 0x00661000, 0x00000002 },
 247         { 0x0460275d, 0x00000020 },
 248         { 0x00004000, 0000000000 },
 249         { 0x00007999, 0x00000002 },
 250         { 0x00a05000, 0x00000002 },
 251         { 0x00661000, 0x00000002 },
 252         { 0x0460299b, 0x00000020 },
 253         { 0x00004000, 0000000000 },
 254         { 0x01e00830, 0x00000002 },
 255         { 0x21007000, 0000000000 },
 256         { 0x00005000, 0x00000002 },
 257         { 0x00038042, 0x00000002 },
 258         { 0x040025e0, 0x00000002 },
 259         { 0x000075e1, 0000000000 },
 260         { 0x00000001, 0000000000 },
 261         { 0x000380d9, 0x00000002 },
 262         { 0x04007394, 0000000000 },
 263         { 0000000000, 0000000000 },
 264         { 0000000000, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299 };
 300
 301
 302 static u32 radeon_cp_microcode[][2] = {
 303         { 0x21007000, 0000000000 },
 304         { 0x20007000, 0000000000 },
 305         { 0x000000b4, 0x00000004 },
 306         { 0x000000b8, 0x00000004 },
 307         { 0x6f5b4d4c, 0000000000 },
 308         { 0x4c4c427f, 0000000000 },
 309         { 0x5b568a92, 0000000000 },
 310         { 0x4ca09c6d, 0000000000 },
 311         { 0xad4c4c4c, 0000000000 },
 312         { 0x4ce1af3d, 0000000000 },
 313         { 0xd8afafaf, 0000000000 },
 314         { 0xd64c4cdc, 0000000000 },
 315         { 0x4cd10d10, 0000000000 },
 316         { 0x000f0000, 0x00000016 },
 317         { 0x362f242d, 0000000000 },
 318         { 0x00000012, 0x00000004 },
 319         { 0x000f0000, 0x00000016 },
 320         { 0x362f282d, 0000000000 },
 321         { 0x000380e7, 0x00000002 },
 322         { 0x04002c97, 0x00000002 },
 323         { 0x000f0001, 0x00000016 },
 324         { 0x333a3730, 0000000000 },
 325         { 0x000077ef, 0x00000002 },
 326         { 0x00061000, 0x00000002 },
 327         { 0x00000021, 0x0000001a },
 328         { 0x00004000, 0x0000001e },
 329         { 0x00061000, 0x00000002 },
 330         { 0x00000021, 0x0000001a },
 331         { 0x00004000, 0x0000001e },
 332         { 0x00061000, 0x00000002 },
 333         { 0x00000021, 0x0000001a },
 334         { 0x00004000, 0x0000001e },
 335         { 0x00000017, 0x00000004 },
 336         { 0x0003802b, 0x00000002 },
 337         { 0x040067e0, 0x00000002 },
 338         { 0x00000017, 0x00000004 },
 339         { 0x000077e0, 0x00000002 },
 340         { 0x00065000, 0x00000002 },
 341         { 0x000037e1, 0x00000002 },
 342         { 0x040067e1, 0x00000006 },
 343         { 0x000077e0, 0x00000002 },
 344         { 0x000077e1, 0x00000002 },
 345         { 0x000077e1, 0x00000006 },
 346         { 0xffffffff, 0000000000 },
 347         { 0x10000000, 0000000000 },
 348         { 0x0003802b, 0x00000002 },
 349         { 0x040067e0, 0x00000006 },
 350         { 0x00007675, 0x00000002 },
 351         { 0x00007676, 0x00000002 },
 352         { 0x00007677, 0x00000002 },
 353         { 0x00007678, 0x00000006 },
 354         { 0x0003802c, 0x00000002 },
 355         { 0x04002676, 0x00000002 },
 356         { 0x00007677, 0x00000002 },
 357         { 0x00007678, 0x00000006 },
 358         { 0x0000002f, 0x00000018 },
 359         { 0x0000002f, 0x00000018 },
 360         { 0000000000, 0x00000006 },
 361         { 0x00000030, 0x00000018 },
 362         { 0x00000030, 0x00000018 },
 363         { 0000000000, 0x00000006 },
 364         { 0x01605000, 0x00000002 },
 365         { 0x00065000, 0x00000002 },
 366         { 0x00098000, 0x00000002 },
 367         { 0x00061000, 0x00000002 },
 368         { 0x64c0603e, 0x00000004 },
 369         { 0x000380e6, 0x00000002 },
 370         { 0x040025c5, 0x00000002 },
 371         { 0x00080000, 0x00000016 },
 372         { 0000000000, 0000000000 },
 373         { 0x0400251d, 0x00000002 },
 374         { 0x00007580, 0x00000002 },
 375         { 0x00067581, 0x00000002 },
 376         { 0x04002580, 0x00000002 },
 377         { 0x00067581, 0x00000002 },
 378         { 0x00000049, 0x00000004 },
 379         { 0x00005000, 0000000000 },
 380         { 0x000380e6, 0x00000002 },
 381         { 0x040025c5, 0x00000002 },
 382         { 0x00061000, 0x00000002 },
 383         { 0x0000750e, 0x00000002 },
 384         { 0x00019000, 0x00000002 },
 385         { 0x00011055, 0x00000014 },
 386         { 0x00000055, 0x00000012 },
 387         { 0x0400250f, 0x00000002 },
 388         { 0x0000504f, 0x00000004 },
 389         { 0x000380e6, 0x00000002 },
 390         { 0x040025c5, 0x00000002 },
 391         { 0x00007565, 0x00000002 },
 392         { 0x00007566, 0x00000002 },
 393         { 0x00000058, 0x00000004 },
 394         { 0x000380e6, 0x00000002 },
 395         { 0x040025c5, 0x00000002 },
 396         { 0x01e655b4, 0x00000002 },
 397         { 0x4401b0e4, 0x00000002 },
 398         { 0x01c110e4, 0x00000002 },
 399         { 0x26667066, 0x00000018 },
 400         { 0x040c2565, 0x00000002 },
 401         { 0x00000066, 0x00000018 },
 402         { 0x04002564, 0x00000002 },
 403         { 0x00007566, 0x00000002 },
 404         { 0x0000005d, 0x00000004 },
 405         { 0x00401069, 0x00000008 },
 406         { 0x00101000, 0x00000002 },
 407         { 0x000d80ff, 0x00000002 },
 408         { 0x0080006c, 0x00000008 },
 409         { 0x000f9000, 0x00000002 },
 410         { 0x000e00ff, 0x00000002 },
 411         { 0000000000, 0x00000006 },
 412         { 0x0000008f, 0x00000018 },
 413         { 0x0000005b, 0x00000004 },
 414         { 0x000380e6, 0x00000002 },
 415         { 0x040025c5, 0x00000002 },
 416         { 0x00007576, 0x00000002 },
 417         { 0x00065000, 0x00000002 },
 418         { 0x00009000, 0x00000002 },
 419         { 0x00041000, 0x00000002 },
 420         { 0x0c00350e, 0x00000002 },
 421         { 0x00049000, 0x00000002 },
 422         { 0x00051000, 0x00000002 },
 423         { 0x01e785f8, 0x00000002 },
 424         { 0x00200000, 0x00000002 },
 425         { 0x0060007e, 0x0000000c },
 426         { 0x00007563, 0x00000002 },
 427         { 0x006075f0, 0x00000021 },
 428         { 0x20007073, 0x00000004 },
 429         { 0x00005073, 0x00000004 },
 430         { 0x000380e6, 0x00000002 },
 431         { 0x040025c5, 0x00000002 },
 432         { 0x00007576, 0x00000002 },
 433         { 0x00007577, 0x00000002 },
 434         { 0x0000750e, 0x00000002 },
 435         { 0x0000750f, 0x00000002 },
 436         { 0x00a05000, 0x00000002 },
 437         { 0x00600083, 0x0000000c },
 438         { 0x006075f0, 0x00000021 },
 439         { 0x000075f8, 0x00000002 },
 440         { 0x00000083, 0x00000004 },
 441         { 0x000a750e, 0x00000002 },
 442         { 0x000380e6, 0x00000002 },
 443         { 0x040025c5, 0x00000002 },
 444         { 0x0020750f, 0x00000002 },
 445         { 0x00600086, 0x00000004 },
 446         { 0x00007570, 0x00000002 },
 447         { 0x00007571, 0x00000002 },
 448         { 0x00007572, 0x00000006 },
 449         { 0x000380e6, 0x00000002 },
 450         { 0x040025c5, 0x00000002 },
 451         { 0x00005000, 0x00000002 },
 452         { 0x00a05000, 0x00000002 },
 453         { 0x00007568, 0x00000002 },
 454         { 0x00061000, 0x00000002 },
 455         { 0x00000095, 0x0000000c },
 456         { 0x00058000, 0x00000002 },
 457         { 0x0c607562, 0x00000002 },
 458         { 0x00000097, 0x00000004 },
 459         { 0x000380e6, 0x00000002 },
 460         { 0x040025c5, 0x00000002 },
 461         { 0x00600096, 0x00000004 },
 462         { 0x400070e5, 0000000000 },
 463         { 0x000380e6, 0x00000002 },
 464         { 0x040025c5, 0x00000002 },
 465         { 0x000380e5, 0x00000002 },
 466         { 0x000000a8, 0x0000001c },
 467         { 0x000650aa, 0x00000018 },
 468         { 0x040025bb, 0x00000002 },
 469         { 0x000610ab, 0x00000018 },
 470         { 0x040075bc, 0000000000 },
 471         { 0x000075bb, 0x00000002 },
 472         { 0x000075bc, 0000000000 },
 473         { 0x00090000, 0x00000006 },
 474         { 0x00090000, 0x00000002 },
 475         { 0x000d8002, 0x00000006 },
 476         { 0x00007832, 0x00000002 },
 477         { 0x00005000, 0x00000002 },
 478         { 0x000380e7, 0x00000002 },
 479         { 0x04002c97, 0x00000002 },
 480         { 0x00007820, 0x00000002 },
 481         { 0x00007821, 0x00000002 },
 482         { 0x00007800, 0000000000 },
 483         { 0x01200000, 0x00000002 },
 484         { 0x20077000, 0x00000002 },
 485         { 0x01200000, 0x00000002 },
 486         { 0x20007000, 0x00000002 },
 487         { 0x00061000, 0x00000002 },
 488         { 0x0120751b, 0x00000002 },
 489         { 0x8040750a, 0x00000002 },
 490         { 0x8040750b, 0x00000002 },
 491         { 0x00110000, 0x00000002 },
 492         { 0x000380e5, 0x00000002 },
 493         { 0x000000c6, 0x0000001c },
 494         { 0x000610ab, 0x00000018 },
 495         { 0x844075bd, 0x00000002 },
 496         { 0x000610aa, 0x00000018 },
 497         { 0x840075bb, 0x00000002 },
 498         { 0x000610ab, 0x00000018 },
 499         { 0x844075bc, 0x00000002 },
 500         { 0x000000c9, 0x00000004 },
 501         { 0x804075bd, 0x00000002 },
 502         { 0x800075bb, 0x00000002 },
 503         { 0x804075bc, 0x00000002 },
 504         { 0x00108000, 0x00000002 },
 505         { 0x01400000, 0x00000002 },
 506         { 0x006000cd, 0x0000000c },
 507         { 0x20c07000, 0x00000020 },
 508         { 0x000000cf, 0x00000012 },
 509         { 0x00800000, 0x00000006 },
 510         { 0x0080751d, 0x00000006 },
 511         { 0000000000, 0000000000 },
 512         { 0x0000775c, 0x00000002 },
 513         { 0x00a05000, 0x00000002 },
 514         { 0x00661000, 0x00000002 },
 515         { 0x0460275d, 0x00000020 },
 516         { 0x00004000, 0000000000 },
 517         { 0x01e00830, 0x00000002 },
 518         { 0x21007000, 0000000000 },
 519         { 0x6464614d, 0000000000 },
 520         { 0x69687420, 0000000000 },
 521         { 0x00000073, 0000000000 },
 522         { 0000000000, 0000000000 },
 523         { 0x00005000, 0x00000002 },
 524         { 0x000380d0, 0x00000002 },
 525         { 0x040025e0, 0x00000002 },
 526         { 0x000075e1, 0000000000 },
 527         { 0x00000001, 0000000000 },
 528         { 0x000380e0, 0x00000002 },
 529         { 0x04002394, 0x00000002 },
 530         { 0x00005000, 0000000000 },
 531         { 0000000000, 0000000000 },
 532         { 0000000000, 0000000000 },
 533         { 0x00000008, 0000000000 },
 534         { 0x00000004, 0000000000 },
 535         { 0000000000, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557         { 0000000000, 0000000000 },
 558         { 0000000000, 0000000000 },
 559 };
 560
 561 static u32 R300_cp_microcode[][2] = {
 562         { 0x4200e000, 0000000000 },
 563         { 0x4000e000, 0000000000 },
 564         { 0x000000af, 0x00000008 },
 565         { 0x000000b3, 0x00000008 },
 566         { 0x6c5a504f, 0000000000 },
 567         { 0x4f4f497a, 0000000000 },
 568         { 0x5a578288, 0000000000 },
 569         { 0x4f91906a, 0000000000 },
 570         { 0x4f4f4f4f, 0000000000 },
 571         { 0x4fe24f44, 0000000000 },
 572         { 0x4f9c9c9c, 0000000000 },
 573         { 0xdc4f4fde, 0000000000 },
 574         { 0xa1cd4f4f, 0000000000 },
 575         { 0xd29d9d9d, 0000000000 },
 576         { 0x4f0f9fd7, 0000000000 },
 577         { 0x000ca000, 0x00000004 },
 578         { 0x000d0012, 0x00000038 },
 579         { 0x0000e8b4, 0x00000004 },
 580         { 0x000d0014, 0x00000038 },
 581         { 0x0000e8b6, 0x00000004 },
 582         { 0x000d0016, 0x00000038 },
 583         { 0x0000e854, 0x00000004 },
 584         { 0x000d0018, 0x00000038 },
 585         { 0x0000e855, 0x00000004 },
 586         { 0x000d001a, 0x00000038 },
 587         { 0x0000e856, 0x00000004 },
 588         { 0x000d001c, 0x00000038 },
 589         { 0x0000e857, 0x00000004 },
 590         { 0x000d001e, 0x00000038 },
 591         { 0x0000e824, 0x00000004 },
 592         { 0x000d0020, 0x00000038 },
 593         { 0x0000e825, 0x00000004 },
 594         { 0x000d0022, 0x00000038 },
 595         { 0x0000e830, 0x00000004 },
 596         { 0x000d0024, 0x00000038 },
 597         { 0x0000f0c0, 0x00000004 },
 598         { 0x000d0026, 0x00000038 },
 599         { 0x0000f0c1, 0x00000004 },
 600         { 0x000d0028, 0x00000038 },
 601         { 0x0000f041, 0x00000004 },
 602         { 0x000d002a, 0x00000038 },
 603         { 0x0000f184, 0x00000004 },
 604         { 0x000d002c, 0x00000038 },
 605         { 0x0000f185, 0x00000004 },
 606         { 0x000d002e, 0x00000038 },
 607         { 0x0000f186, 0x00000004 },
 608         { 0x000d0030, 0x00000038 },
 609         { 0x0000f187, 0x00000004 },
 610         { 0x000d0032, 0x00000038 },
 611         { 0x0000f180, 0x00000004 },
 612         { 0x000d0034, 0x00000038 },
 613         { 0x0000f393, 0x00000004 },
 614         { 0x000d0036, 0x00000038 },
 615         { 0x0000f38a, 0x00000004 },
 616         { 0x000d0038, 0x00000038 },
 617         { 0x0000f38e, 0x00000004 },
 618         { 0x0000e821, 0x00000004 },
 619         { 0x0140a000, 0x00000004 },
 620         { 0x00000043, 0x00000018 },
 621         { 0x00cce800, 0x00000004 },
 622         { 0x001b0001, 0x00000004 },
 623         { 0x08004800, 0x00000004 },
 624         { 0x001b0001, 0x00000004 },
 625         { 0x08004800, 0x00000004 },
 626         { 0x001b0001, 0x00000004 },
 627         { 0x08004800, 0x00000004 },
 628         { 0x0000003a, 0x00000008 },
 629         { 0x0000a000, 0000000000 },
 630         { 0x02c0a000, 0x00000004 },
 631         { 0x000ca000, 0x00000004 },
 632         { 0x00130000, 0x00000004 },
 633         { 0x000c2000, 0x00000004 },
 634         { 0xc980c045, 0x00000008 },
 635         { 0x2000451d, 0x00000004 },
 636         { 0x0000e580, 0x00000004 },
 637         { 0x000ce581, 0x00000004 },
 638         { 0x08004580, 0x00000004 },
 639         { 0x000ce581, 0x00000004 },
 640         { 0x0000004c, 0x00000008 },
 641         { 0x0000a000, 0000000000 },
 642         { 0x000c2000, 0x00000004 },
 643         { 0x0000e50e, 0x00000004 },
 644         { 0x00032000, 0x00000004 },
 645         { 0x00022056, 0x00000028 },
 646         { 0x00000056, 0x00000024 },
 647         { 0x0800450f, 0x00000004 },
 648         { 0x0000a050, 0x00000008 },
 649         { 0x0000e565, 0x00000004 },
 650         { 0x0000e566, 0x00000004 },
 651         { 0x00000057, 0x00000008 },
 652         { 0x03cca5b4, 0x00000004 },
 653         { 0x05432000, 0x00000004 },
 654         { 0x00022000, 0x00000004 },
 655         { 0x4ccce063, 0x00000030 },
 656         { 0x08274565, 0x00000004 },
 657         { 0x00000063, 0x00000030 },
 658         { 0x08004564, 0x00000004 },
 659         { 0x0000e566, 0x00000004 },
 660         { 0x0000005a, 0x00000008 },
 661         { 0x00802066, 0x00000010 },
 662         { 0x00202000, 0x00000004 },
 663         { 0x001b00ff, 0x00000004 },
 664         { 0x01000069, 0x00000010 },
 665         { 0x001f2000, 0x00000004 },
 666         { 0x001c00ff, 0x00000004 },
 667         { 0000000000, 0x0000000c },
 668         { 0x00000085, 0x00000030 },
 669         { 0x0000005a, 0x00000008 },
 670         { 0x0000e576, 0x00000004 },
 671         { 0x000ca000, 0x00000004 },
 672         { 0x00012000, 0x00000004 },
 673         { 0x00082000, 0x00000004 },
 674         { 0x1800650e, 0x00000004 },
 675         { 0x00092000, 0x00000004 },
 676         { 0x000a2000, 0x00000004 },
 677         { 0x000f0000, 0x00000004 },
 678         { 0x00400000, 0x00000004 },
 679         { 0x00000079, 0x00000018 },
 680         { 0x0000e563, 0x00000004 },
 681         { 0x00c0e5f9, 0x000000c2 },
 682         { 0x0000006e, 0x00000008 },
 683         { 0x0000a06e, 0x00000008 },
 684         { 0x0000e576, 0x00000004 },
 685         { 0x0000e577, 0x00000004 },
 686         { 0x0000e50e, 0x00000004 },
 687         { 0x0000e50f, 0x00000004 },
 688         { 0x0140a000, 0x00000004 },
 689         { 0x0000007c, 0x00000018 },
 690         { 0x00c0e5f9, 0x000000c2 },
 691         { 0x0000007c, 0x00000008 },
 692         { 0x0014e50e, 0x00000004 },
 693         { 0x0040e50f, 0x00000004 },
 694         { 0x00c0007f, 0x00000008 },
 695         { 0x0000e570, 0x00000004 },
 696         { 0x0000e571, 0x00000004 },
 697         { 0x0000e572, 0x0000000c },
 698         { 0x0000a000, 0x00000004 },
 699         { 0x0140a000, 0x00000004 },
 700         { 0x0000e568, 0x00000004 },
 701         { 0x000c2000, 0x00000004 },
 702         { 0x00000089, 0x00000018 },
 703         { 0x000b0000, 0x00000004 },
 704         { 0x18c0e562, 0x00000004 },
 705         { 0x0000008b, 0x00000008 },
 706         { 0x00c0008a, 0x00000008 },
 707         { 0x000700e4, 0x00000004 },
 708         { 0x00000097, 0x00000038 },
 709         { 0x000ca099, 0x00000030 },
 710         { 0x080045bb, 0x00000004 },
 711         { 0x000c209a, 0x00000030 },
 712         { 0x0800e5bc, 0000000000 },
 713         { 0x0000e5bb, 0x00000004 },
 714         { 0x0000e5bc, 0000000000 },
 715         { 0x00120000, 0x0000000c },
 716         { 0x00120000, 0x00000004 },
 717         { 0x001b0002, 0x0000000c },
 718         { 0x0000a000, 0x00000004 },
 719         { 0x0000e821, 0x00000004 },
 720         { 0x0000e800, 0000000000 },
 721         { 0x0000e821, 0x00000004 },
 722         { 0x0000e82e, 0000000000 },
 723         { 0x02cca000, 0x00000004 },
 724         { 0x00140000, 0x00000004 },
 725         { 0x000ce1cc, 0x00000004 },
 726         { 0x050de1cd, 0x00000004 },
 727         { 0x000000a7, 0x00000020 },
 728         { 0x4200e000, 0000000000 },
 729         { 0x000000ae, 0x00000038 },
 730         { 0x000ca000, 0x00000004 },
 731         { 0x00140000, 0x00000004 },
 732         { 0x000c2000, 0x00000004 },
 733         { 0x00160000, 0x00000004 },
 734         { 0x700ce000, 0x00000004 },
 735         { 0x001400aa, 0x00000008 },
 736         { 0x4000e000, 0000000000 },
 737         { 0x02400000, 0x00000004 },
 738         { 0x400ee000, 0x00000004 },
 739         { 0x02400000, 0x00000004 },
 740         { 0x4000e000, 0000000000 },
 741         { 0x000c2000, 0x00000004 },
 742         { 0x0240e51b, 0x00000004 },
 743         { 0x0080e50a, 0x00000005 },
 744         { 0x0080e50b, 0x00000005 },
 745         { 0x00220000, 0x00000004 },
 746         { 0x000700e4, 0x00000004 },
 747         { 0x000000c1, 0x00000038 },
 748         { 0x000c209a, 0x00000030 },
 749         { 0x0880e5bd, 0x00000005 },
 750         { 0x000c2099, 0x00000030 },
 751         { 0x0800e5bb, 0x00000005 },
 752         { 0x000c209a, 0x00000030 },
 753         { 0x0880e5bc, 0x00000005 },
 754         { 0x000000c4, 0x00000008 },
 755         { 0x0080e5bd, 0x00000005 },
 756         { 0x0000e5bb, 0x00000005 },
 757         { 0x0080e5bc, 0x00000005 },
 758         { 0x00210000, 0x00000004 },
 759         { 0x02800000, 0x00000004 },
 760         { 0x00c000c8, 0x00000018 },
 761         { 0x4180e000, 0x00000040 },
 762         { 0x000000ca, 0x00000024 },
 763         { 0x01000000, 0x0000000c },
 764         { 0x0100e51d, 0x0000000c },
 765         { 0x000045bb, 0x00000004 },
 766         { 0x000080c4, 0x00000008 },
 767         { 0x0000f3ce, 0x00000004 },
 768         { 0x0140a000, 0x00000004 },
 769         { 0x00cc2000, 0x00000004 },
 770         { 0x08c053cf, 0x00000040 },
 771         { 0x00008000, 0000000000 },
 772         { 0x0000f3d2, 0x00000004 },
 773         { 0x0140a000, 0x00000004 },
 774         { 0x00cc2000, 0x00000004 },
 775         { 0x08c053d3, 0x00000040 },
 776         { 0x00008000, 0000000000 },
 777         { 0x0000f39d, 0x00000004 },
 778         { 0x0140a000, 0x00000004 },
 779         { 0x00cc2000, 0x00000004 },
 780         { 0x08c0539e, 0x00000040 },
 781         { 0x00008000, 0000000000 },
 782         { 0x03c00830, 0x00000004 },
 783         { 0x4200e000, 0000000000 },
 784         { 0x0000a000, 0x00000004 },
 785         { 0x200045e0, 0x00000004 },
 786         { 0x0000e5e1, 0000000000 },
 787         { 0x00000001, 0000000000 },
 788         { 0x000700e1, 0x00000004 },
 789         { 0x0800e394, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816         { 0000000000, 0000000000 },
 817         { 0000000000, 0000000000 },
 818 };
 819
 820 static int RADEON_READ_PLL(drm_device_t *dev, int addr)
 821 {
 822         drm_radeon_private_t *dev_priv = dev->dev_private;
 823
 824         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 825         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 826 }
 827
 828 #if RADEON_FIFO_DEBUG
 829 static void radeon_status( drm_radeon_private_t *dev_priv )
 830 {
 831         printk( "%s:\n", __FUNCTION__ );
 832         printk( "RBBM_STATUS = 0x%08x\n",
 833                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 834         printk( "CP_RB_RTPR = 0x%08x\n",
 835                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 836         printk( "CP_RB_WTPR = 0x%08x\n",
 837                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 838         printk( "AIC_CNTL = 0x%08x\n",
 839                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 840         printk( "AIC_STAT = 0x%08x\n",
 841                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 842         printk( "AIC_PT_BASE = 0x%08x\n",
 843                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 844         printk( "TLB_ADDR = 0x%08x\n",
 845                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 846         printk( "TLB_DATA = 0x%08x\n",
 847                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 848 }
 849 #endif
 850
 851
 852 /* ================================================================
 853  * Engine, FIFO control
 854  */
 855
 856 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 857 {
 858         u32 tmp;
 859         int i;
 860
 861         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 862
 863         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 864         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 865         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 866
 867         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 868                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 869                        & RADEON_RB2D_DC_BUSY) ) {
 870                         return 0;
 871                 }
 872                 DRM_UDELAY( 1 );
 873         }
 874
 875 #if RADEON_FIFO_DEBUG
 876         DRM_ERROR( "failed!\n" );
 877         radeon_status( dev_priv );
 878 #endif
 879         return DRM_ERR(EBUSY);
 880 }
 881
 882 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 883                                     int entries )
 884 {
 885         int i;
 886
 887         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 888
 889         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 890                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 891                               & RADEON_RBBM_FIFOCNT_MASK );
 892                 if ( slots >= entries ) return 0;
 893                 DRM_UDELAY( 1 );
 894         }
 895
 896 #if RADEON_FIFO_DEBUG
 897         DRM_ERROR( "failed!\n" );
 898         radeon_status( dev_priv );
 899 #endif
 900         return DRM_ERR(EBUSY);
 901 }
 902
 903 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 904 {
 905         int i, ret;
 906
 907         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 908
 909         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 910         if ( ret ) return ret;
 911
 912         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 913                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 914                        & RADEON_RBBM_ACTIVE) ) {
 915                         radeon_do_pixcache_flush( dev_priv );
 916                         return 0;
 917                 }
 918                 DRM_UDELAY( 1 );
 919         }
 920
 921 #if RADEON_FIFO_DEBUG
 922         DRM_ERROR( "failed!\n" );
 923         radeon_status( dev_priv );
 924 #endif
 925         return DRM_ERR(EBUSY);
 926 }
 927
 928
 929 /* ================================================================
 930  * CP control, initialization
 931  */
 932
 933 /* Load the microcode for the CP */
 934 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 935 {
 936         int i;
 937         DRM_DEBUG( "\n" );
 938
 939         radeon_do_wait_for_idle( dev_priv );
 940
 941         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 942
 943         if (dev_priv->microcode_version==UCODE_R200) {
 944                 DRM_INFO("Loading R200 Microcode\n");
 945                 for ( i = 0 ; i < 256 ; i++ )
 946                 {
 947                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 948                                       R200_cp_microcode[i][1] );
 949                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 950                                       R200_cp_microcode[i][0] );
 951                 }
 952         } else if (dev_priv->microcode_version==UCODE_R300) {
 953                 DRM_INFO("Loading R300 Microcode\n");
 954                 for ( i = 0 ; i < 256 ; i++ )
 955                 {
 956                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 957                                       R300_cp_microcode[i][1] );
 958                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 959                                       R300_cp_microcode[i][0] );
 960                 }
 961         } else {
 962                 for ( i = 0 ; i < 256 ; i++ ) {
 963                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 964                                       radeon_cp_microcode[i][1] );
 965                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 966                                       radeon_cp_microcode[i][0] );
 967                 }
 968         }
 969 }
 970
 971 /* Flush any pending commands to the CP.  This should only be used just
 972  * prior to a wait for idle, as it informs the engine that the command
 973  * stream is ending.
 974  */
 975 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 976 {
 977         DRM_DEBUG( "\n" );
 978 #if 0
 979         u32 tmp;
 980
 981         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 982         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 983 #endif
 984 }
 985
 986 /* Wait for the CP to go idle.
 987  */
 988 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 989 {
 990         RING_LOCALS;
 991         DRM_DEBUG( "\n" );
 992
 993         BEGIN_RING( 6 );
 994
 995         RADEON_PURGE_CACHE();
 996         RADEON_PURGE_ZCACHE();
 997         RADEON_WAIT_UNTIL_IDLE();
 998
 999         ADVANCE_RING();
1000         COMMIT_RING();
1001
1002         return radeon_do_wait_for_idle( dev_priv );
1003 }
1004
1005 /* Start the Command Processor.
1006  */
1007 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1008 {
1009         RING_LOCALS;
1010         DRM_DEBUG( "\n" );
1011
1012         radeon_do_wait_for_idle( dev_priv );
1013
1014         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
1015
1016         dev_priv->cp_running = 1;
1017
1018         BEGIN_RING( 6 );
1019
1020         RADEON_PURGE_CACHE();
1021         RADEON_PURGE_ZCACHE();
1022         RADEON_WAIT_UNTIL_IDLE();
1023
1024         ADVANCE_RING();
1025         COMMIT_RING();
1026 }
1027
1028 /* Reset the Command Processor.  This will not flush any pending
1029  * commands, so you must wait for the CP command stream to complete
1030  * before calling this routine.
1031  */
1032 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1033 {
1034         u32 cur_read_ptr;
1035         DRM_DEBUG( "\n" );
1036
1037         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1038         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1039         SET_RING_HEAD( dev_priv, cur_read_ptr );
1040         dev_priv->ring.tail = cur_read_ptr;
1041 }
1042
1043 /* Stop the Command Processor.  This will not flush any pending
1044  * commands, so you must flush the command stream and wait for the CP
1045  * to go idle before calling this routine.
1046  */
1047 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
1048 {
1049         DRM_DEBUG( "\n" );
1050
1051         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
1052
1053         dev_priv->cp_running = 0;
1054 }
1055
1056 /* Reset the engine.  This will stop the CP if it is running.
1057  */
1058 static int radeon_do_engine_reset( drm_device_t *dev )
1059 {
1060         drm_radeon_private_t *dev_priv = dev->dev_private;
1061         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1062         DRM_DEBUG( "\n" );
1063
1064         radeon_do_pixcache_flush( dev_priv );
1065
1066         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1067         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1068
1069         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1070                                               RADEON_FORCEON_MCLKA |
1071                                               RADEON_FORCEON_MCLKB |
1072                                               RADEON_FORCEON_YCLKA |
1073                                               RADEON_FORCEON_YCLKB |
1074                                               RADEON_FORCEON_MC |
1075                                               RADEON_FORCEON_AIC ) );
1076
1077         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1078
1079         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
1080                                                 RADEON_SOFT_RESET_CP |
1081                                                 RADEON_SOFT_RESET_HI |
1082                                                 RADEON_SOFT_RESET_SE |
1083                                                 RADEON_SOFT_RESET_RE |
1084                                                 RADEON_SOFT_RESET_PP |
1085                                                 RADEON_SOFT_RESET_E2 |
1086                                                 RADEON_SOFT_RESET_RB ) );
1087         RADEON_READ( RADEON_RBBM_SOFT_RESET );
1088         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
1089                                                 ~( RADEON_SOFT_RESET_CP |
1090                                                    RADEON_SOFT_RESET_HI |
1091                                                    RADEON_SOFT_RESET_SE |
1092                                                    RADEON_SOFT_RESET_RE |
1093                                                    RADEON_SOFT_RESET_PP |
1094                                                    RADEON_SOFT_RESET_E2 |
1095                                                    RADEON_SOFT_RESET_RB ) ) );
1096         RADEON_READ( RADEON_RBBM_SOFT_RESET );
1097
1098
1099         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1100         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1101         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
1102
1103         /* Reset the CP ring */
1104         radeon_do_cp_reset( dev_priv );
1105
1106         /* The CP is no longer running after an engine reset */
1107         dev_priv->cp_running = 0;
1108
1109         /* Reset any pending vertex, indirect buffers */
1110         radeon_freelist_reset( dev );
1111
1112         return 0;
1113 }
1114
1115 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1116                                         drm_radeon_private_t *dev_priv )
1117 {
1118         u32 ring_start, cur_read_ptr;
1119         u32 tmp;
1120
1121         /* Initialize the memory controller */
1122         RADEON_WRITE( RADEON_MC_FB_LOCATION,
1123                       ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
1124                     | ( dev_priv->fb_location >> 16 ) );
1125
1126 #if __OS_HAS_AGP
1127         if ( !dev_priv->is_pci ) {
1128                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
1129                               (((dev_priv->gart_vm_start - 1 +
1130                                  dev_priv->gart_size) & 0xffff0000) |
1131                                (dev_priv->gart_vm_start >> 16)) );
1132
1133                 ring_start = (dev_priv->cp_ring->offset
1134                               - dev->agp->base
1135                               + dev_priv->gart_vm_start);
1136         } else
1137 #endif
1138                 ring_start = (dev_priv->cp_ring->offset
1139                               - (unsigned long)dev->sg->virtual
1140                               + dev_priv->gart_vm_start);
1141
1142         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
1143
1144         /* Set the write pointer delay */
1145         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
1146
1147         /* Initialize the ring buffer's read and write pointers */
1148         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1149         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1150         SET_RING_HEAD( dev_priv, cur_read_ptr );
1151         dev_priv->ring.tail = cur_read_ptr;
1152
1153 #if __OS_HAS_AGP
1154         if ( !dev_priv->is_pci ) {
1155                 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1156                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1157                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1158                               dev_priv->ring_rptr->offset
1159                               - dev->agp->base
1160                               + dev_priv->gart_vm_start);
1161         } else
1162 #endif
1163         {
1164                 drm_sg_mem_t *entry = dev->sg;
1165                 unsigned long tmp_ofs, page_ofs;
1166
1167                 tmp_ofs = dev_priv->ring_rptr->offset -
1168                                 (unsigned long)dev->sg->virtual;
1169                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1170
1171                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1172                              entry->busaddr[page_ofs]);
1173                 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
1174                            (unsigned long) entry->busaddr[page_ofs],
1175                            entry->handle + tmp_ofs );
1176         }
1177
1178         /* Initialize the scratch register pointer.  This will cause
1179          * the scratch register values to be written out to memory
1180          * whenever they are updated.
1181          *
1182          * We simply put this behind the ring read pointer, this works
1183          * with PCI GART as well as (whatever kind of) AGP GART
1184          */
1185         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
1186                                          + RADEON_SCRATCH_REG_OFFSET );
1187
1188         dev_priv->scratch = ((__volatile__ u32 *)
1189                              dev_priv->ring_rptr->handle +
1190                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1191
1192         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
1193
1194         /* Writeback doesn't seem to work everywhere, test it first */
1195         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
1196         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
1197
1198         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
1199                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
1200                         break;
1201                 DRM_UDELAY( 1 );
1202         }
1203
1204         if ( tmp < dev_priv->usec_timeout ) {
1205                 dev_priv->writeback_works = 1;
1206                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
1207         } else {
1208                 dev_priv->writeback_works = 0;
1209                 DRM_DEBUG( "writeback test failed\n" );
1210         }
1211
1212         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1213         RADEON_WRITE( RADEON_LAST_FRAME_REG,
1214                       dev_priv->sarea_priv->last_frame );
1215
1216         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1217         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
1218                       dev_priv->sarea_priv->last_dispatch );
1219
1220         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1221         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
1222                       dev_priv->sarea_priv->last_clear );
1223
1224         /* Set ring buffer size */
1225 #ifdef __BIG_ENDIAN
1226         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
1227 #else
1228         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
1229 #endif
1230
1231         radeon_do_wait_for_idle( dev_priv );
1232
1233         /* Turn on bus mastering */
1234         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
1235         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
1236
1237         /* Sync everything up */
1238         RADEON_WRITE( RADEON_ISYNC_CNTL,
1239                       (RADEON_ISYNC_ANY2D_IDLE3D |
1240                        RADEON_ISYNC_ANY3D_IDLE2D |
1241                        RADEON_ISYNC_WAIT_IDLEGUI |
1242                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
1243 }
1244
1245 /* Enable or disable PCI GART on the chip */
1246 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1247 {
1248         u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
1249
1250         if ( on ) {
1251                 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
1252
1253                 /* set PCI GART page-table base address
1254                  */
1255                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1256
1257                 /* set address range for PCI address translate
1258                  */
1259                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
1260                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1261                                                   + dev_priv->gart_size - 1);
1262
1263                 /* Turn off AGP aperture -- is this required for PCI GART?
1264                  */
1265                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1266                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1267         } else {
1268                 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1269         }
1270 }
1271
1272 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1273 {
1274         drm_radeon_private_t *dev_priv = dev->dev_private;;
1275         DRM_DEBUG( "\n" );
1276
1277         dev_priv->is_pci = init->is_pci;
1278
1279         if ( dev_priv->is_pci && !dev->sg ) {
1280                 DRM_ERROR( "PCI GART memory not allocated!\n" );
1281                 dev->dev_private = (void *)dev_priv;
1282                 radeon_do_cleanup_cp(dev);
1283                 return DRM_ERR(EINVAL);
1284         }
1285
1286         dev_priv->usec_timeout = init->usec_timeout;
1287         if ( dev_priv->usec_timeout < 1 ||
1288              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1289                 DRM_DEBUG( "TIMEOUT problem!\n" );
1290                 dev->dev_private = (void *)dev_priv;
1291                 radeon_do_cleanup_cp(dev);
1292                 return DRM_ERR(EINVAL);
1293         }
1294
1295         switch(init->func) {
1296         case RADEON_INIT_R200_CP:
1297                 dev_priv->microcode_version=UCODE_R200;
1298                 break;
1299         case RADEON_INIT_R300_CP:
1300                 dev_priv->microcode_version=UCODE_R300;
1301                 break;
1302         default:
1303                 dev_priv->microcode_version=UCODE_R100;
1304         }
1305
1306         dev_priv->do_boxes = 0;
1307         dev_priv->cp_mode = init->cp_mode;
1308
1309         /* We don't support anything other than bus-mastering ring mode,
1310          * but the ring can be in either AGP or PCI space for the ring
1311          * read pointer.
1312          */
1313         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1314              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1315                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1316                 dev->dev_private = (void *)dev_priv;
1317                 radeon_do_cleanup_cp(dev);
1318                 return DRM_ERR(EINVAL);
1319         }
1320
1321         switch ( init->fb_bpp ) {
1322         case 16:
1323                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1324                 break;
1325         case 32:
1326         default:
1327                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1328                 break;
1329         }
1330         dev_priv->front_offset  = init->front_offset;
1331         dev_priv->front_pitch   = init->front_pitch;
1332         dev_priv->back_offset   = init->back_offset;
1333         dev_priv->back_pitch    = init->back_pitch;
1334
1335         switch ( init->depth_bpp ) {
1336         case 16:
1337                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1338                 break;
1339         case 32:
1340         default:
1341                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1342                 break;
1343         }
1344         dev_priv->depth_offset  = init->depth_offset;
1345         dev_priv->depth_pitch   = init->depth_pitch;
1346
1347         /* Hardware state for depth clears.  Remove this if/when we no
1348          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1349          * all values to prevent unwanted 3D state from slipping through
1350          * and screwing with the clear operation.
1351          */
1352         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1353                                            (dev_priv->color_fmt << 10) |
1354                                            (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1355
1356         dev_priv->depth_clear.rb3d_zstencilcntl =
1357                 (dev_priv->depth_fmt |
1358                  RADEON_Z_TEST_ALWAYS |
1359                  RADEON_STENCIL_TEST_ALWAYS |
1360                  RADEON_STENCIL_S_FAIL_REPLACE |
1361                  RADEON_STENCIL_ZPASS_REPLACE |
1362                  RADEON_STENCIL_ZFAIL_REPLACE |
1363                  RADEON_Z_WRITE_ENABLE);
1364
1365         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1366                                          RADEON_BFACE_SOLID |
1367                                          RADEON_FFACE_SOLID |
1368                                          RADEON_FLAT_SHADE_VTX_LAST |
1369                                          RADEON_DIFFUSE_SHADE_FLAT |
1370                                          RADEON_ALPHA_SHADE_FLAT |
1371                                          RADEON_SPECULAR_SHADE_FLAT |
1372                                          RADEON_FOG_SHADE_FLAT |
1373                                          RADEON_VTX_PIX_CENTER_OGL |
1374                                          RADEON_ROUND_MODE_TRUNC |
1375                                          RADEON_ROUND_PREC_8TH_PIX);
1376
1377         DRM_GETSAREA();
1378
1379         dev_priv->fb_offset = init->fb_offset;
1380         dev_priv->mmio_offset = init->mmio_offset;
1381         dev_priv->ring_offset = init->ring_offset;
1382         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1383         dev_priv->buffers_offset = init->buffers_offset;
1384         dev_priv->gart_textures_offset = init->gart_textures_offset;
1385
1386         if(!dev_priv->sarea) {
1387                 DRM_ERROR("could not find sarea!\n");
1388                 dev->dev_private = (void *)dev_priv;
1389                 radeon_do_cleanup_cp(dev);
1390                 return DRM_ERR(EINVAL);
1391         }
1392
1393         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1394         if(!dev_priv->mmio) {
1395                 DRM_ERROR("could not find mmio region!\n");
1396                 dev->dev_private = (void *)dev_priv;
1397                 radeon_do_cleanup_cp(dev);
1398                 return DRM_ERR(EINVAL);
1399         }
1400         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1401         if(!dev_priv->cp_ring) {
1402                 DRM_ERROR("could not find cp ring region!\n");
1403                 dev->dev_private = (void *)dev_priv;
1404                 radeon_do_cleanup_cp(dev);
1405                 return DRM_ERR(EINVAL);
1406         }
1407         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1408         if(!dev_priv->ring_rptr) {
1409                 DRM_ERROR("could not find ring read pointer!\n");
1410                 dev->dev_private = (void *)dev_priv;
1411                 radeon_do_cleanup_cp(dev);
1412                 return DRM_ERR(EINVAL);
1413         }
1414         dev->agp_buffer_token = init->buffers_offset;
1415         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1416         if(!dev->agp_buffer_map) {
1417                 DRM_ERROR("could not find dma buffer region!\n");
1418                 dev->dev_private = (void *)dev_priv;
1419                 radeon_do_cleanup_cp(dev);
1420                 return DRM_ERR(EINVAL);
1421         }
1422
1423         if ( init->gart_textures_offset ) {
1424                 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1425                 if ( !dev_priv->gart_textures ) {
1426                         DRM_ERROR("could not find GART texture region!\n");
1427                         dev->dev_private = (void *)dev_priv;
1428                         radeon_do_cleanup_cp(dev);
1429                         return DRM_ERR(EINVAL);
1430                 }
1431         }
1432
1433         dev_priv->sarea_priv =
1434                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1435                                        init->sarea_priv_offset);
1436
1437 #if __OS_HAS_AGP
1438         if ( !dev_priv->is_pci ) {
1439                 drm_core_ioremap( dev_priv->cp_ring, dev );
1440                 drm_core_ioremap( dev_priv->ring_rptr, dev );
1441                 drm_core_ioremap( dev->agp_buffer_map, dev );
1442                 if(!dev_priv->cp_ring->handle ||
1443                    !dev_priv->ring_rptr->handle ||
1444                    !dev->agp_buffer_map->handle) {
1445                         DRM_ERROR("could not find ioremap agp regions!\n");
1446                         dev->dev_private = (void *)dev_priv;
1447                         radeon_do_cleanup_cp(dev);
1448                         return DRM_ERR(EINVAL);
1449                 }
1450         } else
1451 #endif
1452         {
1453                 dev_priv->cp_ring->handle =
1454                         (void *)dev_priv->cp_ring->offset;
1455                 dev_priv->ring_rptr->handle =
1456                         (void *)dev_priv->ring_rptr->offset;
1457                 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1458
1459                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1460                            dev_priv->cp_ring->handle );
1461                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1462                            dev_priv->ring_rptr->handle );
1463                 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1464                            dev->agp_buffer_map->handle );
1465         }
1466
1467         dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1468                                 & 0xffff ) << 16;
1469
1470         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1471                                         ( ( dev_priv->front_offset
1472                                           + dev_priv->fb_location ) >> 10 ) );
1473
1474         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1475                                        ( ( dev_priv->back_offset
1476                                          + dev_priv->fb_location ) >> 10 ) );
1477
1478         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1479                                         ( ( dev_priv->depth_offset
1480                                           + dev_priv->fb_location ) >> 10 ) );
1481
1482
1483         dev_priv->gart_size = init->gart_size;
1484         dev_priv->gart_vm_start = dev_priv->fb_location
1485                                 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1486
1487 #if __OS_HAS_AGP
1488         if ( !dev_priv->is_pci )
1489                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1490                                                 - dev->agp->base
1491                                                 + dev_priv->gart_vm_start);
1492         else
1493 #endif
1494                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1495                                         - (unsigned long)dev->sg->virtual
1496                                         + dev_priv->gart_vm_start);
1497
1498         DRM_DEBUG( "dev_priv->gart_size %d\n",
1499                    dev_priv->gart_size );
1500         DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1501                    dev_priv->gart_vm_start );
1502         DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1503                    dev_priv->gart_buffers_offset );
1504
1505         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1506         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1507                               + init->ring_size / sizeof(u32));
1508         dev_priv->ring.size = init->ring_size;
1509         dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
1510
1511         dev_priv->ring.tail_mask =
1512                 (dev_priv->ring.size / sizeof(u32)) - 1;
1513
1514         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1515
1516 #if __OS_HAS_AGP
1517         if ( !dev_priv->is_pci ) {
1518                 /* Turn off PCI GART */
1519                 radeon_set_pcigart( dev_priv, 0 );
1520         } else
1521 #endif
1522         {
1523                 if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
1524                                             &dev_priv->bus_pci_gart)) {
1525                         DRM_ERROR( "failed to init PCI GART!\n" );
1526                         dev->dev_private = (void *)dev_priv;
1527                         radeon_do_cleanup_cp(dev);
1528                         return DRM_ERR(ENOMEM);
1529                 }
1530
1531                 /* Turn on PCI GART */
1532                 radeon_set_pcigart( dev_priv, 1 );
1533         }
1534
1535         radeon_cp_load_microcode( dev_priv );
1536         radeon_cp_init_ring_buffer( dev, dev_priv );
1537
1538         dev_priv->last_buf = 0;
1539
1540         dev->dev_private = (void *)dev_priv;
1541
1542         radeon_do_engine_reset( dev );
1543
1544         return 0;
1545 }
1546
1547 static int radeon_do_cleanup_cp( drm_device_t *dev )
1548 {
1549         drm_radeon_private_t *dev_priv = dev->dev_private;
1550         DRM_DEBUG( "\n" );
1551
1552         /* Make sure interrupts are disabled here because the uninstall ioctl
1553          * may not have been called from userspace and after dev_private
1554          * is freed, it's too late.
1555          */
1556         if ( dev->irq_enabled ) drm_irq_uninstall(dev);
1557
1558 #if __OS_HAS_AGP
1559         if ( !dev_priv->is_pci ) {
1560                 if ( dev_priv->cp_ring != NULL )
1561                         drm_core_ioremapfree( dev_priv->cp_ring, dev );
1562                 if ( dev_priv->ring_rptr != NULL )
1563                         drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1564                 if ( dev->agp_buffer_map != NULL )
1565                 {
1566                         drm_core_ioremapfree( dev->agp_buffer_map, dev );
1567                         dev->agp_buffer_map = NULL;
1568                 }
1569         } else
1570 #endif
1571         {
1572                 if (!drm_ati_pcigart_cleanup( dev,
1573                                               dev_priv->phys_pci_gart,
1574                                               dev_priv->bus_pci_gart ))
1575                         DRM_ERROR( "failed to cleanup PCI GART!\n" );
1576         }
1577
1578         /* only clear to the start of flags */
1579         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1580
1581         return 0;
1582 }
1583
1584 /* This code will reinit the Radeon CP hardware after a resume from disc.
1585  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1586  * here we make sure that all Radeon hardware initialisation is re-done without
1587  * affecting running applications.
1588  *
1589  * Charl P. Botha <http://cpbotha.net>
1590  */
1591 static int radeon_do_resume_cp( drm_device_t *dev )
1592 {
1593         drm_radeon_private_t *dev_priv = dev->dev_private;
1594
1595         if ( !dev_priv ) {
1596                 DRM_ERROR( "Called with no initialization\n" );
1597                 return DRM_ERR( EINVAL );
1598         }
1599
1600         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1601
1602 #if __OS_HAS_AGP
1603         if ( !dev_priv->is_pci ) {
1604                 /* Turn off PCI GART */
1605                 radeon_set_pcigart( dev_priv, 0 );
1606         } else
1607 #endif
1608         {
1609                 /* Turn on PCI GART */
1610                 radeon_set_pcigart( dev_priv, 1 );
1611         }
1612
1613         radeon_cp_load_microcode( dev_priv );
1614         radeon_cp_init_ring_buffer( dev, dev_priv );
1615
1616         radeon_do_engine_reset( dev );
1617
1618         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1619
1620         return 0;
1621 }
1622
1623
1624 int radeon_cp_init( DRM_IOCTL_ARGS )
1625 {
1626         DRM_DEVICE;
1627         drm_radeon_init_t init;
1628
1629         LOCK_TEST_WITH_RETURN( dev, filp );
1630
1631         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1632
1633         if(init.func == RADEON_INIT_R300_CP)
1634                 r300_init_reg_flags();
1635
1636         switch ( init.func ) {
1637         case RADEON_INIT_CP:
1638         case RADEON_INIT_R200_CP:
1639         case RADEON_INIT_R300_CP:
1640                 return radeon_do_init_cp( dev, &init );
1641         case RADEON_CLEANUP_CP:
1642                 return radeon_do_cleanup_cp( dev );
1643         }
1644
1645         return DRM_ERR(EINVAL);
1646 }
1647
1648 int radeon_cp_start( DRM_IOCTL_ARGS )
1649 {
1650         DRM_DEVICE;
1651         drm_radeon_private_t *dev_priv = dev->dev_private;
1652         DRM_DEBUG( "\n" );
1653
1654         LOCK_TEST_WITH_RETURN( dev, filp );
1655
1656         if ( dev_priv->cp_running ) {
1657                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1658                 return 0;
1659         }
1660         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1661                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1662                            __FUNCTION__, dev_priv->cp_mode );
1663                 return 0;
1664         }
1665
1666         radeon_do_cp_start( dev_priv );
1667
1668         return 0;
1669 }
1670
1671 /* Stop the CP.  The engine must have been idled before calling this
1672  * routine.
1673  */
1674 int radeon_cp_stop( DRM_IOCTL_ARGS )
1675 {
1676         DRM_DEVICE;
1677         drm_radeon_private_t *dev_priv = dev->dev_private;
1678         drm_radeon_cp_stop_t stop;
1679         int ret;
1680         DRM_DEBUG( "\n" );
1681
1682         LOCK_TEST_WITH_RETURN( dev, filp );
1683
1684         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1685
1686         if (!dev_priv->cp_running)
1687                 return 0;
1688
1689         /* Flush any pending CP commands.  This ensures any outstanding
1690          * commands are exectuted by the engine before we turn it off.
1691          */
1692         if ( stop.flush ) {
1693                 radeon_do_cp_flush( dev_priv );
1694         }
1695
1696         /* If we fail to make the engine go idle, we return an error
1697          * code so that the DRM ioctl wrapper can try again.
1698          */
1699         if ( stop.idle ) {
1700                 ret = radeon_do_cp_idle( dev_priv );
1701                 if ( ret ) return ret;
1702         }
1703
1704         /* Finally, we can turn off the CP.  If the engine isn't idle,
1705          * we will get some dropped triangles as they won't be fully
1706          * rendered before the CP is shut down.
1707          */
1708         radeon_do_cp_stop( dev_priv );
1709
1710         /* Reset the engine */
1711         radeon_do_engine_reset( dev );
1712
1713         return 0;
1714 }
1715
1716
1717 void radeon_do_release( drm_device_t *dev )
1718 {
1719         drm_radeon_private_t *dev_priv = dev->dev_private;
1720         int i, ret;
1721
1722         if (dev_priv) {
1723                 if (dev_priv->cp_running) {
1724                         /* Stop the cp */
1725                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1726                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1727 #ifdef __linux__
1728                                 schedule();
1729 #else
1730                                 tsleep(&ret, PZERO, "rdnrel", 1);
1731 #endif
1732                         }
1733                         radeon_do_cp_stop( dev_priv );
1734                         radeon_do_engine_reset( dev );
1735                 }
1736
1737                 /* Disable *all* interrupts */
1738                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1739                         RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1740
1741                 if (dev_priv->mmio) {/* remove all surfaces */
1742                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1743                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1744                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1745                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1746                         }
1747                 }
1748
1749                 /* Free memory heap structures */
1750                 radeon_mem_takedown( &(dev_priv->gart_heap) );
1751                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1752
1753                 /* deallocate kernel resources */
1754                 radeon_do_cleanup_cp( dev );
1755         }
1756 }
1757
1758 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1759  */
1760 int radeon_cp_reset( DRM_IOCTL_ARGS )
1761 {
1762         DRM_DEVICE;
1763         drm_radeon_private_t *dev_priv = dev->dev_private;
1764         DRM_DEBUG( "\n" );
1765
1766         LOCK_TEST_WITH_RETURN( dev, filp );
1767
1768         if ( !dev_priv ) {
1769                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1770                 return DRM_ERR(EINVAL);
1771         }
1772
1773         radeon_do_cp_reset( dev_priv );
1774
1775         /* The CP is no longer running after an engine reset */
1776         dev_priv->cp_running = 0;
1777
1778         return 0;
1779 }
1780
1781 int radeon_cp_idle( DRM_IOCTL_ARGS )
1782 {
1783         DRM_DEVICE;
1784         drm_radeon_private_t *dev_priv = dev->dev_private;
1785         DRM_DEBUG( "\n" );
1786
1787         LOCK_TEST_WITH_RETURN( dev, filp );
1788
1789         return radeon_do_cp_idle( dev_priv );
1790 }
1791
1792 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1793  */
1794 int radeon_cp_resume( DRM_IOCTL_ARGS )
1795 {
1796         DRM_DEVICE;
1797
1798         return radeon_do_resume_cp(dev);
1799 }
1800
1801
1802 int radeon_engine_reset( DRM_IOCTL_ARGS )
1803 {
1804         DRM_DEVICE;
1805         DRM_DEBUG( "\n" );
1806
1807         LOCK_TEST_WITH_RETURN( dev, filp );
1808
1809         return radeon_do_engine_reset( dev );
1810 }
1811
1812
1813 /* ================================================================
1814  * Fullscreen mode
1815  */
1816
1817 /* KW: Deprecated to say the least:
1818  */
1819 int radeon_fullscreen( DRM_IOCTL_ARGS )
1820 {
1821         return 0;
1822 }
1823
1824
1825 /* ================================================================
1826  * Freelist management
1827  */
1828
1829 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1830  *   bufs until freelist code is used.  Note this hides a problem with
1831  *   the scratch register * (used to keep track of last buffer
1832  *   completed) being written to before * the last buffer has actually
1833  *   completed rendering.
1834  *
1835  * KW:  It's also a good way to find free buffers quickly.
1836  *
1837  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1838  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1839  * we essentially have to do this, else old clients will break.
1840  *
1841  * However, it does leave open a potential deadlock where all the
1842  * buffers are held by other clients, which can't release them because
1843  * they can't get the lock.
1844  */
1845
1846 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1847 {
1848         drm_device_dma_t *dma = dev->dma;
1849         drm_radeon_private_t *dev_priv = dev->dev_private;
1850         drm_radeon_buf_priv_t *buf_priv;
1851         drm_buf_t *buf;
1852         int i, t;
1853         int start;
1854
1855         if ( ++dev_priv->last_buf >= dma->buf_count )
1856                 dev_priv->last_buf = 0;
1857
1858         start = dev_priv->last_buf;
1859
1860         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1861                 u32 done_age = GET_SCRATCH( 1 );
1862                 DRM_DEBUG("done_age = %d\n",done_age);
1863                 for ( i = start ; i < dma->buf_count ; i++ ) {
1864                         buf = dma->buflist[i];
1865                         buf_priv = buf->dev_private;
1866                         if ( buf->filp == 0 || (buf->pending &&
1867                                                buf_priv->age <= done_age) ) {
1868                                 dev_priv->stats.requested_bufs++;
1869                                 buf->pending = 0;
1870                                 return buf;
1871                         }
1872                         start = 0;
1873                 }
1874
1875                 if (t) {
1876                         DRM_UDELAY( 1 );
1877                         dev_priv->stats.freelist_loops++;
1878                 }
1879         }
1880
1881         DRM_DEBUG( "returning NULL!\n" );
1882         return NULL;
1883 }
1884 #if 0
1885 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1886 {
1887         drm_device_dma_t *dma = dev->dma;
1888         drm_radeon_private_t *dev_priv = dev->dev_private;
1889         drm_radeon_buf_priv_t *buf_priv;
1890         drm_buf_t *buf;
1891         int i, t;
1892         int start;
1893         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1894
1895         if ( ++dev_priv->last_buf >= dma->buf_count )
1896                 dev_priv->last_buf = 0;
1897
1898         start = dev_priv->last_buf;
1899         dev_priv->stats.freelist_loops++;
1900
1901         for ( t = 0 ; t < 2 ; t++ ) {
1902                 for ( i = start ; i < dma->buf_count ; i++ ) {
1903                         buf = dma->buflist[i];
1904                         buf_priv = buf->dev_private;
1905                         if ( buf->filp == 0 || (buf->pending &&
1906                                                buf_priv->age <= done_age) ) {
1907                                 dev_priv->stats.requested_bufs++;
1908                                 buf->pending = 0;
1909                                 return buf;
1910                         }
1911                 }
1912                 start = 0;
1913         }
1914
1915         return NULL;
1916 }
1917 #endif
1918
1919 void radeon_freelist_reset( drm_device_t *dev )
1920 {
1921         drm_device_dma_t *dma = dev->dma;
1922         drm_radeon_private_t *dev_priv = dev->dev_private;
1923         int i;
1924
1925         dev_priv->last_buf = 0;
1926         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1927                 drm_buf_t *buf = dma->buflist[i];
1928                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1929                 buf_priv->age = 0;
1930         }
1931 }
1932
1933
1934 /* ================================================================
1935  * CP command submission
1936  */
1937
1938 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1939 {
1940         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1941         int i;
1942         u32 last_head = GET_RING_HEAD( dev_priv );
1943
1944         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1945                 u32 head = GET_RING_HEAD( dev_priv );
1946
1947                 ring->space = (head - ring->tail) * sizeof(u32);
1948                 if ( ring->space <= 0 )
1949                         ring->space += ring->size;
1950                 if ( ring->space > n )
1951                         return 0;
1952
1953                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1954
1955                 if (head != last_head)
1956                         i = 0;
1957                 last_head = head;
1958
1959                 DRM_UDELAY( 1 );
1960         }
1961
1962         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1963 #if RADEON_FIFO_DEBUG
1964         radeon_status( dev_priv );
1965         DRM_ERROR( "failed!\n" );
1966 #endif
1967         return DRM_ERR(EBUSY);
1968 }
1969
1970 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1971 {
1972         int i;
1973         drm_buf_t *buf;
1974
1975         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1976                 buf = radeon_freelist_get( dev );
1977                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1978
1979                 buf->filp = filp;
1980
1981                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1982                                    sizeof(buf->idx) ) )
1983                         return DRM_ERR(EFAULT);
1984                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1985                                    sizeof(buf->total) ) )
1986                         return DRM_ERR(EFAULT);
1987
1988                 d->granted_count++;
1989         }
1990         return 0;
1991 }
1992
1993 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1994 {
1995         DRM_DEVICE;
1996         drm_device_dma_t *dma = dev->dma;
1997         int ret = 0;
1998         drm_dma_t __user *argp = (void __user *)data;
1999         drm_dma_t d;
2000
2001         LOCK_TEST_WITH_RETURN( dev, filp );
2002
2003         DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
2004
2005         /* Please don't send us buffers.
2006          */
2007         if ( d.send_count != 0 ) {
2008                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
2009                            DRM_CURRENTPID, d.send_count );
2010                 return DRM_ERR(EINVAL);
2011         }
2012
2013         /* We'll send you buffers.
2014          */
2015         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
2016                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
2017                            DRM_CURRENTPID, d.request_count, dma->buf_count );
2018                 return DRM_ERR(EINVAL);
2019         }
2020
2021         d.granted_count = 0;
2022
2023         if ( d.request_count ) {
2024                 ret = radeon_cp_get_buffers( filp, dev, &d );
2025         }
2026
2027         DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
2028
2029         return ret;
2030 }
2031
2032 int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2033 {
2034         drm_radeon_private_t *dev_priv;
2035         int ret = 0;
2036
2037         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2038         if (dev_priv == NULL)
2039                 return DRM_ERR(ENOMEM);
2040
2041         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2042         dev->dev_private = (void *)dev_priv;
2043         dev_priv->flags = flags;
2044
2045         switch (flags & CHIP_FAMILY_MASK) {
2046         case CHIP_R100:
2047         case CHIP_RV200:
2048         case CHIP_R200:
2049         case CHIP_R300:
2050         case CHIP_R420:
2051                 dev_priv->flags |= CHIP_HAS_HIERZ;
2052                 break;
2053         default:
2054         /* all other chips have no hierarchical z buffer */
2055                 break;
2056         }
2057
2058         if (drm_device_is_agp(dev))
2059                 dev_priv->flags |= CHIP_IS_AGP;
2060
2061         DRM_DEBUG("%s card detected\n",
2062                   ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2063         return ret;
2064 }
2065
2066 int radeon_presetup(struct drm_device *dev)
2067 {
2068         int ret;
2069         drm_local_map_t *map;
2070         drm_radeon_private_t *dev_priv = dev->dev_private;
2071
2072         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2073                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2074                          _DRM_READ_ONLY, &dev_priv->mmio);
2075         if (ret != 0)
2076                 return ret;
2077
2078         ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2079                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2080                          _DRM_WRITE_COMBINING, &map);
2081         if (ret != 0)
2082                 return ret;
2083
2084         return 0;
2085 }
2086
2087 int radeon_driver_postcleanup(struct drm_device *dev)
2088 {
2089         drm_radeon_private_t *dev_priv = dev->dev_private;
2090
2091         DRM_DEBUG("\n");
2092
2093         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2094
2095         dev->dev_private = NULL;
2096         return 0;
2097 }