2 ** System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6 ** (c) Copyright 2000-2004 Hewlett-Packard Company
8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17 ** J5000/J7000/N-class/L-class machines and their successors.
19 ** FIXME: add DMA hint support programming in both sba and lba modules.
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
29 #include <linux/string.h>
30 #include <linux/pci.h>
32 #include <asm/byteorder.h>
34 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
36 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
38 #include <linux/proc_fs.h>
39 #include <linux/seq_file.h>
41 #include <asm/mckinley.h> /* for proc_mckinley_root */
42 #include <asm/runway.h> /* for proc_runway_root */
43 #include <asm/pdc.h> /* for PDC_MODEL_* */
44 #include <asm/pdcpat.h> /* for is_pdc_pat() */
45 #include <asm/parisc-device.h>
47 #define MODULE_NAME "SBA"
50 /* depends on proc fs support. But costs CPU performance */
51 #undef SBA_COLLECT_STATS
55 ** The number of debug flags is a clue - this code is fragile.
56 ** Don't even think about messing with it unless you have
57 ** plenty of 710's to sacrifice to the computer gods. :^)
61 #undef DEBUG_SBA_RUN_SG
62 #undef DEBUG_SBA_RESOURCE
63 #undef ASSERT_PDIR_SANITY
64 #undef DEBUG_LARGE_SG_ENTRIES
68 #define DBG_INIT(x...) printk(x)
70 #define DBG_INIT(x...)
74 #define DBG_RUN(x...) printk(x)
79 #ifdef DEBUG_SBA_RUN_SG
80 #define DBG_RUN_SG(x...) printk(x)
82 #define DBG_RUN_SG(x...)
86 #ifdef DEBUG_SBA_RESOURCE
87 #define DBG_RES(x...) printk(x)
92 #if defined(CONFIG_64BIT)
93 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
97 #define SBA_INLINE __inline__
101 ** The number of pdir entries to "free" before issueing
102 ** a read to PCOM register to flush out PCOM writes.
103 ** Interacts with allocation granularity (ie 4 or 8 entries
104 ** allocated and free'd/purged at a time might make this
105 ** less interesting).
107 #define DELAYED_RESOURCE_CNT 16
109 #define DEFAULT_DMA_HINT_REG 0
111 #define ASTRO_RUNWAY_PORT 0x582
112 #define IKE_MERCED_PORT 0x803
113 #define REO_MERCED_PORT 0x804
114 #define REOG_MERCED_PORT 0x805
115 #define PLUTO_MCKINLEY_PORT 0x880
117 #define SBA_FUNC_ID 0x0000 /* function id */
118 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
120 static inline int IS_ASTRO(struct parisc_device *d) {
121 return d->id.hversion == ASTRO_RUNWAY_PORT;
124 static inline int IS_IKE(struct parisc_device *d) {
125 return d->id.hversion == IKE_MERCED_PORT;
128 static inline int IS_PLUTO(struct parisc_device *d) {
129 return d->id.hversion == PLUTO_MCKINLEY_PORT;
132 #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
134 #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
135 #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
136 /* Ike's IOC's occupy functions 2 and 3 */
137 #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
139 #define IOC_CTRL 0x8 /* IOC_CTRL offset */
140 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
141 #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
142 #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
143 #define IOC_CTRL_RM (1 << 8) /* Real Mode */
144 #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
145 #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
146 #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
148 #define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
150 #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
154 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
155 ** Firmware programs this stuff. Don't touch it.
157 #define LMMIO_DIRECT0_BASE 0x300
158 #define LMMIO_DIRECT0_MASK 0x308
159 #define LMMIO_DIRECT0_ROUTE 0x310
161 #define LMMIO_DIST_BASE 0x360
162 #define LMMIO_DIST_MASK 0x368
163 #define LMMIO_DIST_ROUTE 0x370
165 #define IOS_DIST_BASE 0x390
166 #define IOS_DIST_MASK 0x398
167 #define IOS_DIST_ROUTE 0x3A0
169 #define IOS_DIRECT_BASE 0x3C0
170 #define IOS_DIRECT_MASK 0x3C8
171 #define IOS_DIRECT_ROUTE 0x3D0
174 ** Offsets into I/O TLB (Function 2 and 3 on Ike)
176 #define ROPE0_CTL 0x200 /* "regbus pci0" */
177 #define ROPE1_CTL 0x208
178 #define ROPE2_CTL 0x210
179 #define ROPE3_CTL 0x218
180 #define ROPE4_CTL 0x220
181 #define ROPE5_CTL 0x228
182 #define ROPE6_CTL 0x230
183 #define ROPE7_CTL 0x238
185 #define IOC_ROPE0_CFG 0x500 /* pluto only */
186 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
190 #define HF_ENABLE 0x40
193 #define IOC_IBASE 0x300 /* IO TLB */
194 #define IOC_IMASK 0x308
195 #define IOC_PCOM 0x310
196 #define IOC_TCNFG 0x318
197 #define IOC_PDIR_BASE 0x320
199 /* AGP GART driver looks for this */
200 #define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
204 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
205 ** It's safer (avoid memory corruption) to keep DMA page mappings
206 ** equivalently sized to VM PAGE_SIZE.
208 ** We really can't avoid generating a new mapping for each
209 ** page since the Virtual Coherence Index has to be generated
210 ** and updated for each page.
212 ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
214 #define IOVP_SIZE PAGE_SIZE
215 #define IOVP_SHIFT PAGE_SHIFT
216 #define IOVP_MASK PAGE_MASK
218 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
219 #define SBA_PERF_MASK1 0x718
220 #define SBA_PERF_MASK2 0x730
224 ** Offsets into PCI Performance Counters (functions 12 and 13)
225 ** Controlled by PERF registers in function 2 & 3 respectively.
227 #define SBA_PERF_CNT1 0x200
228 #define SBA_PERF_CNT2 0x208
229 #define SBA_PERF_CNT3 0x210
233 void __iomem *ioc_hpa; /* I/O MMU base address */
234 char *res_map; /* resource map, bit == pdir entry */
235 u64 *pdir_base; /* physical base address */
236 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
237 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
239 unsigned long iovp_mask; /* help convert IOVA to IOVP */
241 unsigned long *res_hint; /* next avail IOVP - circular search */
243 unsigned int res_bitshift; /* from the LEFT! */
244 unsigned int res_size; /* size of resource map in bytes */
245 #ifdef SBA_HINT_SUPPORT
246 /* FIXME : DMA HINTs not used */
247 unsigned long hint_mask_pdir; /* bits used for DMA hints */
248 unsigned int hint_shift_pdir;
250 #if DELAYED_RESOURCE_CNT > 0
252 struct sba_dma_pair {
255 } saved[DELAYED_RESOURCE_CNT];
258 #ifdef SBA_COLLECT_STATS
259 #define SBA_SEARCH_SAMPLE 0x100
260 unsigned long avg_search[SBA_SEARCH_SAMPLE];
261 unsigned long avg_idx; /* current index into avg_search */
262 unsigned long used_pages;
263 unsigned long msingle_calls;
264 unsigned long msingle_pages;
265 unsigned long msg_calls;
266 unsigned long msg_pages;
267 unsigned long usingle_calls;
268 unsigned long usingle_pages;
269 unsigned long usg_calls;
270 unsigned long usg_pages;
273 /* STUFF We don't need in performance path */
274 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
278 struct sba_device *next; /* list of SBA's in system */
279 struct parisc_device *dev; /* dev found in bus walk */
281 void __iomem *sba_hpa; /* base address */
283 unsigned int flags; /* state/functionality enabled */
284 unsigned int hw_rev; /* HW revision of chip */
286 struct resource chip_resv; /* MMIO reserved for chip */
287 struct resource iommu_resv; /* MMIO reserved for iommu */
289 unsigned int num_ioc; /* number of on-board IOC's */
290 struct ioc ioc[MAX_IOC];
294 static struct sba_device *sba_list;
296 static unsigned long ioc_needs_fdc = 0;
298 /* global count of IOMMUs in the system */
299 static unsigned int global_ioc_cnt = 0;
301 /* PA8700 (Piranha 2.2) bug workaround */
302 static unsigned long piranha_bad_128k = 0;
304 /* Looks nice and keeps the compiler happy */
305 #define SBA_DEV(d) ((struct sba_device *) (d))
307 #ifdef SBA_AGP_SUPPORT
308 static int reserve_sba_gart = 1;
311 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
314 /************************************
315 ** SBA register read and write support
317 ** BE WARNED: register writes are posted.
318 ** (ie follow writes which must reach HW with a read)
320 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
322 #define READ_REG32(addr) readl(addr)
323 #define READ_REG64(addr) readq(addr)
324 #define WRITE_REG32(val, addr) writel((val), (addr))
325 #define WRITE_REG64(val, addr) writeq((val), (addr))
328 #define READ_REG(addr) READ_REG64(addr)
329 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
331 #define READ_REG(addr) READ_REG32(addr)
332 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
335 #ifdef DEBUG_SBA_INIT
337 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
340 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
341 * @hpa: base address of the sba
343 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
344 * IO Adapter (aka Bus Converter).
347 sba_dump_ranges(void __iomem *hpa)
349 DBG_INIT("SBA at 0x%p\n", hpa);
350 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
351 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
352 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
354 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
355 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
356 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
360 * sba_dump_tlb - debugging only - print IOMMU operating parameters
361 * @hpa: base address of the IOMMU
363 * Print the size/location of the IO MMU PDIR.
365 static void sba_dump_tlb(void __iomem *hpa)
367 DBG_INIT("IO TLB at 0x%p\n", hpa);
368 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
369 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
370 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
371 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
375 #define sba_dump_ranges(x)
376 #define sba_dump_tlb(x)
377 #endif /* DEBUG_SBA_INIT */
380 #ifdef ASSERT_PDIR_SANITY
383 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
384 * @ioc: IO MMU structure which owns the pdir we are interested in.
385 * @msg: text to print ont the output line.
388 * Print one entry of the IO MMU PDIR in human readable form.
391 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
393 /* start printing from lowest pde in rval */
394 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
395 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
398 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
400 rptr, pide & (BITS_PER_LONG - 1), *rptr);
403 while (rcnt < BITS_PER_LONG) {
404 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
405 (rcnt == (pide & (BITS_PER_LONG - 1)))
411 printk(KERN_DEBUG "%s", msg);
416 * sba_check_pdir - debugging only - consistency checker
417 * @ioc: IO MMU structure which owns the pdir we are interested in.
418 * @msg: text to print ont the output line.
420 * Verify the resource map and pdir state is consistent
423 sba_check_pdir(struct ioc *ioc, char *msg)
425 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
426 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
427 u64 *pptr = ioc->pdir_base; /* pdir ptr */
430 while (rptr < rptr_end) {
432 int rcnt = 32; /* number of bits we might check */
435 /* Get last byte and highest bit from that */
436 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
437 if ((rval ^ pde) & 0x80000000)
440 ** BUMMER! -- res_map != pdir --
441 ** Dump rval and matching pdir entries
443 sba_dump_pdir_entry(ioc, msg, pide);
447 rval <<= 1; /* try the next bit */
451 rptr++; /* look at next word of res_map */
453 /* It'd be nice if we always got here :^) */
459 * sba_dump_sg - debugging only - print Scatter-Gather list
460 * @ioc: IO MMU structure which owns the pdir we are interested in.
461 * @startsg: head of the SG list
462 * @nents: number of entries in SG list
464 * print the SG list so we can verify it's correct by hand.
467 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
469 while (nents-- > 0) {
470 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
472 (unsigned long) sg_dma_address(startsg),
474 sg_virt_addr(startsg), startsg->length);
479 #endif /* ASSERT_PDIR_SANITY */
484 /**************************************************************
486 * I/O Pdir Resource Management
488 * Bits set in the resource map are in use.
489 * Each bit can represent a number of pages.
490 * LSbs represent lower addresses (IOVA's).
492 ***************************************************************/
493 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
495 /* Convert from IOVP to IOVA and vice versa. */
498 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
499 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
500 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
502 /* only support Astro and ancestors. Saves a few cycles in key places */
503 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
504 #define SBA_IOVP(ioc,iova) (iova)
507 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
509 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
510 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
514 * sba_search_bitmap - find free space in IO PDIR resource bitmap
515 * @ioc: IO MMU structure which owns the pdir we are interested in.
516 * @bits_wanted: number of entries we need.
518 * Find consecutive free bits in resource bitmap.
519 * Each bit represents one entry in the IO Pdir.
520 * Cool perf optimization: search for log2(size) bits at a time.
522 static SBA_INLINE unsigned long
523 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
525 unsigned long *res_ptr = ioc->res_hint;
526 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
527 unsigned long pide = ~0UL;
529 if (bits_wanted > (BITS_PER_LONG/2)) {
530 /* Search word at a time - no mask needed */
531 for(; res_ptr < res_end; ++res_ptr) {
533 *res_ptr = RESMAP_MASK(bits_wanted);
534 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
535 pide <<= 3; /* convert to bit address */
539 /* point to the next word on next pass */
541 ioc->res_bitshift = 0;
544 ** Search the resource bit map on well-aligned values.
545 ** "o" is the alignment.
546 ** We need the alignment to invalidate I/O TLB using
547 ** SBA HW features in the unmap path.
549 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
550 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
553 if (bitshiftcnt >= BITS_PER_LONG) {
557 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
559 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
560 while(res_ptr < res_end)
562 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
564 if(((*res_ptr) & mask) == 0) {
565 *res_ptr |= mask; /* mark resources busy! */
566 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
567 pide <<= 3; /* convert to bit address */
574 mask = RESMAP_MASK(bits_wanted);
579 /* look in the same word on the next pass */
580 ioc->res_bitshift = bitshiftcnt + bits_wanted;
584 if (res_end <= res_ptr) {
585 ioc->res_hint = (unsigned long *) ioc->res_map;
586 ioc->res_bitshift = 0;
588 ioc->res_hint = res_ptr;
595 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
596 * @ioc: IO MMU structure which owns the pdir we are interested in.
597 * @size: number of bytes to create a mapping for
599 * Given a size, find consecutive unmarked and then mark those bits in the
603 sba_alloc_range(struct ioc *ioc, size_t size)
605 unsigned int pages_needed = size >> IOVP_SHIFT;
606 #ifdef SBA_COLLECT_STATS
607 unsigned long cr_start = mfctl(16);
611 pide = sba_search_bitmap(ioc, pages_needed);
612 if (pide >= (ioc->res_size << 3)) {
613 pide = sba_search_bitmap(ioc, pages_needed);
614 if (pide >= (ioc->res_size << 3))
615 panic("%s: I/O MMU @ %p is out of mapping resources\n",
616 __FILE__, ioc->ioc_hpa);
619 #ifdef ASSERT_PDIR_SANITY
620 /* verify the first enable bit is clear */
621 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
622 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
626 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
627 __FUNCTION__, size, pages_needed, pide,
628 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
631 #ifdef SBA_COLLECT_STATS
633 unsigned long cr_end = mfctl(16);
634 unsigned long tmp = cr_end - cr_start;
635 /* check for roll over */
636 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
638 ioc->avg_search[ioc->avg_idx++] = cr_start;
639 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
641 ioc->used_pages += pages_needed;
649 * sba_free_range - unmark bits in IO PDIR resource bitmap
650 * @ioc: IO MMU structure which owns the pdir we are interested in.
651 * @iova: IO virtual address which was previously allocated.
652 * @size: number of bytes to create a mapping for
654 * clear bits in the ioc's resource map
656 static SBA_INLINE void
657 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
659 unsigned long iovp = SBA_IOVP(ioc, iova);
660 unsigned int pide = PDIR_INDEX(iovp);
661 unsigned int ridx = pide >> 3; /* convert bit to byte address */
662 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
664 int bits_not_wanted = size >> IOVP_SHIFT;
666 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
667 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
669 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
670 __FUNCTION__, (uint) iova, size,
671 bits_not_wanted, m, pide, res_ptr, *res_ptr);
673 #ifdef SBA_COLLECT_STATS
674 ioc->used_pages -= bits_not_wanted;
681 /**************************************************************
683 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
685 ***************************************************************/
687 #ifdef SBA_HINT_SUPPORT
688 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
691 typedef unsigned long space_t;
692 #define KERNEL_SPACE 0
695 * sba_io_pdir_entry - fill in one IO PDIR entry
696 * @pdir_ptr: pointer to IO PDIR entry
697 * @sid: process Space ID - currently only support KERNEL_SPACE
698 * @vba: Virtual CPU address of buffer to map
699 * @hint: DMA hint set to use for this mapping
701 * SBA Mapping Routine
703 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
704 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
706 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
707 * for Astro/Ike looks like:
711 * +-+---------------------+----------------------------------+----+--------+
712 * |V| U | PPN[43:12] | U | VI |
713 * +-+---------------------+----------------------------------+----+--------+
715 * Pluto is basically identical, supports fewer physical address bits:
718 * +-+------------------------+-------------------------------+----+--------+
719 * |V| U | PPN[39:12] | U | VI |
720 * +-+------------------------+-------------------------------+----+--------+
722 * V == Valid Bit (Most Significant Bit is bit 0)
724 * PPN == Physical Page Number
725 * VI == Virtual Index (aka Coherent Index)
727 * LPA instruction output is put into PPN field.
728 * LCI (Load Coherence Index) instruction provides the "VI" bits.
730 * We pre-swap the bytes since PCX-W is Big Endian and the
731 * IOMMU uses little endian for the pdir.
735 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
738 u64 pa; /* physical address */
739 register unsigned ci; /* coherent index */
741 pa = virt_to_phys(vba);
745 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
746 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
748 pa |= 0x8000000000000000ULL; /* set "valid" bit */
749 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
752 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
753 * (bit #61, big endian), we have to flush and sync every time
754 * IO-PDIR is changed in Ike/Astro.
757 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
762 * sba_mark_invalid - invalidate one or more IO PDIR entries
763 * @ioc: IO MMU structure which owns the pdir we are interested in.
764 * @iova: IO Virtual Address mapped earlier
765 * @byte_cnt: number of bytes this mapping covers.
767 * Marking the IO PDIR entry(ies) as Invalid and invalidate
768 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
769 * is to purge stale entries in the IO TLB when unmapping entries.
771 * The PCOM register supports purging of multiple pages, with a minium
772 * of 1 page and a maximum of 2GB. Hardware requires the address be
773 * aligned to the size of the range being purged. The size of the range
774 * must be a power of 2. The "Cool perf optimization" in the
775 * allocation routine helps keep that true.
777 static SBA_INLINE void
778 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
780 u32 iovp = (u32) SBA_IOVP(ioc,iova);
781 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
783 #ifdef ASSERT_PDIR_SANITY
784 /* Assert first pdir entry is set.
786 ** Even though this is a big-endian machine, the entries
787 ** in the iopdir are little endian. That's why we look at
788 ** the byte at +7 instead of at +0.
790 if (0x80 != (((u8 *) pdir_ptr)[7])) {
791 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
795 if (byte_cnt > IOVP_SIZE)
798 unsigned long entries_per_cacheline = ioc_needs_fdc ?
799 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
800 - (unsigned long) pdir_ptr;
804 /* set "size" field for PCOM */
805 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
808 /* clear I/O Pdir entry "valid" bit first */
809 ((u8 *) pdir_ptr)[7] = 0;
811 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
813 entries_per_cacheline = L1_CACHE_SHIFT - 3;
817 byte_cnt -= IOVP_SIZE;
818 } while (byte_cnt > IOVP_SIZE);
820 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
823 ** clear I/O PDIR entry "valid" bit.
824 ** We have to R/M/W the cacheline regardless how much of the
825 ** pdir entry that we clobber.
826 ** The rest of the entry would be useful for debugging if we
827 ** could dump core on HPMC.
829 ((u8 *) pdir_ptr)[7] = 0;
831 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
833 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
837 * sba_dma_supported - PCI driver can query DMA support
838 * @dev: instance of PCI owned by the driver that's asking
839 * @mask: number of address bits this PCI device can handle
841 * See Documentation/DMA-mapping.txt
843 static int sba_dma_supported( struct device *dev, u64 mask)
848 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
853 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
854 * then fall back to 32-bit if that fails.
855 * We are just "encouraging" 32-bit DMA masks here since we can
856 * never allow IOMMU bypass unless we add special support for ZX1.
864 * check if mask is >= than the current max IO Virt Address
865 * The max IO Virt address will *always* < 30 bits.
867 return((int)(mask >= (ioc->ibase - 1 +
868 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
873 * sba_map_single - map one buffer and return IOVA for DMA
874 * @dev: instance of PCI owned by the driver that's asking.
875 * @addr: driver buffer to map.
876 * @size: number of bytes to map in driver buffer.
877 * @direction: R/W or both.
879 * See Documentation/DMA-mapping.txt
882 sba_map_single(struct device *dev, void *addr, size_t size,
883 enum dma_data_direction direction)
894 /* save offset bits */
895 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
897 /* round up to nearest IOVP_SIZE */
898 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
900 spin_lock_irqsave(&ioc->res_lock, flags);
901 #ifdef ASSERT_PDIR_SANITY
902 sba_check_pdir(ioc,"Check before sba_map_single()");
905 #ifdef SBA_COLLECT_STATS
906 ioc->msingle_calls++;
907 ioc->msingle_pages += size >> IOVP_SHIFT;
909 pide = sba_alloc_range(ioc, size);
910 iovp = (dma_addr_t) pide << IOVP_SHIFT;
912 DBG_RUN("%s() 0x%p -> 0x%lx\n",
913 __FUNCTION__, addr, (long) iovp | offset);
915 pdir_start = &(ioc->pdir_base[pide]);
918 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
920 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
922 (u8) (((u8 *) pdir_start)[7]),
923 (u8) (((u8 *) pdir_start)[6]),
924 (u8) (((u8 *) pdir_start)[5]),
925 (u8) (((u8 *) pdir_start)[4]),
926 (u8) (((u8 *) pdir_start)[3]),
927 (u8) (((u8 *) pdir_start)[2]),
928 (u8) (((u8 *) pdir_start)[1]),
929 (u8) (((u8 *) pdir_start)[0])
937 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
939 asm volatile("sync" : : );
941 #ifdef ASSERT_PDIR_SANITY
942 sba_check_pdir(ioc,"Check after sba_map_single()");
944 spin_unlock_irqrestore(&ioc->res_lock, flags);
946 /* form complete address */
947 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
952 * sba_unmap_single - unmap one IOVA and free resources
953 * @dev: instance of PCI owned by the driver that's asking.
954 * @iova: IOVA of driver buffer previously mapped.
955 * @size: number of bytes mapped in driver buffer.
956 * @direction: R/W or both.
958 * See Documentation/DMA-mapping.txt
961 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
962 enum dma_data_direction direction)
965 #if DELAYED_RESOURCE_CNT > 0
966 struct sba_dma_pair *d;
971 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
974 offset = iova & ~IOVP_MASK;
975 iova ^= offset; /* clear offset bits */
977 size = ROUNDUP(size, IOVP_SIZE);
979 spin_lock_irqsave(&ioc->res_lock, flags);
981 #ifdef SBA_COLLECT_STATS
982 ioc->usingle_calls++;
983 ioc->usingle_pages += size >> IOVP_SHIFT;
986 sba_mark_invalid(ioc, iova, size);
988 #if DELAYED_RESOURCE_CNT > 0
989 /* Delaying when we re-use a IO Pdir entry reduces the number
990 * of MMIO reads needed to flush writes to the PCOM register.
992 d = &(ioc->saved[ioc->saved_cnt]);
995 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
996 int cnt = ioc->saved_cnt;
998 sba_free_range(ioc, d->iova, d->size);
1003 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1005 #else /* DELAYED_RESOURCE_CNT == 0 */
1006 sba_free_range(ioc, iova, size);
1008 /* If fdc's were issued, force fdc's to be visible now */
1010 asm volatile("sync" : : );
1012 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1013 #endif /* DELAYED_RESOURCE_CNT == 0 */
1015 spin_unlock_irqrestore(&ioc->res_lock, flags);
1017 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
1018 ** For Astro based systems this isn't a big deal WRT performance.
1019 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
1020 ** we don't need the syncdma. The issue here is I/O MMU cachelines
1021 ** are *not* coherent in all cases. May be hwrev dependent.
1022 ** Need to investigate more.
1023 asm volatile("syncdma");
1029 * sba_alloc_consistent - allocate/map shared mem for DMA
1030 * @hwdev: instance of PCI owned by the driver that's asking.
1031 * @size: number of bytes mapped in driver buffer.
1032 * @dma_handle: IOVA of new buffer.
1034 * See Documentation/DMA-mapping.txt
1036 static void *sba_alloc_consistent(struct device *hwdev, size_t size,
1037 dma_addr_t *dma_handle, gfp_t gfp)
1042 /* only support PCI */
1047 ret = (void *) __get_free_pages(gfp, get_order(size));
1050 memset(ret, 0, size);
1051 *dma_handle = sba_map_single(hwdev, ret, size, 0);
1059 * sba_free_consistent - free/unmap shared mem for DMA
1060 * @hwdev: instance of PCI owned by the driver that's asking.
1061 * @size: number of bytes mapped in driver buffer.
1062 * @vaddr: virtual address IOVA of "consistent" buffer.
1063 * @dma_handler: IO virtual address of "consistent" buffer.
1065 * See Documentation/DMA-mapping.txt
1068 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
1069 dma_addr_t dma_handle)
1071 sba_unmap_single(hwdev, dma_handle, size, 0);
1072 free_pages((unsigned long) vaddr, get_order(size));
1077 ** Since 0 is a valid pdir_base index value, can't use that
1078 ** to determine if a value is valid or not. Use a flag to indicate
1079 ** the SG list entry contains a valid pdir index.
1081 #define PIDE_FLAG 0x80000000UL
1083 #ifdef SBA_COLLECT_STATS
1084 #define IOMMU_MAP_STATS
1086 #include "iommu-helpers.h"
1088 #ifdef DEBUG_LARGE_SG_ENTRIES
1089 int dump_run_sg = 0;
1094 * sba_map_sg - map Scatter/Gather list
1095 * @dev: instance of PCI owned by the driver that's asking.
1096 * @sglist: array of buffer/length pairs
1097 * @nents: number of entries in list
1098 * @direction: R/W or both.
1100 * See Documentation/DMA-mapping.txt
1103 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
1104 enum dma_data_direction direction)
1107 int coalesced, filled = 0;
1108 unsigned long flags;
1110 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1114 /* Fast path single entry scatterlists. */
1116 sg_dma_address(sglist) = sba_map_single(dev,
1117 (void *)sg_virt_addr(sglist),
1118 sglist->length, direction);
1119 sg_dma_len(sglist) = sglist->length;
1123 spin_lock_irqsave(&ioc->res_lock, flags);
1125 #ifdef ASSERT_PDIR_SANITY
1126 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1128 sba_dump_sg(ioc, sglist, nents);
1129 panic("Check before sba_map_sg()");
1133 #ifdef SBA_COLLECT_STATS
1138 ** First coalesce the chunks and allocate I/O pdir space
1140 ** If this is one DMA stream, we can properly map using the
1141 ** correct virtual address associated with each DMA page.
1142 ** w/o this association, we wouldn't have coherent DMA!
1143 ** Access to the virtual address is what forces a two pass algorithm.
1145 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
1148 ** Program the I/O Pdir
1150 ** map the virtual addresses to the I/O Pdir
1151 ** o dma_address will contain the pdir index
1152 ** o dma_len will contain the number of bytes to map
1153 ** o address contains the virtual address.
1155 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1157 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1159 asm volatile("sync" : : );
1161 #ifdef ASSERT_PDIR_SANITY
1162 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1164 sba_dump_sg(ioc, sglist, nents);
1165 panic("Check after sba_map_sg()\n");
1169 spin_unlock_irqrestore(&ioc->res_lock, flags);
1171 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1178 * sba_unmap_sg - unmap Scatter/Gather list
1179 * @dev: instance of PCI owned by the driver that's asking.
1180 * @sglist: array of buffer/length pairs
1181 * @nents: number of entries in list
1182 * @direction: R/W or both.
1184 * See Documentation/DMA-mapping.txt
1187 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1188 enum dma_data_direction direction)
1191 #ifdef ASSERT_PDIR_SANITY
1192 unsigned long flags;
1195 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1196 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1200 #ifdef SBA_COLLECT_STATS
1204 #ifdef ASSERT_PDIR_SANITY
1205 spin_lock_irqsave(&ioc->res_lock, flags);
1206 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1207 spin_unlock_irqrestore(&ioc->res_lock, flags);
1210 while (sg_dma_len(sglist) && nents--) {
1212 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1213 #ifdef SBA_COLLECT_STATS
1214 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1215 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1220 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1222 #ifdef ASSERT_PDIR_SANITY
1223 spin_lock_irqsave(&ioc->res_lock, flags);
1224 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1225 spin_unlock_irqrestore(&ioc->res_lock, flags);
1230 static struct hppa_dma_ops sba_ops = {
1231 .dma_supported = sba_dma_supported,
1232 .alloc_consistent = sba_alloc_consistent,
1233 .alloc_noncoherent = sba_alloc_consistent,
1234 .free_consistent = sba_free_consistent,
1235 .map_single = sba_map_single,
1236 .unmap_single = sba_unmap_single,
1237 .map_sg = sba_map_sg,
1238 .unmap_sg = sba_unmap_sg,
1239 .dma_sync_single_for_cpu = NULL,
1240 .dma_sync_single_for_device = NULL,
1241 .dma_sync_sg_for_cpu = NULL,
1242 .dma_sync_sg_for_device = NULL,
1246 /**************************************************************************
1248 ** SBA PAT PDC support
1250 ** o call pdc_pat_cell_module()
1251 ** o store ranges in PCI "resource" structures
1253 **************************************************************************/
1256 sba_get_pat_resources(struct sba_device *sba_dev)
1260 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1261 ** PAT PDC to program the SBA/LBA directed range registers...this
1262 ** burden may fall on the LBA code since it directly supports the
1263 ** PCI subsystem. It's not clear yet. - ggg
1265 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1267 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1268 Tells where the dvi bits are located in the address.
1269 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1275 /**************************************************************
1277 * Initialization and claim
1279 ***************************************************************/
1280 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1281 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1283 sba_alloc_pdir(unsigned int pdir_size)
1285 unsigned long pdir_base;
1286 unsigned long pdir_order = get_order(pdir_size);
1288 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1289 if (NULL == (void *) pdir_base) {
1290 panic("%s() could not allocate I/O Page Table\n",
1294 /* If this is not PA8700 (PCX-W2)
1295 ** OR newer than ver 2.2
1296 ** OR in a system that doesn't need VINDEX bits from SBA,
1298 ** then we aren't exposed to the HW bug.
1300 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1301 || (boot_cpu_data.pdc.versions > 0x202)
1302 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1303 return (void *) pdir_base;
1306 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1308 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1309 * Ike/Astro can cause silent data corruption. This is only
1310 * a problem if the I/O PDIR is located in memory such that
1311 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1313 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1314 * right physical address, we can either avoid (IOPDIR <= 1MB)
1315 * or minimize (2MB IO Pdir) the problem if we restrict the
1316 * IO Pdir to a maximum size of 2MB-128K (1902K).
1318 * Because we always allocate 2^N sized IO pdirs, either of the
1319 * "bad" regions will be the last 128K if at all. That's easy
1323 if (pdir_order <= (19-12)) {
1324 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1325 /* allocate a new one on 512k alignment */
1326 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1327 /* release original */
1328 free_pages(pdir_base, pdir_order);
1330 pdir_base = new_pdir;
1332 /* release excess */
1333 while (pdir_order < (19-12)) {
1334 new_pdir += pdir_size;
1335 free_pages(new_pdir, pdir_order);
1343 ** Needs to be aligned on an "odd" 1MB boundary.
1345 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1347 /* release original */
1348 free_pages( pdir_base, pdir_order);
1350 /* release first 1MB */
1351 free_pages(new_pdir, 20-12);
1353 pdir_base = new_pdir + 1024*1024;
1355 if (pdir_order > (20-12)) {
1359 ** Flag tells init_bitmap() to mark bad 128k as used
1360 ** and to reduce the size by 128k.
1362 piranha_bad_128k = 1;
1364 new_pdir += 3*1024*1024;
1365 /* release last 1MB */
1366 free_pages(new_pdir, 20-12);
1368 /* release unusable 128KB */
1369 free_pages(new_pdir - 128*1024 , 17-12);
1371 pdir_size -= 128*1024;
1375 memset((void *) pdir_base, 0, pdir_size);
1376 return (void *) pdir_base;
1379 static struct device *next_device(struct klist_iter *i)
1381 struct klist_node * n = klist_next(i);
1382 return n ? container_of(n, struct device, knode_parent) : NULL;
1385 /* setup Mercury or Elroy IBASE/IMASK registers. */
1387 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1389 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1390 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1392 struct klist_iter i;
1394 klist_iter_init(&sba->dev.klist_children, &i);
1395 while ((dev = next_device(&i))) {
1396 struct parisc_device *lba = to_parisc_device(dev);
1397 int rope_num = (lba->hpa.start >> 13) & 0xf;
1398 if (rope_num >> 3 == ioc_num)
1399 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1401 klist_iter_exit(&i);
1405 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1407 u32 iova_space_mask;
1408 u32 iova_space_size;
1409 int iov_order, tcnfg;
1410 #ifdef SBA_AGP_SUPPORT
1414 ** Firmware programs the base and size of a "safe IOVA space"
1415 ** (one that doesn't overlap memory or LMMIO space) in the
1416 ** IBASE and IMASK registers.
1418 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1419 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1421 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1422 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1423 iova_space_size /= 2;
1427 ** iov_order is always based on a 1GB IOVA space since we want to
1428 ** turn on the other half for AGP GART.
1430 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1431 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1433 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1434 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
1435 iov_order + PAGE_SHIFT);
1437 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1438 get_order(ioc->pdir_size));
1439 if (!ioc->pdir_base)
1440 panic("Couldn't allocate I/O Page Table\n");
1442 memset(ioc->pdir_base, 0, ioc->pdir_size);
1444 DBG_INIT("%s() pdir %p size %x\n",
1445 __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
1447 #ifdef SBA_HINT_SUPPORT
1448 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1449 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1451 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1452 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1455 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1456 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1458 /* build IMASK for IOC and Elroy */
1459 iova_space_mask = 0xffffffff;
1460 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1461 ioc->imask = iova_space_mask;
1463 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1465 sba_dump_tlb(ioc->ioc_hpa);
1467 setup_ibase_imask(sba, ioc, ioc_num);
1469 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1473 ** Setting the upper bits makes checking for bypass addresses
1474 ** a little faster later on.
1476 ioc->imask |= 0xFFFFFFFF00000000UL;
1479 /* Set I/O PDIR Page size to system page size */
1480 switch (PAGE_SHIFT) {
1481 case 12: tcnfg = 0; break; /* 4K */
1482 case 13: tcnfg = 1; break; /* 8K */
1483 case 14: tcnfg = 2; break; /* 16K */
1484 case 16: tcnfg = 3; break; /* 64K */
1486 panic(__FILE__ "Unsupported system page size %d",
1490 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1493 ** Program the IOC's ibase and enable IOVA translation
1494 ** Bit zero == enable bit.
1496 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1499 ** Clear I/O TLB of any possible entries.
1500 ** (Yes. This is a bit paranoid...but so what)
1502 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1504 #ifdef SBA_AGP_SUPPORT
1506 ** If an AGP device is present, only use half of the IOV space
1507 ** for PCI DMA. Unfortunately we can't know ahead of time
1508 ** whether GART support will actually be used, for now we
1509 ** can just key on any AGP device found in the system.
1510 ** We program the next pdir index after we stop w/ a key for
1511 ** the GART code to handshake on.
1514 for (lba = sba->child; lba; lba = lba->sibling) {
1515 if (IS_QUICKSILVER(lba))
1520 DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
1521 ioc->pdir_size /= 2;
1522 ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
1524 DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
1531 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1533 u32 iova_space_size, iova_space_mask;
1534 unsigned int pdir_size, iov_order;
1537 ** Determine IOVA Space size from memory size.
1539 ** Ideally, PCI drivers would register the maximum number
1540 ** of DMA they can have outstanding for each device they
1541 ** own. Next best thing would be to guess how much DMA
1542 ** can be outstanding based on PCI Class/sub-class. Both
1543 ** methods still require some "extra" to support PCI
1544 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1546 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1547 ** for DMA hints - ergo only 30 bits max.
1550 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1552 /* limit IOVA space size to 1MB-1GB */
1553 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1554 iova_space_size = 1 << (20 - PAGE_SHIFT);
1556 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1557 iova_space_size = 1 << (30 - PAGE_SHIFT);
1561 ** iova space must be log2() in size.
1562 ** thus, pdir/res_map will also be log2().
1563 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1565 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1567 /* iova_space_size is now bytes, not pages */
1568 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1570 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1572 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1575 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1576 iova_space_size>>20,
1577 iov_order + PAGE_SHIFT);
1579 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1581 DBG_INIT("%s() pdir %p size %x\n",
1582 __FUNCTION__, ioc->pdir_base, pdir_size);
1584 #ifdef SBA_HINT_SUPPORT
1585 /* FIXME : DMA HINTs not used */
1586 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1587 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1589 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1590 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1593 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1595 /* build IMASK for IOC and Elroy */
1596 iova_space_mask = 0xffffffff;
1597 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1600 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1601 ** ibase=0, imask=0xFE000000, size=0x2000000.
1604 ioc->imask = iova_space_mask; /* save it */
1606 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1609 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1610 __FUNCTION__, ioc->ibase, ioc->imask);
1613 ** FIXME: Hint registers are programmed with default hint
1614 ** values during boot, so hints should be sane even if we
1615 ** can't reprogram them the way drivers want.
1618 setup_ibase_imask(sba, ioc, ioc_num);
1621 ** Program the IOC's ibase and enable IOVA translation
1623 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1624 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1626 /* Set I/O PDIR Page size to 4K */
1627 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1630 ** Clear I/O TLB of any possible entries.
1631 ** (Yes. This is a bit paranoid...but so what)
1633 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1635 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1637 DBG_INIT("%s() DONE\n", __FUNCTION__);
1642 /**************************************************************************
1644 ** SBA initialization code (HW and SW)
1646 ** o identify SBA chip itself
1647 ** o initialize SBA chip modes (HardFail)
1648 ** o initialize SBA chip modes (HardFail)
1649 ** o FIXME: initialize DMA hints for reasonable defaults
1651 **************************************************************************/
1653 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1655 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1658 static void sba_hw_init(struct sba_device *sba_dev)
1664 if (!is_pdc_pat()) {
1665 /* Shutdown the USB controller on Astro-based workstations.
1666 ** Once we reprogram the IOMMU, the next DMA performed by
1667 ** USB will HPMC the box. USB is only enabled if a
1668 ** keyboard is present and found.
1670 ** With serial console, j6k v5.0 firmware says:
1671 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1673 ** FIXME: Using GFX+USB console at power up but direct
1674 ** linux to serial console is still broken.
1675 ** USB could generate DMA so we must reset USB.
1676 ** The proper sequence would be:
1677 ** o block console output
1678 ** o reset USB device
1679 ** o reprogram serial port
1680 ** o unblock console output
1682 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1683 pdc_io_reset_devices();
1690 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1691 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1694 ** Need to deal with DMA from LAN.
1695 ** Maybe use page zero boot device as a handle to talk
1696 ** to PDC about which device to shutdown.
1698 ** Netbooting, j6k v5.0 firmware says:
1699 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1700 ** ARGH! invalid class.
1702 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1703 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1708 if (!IS_PLUTO(sba_dev->dev)) {
1709 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1710 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1711 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1712 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1713 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1714 /* j6700 v1.6 firmware sets 0x294f */
1715 /* A500 firmware sets 0x4d */
1717 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1719 #ifdef DEBUG_SBA_INIT
1720 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1721 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1725 if (IS_ASTRO(sba_dev->dev)) {
1727 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1730 sba_dev->chip_resv.name = "Astro Intr Ack";
1731 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1732 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1733 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1736 } else if (IS_PLUTO(sba_dev->dev)) {
1739 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1742 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1743 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1744 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1745 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1748 sba_dev->iommu_resv.name = "IOVA Space";
1749 sba_dev->iommu_resv.start = 0x40000000UL;
1750 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1751 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1755 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1756 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1759 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1761 /* XXX: What about Reo Grande? */
1763 sba_dev->num_ioc = num_ioc;
1764 for (i = 0; i < num_ioc; i++) {
1765 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1768 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1771 * Clear ROPE(N)_CONFIG AO bit.
1772 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1773 * Overrides bit 1 in DMA Hint Sets.
1774 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1776 if (IS_PLUTO(sba_dev->dev)) {
1777 void __iomem *rope_cfg;
1778 unsigned long cfg_val;
1780 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1781 cfg_val = READ_REG(rope_cfg);
1782 cfg_val &= ~IOC_ROPE_AO;
1783 WRITE_REG(cfg_val, rope_cfg);
1787 ** Make sure the box crashes on rope errors.
1789 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1792 /* flush out the last writes */
1793 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1795 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1797 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1798 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1800 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1801 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1802 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1805 if (IS_PLUTO(sba_dev->dev)) {
1806 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1808 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1814 sba_common_init(struct sba_device *sba_dev)
1818 /* add this one to the head of the list (order doesn't matter)
1819 ** This will be useful for debugging - especially if we get coredumps
1821 sba_dev->next = sba_list;
1824 for(i=0; i< sba_dev->num_ioc; i++) {
1826 #ifdef DEBUG_DMB_TRAP
1827 extern void iterate_pages(unsigned long , unsigned long ,
1828 void (*)(pte_t * , unsigned long),
1830 void set_data_memory_break(pte_t * , unsigned long);
1832 /* resource map size dictated by pdir_size */
1833 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1835 /* Second part of PIRANHA BUG */
1836 if (piranha_bad_128k) {
1837 res_size -= (128*1024)/sizeof(u64);
1840 res_size >>= 3; /* convert bit count to byte count */
1841 DBG_INIT("%s() res_size 0x%x\n",
1842 __FUNCTION__, res_size);
1844 sba_dev->ioc[i].res_size = res_size;
1845 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1847 #ifdef DEBUG_DMB_TRAP
1848 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1849 set_data_memory_break, 0);
1852 if (NULL == sba_dev->ioc[i].res_map)
1854 panic("%s:%s() could not allocate resource map\n",
1855 __FILE__, __FUNCTION__ );
1858 memset(sba_dev->ioc[i].res_map, 0, res_size);
1859 /* next available IOVP - circular search */
1860 sba_dev->ioc[i].res_hint = (unsigned long *)
1861 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1863 #ifdef ASSERT_PDIR_SANITY
1864 /* Mark first bit busy - ie no IOVA 0 */
1865 sba_dev->ioc[i].res_map[0] = 0x80;
1866 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1869 /* Third (and last) part of PIRANHA BUG */
1870 if (piranha_bad_128k) {
1871 /* region from +1408K to +1536 is un-usable. */
1873 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1874 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1875 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1876 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1878 /* mark that part of the io pdir busy */
1879 while (p_start < p_end)
1884 #ifdef DEBUG_DMB_TRAP
1885 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1886 set_data_memory_break, 0);
1887 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1888 set_data_memory_break, 0);
1891 DBG_INIT("%s() %d res_map %x %p\n",
1892 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1895 spin_lock_init(&sba_dev->sba_lock);
1896 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1898 #ifdef DEBUG_SBA_INIT
1900 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1901 * (bit #61, big endian), we have to flush and sync every time
1902 * IO-PDIR is changed in Ike/Astro.
1904 if (ioc_needs_fdc) {
1905 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1907 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1912 #ifdef CONFIG_PROC_FS
1913 static int sba_proc_info(struct seq_file *m, void *p)
1915 struct sba_device *sba_dev = sba_list;
1916 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1917 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1918 #ifdef SBA_COLLECT_STATS
1919 unsigned long avg = 0, min, max;
1923 len += seq_printf(m, "%s rev %d.%d\n",
1925 (sba_dev->hw_rev & 0x7) + 1,
1926 (sba_dev->hw_rev & 0x18) >> 3
1928 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1929 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1932 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1933 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1935 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1936 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1937 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1938 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1942 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
1943 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1944 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1945 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1948 #ifdef SBA_COLLECT_STATS
1949 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1950 total_pages - ioc->used_pages, ioc->used_pages,
1951 (int) (ioc->used_pages * 100 / total_pages));
1953 min = max = ioc->avg_search[0];
1954 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1955 avg += ioc->avg_search[i];
1956 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1957 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1959 avg /= SBA_SEARCH_SAMPLE;
1960 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1963 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1964 ioc->msingle_calls, ioc->msingle_pages,
1965 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1967 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1968 min = ioc->usingle_calls;
1969 max = ioc->usingle_pages - ioc->usg_pages;
1970 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1971 min, max, (int) ((max * 1000)/min));
1973 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1974 ioc->msg_calls, ioc->msg_pages,
1975 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1977 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1978 ioc->usg_calls, ioc->usg_pages,
1979 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1986 sba_proc_open(struct inode *i, struct file *f)
1988 return single_open(f, &sba_proc_info, NULL);
1991 static struct file_operations sba_proc_fops = {
1992 .owner = THIS_MODULE,
1993 .open = sba_proc_open,
1995 .llseek = seq_lseek,
1996 .release = single_release,
2000 sba_proc_bitmap_info(struct seq_file *m, void *p)
2002 struct sba_device *sba_dev = sba_list;
2003 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
2004 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
2007 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
2009 len += seq_printf(m, "\n ");
2010 len += seq_printf(m, " %08x", *res_ptr);
2012 len += seq_printf(m, "\n");
2018 sba_proc_bitmap_open(struct inode *i, struct file *f)
2020 return single_open(f, &sba_proc_bitmap_info, NULL);
2023 static struct file_operations sba_proc_bitmap_fops = {
2024 .owner = THIS_MODULE,
2025 .open = sba_proc_bitmap_open,
2027 .llseek = seq_lseek,
2028 .release = single_release,
2030 #endif /* CONFIG_PROC_FS */
2032 static struct parisc_device_id sba_tbl[] = {
2033 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
2034 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
2035 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
2036 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
2037 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
2041 int sba_driver_callback(struct parisc_device *);
2043 static struct parisc_driver sba_driver = {
2044 .name = MODULE_NAME,
2045 .id_table = sba_tbl,
2046 .probe = sba_driver_callback,
2050 ** Determine if sba should claim this chip (return 0) or not (return 1).
2051 ** If so, initialize the chip and tell other partners in crime they
2055 sba_driver_callback(struct parisc_device *dev)
2057 struct sba_device *sba_dev;
2061 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
2062 struct proc_dir_entry *info_entry, *bitmap_entry, *root;
2064 sba_dump_ranges(sba_addr);
2066 /* Read HW Rev First */
2067 func_class = READ_REG(sba_addr + SBA_FCLASS);
2069 if (IS_ASTRO(dev)) {
2070 unsigned long fclass;
2071 static char astro_rev[]="Astro ?.?";
2073 /* Astro is broken...Read HW Rev First */
2074 fclass = READ_REG(sba_addr);
2076 astro_rev[6] = '1' + (char) (fclass & 0x7);
2077 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
2078 version = astro_rev;
2080 } else if (IS_IKE(dev)) {
2081 static char ike_rev[] = "Ike rev ?";
2082 ike_rev[8] = '0' + (char) (func_class & 0xff);
2084 } else if (IS_PLUTO(dev)) {
2085 static char pluto_rev[]="Pluto ?.?";
2086 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
2087 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
2088 version = pluto_rev;
2090 static char reo_rev[] = "REO rev ?";
2091 reo_rev[8] = '0' + (char) (func_class & 0xff);
2095 if (!global_ioc_cnt) {
2096 global_ioc_cnt = count_parisc_driver(&sba_driver);
2098 /* Astro and Pluto have one IOC per SBA */
2099 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
2100 global_ioc_cnt *= 2;
2103 printk(KERN_INFO "%s found %s at 0x%lx\n",
2104 MODULE_NAME, version, dev->hpa.start);
2106 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
2108 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
2112 parisc_set_drvdata(dev, sba_dev);
2114 for(i=0; i<MAX_IOC; i++)
2115 spin_lock_init(&(sba_dev->ioc[i].res_lock));
2118 sba_dev->hw_rev = func_class;
2119 sba_dev->name = dev->name;
2120 sba_dev->sba_hpa = sba_addr;
2122 sba_get_pat_resources(sba_dev);
2123 sba_hw_init(sba_dev);
2124 sba_common_init(sba_dev);
2126 hppa_dma_ops = &sba_ops;
2128 #ifdef CONFIG_PROC_FS
2129 switch (dev->id.hversion) {
2130 case PLUTO_MCKINLEY_PORT:
2131 root = proc_mckinley_root;
2133 case ASTRO_RUNWAY_PORT:
2134 case IKE_MERCED_PORT:
2136 root = proc_runway_root;
2140 info_entry = create_proc_entry("sba_iommu", 0, root);
2141 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root);
2144 info_entry->proc_fops = &sba_proc_fops;
2147 bitmap_entry->proc_fops = &sba_proc_bitmap_fops;
2150 parisc_vmerge_boundary = IOVP_SIZE;
2151 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
2157 ** One time initialization to let the world know the SBA was found.
2158 ** This is the only routine which is NOT static.
2159 ** Must be called exactly once before pci_init().
2161 void __init sba_init(void)
2163 register_parisc_driver(&sba_driver);
2168 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2169 * @dev: The parisc device.
2171 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2172 * This is cached and used later for PCI DMA Mapping.
2174 void * sba_get_iommu(struct parisc_device *pci_hba)
2176 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2177 struct sba_device *sba = sba_dev->dev.driver_data;
2178 char t = sba_dev->id.hw_type;
2179 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2181 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2183 return &(sba->ioc[iocnum]);
2188 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2189 * @pa_dev: The parisc device.
2190 * @r: resource PCI host controller wants start/end fields assigned.
2192 * For the given parisc PCI controller, determine if any direct ranges
2193 * are routed down the corresponding rope.
2195 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2197 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2198 struct sba_device *sba = sba_dev->dev.driver_data;
2199 char t = sba_dev->id.hw_type;
2201 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2203 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2205 r->start = r->end = 0;
2207 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2208 for (i=0; i<4; i++) {
2210 void __iomem *reg = sba->sba_hpa + i*0x18;
2212 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2213 if ((base & 1) == 0)
2214 continue; /* not enabled */
2216 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2218 if ((size & (ROPES_PER_IOC-1)) != rope)
2219 continue; /* directed down different rope */
2221 r->start = (base & ~1UL) | PCI_F_EXTEND;
2222 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2223 r->end = r->start + size;
2229 * sba_distributed_lmmio - return portion of distributed LMMIO range
2230 * @pa_dev: The parisc device.
2231 * @r: resource PCI host controller wants start/end fields assigned.
2233 * For the given parisc PCI controller, return portion of distributed LMMIO
2234 * range. The distributed LMMIO is always present and it's just a question
2235 * of the base address and size of the range.
2237 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2239 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2240 struct sba_device *sba = sba_dev->dev.driver_data;
2241 char t = sba_dev->id.hw_type;
2243 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2245 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2247 r->start = r->end = 0;
2249 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2250 if ((base & 1) == 0) {
2251 BUG(); /* Gah! Distr Range wasn't enabled! */
2255 r->start = (base & ~1UL) | PCI_F_EXTEND;
2257 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2258 r->start += rope * (size + 1); /* adjust base for this rope */
2259 r->end = r->start + size;