git.oblomov.eu Git - linux-2.6/blob - arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
  12  *  Gordon McNutt and RidgeRun, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/bitops.h>
  30
  31 #include <mach/clock.h>
  32 #include <mach/sram.h>
  33 #include <asm/div64.h>
  34 #include <asm/clkdev.h>
  35
  36 #include <mach/sdrc.h>
  37 #include "clock.h"
  38 #include "prm.h"
  39 #include "prm-regbits-24xx.h"
  40 #include "cm.h"
  41 #include "cm-regbits-24xx.h"
  42
  43 static const struct clkops clkops_oscck;
  44 static const struct clkops clkops_fixed;
  45
  46 #include "clock24xx.h"
  47
  48 struct omap_clk {
  49         u32             cpu;
  50         struct clk_lookup lk;
  51 };
  52
  53 #define CLK(dev, con, ck, cp)           \
  54         {                               \
  55                  .cpu = cp,             \
  56                 .lk = {                 \
  57                         .dev_id = dev,  \
  58                         .con_id = con,  \
  59                         .clk = ck,      \
  60                 },                      \
  61         }
  62
  63 #define CK_243X (1 << 0)
  64 #define CK_242X (1 << 1)
  65
  66 static struct omap_clk omap24xx_clks[] = {
  67         /* external root sources */
  68         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
  69         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
  70         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
  71         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
  72         /* internal analog sources */
  73         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
  74         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
  75         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
  76         /* internal prcm root sources */
  77         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
  78         CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
  79         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
  80         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
  81         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
  82         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
  83         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
  84         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
  85         CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
  86         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
  87         CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
  88         /* mpu domain clocks */
  89         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
  90         /* dsp domain clocks */
  91         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
  92         CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
  93         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
  94         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
  95         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
  96         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
  97         /* GFX domain clocks */
  98         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
  99         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
 100         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
 101         /* Modem domain clocks */
 102         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
 103         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
 104         /* DSS domain clocks */
 105         CLK(NULL,       "dss_ick",      &dss_ick,       CK_243X | CK_242X),
 106         CLK(NULL,       "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
 107         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
 108         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X | CK_242X),
 109         /* L3 domain clocks */
 110         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
 111         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
 112         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
 113         /* L4 domain clocks */
 114         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
 115         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
 116         /* virtual meta-group clock */
 117         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
 118         /* general l4 interface ck, multi-parent functional clk */
 119         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
 120         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
 121         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
 122         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
 123         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
 124         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
 125         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
 126         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
 127         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
 128         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
 129         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
 130         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
 131         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
 132         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
 133         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
 134         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
 135         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
 136         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
 137         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
 138         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
 139         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
 140         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
 141         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
 142         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
 143         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
 144         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
 145         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
 146         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
 147         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
 148         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
 149         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
 150         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
 151         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
 152         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
 153         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
 154         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
 155         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
 156         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
 157         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
 158         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
 159         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
 160         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
 161         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
 162         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
 163         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
 164         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
 165         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
 166         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
 167         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
 168         CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
 169         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
 170         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
 171         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
 172         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
 173         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
 174         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
 175         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
 176         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
 177         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
 178         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
 179         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
 180         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
 181         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
 182         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
 183         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
 184         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
 185         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
 186         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
 187         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
 188         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
 189         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
 190         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
 191         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
 192         CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
 193         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
 194         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
 195         CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
 196         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
 197         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
 198         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
 199         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
 200         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
 201         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
 202         CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
 203         CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
 204         CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
 205         CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
 206         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
 207         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
 208         CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
 209         CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
 210         CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
 211         CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
 212         CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
 213         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
 214         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
 215         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
 216         CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
 217         CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
 218 };
 219
 220 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
 221 #define EN_APLL_STOPPED                 0
 222 #define EN_APLL_LOCKED                  3
 223
 224 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
 225 #define APLLS_CLKIN_19_2MHZ             0
 226 #define APLLS_CLKIN_13MHZ               2
 227 #define APLLS_CLKIN_12MHZ               3
 228
 229 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
 230
 231 static struct prcm_config *curr_prcm_set;
 232 static struct clk *vclk;
 233 static struct clk *sclk;
 234
 235 /*-------------------------------------------------------------------------
 236  * Omap24xx specific clock functions
 237  *-------------------------------------------------------------------------*/
 238
 239 /**
 240  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
 241  * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
 242  *
 243  * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
 244  * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
 245  * (the latter is unusual).  This currently should be called with
 246  * struct clk *dpll_ck, which is a composite clock of dpll_ck and
 247  * core_ck.
 248  */
 249 static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
 250 {
 251         long long core_clk;
 252         u32 v;
 253
 254         core_clk = omap2_get_dpll_rate(clk);
 255
 256         v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 257         v &= OMAP24XX_CORE_CLK_SRC_MASK;
 258
 259         if (v == CORE_CLK_SRC_32K)
 260                 core_clk = 32768;
 261         else
 262                 core_clk *= v;
 263
 264         return core_clk;
 265 }
 266
 267 static int omap2_enable_osc_ck(struct clk *clk)
 268 {
 269         u32 pcc;
 270
 271         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 272
 273         __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
 274                       OMAP24XX_PRCM_CLKSRC_CTRL);
 275
 276         return 0;
 277 }
 278
 279 static void omap2_disable_osc_ck(struct clk *clk)
 280 {
 281         u32 pcc;
 282
 283         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 284
 285         __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
 286                       OMAP24XX_PRCM_CLKSRC_CTRL);
 287 }
 288
 289 static const struct clkops clkops_oscck = {
 290         .enable         = &omap2_enable_osc_ck,
 291         .disable        = &omap2_disable_osc_ck,
 292 };
 293
 294 #ifdef OLD_CK
 295 /* Recalculate SYST_CLK */
 296 static void omap2_sys_clk_recalc(struct clk * clk)
 297 {
 298         u32 div = PRCM_CLKSRC_CTRL;
 299         div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
 300         div >>= clk->rate_offset;
 301         clk->rate = (clk->parent->rate / div);
 302         propagate_rate(clk);
 303 }
 304 #endif  /* OLD_CK */
 305
 306 /* Enable an APLL if off */
 307 static int omap2_clk_fixed_enable(struct clk *clk)
 308 {
 309         u32 cval, apll_mask;
 310
 311         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 312
 313         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 314
 315         if ((cval & apll_mask) == apll_mask)
 316                 return 0;   /* apll already enabled */
 317
 318         cval &= ~apll_mask;
 319         cval |= apll_mask;
 320         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 321
 322         if (clk == &apll96_ck)
 323                 cval = OMAP24XX_ST_96M_APLL;
 324         else if (clk == &apll54_ck)
 325                 cval = OMAP24XX_ST_54M_APLL;
 326
 327         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
 328                             clk->name);
 329
 330         /*
 331          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 332          * fails?
 333          */
 334         return 0;
 335 }
 336
 337 /* Stop APLL */
 338 static void omap2_clk_fixed_disable(struct clk *clk)
 339 {
 340         u32 cval;
 341
 342         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 343         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 344         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 345 }
 346
 347 static const struct clkops clkops_fixed = {
 348         .enable         = &omap2_clk_fixed_enable,
 349         .disable        = &omap2_clk_fixed_disable,
 350 };
 351
 352 /*
 353  * Uses the current prcm set to tell if a rate is valid.
 354  * You can go slower, but not faster within a given rate set.
 355  */
 356 static long omap2_dpllcore_round_rate(unsigned long target_rate)
 357 {
 358         u32 high, low, core_clk_src;
 359
 360         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 361         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 362
 363         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 364                 high = curr_prcm_set->dpll_speed * 2;
 365                 low = curr_prcm_set->dpll_speed;
 366         } else {                                /* DPLL clockout x 2 */
 367                 high = curr_prcm_set->dpll_speed;
 368                 low = curr_prcm_set->dpll_speed / 2;
 369         }
 370
 371 #ifdef DOWN_VARIABLE_DPLL
 372         if (target_rate > high)
 373                 return high;
 374         else
 375                 return target_rate;
 376 #else
 377         if (target_rate > low)
 378                 return high;
 379         else
 380                 return low;
 381 #endif
 382
 383 }
 384
 385 static unsigned long omap2_dpllcore_recalc(struct clk *clk)
 386 {
 387         return omap2xxx_clk_get_core_rate(clk);
 388 }
 389
 390 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 391 {
 392         u32 cur_rate, low, mult, div, valid_rate, done_rate;
 393         u32 bypass = 0;
 394         struct prcm_config tmpset;
 395         const struct dpll_data *dd;
 396
 397         cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
 398         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 399         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 400
 401         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 402                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
 403         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 404                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 405         } else if (rate != cur_rate) {
 406                 valid_rate = omap2_dpllcore_round_rate(rate);
 407                 if (valid_rate != rate)
 408                         return -EINVAL;
 409
 410                 if (mult == 1)
 411                         low = curr_prcm_set->dpll_speed;
 412                 else
 413                         low = curr_prcm_set->dpll_speed / 2;
 414
 415                 dd = clk->dpll_data;
 416                 if (!dd)
 417                         return -EINVAL;
 418
 419                 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
 420                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 421                                            dd->div1_mask);
 422                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 423                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 424                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 425                 if (rate > low) {
 426                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 427                         mult = ((rate / 2) / 1000000);
 428                         done_rate = CORE_CLK_SRC_DPLL_X2;
 429                 } else {
 430                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 431                         mult = (rate / 1000000);
 432                         done_rate = CORE_CLK_SRC_DPLL;
 433                 }
 434                 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
 435                 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
 436
 437                 /* Worst case */
 438                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 439
 440                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 441                         bypass = 1;
 442
 443                 /* For omap2xxx_sdrc_init_params() */
 444                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 445
 446                 /* Force dll lock mode */
 447                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 448                                bypass);
 449
 450                 /* Errata: ret dll entry state */
 451                 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
 452                 omap2xxx_sdrc_reprogram(done_rate, 0);
 453         }
 454
 455         return 0;
 456 }
 457
 458 /**
 459  * omap2_table_mpu_recalc - just return the MPU speed
 460  * @clk: virt_prcm_set struct clk
 461  *
 462  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 463  */
 464 static unsigned long omap2_table_mpu_recalc(struct clk *clk)
 465 {
 466         return curr_prcm_set->mpu_speed;
 467 }
 468
 469 /*
 470  * Look for a rate equal or less than the target rate given a configuration set.
 471  *
 472  * What's not entirely clear is "which" field represents the key field.
 473  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 474  * just uses the ARM rates.
 475  */
 476 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 477 {
 478         struct prcm_config *ptr;
 479         long highest_rate;
 480
 481         if (clk != &virt_prcm_set)
 482                 return -EINVAL;
 483
 484         highest_rate = -EINVAL;
 485
 486         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 487                 if (!(ptr->flags & cpu_mask))
 488                         continue;
 489                 if (ptr->xtal_speed != sys_ck.rate)
 490                         continue;
 491
 492                 highest_rate = ptr->mpu_speed;
 493
 494                 /* Can check only after xtal frequency check */
 495                 if (ptr->mpu_speed <= rate)
 496                         break;
 497         }
 498         return highest_rate;
 499 }
 500
 501 /* Sets basic clocks based on the specified rate */
 502 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 503 {
 504         u32 cur_rate, done_rate, bypass = 0, tmp;
 505         struct prcm_config *prcm;
 506         unsigned long found_speed = 0;
 507         unsigned long flags;
 508
 509         if (clk != &virt_prcm_set)
 510                 return -EINVAL;
 511
 512         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 513                 if (!(prcm->flags & cpu_mask))
 514                         continue;
 515
 516                 if (prcm->xtal_speed != sys_ck.rate)
 517                         continue;
 518
 519                 if (prcm->mpu_speed <= rate) {
 520                         found_speed = prcm->mpu_speed;
 521                         break;
 522                 }
 523         }
 524
 525         if (!found_speed) {
 526                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 527                        rate / 1000000);
 528                 return -EINVAL;
 529         }
 530
 531         curr_prcm_set = prcm;
 532         cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
 533
 534         if (prcm->dpll_speed == cur_rate / 2) {
 535                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
 536         } else if (prcm->dpll_speed == cur_rate * 2) {
 537                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 538         } else if (prcm->dpll_speed != cur_rate) {
 539                 local_irq_save(flags);
 540
 541                 if (prcm->dpll_speed == prcm->xtal_speed)
 542                         bypass = 1;
 543
 544                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 545                     CORE_CLK_SRC_DPLL_X2)
 546                         done_rate = CORE_CLK_SRC_DPLL_X2;
 547                 else
 548                         done_rate = CORE_CLK_SRC_DPLL;
 549
 550                 /* MPU divider */
 551                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 552
 553                 /* dsp + iva1 div(2420), iva2.1(2430) */
 554                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 555                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 556
 557                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 558
 559                 /* Major subsystem dividers */
 560                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 561                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
 562                                  CM_CLKSEL1);
 563
 564                 if (cpu_is_omap2430())
 565                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 566                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 567
 568                 /* x2 to enter omap2xxx_sdrc_init_params() */
 569                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 570
 571                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 572                                bypass);
 573
 574                 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
 575                 omap2xxx_sdrc_reprogram(done_rate, 0);
 576
 577                 local_irq_restore(flags);
 578         }
 579
 580         return 0;
 581 }
 582
 583 #ifdef CONFIG_CPU_FREQ
 584 /*
 585  * Walk PRCM rate table and fillout cpufreq freq_table
 586  */
 587 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
 588
 589 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 590 {
 591         struct prcm_config *prcm;
 592         int i = 0;
 593
 594         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 595                 if (!(prcm->flags & cpu_mask))
 596                         continue;
 597                 if (prcm->xtal_speed != sys_ck.rate)
 598                         continue;
 599
 600                 /* don't put bypass rates in table */
 601                 if (prcm->dpll_speed == prcm->xtal_speed)
 602                         continue;
 603
 604                 freq_table[i].index = i;
 605                 freq_table[i].frequency = prcm->mpu_speed / 1000;
 606                 i++;
 607         }
 608
 609         if (i == 0) {
 610                 printk(KERN_WARNING "%s: failed to initialize frequency "
 611                        "table\n", __func__);
 612                 return;
 613         }
 614
 615         freq_table[i].index = i;
 616         freq_table[i].frequency = CPUFREQ_TABLE_END;
 617
 618         *table = &freq_table[0];
 619 }
 620 #endif
 621
 622 static struct clk_functions omap2_clk_functions = {
 623         .clk_enable             = omap2_clk_enable,
 624         .clk_disable            = omap2_clk_disable,
 625         .clk_round_rate         = omap2_clk_round_rate,
 626         .clk_set_rate           = omap2_clk_set_rate,
 627         .clk_set_parent         = omap2_clk_set_parent,
 628         .clk_disable_unused     = omap2_clk_disable_unused,
 629 #ifdef  CONFIG_CPU_FREQ
 630         .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
 631 #endif
 632 };
 633
 634 static u32 omap2_get_apll_clkin(void)
 635 {
 636         u32 aplls, srate = 0;
 637
 638         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 639         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 640         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 641
 642         if (aplls == APLLS_CLKIN_19_2MHZ)
 643                 srate = 19200000;
 644         else if (aplls == APLLS_CLKIN_13MHZ)
 645                 srate = 13000000;
 646         else if (aplls == APLLS_CLKIN_12MHZ)
 647                 srate = 12000000;
 648
 649         return srate;
 650 }
 651
 652 static u32 omap2_get_sysclkdiv(void)
 653 {
 654         u32 div;
 655
 656         div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 657         div &= OMAP_SYSCLKDIV_MASK;
 658         div >>= OMAP_SYSCLKDIV_SHIFT;
 659
 660         return div;
 661 }
 662
 663 static unsigned long omap2_osc_clk_recalc(struct clk *clk)
 664 {
 665         return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 666 }
 667
 668 static unsigned long omap2_sys_clk_recalc(struct clk *clk)
 669 {
 670         return clk->parent->rate / omap2_get_sysclkdiv();
 671 }
 672
 673 /*
 674  * Set clocks for bypass mode for reboot to work.
 675  */
 676 void omap2_clk_prepare_for_reboot(void)
 677 {
 678         u32 rate;
 679
 680         if (vclk == NULL || sclk == NULL)
 681                 return;
 682
 683         rate = clk_get_rate(sclk);
 684         clk_set_rate(vclk, rate);
 685 }
 686
 687 /*
 688  * Switch the MPU rate if specified on cmdline.
 689  * We cannot do this early until cmdline is parsed.
 690  */
 691 static int __init omap2_clk_arch_init(void)
 692 {
 693         if (!mpurate)
 694                 return -EINVAL;
 695
 696         if (clk_set_rate(&virt_prcm_set, mpurate))
 697                 printk(KERN_ERR "Could not find matching MPU rate\n");
 698
 699         recalculate_root_clocks();
 700
 701         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 702                "%ld.%01ld/%ld/%ld MHz\n",
 703                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 704                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 705
 706         return 0;
 707 }
 708 arch_initcall(omap2_clk_arch_init);
 709
 710 int __init omap2_clk_init(void)
 711 {
 712         struct prcm_config *prcm;
 713         struct omap_clk *c;
 714         u32 clkrate, cpu_mask;
 715
 716         if (cpu_is_omap242x())
 717                 cpu_mask = RATE_IN_242X;
 718         else if (cpu_is_omap2430())
 719                 cpu_mask = RATE_IN_243X;
 720
 721         clk_init(&omap2_clk_functions);
 722
 723         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
 724         propagate_rate(&osc_ck);
 725         sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
 726         propagate_rate(&sys_ck);
 727
 728         for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
 729                 clk_init_one(c->lk.clk);
 730
 731         cpu_mask = 0;
 732         if (cpu_is_omap2420())
 733                 cpu_mask |= CK_242X;
 734         if (cpu_is_omap2430())
 735                 cpu_mask |= CK_243X;
 736
 737         for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
 738                 if (c->cpu & cpu_mask) {
 739                         clkdev_add(&c->lk);
 740                         clk_register(c->lk.clk);
 741                 }
 742
 743         /* Check the MPU rate set by bootloader */
 744         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
 745         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 746                 if (!(prcm->flags & cpu_mask))
 747                         continue;
 748                 if (prcm->xtal_speed != sys_ck.rate)
 749                         continue;
 750                 if (prcm->dpll_speed <= clkrate)
 751                          break;
 752         }
 753         curr_prcm_set = prcm;
 754
 755         recalculate_root_clocks();
 756
 757         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 758                "%ld.%01ld/%ld/%ld MHz\n",
 759                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 760                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 761
 762         /*
 763          * Only enable those clocks we will need, let the drivers
 764          * enable other clocks as necessary
 765          */
 766         clk_enable_init_clocks();
 767
 768         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 769         vclk = clk_get(NULL, "virt_prcm_set");
 770         sclk = clk_get(NULL, "sys_ck");
 771
 772         return 0;
 773 }