git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/cpu/cpufreq/speedstep-lib.c

   1 /*
   2  * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Library for common functions for Intel SpeedStep v.1 and v.2 support
   7  *
   8  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/slab.h>
  17
  18 #include <asm/msr.h>
  19 #include <asm/tsc.h>
  20 #include "speedstep-lib.h"
  21
  22 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
  23                 "speedstep-lib", msg)
  24
  25 #define PFX "speedstep-lib: "
  26
  27 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  28 static int relaxed_check;
  29 #else
  30 #define relaxed_check 0
  31 #endif
  32
  33 /*********************************************************************
  34  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  35  *********************************************************************/
  36
  37 static unsigned int pentium3_get_frequency(unsigned int processor)
  38 {
  39         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  40         struct {
  41                 unsigned int ratio;     /* Frequency Multiplier (x10) */
  42                 u8 bitmap;              /* power on configuration bits
  43                                         [27, 25:22] (in MSR 0x2a) */
  44         } msr_decode_mult[] = {
  45                 { 30, 0x01 },
  46                 { 35, 0x05 },
  47                 { 40, 0x02 },
  48                 { 45, 0x06 },
  49                 { 50, 0x00 },
  50                 { 55, 0x04 },
  51                 { 60, 0x0b },
  52                 { 65, 0x0f },
  53                 { 70, 0x09 },
  54                 { 75, 0x0d },
  55                 { 80, 0x0a },
  56                 { 85, 0x26 },
  57                 { 90, 0x20 },
  58                 { 100, 0x2b },
  59                 { 0, 0xff }     /* error or unknown value */
  60         };
  61
  62         /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  63         struct {
  64                 unsigned int value;     /* Front Side Bus speed in MHz */
  65                 u8 bitmap;              /* power on configuration bits [18: 19]
  66                                         (in MSR 0x2a) */
  67         } msr_decode_fsb[] = {
  68                 {  66, 0x0 },
  69                 { 100, 0x2 },
  70                 { 133, 0x1 },
  71                 {   0, 0xff}
  72         };
  73
  74         u32 msr_lo, msr_tmp;
  75         int i = 0, j = 0;
  76
  77         /* read MSR 0x2a - we only need the low 32 bits */
  78         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  79         dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  80         msr_tmp = msr_lo;
  81
  82         /* decode the FSB */
  83         msr_tmp &= 0x00c0000;
  84         msr_tmp >>= 18;
  85         while (msr_tmp != msr_decode_fsb[i].bitmap) {
  86                 if (msr_decode_fsb[i].bitmap == 0xff)
  87                         return 0;
  88                 i++;
  89         }
  90
  91         /* decode the multiplier */
  92         if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
  93                 dprintk("workaround for early PIIIs\n");
  94                 msr_lo &= 0x03c00000;
  95         } else
  96                 msr_lo &= 0x0bc00000;
  97         msr_lo >>= 22;
  98         while (msr_lo != msr_decode_mult[j].bitmap) {
  99                 if (msr_decode_mult[j].bitmap == 0xff)
 100                         return 0;
 101                 j++;
 102         }
 103
 104         dprintk("speed is %u\n",
 105                 (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
 106
 107         return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
 108 }
 109
 110
 111 static unsigned int pentiumM_get_frequency(void)
 112 {
 113         u32 msr_lo, msr_tmp;
 114
 115         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 116         dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 117
 118         /* see table B-2 of 24547212.pdf */
 119         if (msr_lo & 0x00040000) {
 120                 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
 121                                 msr_lo, msr_tmp);
 122                 return 0;
 123         }
 124
 125         msr_tmp = (msr_lo >> 22) & 0x1f;
 126         dprintk("bits 22-26 are 0x%x, speed is %u\n",
 127                         msr_tmp, (msr_tmp * 100 * 1000));
 128
 129         return msr_tmp * 100 * 1000;
 130 }
 131
 132 static unsigned int pentium_core_get_frequency(void)
 133 {
 134         u32 fsb = 0;
 135         u32 msr_lo, msr_tmp;
 136         int ret;
 137
 138         rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
 139         /* see table B-2 of 25366920.pdf */
 140         switch (msr_lo & 0x07) {
 141         case 5:
 142                 fsb = 100000;
 143                 break;
 144         case 1:
 145                 fsb = 133333;
 146                 break;
 147         case 3:
 148                 fsb = 166667;
 149                 break;
 150         case 2:
 151                 fsb = 200000;
 152                 break;
 153         case 0:
 154                 fsb = 266667;
 155                 break;
 156         case 4:
 157                 fsb = 333333;
 158                 break;
 159         default:
 160                 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
 161         }
 162
 163         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 164         dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
 165                         msr_lo, msr_tmp);
 166
 167         msr_tmp = (msr_lo >> 22) & 0x1f;
 168         dprintk("bits 22-26 are 0x%x, speed is %u\n",
 169                         msr_tmp, (msr_tmp * fsb));
 170
 171         ret = (msr_tmp * fsb);
 172         return ret;
 173 }
 174
 175
 176 static unsigned int pentium4_get_frequency(void)
 177 {
 178         struct cpuinfo_x86 *c = &boot_cpu_data;
 179         u32 msr_lo, msr_hi, mult;
 180         unsigned int fsb = 0;
 181         unsigned int ret;
 182         u8 fsb_code;
 183
 184         /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
 185          * to System Bus Frequency Ratio Field in the Processor Frequency
 186          * Configuration Register of the MSR. Therefore the current
 187          * frequency cannot be calculated and has to be measured.
 188          */
 189         if (c->x86_model < 2)
 190                 return cpu_khz;
 191
 192         rdmsr(0x2c, msr_lo, msr_hi);
 193
 194         dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
 195
 196         /* decode the FSB: see IA-32 Intel (C) Architecture Software
 197          * Developer's Manual, Volume 3: System Prgramming Guide,
 198          * revision #12 in Table B-1: MSRs in the Pentium 4 and
 199          * Intel Xeon Processors, on page B-4 and B-5.
 200          */
 201         fsb_code = (msr_lo >> 16) & 0x7;
 202         switch (fsb_code) {
 203         case 0:
 204                 fsb = 100 * 1000;
 205                 break;
 206         case 1:
 207                 fsb = 13333 * 10;
 208                 break;
 209         case 2:
 210                 fsb = 200 * 1000;
 211                 break;
 212         }
 213
 214         if (!fsb)
 215                 printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
 216                                 "Please send an e-mail to <linux@brodo.de>\n");
 217
 218         /* Multiplier. */
 219         mult = msr_lo >> 24;
 220
 221         dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
 222                         fsb, mult, (fsb * mult));
 223
 224         ret = (fsb * mult);
 225         return ret;
 226 }
 227
 228
 229 unsigned int speedstep_get_frequency(unsigned int processor)
 230 {
 231         switch (processor) {
 232         case SPEEDSTEP_CPU_PCORE:
 233                 return pentium_core_get_frequency();
 234         case SPEEDSTEP_CPU_PM:
 235                 return pentiumM_get_frequency();
 236         case SPEEDSTEP_CPU_P4D:
 237         case SPEEDSTEP_CPU_P4M:
 238                 return pentium4_get_frequency();
 239         case SPEEDSTEP_CPU_PIII_T:
 240         case SPEEDSTEP_CPU_PIII_C:
 241         case SPEEDSTEP_CPU_PIII_C_EARLY:
 242                 return pentium3_get_frequency(processor);
 243         default:
 244                 return 0;
 245         };
 246         return 0;
 247 }
 248 EXPORT_SYMBOL_GPL(speedstep_get_frequency);
 249
 250
 251 /*********************************************************************
 252  *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 253  *********************************************************************/
 254
 255 unsigned int speedstep_detect_processor(void)
 256 {
 257         struct cpuinfo_x86 *c = &cpu_data(0);
 258         u32 ebx, msr_lo, msr_hi;
 259
 260         dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
 261
 262         if ((c->x86_vendor != X86_VENDOR_INTEL) ||
 263             ((c->x86 != 6) && (c->x86 != 0xF)))
 264                 return 0;
 265
 266         if (c->x86 == 0xF) {
 267                 /* Intel Mobile Pentium 4-M
 268                  * or Intel Mobile Pentium 4 with 533 MHz FSB */
 269                 if (c->x86_model != 2)
 270                         return 0;
 271
 272                 ebx = cpuid_ebx(0x00000001);
 273                 ebx &= 0x000000FF;
 274
 275                 dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
 276
 277                 switch (c->x86_mask) {
 278                 case 4:
 279                         /*
 280                          * B-stepping [M-P4-M]
 281                          * sample has ebx = 0x0f, production has 0x0e.
 282                          */
 283                         if ((ebx == 0x0e) || (ebx == 0x0f))
 284                                 return SPEEDSTEP_CPU_P4M;
 285                         break;
 286                 case 7:
 287                         /*
 288                          * C-stepping [M-P4-M]
 289                          * needs to have ebx=0x0e, else it's a celeron:
 290                          * cf. 25130917.pdf / page 7, footnote 5 even
 291                          * though 25072120.pdf / page 7 doesn't say
 292                          * samples are only of B-stepping...
 293                          */
 294                         if (ebx == 0x0e)
 295                                 return SPEEDSTEP_CPU_P4M;
 296                         break;
 297                 case 9:
 298                         /*
 299                          * D-stepping [M-P4-M or M-P4/533]
 300                          *
 301                          * this is totally strange: CPUID 0x0F29 is
 302                          * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
 303                          * The latter need to be sorted out as they don't
 304                          * support speedstep.
 305                          * Celerons with CPUID 0x0F29 may have either
 306                          * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
 307                          * specific.
 308                          * M-P4-Ms may have either ebx=0xe or 0xf [see above]
 309                          * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
 310                          * also, M-P4M HTs have ebx=0x8, too
 311                          * For now, they are distinguished by the model_id
 312                          * string
 313                          */
 314                         if ((ebx == 0x0e) ||
 315                                 (strstr(c->x86_model_id,
 316                                     "Mobile Intel(R) Pentium(R) 4") != NULL))
 317                                 return SPEEDSTEP_CPU_P4M;
 318                         break;
 319                 default:
 320                         break;
 321                 }
 322                 return 0;
 323         }
 324
 325         switch (c->x86_model) {
 326         case 0x0B: /* Intel PIII [Tualatin] */
 327                 /* cpuid_ebx(1) is 0x04 for desktop PIII,
 328                  * 0x06 for mobile PIII-M */
 329                 ebx = cpuid_ebx(0x00000001);
 330                 dprintk("ebx is %x\n", ebx);
 331
 332                 ebx &= 0x000000FF;
 333
 334                 if (ebx != 0x06)
 335                         return 0;
 336
 337                 /* So far all PIII-M processors support SpeedStep. See
 338                  * Intel's 24540640.pdf of June 2003
 339                  */
 340                 return SPEEDSTEP_CPU_PIII_T;
 341
 342         case 0x08: /* Intel PIII [Coppermine] */
 343
 344                 /* all mobile PIII Coppermines have FSB 100 MHz
 345                  * ==> sort out a few desktop PIIIs. */
 346                 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
 347                 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
 348                                 msr_lo, msr_hi);
 349                 msr_lo &= 0x00c0000;
 350                 if (msr_lo != 0x0080000)
 351                         return 0;
 352
 353                 /*
 354                  * If the processor is a mobile version,
 355                  * platform ID has bit 50 set
 356                  * it has SpeedStep technology if either
 357                  * bit 56 or 57 is set
 358                  */
 359                 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
 360                 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
 361                                 msr_lo, msr_hi);
 362                 if ((msr_hi & (1<<18)) &&
 363                     (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
 364                         if (c->x86_mask == 0x01) {
 365                                 dprintk("early PIII version\n");
 366                                 return SPEEDSTEP_CPU_PIII_C_EARLY;
 367                         } else
 368                                 return SPEEDSTEP_CPU_PIII_C;
 369                 }
 370
 371         default:
 372                 return 0;
 373         }
 374 }
 375 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
 376
 377
 378 /*********************************************************************
 379  *                     DETECT SPEEDSTEP SPEEDS                       *
 380  *********************************************************************/
 381
 382 unsigned int speedstep_get_freqs(unsigned int processor,
 383                                   unsigned int *low_speed,
 384                                   unsigned int *high_speed,
 385                                   unsigned int *transition_latency,
 386                                   void (*set_state) (unsigned int state))
 387 {
 388         unsigned int prev_speed;
 389         unsigned int ret = 0;
 390         unsigned long flags;
 391         struct timeval tv1, tv2;
 392
 393         if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
 394                 return -EINVAL;
 395
 396         dprintk("trying to determine both speeds\n");
 397
 398         /* get current speed */
 399         prev_speed = speedstep_get_frequency(processor);
 400         if (!prev_speed)
 401                 return -EIO;
 402
 403         dprintk("previous speed is %u\n", prev_speed);
 404
 405         local_irq_save(flags);
 406
 407         /* switch to low state */
 408         set_state(SPEEDSTEP_LOW);
 409         *low_speed = speedstep_get_frequency(processor);
 410         if (!*low_speed) {
 411                 ret = -EIO;
 412                 goto out;
 413         }
 414
 415         dprintk("low speed is %u\n", *low_speed);
 416
 417         /* start latency measurement */
 418         if (transition_latency)
 419                 do_gettimeofday(&tv1);
 420
 421         /* switch to high state */
 422         set_state(SPEEDSTEP_HIGH);
 423
 424         /* end latency measurement */
 425         if (transition_latency)
 426                 do_gettimeofday(&tv2);
 427
 428         *high_speed = speedstep_get_frequency(processor);
 429         if (!*high_speed) {
 430                 ret = -EIO;
 431                 goto out;
 432         }
 433
 434         dprintk("high speed is %u\n", *high_speed);
 435
 436         if (*low_speed == *high_speed) {
 437                 ret = -ENODEV;
 438                 goto out;
 439         }
 440
 441         /* switch to previous state, if necessary */
 442         if (*high_speed != prev_speed)
 443                 set_state(SPEEDSTEP_LOW);
 444
 445         if (transition_latency) {
 446                 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
 447                         tv2.tv_usec - tv1.tv_usec;
 448                 dprintk("transition latency is %u uSec\n", *transition_latency);
 449
 450                 /* convert uSec to nSec and add 20% for safety reasons */
 451                 *transition_latency *= 1200;
 452
 453                 /* check if the latency measurement is too high or too low
 454                  * and set it to a safe value (500uSec) in that case
 455                  */
 456                 if (*transition_latency > 10000000 ||
 457                     *transition_latency < 50000) {
 458                         printk(KERN_WARNING PFX "frequency transition "
 459                                         "measured seems out of range (%u "
 460                                         "nSec), falling back to a safe one of"
 461                                         "%u nSec.\n",
 462                                         *transition_latency, 500000);
 463                         *transition_latency = 500000;
 464                 }
 465         }
 466
 467 out:
 468         local_irq_restore(flags);
 469         return ret;
 470 }
 471 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
 472
 473 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
 474 module_param(relaxed_check, int, 0444);
 475 MODULE_PARM_DESC(relaxed_check,
 476                 "Don't do all checks for speedstep capability.");
 477 #endif
 478
 479 MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
 480 MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
 481 MODULE_LICENSE("GPL");