git.oblomov.eu Git - linux-2.6/blob - drivers/video/aty/radeon_pm.c

   1 /*
   2  *      drivers/video/aty/radeon_pm.c
   3  *
   4  *      Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
   5  *      Copyright 2004 Paul Mackerras <paulus@samba.org>
   6  *
   7  *      This is the power management code for ATI radeon chipsets. It contains
   8  *      some dynamic clock PM enable/disable code similar to what X.org does,
   9  *      some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
  10  *      and the necessary bits to re-initialize from scratch a few chips found
  11  *      on PowerMacs as well. The later could be extended to more platforms
  12  *      provided the memory controller configuration code be made more generic,
  13  *      and you can get the proper mode register commands for your RAMs.
  14  *      Those things may be found in the BIOS image...
  15  */
  16
  17 #include "radeonfb.h"
  18
  19 #include <linux/console.h>
  20 #include <linux/agp_backend.h>
  21
  22 #ifdef CONFIG_PPC_PMAC
  23 #include <asm/machdep.h>
  24 #include <asm/prom.h>
  25 #include <asm/pmac_feature.h>
  26 #endif
  27
  28 #include "ati_ids.h"
  29
  30 /*
  31  * Workarounds for bugs in PC laptops:
  32  * - enable D2 sleep in some IBM Thinkpads
  33  * - special case for Samsung P35
  34  *
  35  * Whitelist by subsystem vendor/device because
  36  * its the subsystem vendor's fault!
  37  */
  38
  39 #if defined(CONFIG_PM) && defined(CONFIG_X86)
  40 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
  41
  42 struct radeon_device_id {
  43         const char *ident;                     /* (arbitrary) Name */
  44         const unsigned short subsystem_vendor; /* Subsystem Vendor ID */
  45         const unsigned short subsystem_device; /* Subsystem Device ID */
  46         const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */
  47         const reinit_function_ptr new_reinit_func;   /* changed reinit_func */
  48 };
  49
  50 #define BUGFIX(model, sv, sd, pm, fn) { \
  51         .ident = model, \
  52         .subsystem_vendor = sv, \
  53         .subsystem_device = sd, \
  54         .pm_mode_modifier = pm, \
  55         .new_reinit_func  = fn  \
  56 }
  57
  58 static struct radeon_device_id radeon_workaround_list[] = {
  59         BUGFIX("IBM Thinkpad R32",
  60                PCI_VENDOR_ID_IBM, 0x1905,
  61                radeon_pm_d2, NULL),
  62         BUGFIX("IBM Thinkpad R40",
  63                PCI_VENDOR_ID_IBM, 0x0526,
  64                radeon_pm_d2, NULL),
  65         BUGFIX("IBM Thinkpad R40",
  66                PCI_VENDOR_ID_IBM, 0x0527,
  67                radeon_pm_d2, NULL),
  68         BUGFIX("IBM Thinkpad R50/R51/T40/T41",
  69                PCI_VENDOR_ID_IBM, 0x0531,
  70                radeon_pm_d2, NULL),
  71         BUGFIX("IBM Thinkpad R51/T40/T41/T42",
  72                PCI_VENDOR_ID_IBM, 0x0530,
  73                radeon_pm_d2, NULL),
  74         BUGFIX("IBM Thinkpad T30",
  75                PCI_VENDOR_ID_IBM, 0x0517,
  76                radeon_pm_d2, NULL),
  77         BUGFIX("IBM Thinkpad T40p",
  78                PCI_VENDOR_ID_IBM, 0x054d,
  79                radeon_pm_d2, NULL),
  80         BUGFIX("IBM Thinkpad T42",
  81                PCI_VENDOR_ID_IBM, 0x0550,
  82                radeon_pm_d2, NULL),
  83         BUGFIX("IBM Thinkpad X31/X32",
  84                PCI_VENDOR_ID_IBM, 0x052f,
  85                radeon_pm_d2, NULL),
  86         BUGFIX("Samsung P35",
  87                PCI_VENDOR_ID_SAMSUNG, 0xc00c,
  88                radeon_pm_off, radeon_reinitialize_M10),
  89         BUGFIX("Acer Aspire 2010",
  90                PCI_VENDOR_ID_AI, 0x0061,
  91                radeon_pm_off, radeon_reinitialize_M10),
  92         BUGFIX("Acer Travelmate 290D/292LMi",
  93                PCI_VENDOR_ID_AI, 0x005a,
  94                radeon_pm_off, radeon_reinitialize_M10),
  95         { .ident = NULL }
  96 };
  97
  98 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
  99 {
 100         struct radeon_device_id *id;
 101
 102         for (id = radeon_workaround_list; id->ident != NULL; id++ )
 103                 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
 104                     (id->subsystem_device == rinfo->pdev->subsystem_device )) {
 105
 106                         /* we found a device that requires workaround */
 107                         printk(KERN_DEBUG "radeonfb: %s detected"
 108                                ", enabling workaround\n", id->ident);
 109
 110                         rinfo->pm_mode |= id->pm_mode_modifier;
 111
 112                         if (id->new_reinit_func != NULL)
 113                                 rinfo->reinit_func = id->new_reinit_func;
 114
 115                         return 1;
 116                 }
 117         return 0;  /* not found */
 118 }
 119
 120 #else  /* defined(CONFIG_PM) && defined(CONFIG_X86) */
 121 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
 122 {
 123         return 0;
 124 }
 125 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
 126
 127
 128
 129 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
 130 {
 131         u32 tmp;
 132
 133         /* RV100 */
 134         if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
 135                 if (rinfo->has_CRTC2) {
 136                         tmp = INPLL(pllSCLK_CNTL);
 137                         tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
 138                         tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
 139                         OUTPLL(pllSCLK_CNTL, tmp);
 140                 }
 141                 tmp = INPLL(pllMCLK_CNTL);
 142                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 143                         MCLK_CNTL__FORCE_MCLKB |
 144                         MCLK_CNTL__FORCE_YCLKA |
 145                         MCLK_CNTL__FORCE_YCLKB |
 146                         MCLK_CNTL__FORCE_AIC |
 147                         MCLK_CNTL__FORCE_MC);
 148                 OUTPLL(pllMCLK_CNTL, tmp);
 149                 return;
 150         }
 151         /* R100 */
 152         if (!rinfo->has_CRTC2) {
 153                 tmp = INPLL(pllSCLK_CNTL);
 154                 tmp |= (SCLK_CNTL__FORCE_CP     | SCLK_CNTL__FORCE_HDP  |
 155                         SCLK_CNTL__FORCE_DISP1  | SCLK_CNTL__FORCE_TOP  |
 156                         SCLK_CNTL__FORCE_E2     | SCLK_CNTL__FORCE_SE   |
 157                         SCLK_CNTL__FORCE_IDCT   | SCLK_CNTL__FORCE_VIP  |
 158                         SCLK_CNTL__FORCE_RE     | SCLK_CNTL__FORCE_PB   |
 159                         SCLK_CNTL__FORCE_TAM    | SCLK_CNTL__FORCE_TDM  |
 160                         SCLK_CNTL__FORCE_RB);
 161                 OUTPLL(pllSCLK_CNTL, tmp);
 162                 return;
 163         }
 164         /* RV350 (M10/M11) */
 165         if (rinfo->family == CHIP_FAMILY_RV350) {
 166                 /* for RV350/M10/M11, no delays are required. */
 167                 tmp = INPLL(pllSCLK_CNTL2);
 168                 tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
 169                         SCLK_CNTL2__R300_FORCE_GA  |
 170                         SCLK_CNTL2__R300_FORCE_CBA);
 171                 OUTPLL(pllSCLK_CNTL2, tmp);
 172
 173                 tmp = INPLL(pllSCLK_CNTL);
 174                 tmp |= (SCLK_CNTL__FORCE_DISP2          | SCLK_CNTL__FORCE_CP           |
 175                         SCLK_CNTL__FORCE_HDP            | SCLK_CNTL__FORCE_DISP1        |
 176                         SCLK_CNTL__FORCE_TOP            | SCLK_CNTL__FORCE_E2           |
 177                         SCLK_CNTL__R300_FORCE_VAP       | SCLK_CNTL__FORCE_IDCT         |
 178                         SCLK_CNTL__FORCE_VIP            | SCLK_CNTL__R300_FORCE_SR      |
 179                         SCLK_CNTL__R300_FORCE_PX        | SCLK_CNTL__R300_FORCE_TX      |
 180                         SCLK_CNTL__R300_FORCE_US        | SCLK_CNTL__FORCE_TV_SCLK      |
 181                         SCLK_CNTL__R300_FORCE_SU        | SCLK_CNTL__FORCE_OV0);
 182                 OUTPLL(pllSCLK_CNTL, tmp);
 183
 184                 tmp = INPLL(pllSCLK_MORE_CNTL);
 185                 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS  | SCLK_MORE_CNTL__FORCE_MC_GUI  |
 186                         SCLK_MORE_CNTL__FORCE_MC_HOST);
 187                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 188
 189                 tmp = INPLL(pllMCLK_CNTL);
 190                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 191                         MCLK_CNTL__FORCE_MCLKB |
 192                         MCLK_CNTL__FORCE_YCLKA |
 193                         MCLK_CNTL__FORCE_YCLKB |
 194                         MCLK_CNTL__FORCE_MC);
 195                 OUTPLL(pllMCLK_CNTL, tmp);
 196
 197                 tmp = INPLL(pllVCLK_ECP_CNTL);
 198                 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb  |
 199                          VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
 200                          VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
 201                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
 202
 203                 tmp = INPLL(pllPIXCLKS_CNTL);
 204                 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb               |
 205                          PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb           |
 206                          PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb  |
 207                          PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb           |
 208                          PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb          |
 209                          PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb             |
 210                          PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb       |
 211                          PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb           |
 212                          PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb           |
 213                          PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb     |
 214                          PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb       |
 215                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
 216                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
 217                          PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
 218                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 219
 220                 return;
 221         }
 222
 223         /* Default */
 224
 225         /* Force Core Clocks */
 226         tmp = INPLL(pllSCLK_CNTL);
 227         tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
 228
 229         /* XFree doesn't do that case, but we had this code from Apple and it
 230          * seem necessary for proper suspend/resume operations
 231          */
 232         if (rinfo->is_mobility) {
 233                 tmp |=  SCLK_CNTL__FORCE_HDP|
 234                         SCLK_CNTL__FORCE_DISP1|
 235                         SCLK_CNTL__FORCE_DISP2|
 236                         SCLK_CNTL__FORCE_TOP|
 237                         SCLK_CNTL__FORCE_SE|
 238                         SCLK_CNTL__FORCE_IDCT|
 239                         SCLK_CNTL__FORCE_VIP|
 240                         SCLK_CNTL__FORCE_PB|
 241                         SCLK_CNTL__FORCE_RE|
 242                         SCLK_CNTL__FORCE_TAM|
 243                         SCLK_CNTL__FORCE_TDM|
 244                         SCLK_CNTL__FORCE_RB|
 245                         SCLK_CNTL__FORCE_TV_SCLK|
 246                         SCLK_CNTL__FORCE_SUBPIC|
 247                         SCLK_CNTL__FORCE_OV0;
 248         }
 249         else if (rinfo->family == CHIP_FAMILY_R300 ||
 250                    rinfo->family == CHIP_FAMILY_R350) {
 251                 tmp |=  SCLK_CNTL__FORCE_HDP   |
 252                         SCLK_CNTL__FORCE_DISP1 |
 253                         SCLK_CNTL__FORCE_DISP2 |
 254                         SCLK_CNTL__FORCE_TOP   |
 255                         SCLK_CNTL__FORCE_IDCT  |
 256                         SCLK_CNTL__FORCE_VIP;
 257         }
 258         OUTPLL(pllSCLK_CNTL, tmp);
 259         radeon_msleep(16);
 260
 261         if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
 262                 tmp = INPLL(pllSCLK_CNTL2);
 263                 tmp |=  SCLK_CNTL2__R300_FORCE_TCL |
 264                         SCLK_CNTL2__R300_FORCE_GA  |
 265                         SCLK_CNTL2__R300_FORCE_CBA;
 266                 OUTPLL(pllSCLK_CNTL2, tmp);
 267                 radeon_msleep(16);
 268         }
 269
 270         tmp = INPLL(pllCLK_PIN_CNTL);
 271         tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
 272         OUTPLL(pllCLK_PIN_CNTL, tmp);
 273         radeon_msleep(15);
 274
 275         if (rinfo->is_IGP) {
 276                 /* Weird  ... X is _un_ forcing clocks here, I think it's
 277                  * doing backward. Imitate it for now...
 278                  */
 279                 tmp = INPLL(pllMCLK_CNTL);
 280                 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
 281                          MCLK_CNTL__FORCE_YCLKA);
 282                 OUTPLL(pllMCLK_CNTL, tmp);
 283                 radeon_msleep(16);
 284         }
 285         /* Hrm... same shit, X doesn't do that but I have to */
 286         else if (rinfo->is_mobility) {
 287                 tmp = INPLL(pllMCLK_CNTL);
 288                 tmp |= (MCLK_CNTL__FORCE_MCLKA |
 289                         MCLK_CNTL__FORCE_MCLKB |
 290                         MCLK_CNTL__FORCE_YCLKA |
 291                         MCLK_CNTL__FORCE_YCLKB);
 292                 OUTPLL(pllMCLK_CNTL, tmp);
 293                 radeon_msleep(16);
 294
 295                 tmp = INPLL(pllMCLK_MISC);
 296                 tmp &=  ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
 297                           MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
 298                           MCLK_MISC__MC_MCLK_DYN_ENABLE|
 299                           MCLK_MISC__IO_MCLK_DYN_ENABLE);
 300                 OUTPLL(pllMCLK_MISC, tmp);
 301                 radeon_msleep(15);
 302         }
 303
 304         if (rinfo->is_mobility) {
 305                 tmp = INPLL(pllSCLK_MORE_CNTL);
 306                 tmp |=  SCLK_MORE_CNTL__FORCE_DISPREGS|
 307                         SCLK_MORE_CNTL__FORCE_MC_GUI|
 308                         SCLK_MORE_CNTL__FORCE_MC_HOST;
 309                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 310                 radeon_msleep(16);
 311         }
 312
 313         tmp = INPLL(pllPIXCLKS_CNTL);
 314         tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
 315                  PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 316                  PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
 317                  PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 318                  PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
 319                  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
 320                  PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
 321         OUTPLL(pllPIXCLKS_CNTL, tmp);
 322         radeon_msleep(16);
 323
 324         tmp = INPLL( pllVCLK_ECP_CNTL);
 325         tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 326                  VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 327         OUTPLL( pllVCLK_ECP_CNTL, tmp);
 328         radeon_msleep(16);
 329 }
 330
 331 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
 332 {
 333         u32 tmp;
 334
 335         /* R100 */
 336         if (!rinfo->has_CRTC2) {
 337                 tmp = INPLL(pllSCLK_CNTL);
 338
 339                 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
 340                     tmp &= ~(SCLK_CNTL__FORCE_CP        | SCLK_CNTL__FORCE_RB);
 341                 tmp &= ~(SCLK_CNTL__FORCE_HDP           | SCLK_CNTL__FORCE_DISP1 |
 342                          SCLK_CNTL__FORCE_TOP           | SCLK_CNTL__FORCE_SE   |
 343                          SCLK_CNTL__FORCE_IDCT          | SCLK_CNTL__FORCE_RE   |
 344                          SCLK_CNTL__FORCE_PB            | SCLK_CNTL__FORCE_TAM  |
 345                          SCLK_CNTL__FORCE_TDM);
 346                 OUTPLL(pllSCLK_CNTL, tmp);
 347                 return;
 348         }
 349
 350         /* M10/M11 */
 351         if (rinfo->family == CHIP_FAMILY_RV350) {
 352                 tmp = INPLL(pllSCLK_CNTL2);
 353                 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
 354                          SCLK_CNTL2__R300_FORCE_GA  |
 355                          SCLK_CNTL2__R300_FORCE_CBA);
 356                 tmp |=  (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
 357                          SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT  |
 358                          SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
 359                 OUTPLL(pllSCLK_CNTL2, tmp);
 360
 361                 tmp = INPLL(pllSCLK_CNTL);
 362                 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP      |
 363                          SCLK_CNTL__FORCE_HDP   | SCLK_CNTL__FORCE_DISP1   |
 364                          SCLK_CNTL__FORCE_TOP   | SCLK_CNTL__FORCE_E2      |
 365                          SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
 366                          SCLK_CNTL__FORCE_VIP   | SCLK_CNTL__R300_FORCE_SR |
 367                          SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
 368                          SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
 369                          SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
 370                 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
 371                 OUTPLL(pllSCLK_CNTL, tmp);
 372
 373                 tmp = INPLL(pllSCLK_MORE_CNTL);
 374                 tmp &= ~SCLK_MORE_CNTL__FORCEON;
 375                 tmp |=  SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
 376                         SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
 377                         SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
 378                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 379
 380                 tmp = INPLL(pllVCLK_ECP_CNTL);
 381                 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 382                         VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 383                 OUTPLL(pllVCLK_ECP_CNTL, tmp);
 384
 385                 tmp = INPLL(pllPIXCLKS_CNTL);
 386                 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb         |
 387                         PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb     |
 388                         PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
 389                         PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb            |
 390                         PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb    |
 391                         PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb       |
 392                         PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb        |
 393                         PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb     |
 394                         PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb     |
 395                         PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      |
 396                         PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        |
 397                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           |
 398                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
 399                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 400
 401                 tmp = INPLL(pllMCLK_MISC);
 402                 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
 403                         MCLK_MISC__IO_MCLK_DYN_ENABLE);
 404                 OUTPLL(pllMCLK_MISC, tmp);
 405
 406                 tmp = INPLL(pllMCLK_CNTL);
 407                 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
 408                 tmp &= ~(MCLK_CNTL__FORCE_YCLKA  |
 409                          MCLK_CNTL__FORCE_YCLKB  |
 410                          MCLK_CNTL__FORCE_MC);
 411
 412                 /* Some releases of vbios have set DISABLE_MC_MCLKA
 413                  * and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
 414                  * bits will cause H/W hang when reading video memory with dynamic
 415                  * clocking enabled.
 416                  */
 417                 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
 418                     (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
 419                         /* If both bits are set, then check the active channels */
 420                         tmp = INPLL(pllMCLK_CNTL);
 421                         if (rinfo->vram_width == 64) {
 422                             if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
 423                                 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
 424                             else
 425                                 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
 426                         } else {
 427                             tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
 428                                      MCLK_CNTL__R300_DISABLE_MC_MCLKB);
 429                         }
 430                 }
 431                 OUTPLL(pllMCLK_CNTL, tmp);
 432                 return;
 433         }
 434
 435         /* R300 */
 436         if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
 437                 tmp = INPLL(pllSCLK_CNTL);
 438                 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
 439                 tmp |= SCLK_CNTL__FORCE_CP;
 440                 OUTPLL(pllSCLK_CNTL, tmp);
 441                 radeon_msleep(15);
 442
 443                 tmp = INPLL(pllSCLK_CNTL2);
 444                 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
 445                          SCLK_CNTL2__R300_FORCE_GA  |
 446                          SCLK_CNTL2__R300_FORCE_CBA);
 447                 OUTPLL(pllSCLK_CNTL2, tmp);
 448         }
 449
 450         /* Others */
 451
 452         tmp = INPLL( pllCLK_PWRMGT_CNTL);
 453         tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
 454                  CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
 455                  CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
 456         tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
 457                (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
 458         OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
 459         radeon_msleep(15);
 460
 461         tmp = INPLL(pllCLK_PIN_CNTL);
 462         tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
 463         OUTPLL(pllCLK_PIN_CNTL, tmp);
 464         radeon_msleep(15);
 465
 466         /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
 467          * to lockup randomly, leave them as set by BIOS.
 468          */
 469         tmp = INPLL(pllSCLK_CNTL);
 470         tmp &= ~SCLK_CNTL__FORCEON_MASK;
 471
 472         /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
 473         if ((rinfo->family == CHIP_FAMILY_RV250 &&
 474              ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
 475             ((rinfo->family == CHIP_FAMILY_RV100) &&
 476              ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
 477                 tmp |= SCLK_CNTL__FORCE_CP;
 478                 tmp |= SCLK_CNTL__FORCE_VIP;
 479         }
 480         OUTPLL(pllSCLK_CNTL, tmp);
 481         radeon_msleep(15);
 482
 483         if ((rinfo->family == CHIP_FAMILY_RV200) ||
 484             (rinfo->family == CHIP_FAMILY_RV250) ||
 485             (rinfo->family == CHIP_FAMILY_RV280)) {
 486                 tmp = INPLL(pllSCLK_MORE_CNTL);
 487                 tmp &= ~SCLK_MORE_CNTL__FORCEON;
 488
 489                 /* RV200::A11 A12 RV250::A11 A12 */
 490                 if (((rinfo->family == CHIP_FAMILY_RV200) ||
 491                      (rinfo->family == CHIP_FAMILY_RV250)) &&
 492                     ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
 493                         tmp |= SCLK_MORE_CNTL__FORCEON;
 494
 495                 OUTPLL(pllSCLK_MORE_CNTL, tmp);
 496                 radeon_msleep(15);
 497         }
 498
 499
 500         /* RV200::A11 A12, RV250::A11 A12 */
 501         if (((rinfo->family == CHIP_FAMILY_RV200) ||
 502              (rinfo->family == CHIP_FAMILY_RV250)) &&
 503             ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
 504                 tmp = INPLL(pllPLL_PWRMGT_CNTL);
 505                 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
 506                 OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
 507                 radeon_msleep(15);
 508         }
 509
 510         tmp = INPLL(pllPIXCLKS_CNTL);
 511         tmp |=  PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
 512                 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
 513                 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 514                 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
 515                 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
 516                 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 517                 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
 518         OUTPLL(pllPIXCLKS_CNTL, tmp);
 519         radeon_msleep(15);
 520
 521         tmp = INPLL(pllVCLK_ECP_CNTL);
 522         tmp |=  VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
 523                 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
 524         OUTPLL(pllVCLK_ECP_CNTL, tmp);
 525
 526         /* X doesn't do that ... hrm, we do on mobility && Macs */
 527 #ifdef CONFIG_PPC_OF
 528         if (rinfo->is_mobility) {
 529                 tmp  = INPLL(pllMCLK_CNTL);
 530                 tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
 531                          MCLK_CNTL__FORCE_MCLKB |
 532                          MCLK_CNTL__FORCE_YCLKA |
 533                          MCLK_CNTL__FORCE_YCLKB);
 534                 OUTPLL(pllMCLK_CNTL, tmp);
 535                 radeon_msleep(15);
 536
 537                 tmp = INPLL(pllMCLK_MISC);
 538                 tmp |=  MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
 539                         MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
 540                         MCLK_MISC__MC_MCLK_DYN_ENABLE|
 541                         MCLK_MISC__IO_MCLK_DYN_ENABLE;
 542                 OUTPLL(pllMCLK_MISC, tmp);
 543                 radeon_msleep(15);
 544         }
 545 #endif /* CONFIG_PPC_OF */
 546 }
 547
 548 #ifdef CONFIG_PM
 549
 550 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
 551 {
 552         OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
 553         OUTREG( MC_IND_DATA, value);
 554 }
 555
 556 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
 557 {
 558         OUTREG( MC_IND_INDEX, indx);
 559         return INREG( MC_IND_DATA);
 560 }
 561
 562 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
 563 {
 564         rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
 565         rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
 566         rinfo->save_regs[2] = INPLL(MCLK_CNTL);
 567         rinfo->save_regs[3] = INPLL(SCLK_CNTL);
 568         rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
 569         rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
 570         rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
 571         rinfo->save_regs[7] = INPLL(MCLK_MISC);
 572         rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
 573
 574         rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
 575         rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
 576         rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
 577         rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
 578         rinfo->save_regs[14] = INREG(BUS_CNTL1);
 579         rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
 580         rinfo->save_regs[16] = INREG(AGP_CNTL);
 581         rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
 582         rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
 583         rinfo->save_regs[19] = INREG(GPIOPAD_A);
 584         rinfo->save_regs[20] = INREG(GPIOPAD_EN);
 585         rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
 586         rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
 587         rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
 588         rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
 589         rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
 590         rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
 591         rinfo->save_regs[27] = INREG(GPIO_MONID);
 592         rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
 593
 594         rinfo->save_regs[29] = INREG(SURFACE_CNTL);
 595         rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
 596         rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
 597         rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
 598         rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
 599
 600         rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
 601         rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
 602         rinfo->save_regs[36] = INREG(BUS_CNTL);
 603         rinfo->save_regs[39] = INREG(RBBM_CNTL);
 604         rinfo->save_regs[40] = INREG(DAC_CNTL);
 605         rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
 606         rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
 607         rinfo->save_regs[38] = INREG(FCP_CNTL);
 608
 609         if (rinfo->is_mobility) {
 610                 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
 611                 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
 612                 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
 613                 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
 614                 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
 615                 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
 616                 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
 617         }
 618
 619         if (rinfo->family >= CHIP_FAMILY_RV200) {
 620                 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
 621                 rinfo->save_regs[46] = INREG(MC_CNTL);
 622                 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
 623                 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
 624                 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
 625                 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
 626                 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
 627                 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
 628                 rinfo->save_regs[53] = INREG(MC_DEBUG);
 629         }
 630         rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
 631         rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
 632         rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
 633         rinfo->save_regs[57] = INREG(FW_CNTL);
 634
 635         if (rinfo->family >= CHIP_FAMILY_R300) {
 636                 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
 637                 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
 638                 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
 639                 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
 640                 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
 641                 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
 642                 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
 643                 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
 644                 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
 645                 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
 646                 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
 647                 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
 648                 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
 649                 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
 650                 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
 651                 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
 652         } else {
 653                 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
 654                 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
 655                 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
 656                 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
 657                 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
 658                 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
 659         }
 660
 661         rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
 662         rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
 663         rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
 664         rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
 665         rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
 666         rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
 667         rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
 668
 669         rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
 670         rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
 671         rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
 672         rinfo->save_regs[84] = INREG(TMDS_CNTL);
 673         rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
 674         rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
 675         rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
 676         rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
 677         rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
 678         rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
 679         rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
 680         rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
 681         rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
 682         rinfo->save_regs[96] = INREG(HDP_DEBUG);
 683         rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
 684         rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
 685         rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
 686 }
 687
 688 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
 689 {
 690         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
 691
 692         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
 693         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
 694         OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
 695         OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
 696         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
 697         OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
 698         OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
 699         OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
 700         if (rinfo->family == CHIP_FAMILY_RV350)
 701                 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
 702
 703         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
 704         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
 705         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
 706         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
 707         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
 708         OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
 709
 710         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
 711         OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
 712         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
 713         OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
 714         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
 715         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
 716         OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
 717         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
 718         OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
 719         OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
 720         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
 721
 722         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
 723         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
 724         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
 725         OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
 726         OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
 727         OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
 728         OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
 729         OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
 730         OUTREG(GPIO_MONID, rinfo->save_regs[27]);
 731         OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
 732 }
 733
 734 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
 735 {
 736         OUTREG(GPIOPAD_MASK, 0x0001ffff);
 737         OUTREG(GPIOPAD_EN, 0x00000400);
 738         OUTREG(GPIOPAD_A, 0x00000000);
 739         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
 740         OUTREG(ZV_LCDPAD_EN, 0x00000000);
 741         OUTREG(ZV_LCDPAD_A, 0x00000000);
 742         OUTREG(GPIO_VGA_DDC, 0x00030000);
 743         OUTREG(GPIO_DVI_DDC, 0x00000000);
 744         OUTREG(GPIO_MONID, 0x00030000);
 745         OUTREG(GPIO_CRT2_DDC, 0x00000000);
 746 }
 747
 748 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
 749 {
 750         /* Set v2clk to 65MHz */
 751         if (rinfo->family <= CHIP_FAMILY_RV280) {
 752                 OUTPLL(pllPIXCLKS_CNTL,
 753                          __INPLL(rinfo, pllPIXCLKS_CNTL)
 754                          & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
 755
 756                 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
 757                 OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
 758         } else {
 759                 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
 760                 INPLL(pllP2PLL_REF_DIV);
 761                 OUTPLL(pllP2PLL_CNTL, 0x0000a700);
 762         }
 763
 764         OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
 765
 766         OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
 767         mdelay(1);
 768
 769         OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
 770         mdelay( 1);
 771
 772         OUTPLL(pllPIXCLKS_CNTL,
 773                 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
 774                 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
 775         mdelay( 1);
 776 }
 777
 778 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
 779 {
 780         u32 reg;
 781
 782         reg  = INREG(BUS_CNTL1);
 783         if (rinfo->family <= CHIP_FAMILY_RV280) {
 784                 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
 785                 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
 786         } else {
 787                 reg |= 0x4080;
 788         }
 789         OUTREG(BUS_CNTL1, reg);
 790
 791         reg  = INPLL(PLL_PWRMGT_CNTL);
 792         reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
 793                 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
 794         reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
 795         reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
 796         OUTPLL(PLL_PWRMGT_CNTL, reg);
 797
 798         reg  = INREG(TV_DAC_CNTL);
 799         reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
 800         reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
 801                 TV_DAC_CNTL_BDACPD |
 802                 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
 803         OUTREG(TV_DAC_CNTL, reg);
 804
 805         reg  = INREG(TMDS_TRANSMITTER_CNTL);
 806         reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
 807         OUTREG(TMDS_TRANSMITTER_CNTL, reg);
 808
 809         reg = INREG(DAC_CNTL);
 810         reg &= ~DAC_CMP_EN;
 811         OUTREG(DAC_CNTL, reg);
 812
 813         reg = INREG(DAC_CNTL2);
 814         reg &= ~DAC2_CMP_EN;
 815         OUTREG(DAC_CNTL2, reg);
 816
 817         reg  = INREG(TV_DAC_CNTL);
 818         reg &= ~TV_DAC_CNTL_DETECT;
 819         OUTREG(TV_DAC_CNTL, reg);
 820 }
 821
 822 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
 823 {
 824
 825         u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
 826
 827         u32 pll_pwrmgt_cntl;
 828         u32 clk_pwrmgt_cntl;
 829         u32 clk_pin_cntl;
 830         u32 vclk_ecp_cntl;
 831         u32 pixclks_cntl;
 832         u32 disp_mis_cntl;
 833         u32 disp_pwr_man;
 834         u32 tmp;
 835
 836         /* Force Core Clocks */
 837         sclk_cntl = INPLL( pllSCLK_CNTL);
 838         sclk_cntl |=    SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
 839                         SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
 840                         SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
 841                         SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
 842                         SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
 843                         SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
 844                         SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
 845
 846                         SCLK_CNTL__FORCE_DISP2|
 847                         SCLK_CNTL__FORCE_CP|
 848                         SCLK_CNTL__FORCE_HDP|
 849                         SCLK_CNTL__FORCE_DISP1|
 850                         SCLK_CNTL__FORCE_TOP|
 851                         SCLK_CNTL__FORCE_E2|
 852                         SCLK_CNTL__FORCE_SE|
 853                         SCLK_CNTL__FORCE_IDCT|
 854                         SCLK_CNTL__FORCE_VIP|
 855
 856                         SCLK_CNTL__FORCE_PB|
 857                         SCLK_CNTL__FORCE_TAM|
 858                         SCLK_CNTL__FORCE_TDM|
 859                         SCLK_CNTL__FORCE_RB|
 860                         SCLK_CNTL__FORCE_TV_SCLK|
 861                         SCLK_CNTL__FORCE_SUBPIC|
 862                         SCLK_CNTL__FORCE_OV0;
 863         if (rinfo->family <= CHIP_FAMILY_RV280)
 864                 sclk_cntl |= SCLK_CNTL__FORCE_RE;
 865         else
 866                 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
 867                         SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
 868                         SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
 869                         SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
 870                         SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
 871
 872         OUTPLL( pllSCLK_CNTL, sclk_cntl);
 873
 874         sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
 875         sclk_more_cntl |=       SCLK_MORE_CNTL__FORCE_DISPREGS |
 876                                 SCLK_MORE_CNTL__FORCE_MC_GUI |
 877                                 SCLK_MORE_CNTL__FORCE_MC_HOST;
 878
 879         OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
 880
 881
 882         mclk_cntl = INPLL( pllMCLK_CNTL);
 883         mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
 884                         MCLK_CNTL__FORCE_MCLKB |
 885                         MCLK_CNTL__FORCE_YCLKA |
 886                         MCLK_CNTL__FORCE_YCLKB |
 887                         MCLK_CNTL__FORCE_MC
 888                       );
 889         OUTPLL( pllMCLK_CNTL, mclk_cntl);
 890
 891         /* Force Display clocks */
 892         vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
 893         vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
 894                            | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
 895         vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
 896         OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
 897
 898
 899         pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
 900         pixclks_cntl &= ~(      PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
 901                                 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
 902                                 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
 903                                 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
 904                                 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
 905                                 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
 906                                 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
 907
 908         OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
 909
 910         /* Switch off LVDS interface */
 911         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
 912                ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
 913
 914         /* Enable System power management */
 915         pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
 916
 917         pll_pwrmgt_cntl |=      PLL_PWRMGT_CNTL__SPLL_TURNOFF |
 918                                 PLL_PWRMGT_CNTL__MPLL_TURNOFF|
 919                                 PLL_PWRMGT_CNTL__PPLL_TURNOFF|
 920                                 PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
 921                                 PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
 922
 923         OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
 924
 925         clk_pwrmgt_cntl  = INPLL( pllCLK_PWRMGT_CNTL);
 926
 927         clk_pwrmgt_cntl &= ~(   CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
 928                                 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
 929                                 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
 930                                 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
 931                                 CLK_PWRMGT_CNTL__MCLK_TURNOFF|
 932                                 CLK_PWRMGT_CNTL__SCLK_TURNOFF|
 933                                 CLK_PWRMGT_CNTL__PCLK_TURNOFF|
 934                                 CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
 935                                 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
 936                                 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
 937                                 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
 938                                 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
 939                                 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
 940                         );
 941
 942         clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
 943                 | CLK_PWRMGT_CNTL__DISP_PM;
 944
 945         OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
 946
 947         clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
 948
 949         clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
 950
 951         /* because both INPLL and OUTPLL take the same lock, that's why. */
 952         tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
 953         OUTPLL( pllMCLK_MISC, tmp);
 954
 955         /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
 956          * and radeon chip dependent. Thus we only enable it on Mac for
 957          * now (until we get more info on how to compute the correct
 958          * value for various X86 bridges).
 959          */
 960 #ifdef CONFIG_PPC_PMAC
 961         if (machine_is(powermac)) {
 962                 /* AGP PLL control */
 963                 if (rinfo->family <= CHIP_FAMILY_RV280) {
 964                         OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) |  BUS_CNTL1__AGPCLK_VALID);
 965                         OUTREG(BUS_CNTL1,
 966                                (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
 967                                | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT));   // 440BX
 968                 } else {
 969                         OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
 970                         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
 971                 }
 972         }
 973 #endif
 974
 975         OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
 976                                   & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
 977
 978         clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
 979         clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
 980         OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
 981
 982         /* Solano2M */
 983         OUTREG(AGP_CNTL,
 984                 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
 985                 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
 986
 987         /* ACPI mode */
 988         /* because both INPLL and OUTPLL take the same lock, that's why. */
 989         tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
 990         OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
 991
 992
 993         disp_mis_cntl = INREG(DISP_MISC_CNTL);
 994
 995         disp_mis_cntl &= ~(     DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
 996                                 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
 997                                 DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
 998                                 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
 999                                 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
1000                                 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
1001                                 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
1002                                 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
1003                                 DISP_MISC_CNTL__SOFT_RESET_LVDS|
1004                                 DISP_MISC_CNTL__SOFT_RESET_TMDS|
1005                                 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
1006                                 DISP_MISC_CNTL__SOFT_RESET_TV);
1007
1008         OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
1009
1010         disp_pwr_man = INREG(DISP_PWR_MAN);
1011
1012         disp_pwr_man &= ~(      DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN   |
1013                                 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
1014                                 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
1015                                 DISP_PWR_MAN__DISP_D3_RST|
1016                                 DISP_PWR_MAN__DISP_D3_REG_RST
1017                                 );
1018
1019         disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
1020                                         DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
1021                                         DISP_PWR_MAN__DISP_D3_OV0_RST|
1022                                         DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
1023                                         DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
1024                                         DISP_PWR_MAN__DISP_D1D2_OV0_RST|
1025                                         DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
1026                                         DISP_PWR_MAN__TV_ENABLE_RST|
1027 //                                      DISP_PWR_MAN__AUTO_PWRUP_EN|
1028                                         0;
1029
1030         OUTREG(DISP_PWR_MAN, disp_pwr_man);
1031
1032         clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
1033         pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
1034         clk_pin_cntl    = INPLL( pllCLK_PIN_CNTL);
1035         disp_pwr_man    = INREG(DISP_PWR_MAN);
1036
1037
1038         /* D2 */
1039         clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
1040         pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
1041         clk_pin_cntl    |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
1042         disp_pwr_man    &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
1043                              | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
1044
1045         OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
1046         OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
1047         OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
1048         OUTREG(DISP_PWR_MAN, disp_pwr_man);
1049
1050         /* disable display request & disable display */
1051         OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
1052                 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1053         OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
1054                 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1055
1056         mdelay(17);
1057
1058 }
1059
1060 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1061 {
1062         u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1063
1064         mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1065                 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1066         mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1067                 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1068
1069         OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1070                | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1071         OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1072                | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1073
1074         OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1075         OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1076
1077         mdelay( 1);
1078 }
1079
1080 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1081 {
1082         u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
1083
1084         mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1085                 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
1086         mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1087                 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
1088
1089         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1090                mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
1091         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1092                mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
1093
1094         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1095         OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1096
1097         mdelay( 1);
1098 }
1099
1100 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1101                                        u8 delay_required)
1102 {
1103         u32 mem_sdram_mode;
1104
1105         mem_sdram_mode  = INREG( MEM_SDRAM_MODE_REG);
1106
1107         mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
1108         mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
1109                 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
1110         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1111         if (delay_required >= 2)
1112                 mdelay(1);
1113
1114         mem_sdram_mode |=  MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1115         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1116         if (delay_required >= 2)
1117                 mdelay(1);
1118
1119         mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
1120         OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
1121         if (delay_required >= 2)
1122                 mdelay(1);
1123
1124         if (delay_required) {
1125                 do {
1126                         if (delay_required >= 2)
1127                                 mdelay(1);
1128                 } while ((INREG(MC_STATUS)
1129                           & (MC_STATUS__MEM_PWRUP_COMPL_A |
1130                              MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
1131         }
1132 }
1133
1134 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1135 {
1136         int cnt;
1137
1138         for (cnt = 0; cnt < 100; ++cnt) {
1139                 mdelay(1);
1140                 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
1141                                         | MC_STATUS__MEM_PWRUP_COMPL_B))
1142                         break;
1143         }
1144 }
1145
1146
1147 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1148 {
1149 #define DLL_RESET_DELAY         5
1150 #define DLL_SLEEP_DELAY         1
1151
1152         u32 cko = INPLL(pllMDLL_CKO)   | MDLL_CKO__MCKOA_SLEEP
1153                 | MDLL_CKO__MCKOA_RESET;
1154         u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
1155                 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
1156                 | MDLL_RDCKA__MRDCKA1_RESET;
1157         u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
1158                 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
1159                 | MDLL_RDCKB__MRDCKB1_RESET;
1160
1161         /* Setting up the DLL range for write */
1162         OUTPLL(pllMDLL_CKO,     cko);
1163         OUTPLL(pllMDLL_RDCKA,   cka);
1164         OUTPLL(pllMDLL_RDCKB,   ckb);
1165
1166         mdelay(DLL_RESET_DELAY*2);
1167
1168         cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
1169         OUTPLL(pllMDLL_CKO, cko);
1170         mdelay(DLL_SLEEP_DELAY);
1171         cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
1172         OUTPLL(pllMDLL_CKO, cko);
1173         mdelay(DLL_RESET_DELAY);
1174
1175         cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
1176         OUTPLL(pllMDLL_RDCKA, cka);
1177         mdelay(DLL_SLEEP_DELAY);
1178         cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
1179         OUTPLL(pllMDLL_RDCKA, cka);
1180         mdelay(DLL_RESET_DELAY);
1181
1182         ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
1183         OUTPLL(pllMDLL_RDCKB, ckb);
1184         mdelay(DLL_SLEEP_DELAY);
1185         ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
1186         OUTPLL(pllMDLL_RDCKB, ckb);
1187         mdelay(DLL_RESET_DELAY);
1188
1189
1190 #undef DLL_RESET_DELAY
1191 #undef DLL_SLEEP_DELAY
1192 }
1193
1194 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1195 {
1196         u32 dll_value;
1197         u32 dll_sleep_mask = 0;
1198         u32 dll_reset_mask = 0;
1199         u32 mc;
1200
1201 #define DLL_RESET_DELAY         5
1202 #define DLL_SLEEP_DELAY         1
1203
1204         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1205         mc = INREG(MC_CNTL);
1206         /* Check which channels are enabled */
1207         switch (mc & 0x3) {
1208         case 1:
1209                 if (mc & 0x4)
1210                         break;
1211         case 2:
1212                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
1213                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
1214         case 0:
1215                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
1216                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
1217         }
1218         switch (mc & 0x3) {
1219         case 1:
1220                 if (!(mc & 0x4))
1221                         break;
1222         case 2:
1223                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
1224                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
1225                 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
1226                 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
1227         }
1228
1229         dll_value = INPLL(pllMDLL_RDCKA);
1230
1231         /* Power Up */
1232         dll_value &= ~(dll_sleep_mask);
1233         OUTPLL(pllMDLL_RDCKA, dll_value);
1234         mdelay( DLL_SLEEP_DELAY);
1235
1236         dll_value &= ~(dll_reset_mask);
1237         OUTPLL(pllMDLL_RDCKA, dll_value);
1238         mdelay( DLL_RESET_DELAY);
1239
1240 #undef DLL_RESET_DELAY
1241 #undef DLL_SLEEP_DELAY
1242 }
1243
1244
1245 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1246 {
1247         u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
1248                 fp_gen_cntl, fp2_gen_cntl;
1249
1250         crtcGenCntl  = INREG( CRTC_GEN_CNTL);
1251         crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
1252
1253         crtc_more_cntl  = INREG( CRTC_MORE_CNTL);
1254         fp_gen_cntl     = INREG( FP_GEN_CNTL);
1255         fp2_gen_cntl    = INREG( FP2_GEN_CNTL);
1256
1257
1258         OUTREG( CRTC_MORE_CNTL, 0);
1259         OUTREG( FP_GEN_CNTL, 0);
1260         OUTREG( FP2_GEN_CNTL,0);
1261
1262         OUTREG( CRTC_GEN_CNTL,  (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
1263         OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
1264
1265         /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
1266         if (rinfo->family == CHIP_FAMILY_RV350) {
1267                 u32 sdram_mode_reg = rinfo->save_regs[35];
1268                 static const u32 default_mrtable[] =
1269                         { 0x21320032,
1270                           0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1271                           0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1272                           0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1273                           0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1274                           0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1275                           0x31320032 };
1276
1277                 const u32 *mrtable = default_mrtable;
1278                 int i, mrtable_size = ARRAY_SIZE(default_mrtable);
1279
1280                 mdelay(30);
1281
1282                 /* Disable refresh */
1283                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1284                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1285                 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1286                         | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1287
1288                 /* Configure and enable M & SPLLs */
1289                 radeon_pm_enable_dll_m10(rinfo);
1290                 radeon_pm_yclk_mclk_sync_m10(rinfo);
1291
1292 #ifdef CONFIG_PPC_OF
1293                 if (rinfo->of_node != NULL) {
1294                         int size;
1295
1296                         mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
1297                         if (mrtable)
1298                                 mrtable_size = size >> 2;
1299                         else
1300                                 mrtable = default_mrtable;
1301                 }
1302 #endif /* CONFIG_PPC_OF */
1303
1304                 /* Program the SDRAM */
1305                 sdram_mode_reg = mrtable[0];
1306                 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1307                 for (i = 0; i < mrtable_size; i++) {
1308                         if (mrtable[i] == 0xffffffffu)
1309                                 radeon_pm_m10_program_mode_wait(rinfo);
1310                         else {
1311                                 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1312                                                     | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1313                                                     | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
1314                                 sdram_mode_reg |= mrtable[i];
1315
1316                                 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
1317                                 mdelay(1);
1318                         }
1319                 }
1320
1321                 /* Restore memory refresh */
1322                 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
1323                 mdelay(30);
1324
1325         }
1326         /* Here come the desktop RV200 "QW" card */
1327         else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1328                 /* Disable refresh */
1329                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1330                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1331                 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
1332                        | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1333                 mdelay(30);
1334
1335                 /* Reset memory */
1336                 OUTREG(MEM_SDRAM_MODE_REG,
1337                        INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1338
1339                 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1340                 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1341                 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1342
1343                 OUTREG(MEM_SDRAM_MODE_REG,
1344                        INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1345
1346                 OUTREG( MEM_REFRESH_CNTL,       memRefreshCntl);
1347
1348         }
1349         /* The M6 */
1350         else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1351                 /* Disable refresh */
1352                 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
1353                 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
1354
1355                 /* Reset memory */
1356                 OUTREG( MEM_SDRAM_MODE_REG,
1357                         INREG( MEM_SDRAM_MODE_REG)
1358                         & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1359
1360                 /* DLL */
1361                 radeon_pm_enable_dll(rinfo);
1362
1363                 /* MLCK / YCLK sync */
1364                 radeon_pm_yclk_mclk_sync(rinfo);
1365
1366                 /* Program Mode Register */
1367                 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1368                 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1369                 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1370                 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1371                 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1372
1373                 /* Complete & re-enable refresh */
1374                 OUTREG( MEM_SDRAM_MODE_REG,
1375                         INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1376
1377                 OUTREG(EXT_MEM_CNTL, memRefreshCntl);
1378         }
1379         /* And finally, the M7..M9 models, including M9+ (RV280) */
1380         else if (rinfo->is_mobility) {
1381
1382                 /* Disable refresh */
1383                 memRefreshCntl  = INREG( MEM_REFRESH_CNTL)
1384                         & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
1385                 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
1386                         | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1387
1388                 /* Reset memory */
1389                 OUTREG( MEM_SDRAM_MODE_REG,
1390                         INREG( MEM_SDRAM_MODE_REG)
1391                         & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1392
1393                 /* DLL */
1394                 radeon_pm_enable_dll(rinfo);
1395
1396                 /* MLCK / YCLK sync */
1397                 radeon_pm_yclk_mclk_sync(rinfo);
1398
1399                 /* M6, M7 and M9 so far ... */
1400                 if (rinfo->family <= CHIP_FAMILY_RV250) {
1401                         radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1402                         radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1403                         radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1404                         radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1405                         radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1406                 }
1407                 /* M9+ (iBook G4) */
1408                 else if (rinfo->family == CHIP_FAMILY_RV280) {
1409                         radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1410                         radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1411                         radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1412                 }
1413
1414                 /* Complete & re-enable refresh */
1415                 OUTREG( MEM_SDRAM_MODE_REG,
1416                         INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1417
1418                 OUTREG( MEM_REFRESH_CNTL,       memRefreshCntl);
1419         }
1420
1421         OUTREG( CRTC_GEN_CNTL,          crtcGenCntl);
1422         OUTREG( CRTC2_GEN_CNTL,         crtcGenCntl2);
1423         OUTREG( FP_GEN_CNTL,            fp_gen_cntl);
1424         OUTREG( FP2_GEN_CNTL,           fp2_gen_cntl);
1425
1426         OUTREG( CRTC_MORE_CNTL,         crtc_more_cntl);
1427
1428         mdelay( 15);
1429 }
1430
1431 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1432 {
1433         u32 tmp, tmp2;
1434         int i,j;
1435
1436         /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1437         INREG(PAD_CTLR_STRENGTH);
1438         OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
1439         tmp = INREG(PAD_CTLR_STRENGTH);
1440         for (i = j = 0; i < 65; ++i) {
1441                 mdelay(1);
1442                 tmp2 = INREG(PAD_CTLR_STRENGTH);
1443                 if (tmp != tmp2) {
1444                         tmp = tmp2;
1445                         i = 0;
1446                         j++;
1447                         if (j > 10) {
1448                                 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
1449                                        "stabilize !\n");
1450                                 break;
1451                         }
1452                 }
1453         }
1454 }
1455
1456 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1457 {
1458         u32 tmp;
1459
1460         tmp = INPLL(pllPPLL_CNTL);
1461         OUTPLL(pllPPLL_CNTL, tmp | 0x3);
1462         tmp = INPLL(pllP2PLL_CNTL);
1463         OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
1464         tmp = INPLL(pllSPLL_CNTL);
1465         OUTPLL(pllSPLL_CNTL, tmp | 0x3);
1466         tmp = INPLL(pllMPLL_CNTL);
1467         OUTPLL(pllMPLL_CNTL, tmp | 0x3);
1468 }
1469
1470 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1471 {
1472         u32 tmp;
1473
1474         /* Switch SPLL to PCI source */
1475         tmp = INPLL(pllSCLK_CNTL);
1476         OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
1477
1478         /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1479         tmp = INPLL(pllSPLL_CNTL);
1480         OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1481         radeon_pll_errata_after_index(rinfo);
1482         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1483         radeon_pll_errata_after_data(rinfo);
1484
1485         /* Set SPLL feedback divider */
1486         tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1487         tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1488         OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1489
1490         /* Power up SPLL */
1491         tmp = INPLL(pllSPLL_CNTL);
1492         OUTPLL(pllSPLL_CNTL, tmp & ~1);
1493         (void)INPLL(pllSPLL_CNTL);
1494
1495         mdelay(10);
1496
1497         /* Release SPLL reset */
1498         tmp = INPLL(pllSPLL_CNTL);
1499         OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
1500         (void)INPLL(pllSPLL_CNTL);
1501
1502         mdelay(10);
1503
1504         /* Select SCLK source  */
1505         tmp = INPLL(pllSCLK_CNTL);
1506         tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
1507         tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1508         OUTPLL(pllSCLK_CNTL, tmp);
1509         (void)INPLL(pllSCLK_CNTL);
1510
1511         mdelay(10);
1512
1513         /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1514         tmp = INPLL(pllMPLL_CNTL);
1515         OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
1516         radeon_pll_errata_after_index(rinfo);
1517         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1518         radeon_pll_errata_after_data(rinfo);
1519
1520         /* Set MPLL feedback divider */
1521         tmp = INPLL(pllM_SPLL_REF_FB_DIV);
1522         tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1523
1524         OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
1525         /* Power up MPLL */
1526         tmp = INPLL(pllMPLL_CNTL);
1527         OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
1528         (void)INPLL(pllMPLL_CNTL);
1529
1530         mdelay(10);
1531
1532         /* Un-reset MPLL */
1533         tmp = INPLL(pllMPLL_CNTL);
1534         OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
1535         (void)INPLL(pllMPLL_CNTL);
1536
1537         mdelay(10);
1538
1539         /* Select source for MCLK */
1540         tmp = INPLL(pllMCLK_CNTL);
1541         tmp |= rinfo->save_regs[2] & 0xffff;
1542         OUTPLL(pllMCLK_CNTL, tmp);
1543         (void)INPLL(pllMCLK_CNTL);
1544
1545         mdelay(10);
1546 }
1547
1548 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1549 {
1550         u32 r2ec;
1551
1552         /* GACK ! I though we didn't have a DDA on Radeon's anymore
1553          * here we rewrite with the same value, ... I suppose we clear
1554          * some bits that are already clear ? Or maybe this 0x2ec
1555          * register is something new ?
1556          */
1557         mdelay(20);
1558         r2ec = INREG(VGA_DDA_ON_OFF);
1559         OUTREG(VGA_DDA_ON_OFF, r2ec);
1560         mdelay(1);
1561
1562         /* Spread spectrum PLLL off */
1563         OUTPLL(pllSSPLL_CNTL, 0xbf03);
1564
1565         /* Spread spectrum disabled */
1566         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1567
1568         /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1569          * value, not sure what for...
1570          */
1571
1572         r2ec |= 0x3f0;
1573         OUTREG(VGA_DDA_ON_OFF, r2ec);
1574         mdelay(1);
1575 }
1576
1577 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1578 {
1579         u32 r2ec, tmp;
1580
1581         /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1582          * here we rewrite with the same value, ... I suppose we clear/set
1583          * some bits that are already clear/set ?
1584          */
1585         r2ec = INREG(VGA_DDA_ON_OFF);
1586         OUTREG(VGA_DDA_ON_OFF, r2ec);
1587         mdelay(1);
1588
1589         /* Enable spread spectrum */
1590         OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1591         mdelay(3);
1592
1593         OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1594         OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1595         tmp = INPLL(pllSSPLL_CNTL);
1596         OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
1597         mdelay(6);
1598         tmp = INPLL(pllSSPLL_CNTL);
1599         OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
1600         mdelay(5);
1601
1602         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1603
1604         r2ec |= 8;
1605         OUTREG(VGA_DDA_ON_OFF, r2ec);
1606         mdelay(20);
1607
1608         /* Enable LVDS interface */
1609         tmp = INREG(LVDS_GEN_CNTL);
1610         OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
1611
1612         /* Enable LVDS_PLL */
1613         tmp = INREG(LVDS_PLL_CNTL);
1614         tmp &= ~0x30000;
1615         tmp |= 0x10000;
1616         OUTREG(LVDS_PLL_CNTL, tmp);
1617
1618         OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1619         OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1620
1621         /* The trace reads that one here, waiting for something to settle down ? */
1622         INREG(RBBM_STATUS);
1623
1624         /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1625          * R300 register spec at least...
1626          */
1627         tmp = INPLL(pllSS_TST_CNTL);
1628         tmp |= 0x00400000;
1629         OUTPLL(pllSS_TST_CNTL, tmp);
1630 }
1631
1632 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1633 {
1634         u32 tmp;
1635
1636         OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
1637         radeon_pll_errata_after_index(rinfo);
1638         OUTREG8(CLOCK_CNTL_DATA, 0);
1639         radeon_pll_errata_after_data(rinfo);
1640
1641         tmp = INPLL(pllVCLK_ECP_CNTL);
1642         OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
1643         mdelay(5);
1644
1645         tmp = INPLL(pllPPLL_REF_DIV);
1646         tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1647         OUTPLL(pllPPLL_REF_DIV, tmp);
1648         INPLL(pllPPLL_REF_DIV);
1649
1650         /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1651          * probably useless since we already did it ...
1652          */
1653         tmp = INPLL(pllPPLL_CNTL);
1654         OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
1655         radeon_pll_errata_after_index(rinfo);
1656         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
1657         radeon_pll_errata_after_data(rinfo);
1658
1659         /* Restore our "reference" PPLL divider set by firmware
1660          * according to proper spread spectrum calculations
1661          */
1662         OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1663
1664         tmp = INPLL(pllPPLL_CNTL);
1665         OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
1666         mdelay(5);
1667
1668         tmp = INPLL(pllPPLL_CNTL);
1669         OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
1670         mdelay(5);
1671
1672         tmp = INPLL(pllVCLK_ECP_CNTL);
1673         OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1674         mdelay(5);
1675
1676         tmp = INPLL(pllVCLK_ECP_CNTL);
1677         OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
1678         mdelay(5);
1679
1680         /* Switch pixel clock to firmware default div 0 */
1681         OUTREG8(CLOCK_CNTL_INDEX+1, 0);
1682         radeon_pll_errata_after_index(rinfo);
1683         radeon_pll_errata_after_data(rinfo);
1684 }
1685
1686 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1687 {
1688         OUTREG(MC_CNTL, rinfo->save_regs[46]);
1689         OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1690         OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1691         OUTREG(MEM_SDRAM_MODE_REG,
1692                rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1693         OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1694         OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1695         OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1696         OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1697         OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1698         OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1699
1700         OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1701         OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1702         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1703         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1704         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1705         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1706         OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1707         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1708         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1709         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1710         OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1711         OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1712         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1713         OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1714         OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1715         OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1716         OUTREG(MC_IND_INDEX, 0);
1717 }
1718
1719 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1720 {
1721         u32 tmp, i;
1722
1723         /* Restore a bunch of registers first */
1724         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1725         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1726         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1727         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1728         OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1729         OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1730         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1731         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1732         OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1733         OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1734         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1735         OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1736         OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1737         OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
1738
1739         /* Hrm... */
1740         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1741
1742         /* Reset the PAD CTLR */
1743         radeon_pm_reset_pad_ctlr_strength(rinfo);
1744
1745         /* Some PLLs are Read & written identically in the trace here...
1746          * I suppose it's actually to switch them all off & reset,
1747          * let's assume off is what we want. I'm just doing that for all major PLLs now.
1748          */
1749         radeon_pm_all_ppls_off(rinfo);
1750
1751         /* Clear tiling, reset swappers */
1752         INREG(SURFACE_CNTL);
1753         OUTREG(SURFACE_CNTL, 0);
1754
1755         /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1756          * rather than hard coding...
1757          */
1758         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
1759         tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
1760         OUTREG(TV_DAC_CNTL, tmp);
1761
1762         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
1763         tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
1764         OUTREG(TV_DAC_CNTL, tmp);
1765
1766         /* More registers restored */
1767         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1768         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1769         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1770
1771         /* Hrmmm ... What is that ? */
1772         tmp = rinfo->save_regs[1]
1773                 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
1774                     CLK_PWRMGT_CNTL__MC_BUSY);
1775         OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
1776
1777         OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1778         OUTREG(FW_CNTL, rinfo->save_regs[57]);
1779         OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1780         OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1781         OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1782         OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1783
1784         /* Restore Memory Controller configuration */
1785         radeon_pm_m10_reconfigure_mc(rinfo);
1786
1787         /* Make sure CRTC's dont touch memory */
1788         OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
1789                | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
1790         OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
1791                | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
1792         mdelay(30);
1793
1794         /* Disable SDRAM refresh */
1795         OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
1796                | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
1797
1798         /* Restore XTALIN routing (CLK_PIN_CNTL) */
1799         OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1800
1801         /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1802         tmp = rinfo->save_regs[2] & 0xff000000;
1803         tmp |=  MCLK_CNTL__FORCE_MCLKA |
1804                 MCLK_CNTL__FORCE_MCLKB |
1805                 MCLK_CNTL__FORCE_YCLKA |
1806                 MCLK_CNTL__FORCE_YCLKB |
1807                 MCLK_CNTL__FORCE_MC;
1808         OUTPLL(pllMCLK_CNTL, tmp);
1809
1810         /* Force all clocks on in SCLK */
1811         tmp = INPLL(pllSCLK_CNTL);
1812         tmp |=  SCLK_CNTL__FORCE_DISP2|
1813                 SCLK_CNTL__FORCE_CP|
1814                 SCLK_CNTL__FORCE_HDP|
1815                 SCLK_CNTL__FORCE_DISP1|
1816                 SCLK_CNTL__FORCE_TOP|
1817                 SCLK_CNTL__FORCE_E2|
1818                 SCLK_CNTL__FORCE_SE|
1819                 SCLK_CNTL__FORCE_IDCT|
1820                 SCLK_CNTL__FORCE_VIP|
1821                 SCLK_CNTL__FORCE_PB|
1822                 SCLK_CNTL__FORCE_TAM|
1823                 SCLK_CNTL__FORCE_TDM|
1824                 SCLK_CNTL__FORCE_RB|
1825                 SCLK_CNTL__FORCE_TV_SCLK|
1826                 SCLK_CNTL__FORCE_SUBPIC|
1827                 SCLK_CNTL__FORCE_OV0;
1828         tmp |=  SCLK_CNTL__CP_MAX_DYN_STOP_LAT  |
1829                 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
1830                 SCLK_CNTL__TV_MAX_DYN_STOP_LAT  |
1831                 SCLK_CNTL__E2_MAX_DYN_STOP_LAT  |
1832                 SCLK_CNTL__SE_MAX_DYN_STOP_LAT  |
1833                 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
1834                 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
1835                 SCLK_CNTL__RE_MAX_DYN_STOP_LAT  |
1836                 SCLK_CNTL__PB_MAX_DYN_STOP_LAT  |
1837                 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
1838                 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
1839                 SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
1840         OUTPLL(pllSCLK_CNTL, tmp);
1841
1842         OUTPLL(pllVCLK_ECP_CNTL, 0);
1843         OUTPLL(pllPIXCLKS_CNTL, 0);
1844         OUTPLL(pllMCLK_MISC,
1845                MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
1846                MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
1847
1848         mdelay(5);
1849
1850         /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1851         OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1852         OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1853         OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1854
1855         /* Now restore the major PLLs settings, keeping them off & reset though */
1856         OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1857         OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1858         OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1859         OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1860
1861         /* Restore MC DLL state and switch it off/reset too  */
1862         OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1863
1864         /* Switch MDLL off & reset */
1865         OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1866         mdelay(5);
1867
1868         /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1869          * 0xa1100007... and MacOS writes 0xa1000007 ..
1870          */
1871         OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1872
1873         /* Restore more stuffs */
1874         OUTPLL(pllHTOTAL_CNTL, 0);
1875         OUTPLL(pllHTOTAL2_CNTL, 0);
1876
1877         /* More PLL initial configuration */
1878         tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
1879         OUTPLL(pllSCLK_CNTL2, tmp);
1880
1881         tmp = INPLL(pllSCLK_MORE_CNTL);
1882         tmp |=  SCLK_MORE_CNTL__FORCE_DISPREGS |        /* a guess */
1883                 SCLK_MORE_CNTL__FORCE_MC_GUI |
1884                 SCLK_MORE_CNTL__FORCE_MC_HOST;
1885         OUTPLL(pllSCLK_MORE_CNTL, tmp);
1886
1887         /* Now we actually start MCLK and SCLK */
1888         radeon_pm_start_mclk_sclk(rinfo);
1889
1890         /* Full reset sdrams, this also re-inits the MDLL */
1891         radeon_pm_full_reset_sdram(rinfo);
1892
1893         /* Fill palettes */
1894         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
1895         for (i=0; i<256; i++)
1896                 OUTREG(PALETTE_30_DATA, 0x15555555);
1897         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
1898         udelay(20);
1899         for (i=0; i<256; i++)
1900                 OUTREG(PALETTE_30_DATA, 0x15555555);
1901
1902         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
1903         mdelay(3);
1904
1905         /* Restore TMDS */
1906         OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1907         OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1908
1909         /* Set LVDS registers but keep interface & pll down */
1910         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1911                ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
1912         OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1913
1914         OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1915
1916         /* Restore GPIOPAD state */
1917         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1918         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1919         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1920
1921         /* write some stuff to the framebuffer... */
1922         for (i = 0; i < 0x8000; ++i)
1923                 writeb(0, rinfo->fb_base + i);
1924
1925         mdelay(40);
1926         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
1927         mdelay(40);
1928
1929         /* Restore a few more things */
1930         OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1931         OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1932
1933         /* Take care of spread spectrum & PPLLs now */
1934         radeon_pm_m10_disable_spread_spectrum(rinfo);
1935         radeon_pm_restore_pixel_pll(rinfo);
1936
1937         /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1938          * code I have for blank/unblank doesn't quite work on some laptop models
1939          * it seems ... Hrm. What I have here works most of the time ...
1940          */
1941         radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1942 }
1943
1944 #ifdef CONFIG_PPC_OF
1945
1946 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1947 {
1948         OUTREG(MC_CNTL, rinfo->save_regs[46]);
1949         OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1950         OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1951         OUTREG(MEM_SDRAM_MODE_REG,
1952                rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1953         OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1954         OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1955         OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1956         OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1957         OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1958         OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1959
1960         OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1961         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1962         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1963         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1964         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1965         OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1966         OUTREG(MC_IND_INDEX, 0);
1967         OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1968
1969         mdelay(20);
1970 }
1971
1972 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1973 {
1974         u32 tmp, i;
1975
1976         /* Restore a bunch of registers first */
1977         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1978         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1979         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1980         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1981         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1982         OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1983         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1984         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1985         OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1986         OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1987         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1988
1989         OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1990         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
1991
1992         /* Reset the PAD CTLR */
1993         radeon_pm_reset_pad_ctlr_strength(rinfo);
1994
1995         /* Some PLLs are Read & written identically in the trace here...
1996          * I suppose it's actually to switch them all off & reset,
1997          * let's assume off is what we want. I'm just doing that for all major PLLs now.
1998          */
1999         radeon_pm_all_ppls_off(rinfo);
2000
2001         /* Clear tiling, reset swappers */
2002         INREG(SURFACE_CNTL);
2003         OUTREG(SURFACE_CNTL, 0);
2004
2005         /* Some black magic with TV_DAC_CNTL, we should restore those from backups
2006          * rather than hard coding...
2007          */
2008         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
2009         tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
2010         OUTREG(TV_DAC_CNTL, tmp);
2011
2012         tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
2013         tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
2014         OUTREG(TV_DAC_CNTL, tmp);
2015
2016         OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2017
2018         OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2019         OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2020         OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2021
2022         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2023         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2024         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2025
2026         tmp  = rinfo->save_regs[1]
2027                 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
2028                     CLK_PWRMGT_CNTL__MC_BUSY);
2029         OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
2030
2031         OUTREG(FW_CNTL, rinfo->save_regs[57]);
2032
2033         /* Disable SDRAM refresh */
2034         OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
2035                | MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
2036
2037         /* Restore XTALIN routing (CLK_PIN_CNTL) */
2038         OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2039
2040         /* Force MCLK to be PCI sourced and forced ON */
2041         tmp = rinfo->save_regs[2] & 0xff000000;
2042         tmp |=  MCLK_CNTL__FORCE_MCLKA |
2043                 MCLK_CNTL__FORCE_MCLKB |
2044                 MCLK_CNTL__FORCE_YCLKA |
2045                 MCLK_CNTL__FORCE_YCLKB |
2046                 MCLK_CNTL__FORCE_MC    |
2047                 MCLK_CNTL__FORCE_AIC;
2048         OUTPLL(pllMCLK_CNTL, tmp);
2049
2050         /* Force SCLK to be PCI sourced with a bunch forced */
2051         tmp =   0 |
2052                 SCLK_CNTL__FORCE_DISP2|
2053                 SCLK_CNTL__FORCE_CP|
2054                 SCLK_CNTL__FORCE_HDP|
2055                 SCLK_CNTL__FORCE_DISP1|
2056                 SCLK_CNTL__FORCE_TOP|
2057                 SCLK_CNTL__FORCE_E2|
2058                 SCLK_CNTL__FORCE_SE|
2059                 SCLK_CNTL__FORCE_IDCT|
2060                 SCLK_CNTL__FORCE_VIP|
2061                 SCLK_CNTL__FORCE_RE|
2062                 SCLK_CNTL__FORCE_PB|
2063                 SCLK_CNTL__FORCE_TAM|
2064                 SCLK_CNTL__FORCE_TDM|
2065                 SCLK_CNTL__FORCE_RB;
2066         OUTPLL(pllSCLK_CNTL, tmp);
2067
2068         /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL  */
2069         OUTPLL(pllVCLK_ECP_CNTL, 0);
2070         OUTPLL(pllPIXCLKS_CNTL, 0);
2071
2072         /* Setup MCLK_MISC, non dynamic mode */
2073         OUTPLL(pllMCLK_MISC,
2074                MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
2075                MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
2076
2077         mdelay(5);
2078
2079         /* Set back the default clock dividers */
2080         OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2081         OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2082         OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2083
2084         /* PPLL and P2PLL default values & off */
2085         OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2086         OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2087
2088         /* S and M PLLs are reset & off, configure them */
2089         OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2090         OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2091
2092         /* Default values for MDLL ... fixme */
2093         OUTPLL(pllMDLL_CKO, 0x9c009c);
2094         OUTPLL(pllMDLL_RDCKA, 0x08830883);
2095         OUTPLL(pllMDLL_RDCKB, 0x08830883);
2096         mdelay(5);
2097
2098         /* Restore PLL_PWRMGT_CNTL */ // XXXX
2099         tmp = rinfo->save_regs[0];
2100         tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
2101         tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2102         OUTPLL(PLL_PWRMGT_CNTL,  tmp);
2103
2104         /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
2105         OUTPLL(pllHTOTAL_CNTL, 0);
2106         OUTPLL(pllHTOTAL2_CNTL, 0);
2107
2108         /* All outputs off */
2109         OUTREG(CRTC_GEN_CNTL, 0x04000000);
2110         OUTREG(CRTC2_GEN_CNTL, 0x04000000);
2111         OUTREG(FP_GEN_CNTL, 0x00004008);
2112         OUTREG(FP2_GEN_CNTL, 0x00000008);
2113         OUTREG(LVDS_GEN_CNTL, 0x08000008);
2114
2115         /* Restore Memory Controller configuration */
2116         radeon_pm_m9p_reconfigure_mc(rinfo);
2117
2118         /* Now we actually start MCLK and SCLK */
2119         radeon_pm_start_mclk_sclk(rinfo);
2120
2121         /* Full reset sdrams, this also re-inits the MDLL */
2122         radeon_pm_full_reset_sdram(rinfo);
2123
2124         /* Fill palettes */
2125         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
2126         for (i=0; i<256; i++)
2127                 OUTREG(PALETTE_30_DATA, 0x15555555);
2128         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
2129         udelay(20);
2130         for (i=0; i<256; i++)
2131                 OUTREG(PALETTE_30_DATA, 0x15555555);
2132
2133         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
2134         mdelay(3);
2135
2136         /* Restore TV stuff, make sure TV DAC is down */
2137         OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2138         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2139
2140         /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2141          * possibly related to the weird PLL related workarounds and to the
2142          * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2143          * but we keep things the simple way here
2144          */
2145         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2146         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2147         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2148
2149         /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2150          * high bits from backup
2151          */
2152         tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2153         tmp |= rinfo->save_regs[34] & 0xffff0000;
2154         tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2155         OUTPLL(pllSCLK_MORE_CNTL, tmp);
2156
2157         tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
2158         tmp |= rinfo->save_regs[34] & 0xffff0000;
2159         tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
2160         OUTPLL(pllSCLK_MORE_CNTL, tmp);
2161
2162         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2163                ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
2164         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
2165         OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2166         mdelay(20);
2167
2168         /* write some stuff to the framebuffer... */
2169         for (i = 0; i < 0x8000; ++i)
2170                 writeb(0, rinfo->fb_base + i);
2171
2172         OUTREG(0x2ec, 0x6332a020);
2173         OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2174         OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2175         tmp = INPLL(pllSSPLL_CNTL);
2176         tmp &= ~2;
2177         OUTPLL(pllSSPLL_CNTL, tmp);
2178         mdelay(6);
2179         tmp &= ~1;
2180         OUTPLL(pllSSPLL_CNTL, tmp);
2181         mdelay(5);
2182         tmp |= 3;
2183         OUTPLL(pllSSPLL_CNTL, tmp);
2184         mdelay(5);
2185
2186         OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2187         OUTREG(0x2ec, 0x6332a3f0);
2188         mdelay(17);
2189
2190         OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2191         OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2192
2193         mdelay(40);
2194         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
2195         mdelay(40);
2196
2197         /* Restore a few more things */
2198         OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2199         OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2200
2201         /* Restore PPLL, spread spectrum & LVDS */
2202         radeon_pm_m10_disable_spread_spectrum(rinfo);
2203         radeon_pm_restore_pixel_pll(rinfo);
2204         radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2205 }
2206
2207 #if 0 /* Not ready yet */
2208 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2209 {
2210         int i;
2211         u32 tmp, tmp2;
2212         u32 cko, cka, ckb;
2213         u32 cgc, cec, c2gc;
2214
2215         OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2216         OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2217         OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2218         OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2219         OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2220         OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2221
2222         INREG(PAD_CTLR_STRENGTH);
2223         OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2224         for (i = 0; i < 65; ++i) {
2225                 mdelay(1);
2226                 INREG(PAD_CTLR_STRENGTH);
2227         }
2228
2229         OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2230         OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2231         OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2232         OUTREG(DAC_CNTL, 0xff00410a);
2233         OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2234         OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2235
2236         OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2237         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2238         OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2239         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2240
2241         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2242         OUTREG(MC_IND_INDEX, 0);
2243         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2244         OUTREG(MC_IND_INDEX, 0);
2245
2246         OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2247
2248         tmp = INPLL(pllVCLK_ECP_CNTL);
2249         OUTPLL(pllVCLK_ECP_CNTL, tmp);
2250         tmp = INPLL(pllPIXCLKS_CNTL);
2251         OUTPLL(pllPIXCLKS_CNTL, tmp);
2252
2253         OUTPLL(MCLK_CNTL, 0xaa3f0000);
2254         OUTPLL(SCLK_CNTL, 0xffff0000);
2255         OUTPLL(pllMPLL_AUX_CNTL, 6);
2256         OUTPLL(pllSPLL_AUX_CNTL, 1);
2257         OUTPLL(MDLL_CKO, 0x9f009f);
2258         OUTPLL(MDLL_RDCKA, 0x830083);
2259         OUTPLL(pllMDLL_RDCKB, 0x830083);
2260         OUTPLL(PPLL_CNTL, 0xa433);
2261         OUTPLL(P2PLL_CNTL, 0xa433);
2262         OUTPLL(MPLL_CNTL, 0x0400a403);
2263         OUTPLL(SPLL_CNTL, 0x0400a433);
2264
2265         tmp = INPLL(M_SPLL_REF_FB_DIV);
2266         OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2267         tmp = INPLL(M_SPLL_REF_FB_DIV);
2268         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2269         INPLL(M_SPLL_REF_FB_DIV);
2270
2271         tmp = INPLL(MPLL_CNTL);
2272         OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2273         radeon_pll_errata_after_index(rinfo);
2274         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2275         radeon_pll_errata_after_data(rinfo);
2276
2277         tmp = INPLL(M_SPLL_REF_FB_DIV);
2278         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2279
2280         tmp = INPLL(MPLL_CNTL);
2281         OUTPLL(MPLL_CNTL, tmp & ~0x2);
2282         mdelay(1);
2283         tmp = INPLL(MPLL_CNTL);
2284         OUTPLL(MPLL_CNTL, tmp & ~0x1);
2285         mdelay(10);
2286
2287         OUTPLL(MCLK_CNTL, 0xaa3f1212);
2288         mdelay(1);
2289
2290         INPLL(M_SPLL_REF_FB_DIV);
2291         INPLL(MCLK_CNTL);
2292         INPLL(M_SPLL_REF_FB_DIV);
2293
2294         tmp = INPLL(SPLL_CNTL);
2295         OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2296         radeon_pll_errata_after_index(rinfo);
2297         OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
2298         radeon_pll_errata_after_data(rinfo);
2299
2300         tmp = INPLL(M_SPLL_REF_FB_DIV);
2301         OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2302
2303         tmp = INPLL(SPLL_CNTL);
2304         OUTPLL(SPLL_CNTL, tmp & ~0x1);
2305         mdelay(1);
2306         tmp = INPLL(SPLL_CNTL);
2307         OUTPLL(SPLL_CNTL, tmp & ~0x2);
2308         mdelay(10);
2309
2310         tmp = INPLL(SCLK_CNTL);
2311         OUTPLL(SCLK_CNTL, tmp | 2);
2312         mdelay(1);
2313
2314         cko = INPLL(pllMDLL_CKO);
2315         cka = INPLL(pllMDLL_RDCKA);
2316         ckb = INPLL(pllMDLL_RDCKB);
2317
2318         cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
2319         OUTPLL(pllMDLL_CKO, cko);
2320         mdelay(1);
2321         cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
2322         OUTPLL(pllMDLL_CKO, cko);
2323         mdelay(5);
2324
2325         cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
2326         OUTPLL(pllMDLL_RDCKA, cka);
2327         mdelay(1);
2328         cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
2329         OUTPLL(pllMDLL_RDCKA, cka);
2330         mdelay(5);
2331
2332         ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
2333         OUTPLL(pllMDLL_RDCKB, ckb);
2334         mdelay(1);
2335         ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
2336         OUTPLL(pllMDLL_RDCKB, ckb);
2337         mdelay(5);
2338
2339         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2340         OUTREG(MC_IND_INDEX, 0);
2341         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2342         OUTREG(MC_IND_INDEX, 0);
2343         mdelay(1);
2344         OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2345         OUTREG(MC_IND_INDEX, 0);
2346         OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2347         OUTREG(MC_IND_INDEX, 0);
2348         mdelay(1);
2349
2350         OUTPLL(pllHTOTAL_CNTL, 0);
2351         OUTPLL(pllHTOTAL2_CNTL, 0);
2352
2353         OUTREG(MEM_CNTL, 0x29002901);
2354         OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2355         OUTREG(EXT_MEM_CNTL, 0x1a394333);
2356         OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2357         OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2358         OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218);   /* XXX or save_regs[42]? */
2359         OUTREG(MC_DEBUG, 0);
2360         OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2361
2362         OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2363         OUTREG(MC_IND_INDEX, 0);
2364         OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2365         OUTREG(MC_IND_INDEX, 0);
2366
2367         OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2368
2369         radeon_pm_full_reset_sdram(rinfo);
2370
2371         INREG(FP_GEN_CNTL);
2372         OUTREG(TMDS_CNTL, 0x01000000);  /* XXX ? */
2373         tmp = INREG(FP_GEN_CNTL);
2374         tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
2375         OUTREG(FP_GEN_CNTL, tmp);
2376
2377         tmp = INREG(DISP_OUTPUT_CNTL);
2378         tmp &= ~0x400;
2379         OUTREG(DISP_OUTPUT_CNTL, tmp);
2380
2381         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2382         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2383         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2384
2385         tmp = INPLL(MCLK_MISC);
2386         tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
2387         OUTPLL(MCLK_MISC, tmp);
2388
2389         tmp = INPLL(SCLK_CNTL);
2390         OUTPLL(SCLK_CNTL, tmp);
2391
2392         OUTREG(CRTC_MORE_CNTL, 0);
2393         OUTREG8(CRTC_GEN_CNTL+1, 6);
2394         OUTREG8(CRTC_GEN_CNTL+3, 1);
2395         OUTREG(CRTC_PITCH, 32);
2396
2397         tmp = INPLL(VCLK_ECP_CNTL);
2398         OUTPLL(VCLK_ECP_CNTL, tmp);
2399
2400         tmp = INPLL(PPLL_CNTL);
2401         OUTPLL(PPLL_CNTL, tmp);
2402
2403         /* palette stuff and BIOS_1_SCRATCH... */
2404
2405         tmp = INREG(FP_GEN_CNTL);
2406         tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2407         tmp |= 2;
2408         OUTREG(FP_GEN_CNTL, tmp);
2409         mdelay(5);
2410         OUTREG(FP_GEN_CNTL, tmp);
2411         mdelay(5);
2412         OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2413         OUTREG(CRTC_MORE_CNTL, 0);
2414         mdelay(20);
2415
2416         tmp = INREG(CRTC_MORE_CNTL);
2417         OUTREG(CRTC_MORE_CNTL, tmp);
2418
2419         cgc = INREG(CRTC_GEN_CNTL);
2420         cec = INREG(CRTC_EXT_CNTL);
2421         c2gc = INREG(CRTC2_GEN_CNTL);
2422
2423         OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2424         OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2425         OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2426         radeon_pll_errata_after_index(rinfo);
2427         OUTREG8(CLOCK_CNTL_DATA, 0);
2428         radeon_pll_errata_after_data(rinfo);
2429         OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2430         OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2431         OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2432         OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2433         OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2434         OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2435         OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2436         OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2437         OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2438         OUTREG(FP_HORZ_STRETCH, 0);
2439         OUTREG(FP_VERT_STRETCH, 0);
2440         OUTREG(OVR_CLR, 0);
2441         OUTREG(OVR_WID_LEFT_RIGHT, 0);
2442         OUTREG(OVR_WID_TOP_BOTTOM, 0);
2443
2444         tmp = INPLL(PPLL_REF_DIV);
2445         tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2446         OUTPLL(PPLL_REF_DIV, tmp);
2447         INPLL(PPLL_REF_DIV);
2448
2449         OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2450         radeon_pll_errata_after_index(rinfo);
2451         OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
2452         radeon_pll_errata_after_data(rinfo);
2453
2454         tmp = INREG(CLOCK_CNTL_INDEX);
2455         radeon_pll_errata_after_index(rinfo);
2456         OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2457         radeon_pll_errata_after_index(rinfo);
2458         radeon_pll_errata_after_data(rinfo);
2459
2460         OUTPLL(PPLL_DIV_0, 0x48090);
2461
2462         tmp = INPLL(PPLL_CNTL);
2463         OUTPLL(PPLL_CNTL, tmp & ~0x2);
2464         mdelay(1);
2465         tmp = INPLL(PPLL_CNTL);
2466         OUTPLL(PPLL_CNTL, tmp & ~0x1);
2467         mdelay(10);
2468
2469         tmp = INPLL(VCLK_ECP_CNTL);
2470         OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2471         mdelay(1);
2472
2473         tmp = INPLL(VCLK_ECP_CNTL);
2474         OUTPLL(VCLK_ECP_CNTL, tmp);
2475
2476         c2gc |= CRTC2_DISP_REQ_EN_B;
2477         OUTREG(CRTC2_GEN_CNTL, c2gc);
2478         cgc |= CRTC_EN;
2479         OUTREG(CRTC_GEN_CNTL, cgc);
2480         OUTREG(CRTC_EXT_CNTL, cec);
2481         OUTREG(CRTC_PITCH, 0xa0);
2482         OUTREG(CRTC_OFFSET, 0);
2483         OUTREG(CRTC_OFFSET_CNTL, 0);
2484
2485         OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2486         OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2487
2488         tmp2 = INREG(FP_GEN_CNTL);
2489         tmp = INREG(TMDS_TRANSMITTER_CNTL);
2490         OUTREG(0x2a8, 0x0000061b);
2491         tmp |= TMDS_PLL_EN;
2492         OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2493         mdelay(1);
2494         tmp &= ~TMDS_PLLRST;
2495         OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2496         tmp2 &= ~2;
2497         tmp2 |= FP_TMDS_EN;
2498         OUTREG(FP_GEN_CNTL, tmp2);
2499         mdelay(5);
2500         tmp2 |= FP_FPON;
2501         OUTREG(FP_GEN_CNTL, tmp2);
2502
2503         OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2504         cgc = INREG(CRTC_GEN_CNTL);
2505         OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2506         cgc |= 0x10000;
2507         OUTREG(CUR_OFFSET, 0);
2508 }
2509 #endif /* 0 */
2510
2511 #endif /* CONFIG_PPC_OF */
2512
2513 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
2514 {
2515         u16 pwr_cmd;
2516
2517         for (;;) {
2518                 pci_read_config_word(rinfo->pdev,
2519                                      rinfo->pm_reg+PCI_PM_CTRL,
2520                                      &pwr_cmd);
2521                 if (pwr_cmd & 2)
2522                         break;
2523                 pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2;
2524                 pci_write_config_word(rinfo->pdev,
2525                                       rinfo->pm_reg+PCI_PM_CTRL,
2526                                       pwr_cmd);
2527                 msleep(500);
2528         }
2529         rinfo->pdev->current_state = state;
2530 }
2531
2532 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2533 {
2534         u32 tmp;
2535
2536         if (!rinfo->pm_reg)
2537                 return;
2538
2539         /* Set the chip into appropriate suspend mode (we use D2,
2540          * D3 would require a compete re-initialization of the chip,
2541          * including PCI config registers, clocks, AGP conf, ...)
2542          */
2543         if (suspend) {
2544                 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
2545                        pci_name(rinfo->pdev));
2546
2547                 /* Disable dynamic power management of clocks for the
2548                  * duration of the suspend/resume process
2549                  */
2550                 radeon_pm_disable_dynamic_mode(rinfo);
2551
2552                 /* Save some registers */
2553                 radeon_pm_save_regs(rinfo, 0);
2554
2555                 /* Prepare mobility chips for suspend.
2556                  */
2557                 if (rinfo->is_mobility) {
2558                         /* Program V2CLK */
2559                         radeon_pm_program_v2clk(rinfo);
2560
2561                         /* Disable IO PADs */
2562                         radeon_pm_disable_iopad(rinfo);
2563
2564                         /* Set low current */
2565                         radeon_pm_low_current(rinfo);
2566
2567                         /* Prepare chip for power management */
2568                         radeon_pm_setup_for_suspend(rinfo);
2569
2570                         if (rinfo->family <= CHIP_FAMILY_RV280) {
2571                                 /* Reset the MDLL */
2572                                 /* because both INPLL and OUTPLL take the same
2573                                  * lock, that's why. */
2574                                 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
2575                                         | MDLL_CKO__MCKOB_RESET;
2576                                 OUTPLL( pllMDLL_CKO, tmp );
2577                         }
2578                 }
2579
2580                 /* Switch PCI power management to D2. */
2581                 pci_disable_device(rinfo->pdev);
2582                 pci_save_state(rinfo->pdev);
2583                 /* The chip seems to need us to whack the PM register
2584                  * repeatedly until it sticks. We do that -prior- to
2585                  * calling pci_set_power_state()
2586                  */
2587                 radeonfb_whack_power_state(rinfo, PCI_D2);
2588                 __pci_complete_power_transition(rinfo->pdev, PCI_D2);
2589         } else {
2590                 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
2591                        pci_name(rinfo->pdev));
2592
2593                 if (rinfo->family <= CHIP_FAMILY_RV250) {
2594                         /* Reset the SDRAM controller  */
2595                         radeon_pm_full_reset_sdram(rinfo);
2596
2597                         /* Restore some registers */
2598                         radeon_pm_restore_regs(rinfo);
2599                 } else {
2600                         /* Restore registers first */
2601                         radeon_pm_restore_regs(rinfo);
2602                         /* init sdram controller */
2603                         radeon_pm_full_reset_sdram(rinfo);
2604                 }
2605         }
2606 }
2607
2608 int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2609 {
2610         struct fb_info *info = pci_get_drvdata(pdev);
2611         struct radeonfb_info *rinfo = info->par;
2612
2613         if (mesg.event == pdev->dev.power.power_state.event)
2614                 return 0;
2615
2616         printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n",
2617                pci_name(pdev), mesg.event);
2618
2619         /* For suspend-to-disk, we cheat here. We don't suspend anything and
2620          * let fbcon continue drawing until we are all set. That shouldn't
2621          * really cause any problem at this point, provided that the wakeup
2622          * code knows that any state in memory may not match the HW
2623          */
2624         switch (mesg.event) {
2625         case PM_EVENT_FREEZE:           /* about to take snapshot */
2626         case PM_EVENT_PRETHAW:          /* before restoring snapshot */
2627                 goto done;
2628         }
2629
2630         acquire_console_sem();
2631
2632         fb_set_suspend(info, 1);
2633
2634         if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2635                 /* Make sure engine is reset */
2636                 radeon_engine_idle();
2637                 radeonfb_engine_reset(rinfo);
2638                 radeon_engine_idle();
2639         }
2640
2641         /* Blank display and LCD */
2642         radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2643
2644         /* Sleep */
2645         rinfo->asleep = 1;
2646         rinfo->lock_blank = 1;
2647         del_timer_sync(&rinfo->lvds_timer);
2648
2649 #ifdef CONFIG_PPC_PMAC
2650         /* On powermac, we have hooks to properly suspend/resume AGP now,
2651          * use them here. We'll ultimately need some generic support here,
2652          * but the generic code isn't quite ready for that yet
2653          */
2654         pmac_suspend_agp_for_card(pdev);
2655 #endif /* CONFIG_PPC_PMAC */
2656
2657         /* It's unclear whether or when the generic code will do that, so let's
2658          * do it ourselves. We save state before we do any power management
2659          */
2660         pci_save_state(pdev);
2661
2662         /* If we support wakeup from poweroff, we save all regs we can including cfg
2663          * space
2664          */
2665         if (rinfo->pm_mode & radeon_pm_off) {
2666                 /* Always disable dynamic clocks or weird things are happening when
2667                  * the chip goes off (basically the panel doesn't shut down properly
2668                  * and we crash on wakeup),
2669                  * also, we want the saved regs context to have no dynamic clocks in
2670                  * it, we'll restore the dynamic clocks state on wakeup
2671                  */
2672                 radeon_pm_disable_dynamic_mode(rinfo);
2673                 mdelay(50);
2674                 radeon_pm_save_regs(rinfo, 1);
2675
2676                 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2677                         /* Switch off LVDS interface */
2678                         mdelay(1);
2679                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
2680                         mdelay(1);
2681                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
2682                         OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
2683                         mdelay(20);
2684                         OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
2685                 }
2686                 pci_disable_device(pdev);
2687         }
2688         /* If we support D2, we go to it (should be fixed later with a flag forcing
2689          * D3 only for some laptops)
2690          */
2691         if (rinfo->pm_mode & radeon_pm_d2)
2692                 radeon_set_suspend(rinfo, 1);
2693
2694         release_console_sem();
2695
2696  done:
2697         pdev->dev.power.power_state = mesg;
2698
2699         return 0;
2700 }
2701
2702 static int radeon_check_power_loss(struct radeonfb_info *rinfo)
2703 {
2704         return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
2705                rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
2706                rinfo->save_regs[3] != INPLL(SCLK_CNTL);
2707 }
2708
2709 int radeonfb_pci_resume(struct pci_dev *pdev)
2710 {
2711         struct fb_info *info = pci_get_drvdata(pdev);
2712         struct radeonfb_info *rinfo = info->par;
2713         int rc = 0;
2714
2715         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2716                 return 0;
2717
2718         if (rinfo->no_schedule) {
2719                 if (try_acquire_console_sem())
2720                         return 0;
2721         } else
2722                 acquire_console_sem();
2723
2724         printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
2725                pci_name(pdev), pdev->dev.power.power_state.event);
2726
2727         /* PCI state will have been restored by the core, so
2728          * we should be in D0 now with our config space fully
2729          * restored
2730          */
2731         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2732                 /* Wakeup chip */
2733                 if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
2734                         if (rinfo->reinit_func != NULL)
2735                                 rinfo->reinit_func(rinfo);
2736                         else {
2737                                 printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
2738                                        " D3 cold, need softboot !", pci_name(pdev));
2739                                 rc = -EIO;
2740                                 goto bail;
2741                         }
2742                 }
2743                 /* If we support D2, try to resume... we should check what was our
2744                  * state though... (were we really in D2 state ?). Right now, this code
2745                  * is only enable on Macs so it's fine.
2746                  */
2747                 else if (rinfo->pm_mode & radeon_pm_d2)
2748                         radeon_set_suspend(rinfo, 0);
2749
2750                 rinfo->asleep = 0;
2751         } else
2752                 radeon_engine_idle();
2753
2754         /* Restore display & engine */
2755         radeon_write_mode (rinfo, &rinfo->state, 1);
2756         if (!(info->flags & FBINFO_HWACCEL_DISABLED))
2757                 radeonfb_engine_init (rinfo);
2758
2759         fb_pan_display(info, &info->var);
2760         fb_set_cmap(&info->cmap, info);
2761
2762         /* Refresh */
2763         fb_set_suspend(info, 0);
2764
2765         /* Unblank */
2766         rinfo->lock_blank = 0;
2767         radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2768
2769 #ifdef CONFIG_PPC_PMAC
2770         /* On powermac, we have hooks to properly suspend/resume AGP now,
2771          * use them here. We'll ultimately need some generic support here,
2772          * but the generic code isn't quite ready for that yet
2773          */
2774         pmac_resume_agp_for_card(pdev);
2775 #endif /* CONFIG_PPC_PMAC */
2776
2777
2778         /* Check status of dynclk */
2779         if (rinfo->dynclk == 1)
2780                 radeon_pm_enable_dynamic_mode(rinfo);
2781         else if (rinfo->dynclk == 0)
2782                 radeon_pm_disable_dynamic_mode(rinfo);
2783
2784         pdev->dev.power.power_state = PMSG_ON;
2785
2786  bail:
2787         release_console_sem();
2788
2789         return rc;
2790 }
2791
2792 #ifdef CONFIG_PPC_OF__disabled
2793 static void radeonfb_early_resume(void *data)
2794 {
2795         struct radeonfb_info *rinfo = data;
2796
2797         rinfo->no_schedule = 1;
2798         pci_restore_state(rinfo->pdev);
2799         radeonfb_pci_resume(rinfo->pdev);
2800         rinfo->no_schedule = 0;
2801 }
2802 #endif /* CONFIG_PPC_OF */
2803
2804 #endif /* CONFIG_PM */
2805
2806 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2807 {
2808         /* Find PM registers in config space if any*/
2809         rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM);
2810
2811         /* Enable/Disable dynamic clocks: TODO add sysfs access */
2812         if (rinfo->family == CHIP_FAMILY_RS480)
2813                 rinfo->dynclk = -1;
2814         else
2815                 rinfo->dynclk = dynclk;
2816
2817         if (rinfo->dynclk == 1) {
2818                 radeon_pm_enable_dynamic_mode(rinfo);
2819                 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2820         } else if (rinfo->dynclk == 0) {
2821                 radeon_pm_disable_dynamic_mode(rinfo);
2822                 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2823         }
2824
2825 #if defined(CONFIG_PM)
2826 #if defined(CONFIG_PPC_PMAC)
2827         /* Check if we can power manage on suspend/resume. We can do
2828          * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2829          * "Mac" cards, but that's all. We need more infos about what the
2830          * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2831          * reason. --BenH
2832          */
2833         if (machine_is(powermac) && rinfo->of_node) {
2834                 if (rinfo->is_mobility && rinfo->pm_reg &&
2835                     rinfo->family <= CHIP_FAMILY_RV250)
2836                         rinfo->pm_mode |= radeon_pm_d2;
2837
2838                 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2839                  * in some desktop G4s), Via (M9+ chip on iBook G4) and
2840                  * Snowy (M11 chip on iBook G4 manufactured after July 2005)
2841                  */
2842                 if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") ||
2843                     !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) {
2844                         rinfo->reinit_func = radeon_reinitialize_M10;
2845                         rinfo->pm_mode |= radeon_pm_off;
2846                 }
2847 #if 0 /* Not ready yet */
2848                 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2849                         rinfo->reinit_func = radeon_reinitialize_QW;
2850                         rinfo->pm_mode |= radeon_pm_off;
2851                 }
2852 #endif
2853                 if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) {
2854                         rinfo->reinit_func = radeon_reinitialize_M9P;
2855                         rinfo->pm_mode |= radeon_pm_off;
2856                 }
2857
2858                 /* If any of the above is set, we assume the machine can sleep/resume.
2859                  * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2860                  * from the platform about what happens to the chip...
2861                  * Now we tell the platform about our capability
2862                  */
2863                 if (rinfo->pm_mode != radeon_pm_none) {
2864                         pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2865 #if 0 /* Disable the early video resume hack for now as it's causing problems, among
2866        * others we now rely on the PCI core restoring the config space for us, which
2867        * isn't the case with that hack, and that code path causes various things to
2868        * be called with interrupts off while they shouldn't. I'm leaving the code in
2869        * as it can be useful for debugging purposes
2870        */
2871                         pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2872 #endif
2873                 }
2874
2875 #if 0
2876                 /* Power down TV DAC, taht saves a significant amount of power,
2877                  * we'll have something better once we actually have some TVOut
2878                  * support
2879                  */
2880                 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
2881 #endif
2882         }
2883 #endif /* defined(CONFIG_PPC_PMAC) */
2884 #endif /* defined(CONFIG_PM) */
2885
2886         if (ignore_devlist)
2887                 printk(KERN_DEBUG
2888                        "radeonfb: skipping test for device workarounds\n");
2889         else
2890                 radeon_apply_workarounds(rinfo);
2891
2892         if (force_sleep) {
2893                 printk(KERN_DEBUG
2894                        "radeonfb: forcefully enabling D2 sleep mode\n");
2895                 rinfo->pm_mode |= radeon_pm_d2;
2896         }
2897 }
2898
2899 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2900 {
2901 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
2902         if (rinfo->pm_mode != radeon_pm_none)
2903                 pmac_set_early_video_resume(NULL, NULL);
2904 #endif
2905 }