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   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27         Module Name:
  28         rt28xx.h
  29
  30         Abstract:
  31         RT28xx ASIC related definition & structures
  32
  33         Revision History:
  34         Who                     When              What
  35         --------        ----------        ----------------------------------------------
  36        Jan Lee           Jan-3-2006     created for RT2860c
  37 */
  38
  39 #ifndef __RT28XX_H__
  40 #define __RT28XX_H__
  41
  42
  43 //
  44 // PCI registers - base address 0x0000
  45 //
  46 #define PCI_CFG                 0x0000
  47 #define PCI_EECTRL                      0x0004
  48 #define PCI_MCUCTRL                     0x0008
  49
  50 #define OPT_14                  0x114
  51
  52 typedef int                             NTSTATUS;
  53 #define RETRY_LIMIT             10
  54 #define STATUS_SUCCESS                          0x00
  55 #define STATUS_UNSUCCESSFUL             0x01
  56
  57 //
  58 // SCH/DMA registers - base address 0x0200
  59 //
  60 // INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
  61 //
  62 #define DMA_CSR0      0x200
  63 #define INT_SOURCE_CSR      0x200
  64 #ifdef RT_BIG_ENDIAN
  65 typedef union   _INT_SOURCE_CSR_STRUC   {
  66         struct  {
  67                 UINT32          :14;
  68                 UINT32          TxCoherent:1;
  69                 UINT32          RxCoherent:1;
  70                 UINT32          GPTimer:1;
  71                 UINT32          AutoWakeup:1;//bit14
  72                 UINT32          TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
  73                 UINT32          PreTBTT:1;
  74                 UINT32          TBTTInt:1;
  75                 UINT32          RxTxCoherent:1;
  76                 UINT32          MCUCommandINT:1;
  77                 UINT32          MgmtDmaDone:1;
  78                 UINT32          HccaDmaDone:1;
  79                 UINT32          Ac3DmaDone:1;
  80                 UINT32          Ac2DmaDone:1;
  81                 UINT32          Ac1DmaDone:1;
  82                 UINT32          Ac0DmaDone:1;
  83                 UINT32          RxDone:1;
  84                 UINT32          TxDelayINT:1;   //delayed interrupt, not interrupt until several int or time limit hit
  85                 UINT32          RxDelayINT:1; //dealyed interrupt
  86         }       field;
  87         UINT32                  word;
  88 }       INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
  89 #else
  90 typedef union   _INT_SOURCE_CSR_STRUC   {
  91         struct  {
  92                 UINT32          RxDelayINT:1;
  93                 UINT32          TxDelayINT:1;
  94                 UINT32          RxDone:1;
  95                 UINT32          Ac0DmaDone:1;//4
  96                 UINT32          Ac1DmaDone:1;
  97                 UINT32          Ac2DmaDone:1;
  98                 UINT32          Ac3DmaDone:1;
  99                 UINT32          HccaDmaDone:1; // bit7
 100                 UINT32          MgmtDmaDone:1;
 101                 UINT32          MCUCommandINT:1;//bit 9
 102                 UINT32          RxTxCoherent:1;
 103                 UINT32          TBTTInt:1;
 104                 UINT32          PreTBTT:1;
 105                 UINT32          TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
 106                 UINT32          AutoWakeup:1;//bit14
 107                 UINT32          GPTimer:1;
 108                 UINT32          RxCoherent:1;//bit16
 109                 UINT32          TxCoherent:1;
 110                 UINT32          :14;
 111         }       field;
 112         UINT32                  word;
 113 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
 114 #endif
 115
 116 //
 117 // INT_MASK_CSR:   Interrupt MASK register.   1: the interrupt is mask OFF
 118 //
 119 #define INT_MASK_CSR        0x204
 120 #ifdef RT_BIG_ENDIAN
 121 typedef union   _INT_MASK_CSR_STRUC     {
 122         struct  {
 123                 UINT32          TxCoherent:1;
 124                 UINT32          RxCoherent:1;
 125                 UINT32          :20;
 126                 UINT32          MCUCommandINT:1;
 127                 UINT32          MgmtDmaDone:1;
 128                 UINT32          HccaDmaDone:1;
 129                 UINT32          Ac3DmaDone:1;
 130                 UINT32          Ac2DmaDone:1;
 131                 UINT32          Ac1DmaDone:1;
 132                 UINT32          Ac0DmaDone:1;
 133                 UINT32          RxDone:1;
 134                 UINT32          TxDelay:1;
 135                 UINT32          RXDelay_INT_MSK:1;
 136         }       field;
 137         UINT32                  word;
 138 }INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
 139 #else
 140 typedef union   _INT_MASK_CSR_STRUC     {
 141         struct  {
 142                 UINT32          RXDelay_INT_MSK:1;
 143                 UINT32          TxDelay:1;
 144                 UINT32          RxDone:1;
 145                 UINT32          Ac0DmaDone:1;
 146                 UINT32          Ac1DmaDone:1;
 147                 UINT32          Ac2DmaDone:1;
 148                 UINT32          Ac3DmaDone:1;
 149                 UINT32          HccaDmaDone:1;
 150                 UINT32          MgmtDmaDone:1;
 151                 UINT32          MCUCommandINT:1;
 152                 UINT32          :20;
 153                 UINT32          RxCoherent:1;
 154                 UINT32          TxCoherent:1;
 155         }       field;
 156         UINT32                  word;
 157 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
 158 #endif
 159 #define WPDMA_GLO_CFG   0x208
 160 #ifdef RT_BIG_ENDIAN
 161 typedef union   _WPDMA_GLO_CFG_STRUC    {
 162         struct  {
 163                 UINT32          HDR_SEG_LEN:16;
 164                 UINT32          RXHdrScater:8;
 165                 UINT32          BigEndian:1;
 166                 UINT32          EnTXWriteBackDDONE:1;
 167                 UINT32          WPDMABurstSIZE:2;
 168                 UINT32          RxDMABusy:1;
 169                 UINT32          EnableRxDMA:1;
 170                 UINT32          TxDMABusy:1;
 171                 UINT32          EnableTxDMA:1;
 172         }       field;
 173         UINT32                  word;
 174 }WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
 175 #else
 176 typedef union   _WPDMA_GLO_CFG_STRUC    {
 177         struct  {
 178                 UINT32          EnableTxDMA:1;
 179                 UINT32          TxDMABusy:1;
 180                 UINT32          EnableRxDMA:1;
 181                 UINT32          RxDMABusy:1;
 182                 UINT32          WPDMABurstSIZE:2;
 183                 UINT32          EnTXWriteBackDDONE:1;
 184                 UINT32          BigEndian:1;
 185                 UINT32          RXHdrScater:8;
 186                 UINT32          HDR_SEG_LEN:16;
 187         }       field;
 188         UINT32                  word;
 189 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
 190 #endif
 191 #define WPDMA_RST_IDX   0x20c
 192 #ifdef RT_BIG_ENDIAN
 193 typedef union   _WPDMA_RST_IDX_STRUC    {
 194         struct  {
 195                 UINT32          :15;
 196                 UINT32          RST_DRX_IDX0:1;
 197                 UINT32          rsv:10;
 198                 UINT32          RST_DTX_IDX5:1;
 199                 UINT32          RST_DTX_IDX4:1;
 200                 UINT32          RST_DTX_IDX3:1;
 201                 UINT32          RST_DTX_IDX2:1;
 202                 UINT32          RST_DTX_IDX1:1;
 203                 UINT32          RST_DTX_IDX0:1;
 204         }       field;
 205         UINT32                  word;
 206 }WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
 207 #else
 208 typedef union   _WPDMA_RST_IDX_STRUC    {
 209         struct  {
 210                 UINT32          RST_DTX_IDX0:1;
 211                 UINT32          RST_DTX_IDX1:1;
 212                 UINT32          RST_DTX_IDX2:1;
 213                 UINT32          RST_DTX_IDX3:1;
 214                 UINT32          RST_DTX_IDX4:1;
 215                 UINT32          RST_DTX_IDX5:1;
 216                 UINT32          rsv:10;
 217                 UINT32          RST_DRX_IDX0:1;
 218                 UINT32          :15;
 219         }       field;
 220         UINT32                  word;
 221 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
 222 #endif
 223 #define DELAY_INT_CFG  0x0210
 224 #ifdef RT_BIG_ENDIAN
 225 typedef union   _DELAY_INT_CFG_STRUC    {
 226         struct  {
 227                 UINT32          TXDLY_INT_EN:1;
 228                 UINT32          TXMAX_PINT:7;
 229                 UINT32          TXMAX_PTIME:8;
 230                 UINT32          RXDLY_INT_EN:1;
 231                 UINT32          RXMAX_PINT:7;
 232                 UINT32          RXMAX_PTIME:8;
 233         }       field;
 234         UINT32                  word;
 235 }DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
 236 #else
 237 typedef union   _DELAY_INT_CFG_STRUC    {
 238         struct  {
 239                 UINT32          RXMAX_PTIME:8;
 240                 UINT32          RXMAX_PINT:7;
 241                 UINT32          RXDLY_INT_EN:1;
 242                 UINT32          TXMAX_PTIME:8;
 243                 UINT32          TXMAX_PINT:7;
 244                 UINT32          TXDLY_INT_EN:1;
 245         }       field;
 246         UINT32                  word;
 247 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
 248 #endif
 249 #define WMM_AIFSN_CFG   0x0214
 250 #ifdef RT_BIG_ENDIAN
 251 typedef union   _AIFSN_CSR_STRUC        {
 252         struct  {
 253             UINT32   Rsv:16;
 254             UINT32   Aifsn3:4;       // for AC_VO
 255             UINT32   Aifsn2:4;       // for AC_VI
 256             UINT32   Aifsn1:4;       // for AC_BK
 257             UINT32   Aifsn0:4;       // for AC_BE
 258         }       field;
 259         UINT32                  word;
 260 }       AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
 261 #else
 262 typedef union   _AIFSN_CSR_STRUC        {
 263         struct  {
 264             UINT32   Aifsn0:4;       // for AC_BE
 265             UINT32   Aifsn1:4;       // for AC_BK
 266             UINT32   Aifsn2:4;       // for AC_VI
 267             UINT32   Aifsn3:4;       // for AC_VO
 268             UINT32   Rsv:16;
 269         }       field;
 270         UINT32                  word;
 271 }       AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
 272 #endif
 273 //
 274 // CWMIN_CSR: CWmin for each EDCA AC
 275 //
 276 #define WMM_CWMIN_CFG   0x0218
 277 #ifdef RT_BIG_ENDIAN
 278 typedef union   _CWMIN_CSR_STRUC        {
 279         struct  {
 280             UINT32   Rsv:16;
 281             UINT32   Cwmin3:4;       // for AC_VO
 282             UINT32   Cwmin2:4;       // for AC_VI
 283             UINT32   Cwmin1:4;       // for AC_BK
 284             UINT32   Cwmin0:4;       // for AC_BE
 285         }       field;
 286         UINT32                  word;
 287 }       CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
 288 #else
 289 typedef union   _CWMIN_CSR_STRUC        {
 290         struct  {
 291             UINT32   Cwmin0:4;       // for AC_BE
 292             UINT32   Cwmin1:4;       // for AC_BK
 293             UINT32   Cwmin2:4;       // for AC_VI
 294             UINT32   Cwmin3:4;       // for AC_VO
 295             UINT32   Rsv:16;
 296         }       field;
 297         UINT32                  word;
 298 }       CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
 299 #endif
 300
 301 //
 302 // CWMAX_CSR: CWmin for each EDCA AC
 303 //
 304 #define WMM_CWMAX_CFG   0x021c
 305 #ifdef RT_BIG_ENDIAN
 306 typedef union   _CWMAX_CSR_STRUC        {
 307         struct  {
 308             UINT32   Rsv:16;
 309             UINT32   Cwmax3:4;       // for AC_VO
 310             UINT32   Cwmax2:4;       // for AC_VI
 311             UINT32   Cwmax1:4;       // for AC_BK
 312             UINT32   Cwmax0:4;       // for AC_BE
 313         }       field;
 314         UINT32                  word;
 315 }       CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
 316 #else
 317 typedef union   _CWMAX_CSR_STRUC        {
 318         struct  {
 319             UINT32   Cwmax0:4;       // for AC_BE
 320             UINT32   Cwmax1:4;       // for AC_BK
 321             UINT32   Cwmax2:4;       // for AC_VI
 322             UINT32   Cwmax3:4;       // for AC_VO
 323             UINT32   Rsv:16;
 324         }       field;
 325         UINT32                  word;
 326 }       CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
 327 #endif
 328
 329
 330 //
 331 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
 332 //
 333 #define WMM_TXOP0_CFG    0x0220
 334 #ifdef RT_BIG_ENDIAN
 335 typedef union   _AC_TXOP_CSR0_STRUC     {
 336         struct  {
 337             USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
 338             USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
 339         }       field;
 340         UINT32                  word;
 341 }       AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
 342 #else
 343 typedef union   _AC_TXOP_CSR0_STRUC     {
 344         struct  {
 345             USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
 346             USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
 347         }       field;
 348         UINT32                  word;
 349 }       AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
 350 #endif
 351
 352 //
 353 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
 354 //
 355 #define WMM_TXOP1_CFG    0x0224
 356 #ifdef RT_BIG_ENDIAN
 357 typedef union   _AC_TXOP_CSR1_STRUC     {
 358         struct  {
 359             USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
 360             USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
 361         }       field;
 362         UINT32                  word;
 363 }       AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
 364 #else
 365 typedef union   _AC_TXOP_CSR1_STRUC     {
 366         struct  {
 367             USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
 368             USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
 369         }       field;
 370         UINT32                  word;
 371 }       AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
 372 #endif
 373 #define RINGREG_DIFF                    0x10
 374 #define GPIO_CTRL_CFG    0x0228 //MAC_CSR13
 375 #define MCU_CMD_CFG    0x022c
 376 #define TX_BASE_PTR0     0x0230 //AC_BK base address
 377 #define TX_MAX_CNT0      0x0234
 378 #define TX_CTX_IDX0       0x0238
 379 #define TX_DTX_IDX0      0x023c
 380 #define TX_BASE_PTR1     0x0240         //AC_BE base address
 381 #define TX_MAX_CNT1      0x0244
 382 #define TX_CTX_IDX1       0x0248
 383 #define TX_DTX_IDX1      0x024c
 384 #define TX_BASE_PTR2     0x0250         //AC_VI base address
 385 #define TX_MAX_CNT2      0x0254
 386 #define TX_CTX_IDX2       0x0258
 387 #define TX_DTX_IDX2      0x025c
 388 #define TX_BASE_PTR3     0x0260         //AC_VO base address
 389 #define TX_MAX_CNT3      0x0264
 390 #define TX_CTX_IDX3       0x0268
 391 #define TX_DTX_IDX3      0x026c
 392 #define TX_BASE_PTR4     0x0270         //HCCA base address
 393 #define TX_MAX_CNT4      0x0274
 394 #define TX_CTX_IDX4       0x0278
 395 #define TX_DTX_IDX4      0x027c
 396 #define TX_BASE_PTR5     0x0280         //MGMT base address
 397 #define  TX_MAX_CNT5     0x0284
 398 #define TX_CTX_IDX5       0x0288
 399 #define TX_DTX_IDX5      0x028c
 400 #define TX_MGMTMAX_CNT      TX_MAX_CNT5
 401 #define TX_MGMTCTX_IDX       TX_CTX_IDX5
 402 #define TX_MGMTDTX_IDX      TX_DTX_IDX5
 403 #define RX_BASE_PTR     0x0290  //RX base address
 404 #define RX_MAX_CNT      0x0294
 405 #define RX_CRX_IDX       0x0298
 406 #define RX_DRX_IDX      0x029c
 407 #define USB_DMA_CFG      0x02a0
 408 #ifdef RT_BIG_ENDIAN
 409 typedef union   _USB_DMA_CFG_STRUC      {
 410         struct  {
 411             UINT32  TxBusy:1;           //USB DMA TX FSM busy . debug only
 412             UINT32  RxBusy:1;        //USB DMA RX FSM busy . debug only
 413             UINT32  EpoutValid:6;        //OUT endpoint data valid. debug only
 414             UINT32  TxBulkEn:1;        //Enable USB DMA Tx
 415             UINT32  RxBulkEn:1;        //Enable USB DMA Rx
 416             UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
 417             UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
 418             UINT32  TxClear:1;        //Clear USB DMA TX path
 419             UINT32  rsv:2;
 420             UINT32  phyclear:1;                 //phy watch dog enable. write 1
 421             UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 1024 bytes
 422             UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
 423         }       field;
 424         UINT32                  word;
 425 }       USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
 426 #else
 427 typedef union   _USB_DMA_CFG_STRUC      {
 428         struct  {
 429             UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
 430             UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 256 bytes
 431             UINT32  phyclear:1;                 //phy watch dog enable. write 1
 432             UINT32  rsv:2;
 433             UINT32  TxClear:1;        //Clear USB DMA TX path
 434             UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
 435             UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
 436             UINT32  RxBulkEn:1;        //Enable USB DMA Rx
 437             UINT32  TxBulkEn:1;        //Enable USB DMA Tx
 438             UINT32  EpoutValid:6;        //OUT endpoint data valid
 439             UINT32  RxBusy:1;        //USB DMA RX FSM busy
 440             UINT32  TxBusy:1;           //USB DMA TX FSM busy
 441         }       field;
 442         UINT32                  word;
 443 }       USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
 444 #endif
 445
 446 //
 447 //  3  PBF  registers
 448 //
 449 //
 450 // Most are for debug. Driver doesn't touch PBF register.
 451 #define         PBF_SYS_CTRL     0x0400
 452 #define     PBF_CFG                 0x0408
 453 #define         PBF_MAX_PCNT     0x040C
 454 #define         PBF_CTRL                0x0410
 455 #define         PBF_INT_STA      0x0414
 456 #define         PBF_INT_ENA      0x0418
 457 #define         TXRXQ_PCNT       0x0438
 458 #define         PBF_DBG                  0x043c
 459 #define     PBF_CAP_CTRL     0x0440
 460
 461
 462 // eFuse registers
 463 #define EFUSE_CTRL              0x0580
 464 #define EFUSE_DATA0             0x0590
 465 #define EFUSE_DATA1             0x0594
 466 #define EFUSE_DATA2             0x0598
 467 #define EFUSE_DATA3             0x059c
 468 #define EFUSE_USAGE_MAP_START   0x2d0
 469 #define EFUSE_USAGE_MAP_END     0x2fc
 470 #define EFUSE_TAG               0x2fe
 471 #define EFUSE_USAGE_MAP_SIZE    45
 472
 473 #ifdef RT_BIG_ENDIAN
 474 typedef union   _EFUSE_CTRL_STRUC {
 475         struct  {
 476                 UINT32            SEL_EFUSE:1;
 477                 UINT32            EFSROM_KICK:1;
 478                 UINT32            RESERVED:4;
 479                 UINT32            EFSROM_AIN:10;
 480                 UINT32            EFSROM_LDO_ON_TIME:2;
 481                 UINT32            EFSROM_LDO_OFF_TIME:6;
 482                 UINT32            EFSROM_MODE:2;
 483                 UINT32            EFSROM_AOUT:6;
 484         }       field;
 485         UINT32                  word;
 486 }       EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC;
 487 #else
 488 typedef union   _EFUSE_CTRL_STRUC {
 489         struct  {
 490                 UINT32            EFSROM_AOUT:6;
 491                 UINT32            EFSROM_MODE:2;
 492                 UINT32            EFSROM_LDO_OFF_TIME:6;
 493                 UINT32            EFSROM_LDO_ON_TIME:2;
 494                 UINT32            EFSROM_AIN:10;
 495                 UINT32            RESERVED:4;
 496                 UINT32            EFSROM_KICK:1;
 497                 UINT32            SEL_EFUSE:1;
 498         }       field;
 499         UINT32                  word;
 500 }       EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC;
 501 #endif // RT_BIG_ENDIAN //
 502
 503 #define LDO_CFG0                                0x05d4
 504 #define GPIO_SWITCH                             0x05dc
 505
 506 //
 507 //  4  MAC  registers
 508 //
 509 //
 510 //  4.1 MAC SYSTEM  configuration registers (offset:0x1000)
 511 //
 512 #define MAC_CSR0            0x1000
 513 #ifdef RT_BIG_ENDIAN
 514 typedef union   _ASIC_VER_ID_STRUC      {
 515         struct  {
 516             USHORT  ASICVer;        // version : 2860
 517             USHORT  ASICRev;        // reversion  : 0
 518         }       field;
 519         UINT32                  word;
 520 }       ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
 521 #else
 522 typedef union   _ASIC_VER_ID_STRUC      {
 523         struct  {
 524             USHORT  ASICRev;        // reversion  : 0
 525             USHORT  ASICVer;        // version : 2860
 526         }       field;
 527         UINT32                  word;
 528 }       ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
 529 #endif
 530 #define MAC_SYS_CTRL            0x1004          //MAC_CSR1
 531 #define MAC_ADDR_DW0                            0x1008          // MAC ADDR DW0
 532 #define MAC_ADDR_DW1                     0x100c         // MAC ADDR DW1
 533 //
 534 // MAC_CSR2: STA MAC register 0
 535 //
 536 #ifdef RT_BIG_ENDIAN
 537 typedef union   _MAC_DW0_STRUC  {
 538         struct  {
 539                 UCHAR           Byte3;          // MAC address byte 3
 540                 UCHAR           Byte2;          // MAC address byte 2
 541                 UCHAR           Byte1;          // MAC address byte 1
 542                 UCHAR           Byte0;          // MAC address byte 0
 543         }       field;
 544         UINT32                  word;
 545 }       MAC_DW0_STRUC, *PMAC_DW0_STRUC;
 546 #else
 547 typedef union   _MAC_DW0_STRUC  {
 548         struct  {
 549                 UCHAR           Byte0;          // MAC address byte 0
 550                 UCHAR           Byte1;          // MAC address byte 1
 551                 UCHAR           Byte2;          // MAC address byte 2
 552                 UCHAR           Byte3;          // MAC address byte 3
 553         }       field;
 554         UINT32                  word;
 555 }       MAC_DW0_STRUC, *PMAC_DW0_STRUC;
 556 #endif
 557
 558 //
 559 // MAC_CSR3: STA MAC register 1
 560 //
 561 #ifdef RT_BIG_ENDIAN
 562 typedef union   _MAC_DW1_STRUC  {
 563         struct  {
 564                 UCHAR           Rsvd1;
 565                 UCHAR           U2MeMask;
 566                 UCHAR           Byte5;          // MAC address byte 5
 567                 UCHAR           Byte4;          // MAC address byte 4
 568         }       field;
 569         UINT32                  word;
 570 }       MAC_DW1_STRUC, *PMAC_DW1_STRUC;
 571 #else
 572 typedef union   _MAC_DW1_STRUC  {
 573         struct  {
 574                 UCHAR           Byte4;          // MAC address byte 4
 575                 UCHAR           Byte5;          // MAC address byte 5
 576                 UCHAR           U2MeMask;
 577                 UCHAR           Rsvd1;
 578         }       field;
 579         UINT32                  word;
 580 }       MAC_DW1_STRUC, *PMAC_DW1_STRUC;
 581 #endif
 582
 583 #define MAC_BSSID_DW0                           0x1010          // MAC BSSID DW0
 584 #define MAC_BSSID_DW1                           0x1014          // MAC BSSID DW1
 585
 586 //
 587 // MAC_CSR5: BSSID register 1
 588 //
 589 #ifdef RT_BIG_ENDIAN
 590 typedef union   _MAC_CSR5_STRUC {
 591         struct  {
 592                 USHORT          Rsvd:11;
 593                 USHORT          MBssBcnNum:3;
 594                 USHORT          BssIdMode:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
 595                 UCHAR           Byte5;           // BSSID byte 5
 596                 UCHAR           Byte4;           // BSSID byte 4
 597         }       field;
 598         UINT32                  word;
 599 }       MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
 600 #else
 601 typedef union   _MAC_CSR5_STRUC {
 602         struct  {
 603                 UCHAR           Byte4;           // BSSID byte 4
 604                 UCHAR           Byte5;           // BSSID byte 5
 605                 USHORT          BssIdMask:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
 606                 USHORT          MBssBcnNum:3;
 607                 USHORT          Rsvd:11;
 608         }       field;
 609         UINT32                  word;
 610 }       MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
 611 #endif
 612
 613 #define MAX_LEN_CFG              0x1018         // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 614 #define BBP_CSR_CFG                     0x101c          //
 615 //
 616 // BBP_CSR_CFG: BBP serial control register
 617 //
 618 #ifdef RT_BIG_ENDIAN
 619 typedef union   _BBP_CSR_CFG_STRUC      {
 620         struct  {
 621                 UINT32          :12;
 622                 UINT32          BBP_RW_MODE:1;          // 0: use serial mode  1:parallel
 623                 UINT32          BBP_PAR_DUR:1;              // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
 624                 UINT32          Busy:1;                         // 1: ASIC is busy execute BBP programming.
 625                 UINT32          fRead:1;                    // 0: Write BBP, 1: Read BBP
 626                 UINT32          RegNum:8;                       // Selected     BBP     register
 627                 UINT32          Value:8;                        // Register     value to program into BBP
 628         }       field;
 629         UINT32                  word;
 630 }       BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
 631 #else
 632 typedef union   _BBP_CSR_CFG_STRUC      {
 633         struct  {
 634                 UINT32          Value:8;                        // Register     value to program into BBP
 635                 UINT32          RegNum:8;                       // Selected     BBP     register
 636                 UINT32          fRead:1;                    // 0: Write BBP, 1: Read BBP
 637                 UINT32          Busy:1;                         // 1: ASIC is busy execute BBP programming.
 638                 UINT32          BBP_PAR_DUR:1;               // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
 639                 UINT32          BBP_RW_MODE:1;          // 0: use serial mode  1:parallel
 640                 UINT32          :12;
 641         }       field;
 642         UINT32                  word;
 643 }       BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
 644 #endif
 645 #define RF_CSR_CFG0                     0x1020
 646 //
 647 // RF_CSR_CFG: RF control register
 648 //
 649 #ifdef RT_BIG_ENDIAN
 650 typedef union   _RF_CSR_CFG0_STRUC      {
 651         struct  {
 652                 UINT32          Busy:1;             // 0: idle 1: 8busy
 653                 UINT32          Sel:1;                          // 0:RF_LE0 activate  1:RF_LE1 activate
 654                 UINT32          StandbyMode:1;              // 0: high when stand by 1: low when standby
 655                 UINT32          bitwidth:5;                     // Selected     BBP     register
 656                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 657         }       field;
 658         UINT32                  word;
 659 }       RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
 660 #else
 661 typedef union   _RF_CSR_CFG0_STRUC      {
 662         struct  {
 663                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 664                 UINT32          bitwidth:5;                     // Selected     BBP     register
 665                 UINT32          StandbyMode:1;              // 0: high when stand by 1: low when standby
 666                 UINT32          Sel:1;                          // 0:RF_LE0 activate  1:RF_LE1 activate
 667                 UINT32          Busy:1;             // 0: idle 1: 8busy
 668         }       field;
 669         UINT32                  word;
 670 }       RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
 671 #endif
 672 #define RF_CSR_CFG1                     0x1024
 673 #ifdef RT_BIG_ENDIAN
 674 typedef union   _RF_CSR_CFG1_STRUC      {
 675         struct  {
 676                 UINT32          rsv:7;              // 0: idle 1: 8busy
 677                 UINT32          RFGap:5;                        // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
 678                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 679         }       field;
 680         UINT32                  word;
 681 }       RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
 682 #else
 683 typedef union   _RF_CSR_CFG1_STRUC      {
 684         struct  {
 685                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 686                 UINT32          RFGap:5;                        // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
 687                 UINT32          rsv:7;              // 0: idle 1: 8busy
 688         }       field;
 689         UINT32                  word;
 690 }       RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
 691 #endif
 692 #define RF_CSR_CFG2                     0x1028          //
 693 #ifdef RT_BIG_ENDIAN
 694 typedef union   _RF_CSR_CFG2_STRUC      {
 695         struct  {
 696                 UINT32          rsv:8;              // 0: idle 1: 8busy
 697                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 698         }       field;
 699         UINT32                  word;
 700 }       RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
 701 #else
 702 typedef union   _RF_CSR_CFG2_STRUC      {
 703         struct  {
 704                 UINT32          RegIdAndContent:24;                     // Register     value to program into BBP
 705                 UINT32          rsv:8;              // 0: idle 1: 8busy
 706         }       field;
 707         UINT32                  word;
 708 }       RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
 709 #endif
 710 #define LED_CFG                         0x102c          //  MAC_CSR14
 711 #ifdef RT_BIG_ENDIAN
 712 typedef union   _LED_CFG_STRUC  {
 713         struct  {
 714                 UINT32          :1;
 715                 UINT32          LedPolar:1;                     // Led Polarity.  0: active low1: active high
 716                 UINT32          YLedMode:2;                     // yellow Led Mode
 717                 UINT32          GLedMode:2;                     // green Led Mode
 718                 UINT32          RLedMode:2;                     // red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
 719                 UINT32          rsv:2;
 720                 UINT32          SlowBlinkPeriod:6;                      // slow blinking period. unit:1ms
 721                 UINT32          OffPeriod:8;                    // blinking off period unit 1ms
 722                 UINT32          OnPeriod:8;                     // blinking on period unit 1ms
 723         }       field;
 724         UINT32                  word;
 725 }       LED_CFG_STRUC, *PLED_CFG_STRUC;
 726 #else
 727 typedef union   _LED_CFG_STRUC  {
 728         struct  {
 729                 UINT32          OnPeriod:8;                     // blinking on period unit 1ms
 730                 UINT32          OffPeriod:8;                    // blinking off period unit 1ms
 731                 UINT32          SlowBlinkPeriod:6;                      // slow blinking period. unit:1ms
 732                 UINT32          rsv:2;
 733                 UINT32          RLedMode:2;                     // red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
 734                 UINT32          GLedMode:2;                     // green Led Mode
 735                 UINT32          YLedMode:2;                     // yellow Led Mode
 736                 UINT32          LedPolar:1;                     // Led Polarity.  0: active low1: active high
 737                 UINT32          :1;
 738         }       field;
 739         UINT32                  word;
 740 }       LED_CFG_STRUC, *PLED_CFG_STRUC;
 741 #endif
 742 //
 743 //  4.2 MAC TIMING  configuration registers (offset:0x1100)
 744 //
 745 #define XIFS_TIME_CFG             0x1100                 // MAC_CSR8  MAC_CSR9
 746 #ifdef RT_BIG_ENDIAN
 747 typedef union   _IFS_SLOT_CFG_STRUC     {
 748         struct  {
 749             UINT32  rsv:2;
 750             UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
 751             UINT32  EIFS:9;        //  unit 1us
 752             UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
 753             UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
 754             UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
 755         }       field;
 756         UINT32                  word;
 757 }       IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
 758 #else
 759 typedef union   _IFS_SLOT_CFG_STRUC     {
 760         struct  {
 761             UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
 762             UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
 763             UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
 764             UINT32  EIFS:9;        //  unit 1us
 765             UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
 766             UINT32  rsv:2;
 767         }       field;
 768         UINT32                  word;
 769 }       IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
 770 #endif
 771
 772 #define BKOFF_SLOT_CFG             0x1104                //  mac_csr9 last 8 bits
 773 #define NAV_TIME_CFG             0x1108          // NAV  (MAC_CSR15)
 774 #define CH_TIME_CFG             0x110C                  // Count as channel busy
 775 #define PBF_LIFE_TIMER             0x1110                //TX/RX MPDU timestamp timer (free run)Unit: 1us
 776 #define BCN_TIME_CFG             0x1114          // TXRX_CSR9
 777
 778 #define BCN_OFFSET0                             0x042C
 779 #define BCN_OFFSET1                             0x0430
 780
 781 //
 782 // BCN_TIME_CFG : Synchronization control register
 783 //
 784 #ifdef RT_BIG_ENDIAN
 785 typedef union   _BCN_TIME_CFG_STRUC     {
 786         struct  {
 787                 UINT32          TxTimestampCompensate:8;
 788         UINT32       :3;
 789                 UINT32          bBeaconGen:1;           // Enable beacon generator
 790         UINT32       bTBTTEnable:1;
 791                 UINT32          TsfSyncMode:2;          // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 792                 UINT32          bTsfTicking:1;          // Enable TSF auto counting
 793                 UINT32       BeaconInterval:16;  // in unit of 1/16 TU
 794         }       field;
 795         UINT32                  word;
 796 }       BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
 797 #else
 798 typedef union   _BCN_TIME_CFG_STRUC     {
 799         struct  {
 800                 UINT32       BeaconInterval:16;  // in unit of 1/16 TU
 801                 UINT32          bTsfTicking:1;          // Enable TSF auto counting
 802                 UINT32          TsfSyncMode:2;          // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
 803         UINT32       bTBTTEnable:1;
 804                 UINT32          bBeaconGen:1;           // Enable beacon generator
 805         UINT32       :3;
 806                 UINT32          TxTimestampCompensate:8;
 807         }       field;
 808         UINT32                  word;
 809 }       BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
 810 #endif
 811 #define TBTT_SYNC_CFG            0x1118                 // txrx_csr10
 812 #define TSF_TIMER_DW0             0x111C                // Local TSF timer lsb 32 bits. Read-only
 813 #define TSF_TIMER_DW1             0x1120                // msb 32 bits. Read-only.
 814 #define TBTT_TIMER              0x1124                  // TImer remains till next TBTT. Read-only.  TXRX_CSR14
 815 #define INT_TIMER_CFG                   0x1128                  //
 816 #define INT_TIMER_EN                    0x112c                  //  GP-timer and pre-tbtt Int enable
 817 #define CH_IDLE_STA                     0x1130                  //  channel idle time
 818 #define CH_BUSY_STA                     0x1134                  //  channle busy time
 819 //
 820 //  4.2 MAC POWER  configuration registers (offset:0x1200)
 821 //
 822 #define MAC_STATUS_CFG             0x1200                // old MAC_CSR12
 823 #define PWR_PIN_CFG             0x1204           // old MAC_CSR12
 824 #define AUTO_WAKEUP_CFG             0x1208               // old MAC_CSR10
 825 //
 826 // AUTO_WAKEUP_CFG: Manual power control / status register
 827 //
 828 #ifdef RT_BIG_ENDIAN
 829 typedef union   _AUTO_WAKEUP_STRUC      {
 830         struct  {
 831                 UINT32          :16;
 832                 UINT32          EnableAutoWakeup:1;     // 0:sleep, 1:awake
 833                 UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
 834                 UINT32       AutoLeadTime:8;
 835         }       field;
 836         UINT32                  word;
 837 }       AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
 838 #else
 839 typedef union   _AUTO_WAKEUP_STRUC      {
 840         struct  {
 841                 UINT32       AutoLeadTime:8;
 842                 UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
 843                 UINT32          EnableAutoWakeup:1;     // 0:sleep, 1:awake
 844                 UINT32          :16;
 845         }       field;
 846         UINT32                  word;
 847 }       AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
 848 #endif
 849 //
 850 //  4.3 MAC TX  configuration registers (offset:0x1300)
 851 //
 852
 853 #define EDCA_AC0_CFG    0x1300          //AC_TXOP_CSR0 0x3474
 854 #define EDCA_AC1_CFG    0x1304
 855 #define EDCA_AC2_CFG    0x1308
 856 #define EDCA_AC3_CFG    0x130c
 857 #ifdef RT_BIG_ENDIAN
 858 typedef union   _EDCA_AC_CFG_STRUC      {
 859         struct  {
 860             UINT32  :12;        //
 861             UINT32  Cwmax:4;        //unit power of 2
 862             UINT32  Cwmin:4;        //
 863             UINT32  Aifsn:4;        // # of slot time
 864             UINT32  AcTxop:8;        //  in unit of 32us
 865         }       field;
 866         UINT32                  word;
 867 }       EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
 868 #else
 869 typedef union   _EDCA_AC_CFG_STRUC      {
 870         struct  {
 871             UINT32  AcTxop:8;        //  in unit of 32us
 872             UINT32  Aifsn:4;        // # of slot time
 873             UINT32  Cwmin:4;        //
 874             UINT32  Cwmax:4;        //unit power of 2
 875             UINT32  :12;       //
 876         }       field;
 877         UINT32                  word;
 878 }       EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
 879 #endif
 880
 881 #define EDCA_TID_AC_MAP 0x1310
 882 #define TX_PWR_CFG_0    0x1314
 883 #define TX_PWR_CFG_1    0x1318
 884 #define TX_PWR_CFG_2    0x131C
 885 #define TX_PWR_CFG_3    0x1320
 886 #define TX_PWR_CFG_4    0x1324
 887 #define TX_PIN_CFG              0x1328
 888 #define TX_BAND_CFG     0x132c          // 0x1 use upper 20MHz. 0 juse lower 20MHz
 889 #define TX_SW_CFG0              0x1330
 890 #define TX_SW_CFG1              0x1334
 891 #define TX_SW_CFG2              0x1338
 892 #define TXOP_THRES_CFG          0x133c
 893 #define TXOP_CTRL_CFG           0x1340
 894 #define TX_RTS_CFG              0x1344
 895
 896 #ifdef RT_BIG_ENDIAN
 897 typedef union   _TX_RTS_CFG_STRUC       {
 898         struct  {
 899             UINT32       rsv:7;
 900             UINT32       RtsFbkEn:1;    // enable rts rate fallback
 901             UINT32       RtsThres:16;    // unit:byte
 902             UINT32       AutoRtsRetryLimit:8;
 903         }       field;
 904         UINT32                  word;
 905 }       TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
 906 #else
 907 typedef union   _TX_RTS_CFG_STRUC       {
 908         struct  {
 909             UINT32       AutoRtsRetryLimit:8;
 910             UINT32       RtsThres:16;    // unit:byte
 911             UINT32       RtsFbkEn:1;    // enable rts rate fallback
 912             UINT32       rsv:7;     // 1: HT non-STBC control frame enable
 913         }       field;
 914         UINT32                  word;
 915 }       TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
 916 #endif
 917 #define TX_TIMEOUT_CFG  0x1348
 918 #ifdef RT_BIG_ENDIAN
 919 typedef union   _TX_TIMEOUT_CFG_STRUC   {
 920         struct  {
 921             UINT32       rsv2:8;
 922             UINT32       TxopTimeout:8; //TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
 923             UINT32       RxAckTimeout:8;        // unit:slot. Used for TX precedure
 924             UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
 925             UINT32       rsv:4;
 926         }       field;
 927         UINT32                  word;
 928 }       TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
 929 #else
 930 typedef union   _TX_TIMEOUT_CFG_STRUC   {
 931         struct  {
 932             UINT32       rsv:4;
 933             UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
 934             UINT32       RxAckTimeout:8;        // unit:slot. Used for TX precedure
 935             UINT32       TxopTimeout:8; //TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
 936             UINT32       rsv2:8;     // 1: HT non-STBC control frame enable
 937         }       field;
 938         UINT32                  word;
 939 }       TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
 940 #endif
 941 #define TX_RTY_CFG      0x134c
 942 #ifdef RT_BIG_ENDIAN
 943 typedef union PACKED _TX_RTY_CFG_STRUC  {
 944         struct  {
 945             UINT32       rsv:1;
 946             UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
 947             UINT32       AggRtyMode:1;  // Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 948             UINT32       NonAggRtyMode:1;       // Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 949             UINT32       LongRtyThre:12;        // Long retry threshoold
 950             UINT32       LongRtyLimit:8;        //long retry limit
 951             UINT32       ShortRtyLimit:8;       //  short retry limit
 952
 953         }       field;
 954         UINT32                  word;
 955 }       TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
 956 #else
 957 typedef union PACKED _TX_RTY_CFG_STRUC  {
 958         struct  {
 959             UINT32       ShortRtyLimit:8;       //  short retry limit
 960             UINT32       LongRtyLimit:8;        //long retry limit
 961             UINT32       LongRtyThre:12;        // Long retry threshoold
 962             UINT32       NonAggRtyMode:1;       // Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 963             UINT32       AggRtyMode:1;  // Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
 964             UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
 965             UINT32       rsv:1;     // 1: HT non-STBC control frame enable
 966         }       field;
 967         UINT32                  word;
 968 }       TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
 969 #endif
 970 #define TX_LINK_CFG     0x1350
 971 #ifdef RT_BIG_ENDIAN
 972 typedef union   PACKED _TX_LINK_CFG_STRUC       {
 973         struct PACKED {
 974             UINT32       RemotMFS:8;    //remote MCS feedback sequence number
 975             UINT32       RemotMFB:8;    //  remote MCS feedback
 976             UINT32       rsv:3; //
 977             UINT32       TxCFAckEn:1;   //   Piggyback CF-ACK enable
 978             UINT32       TxRDGEn:1;     // RDG TX enable
 979             UINT32       TxMRQEn:1;     //  MCS request TX enable
 980             UINT32       RemoteUMFSEnable:1;    //  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
 981             UINT32       MFBEnable:1;   //  TX apply remote MFB 1:enable
 982             UINT32       RemoteMFBLifeTime:8;   //remote MFB life time. unit : 32us
 983         }       field;
 984         UINT32                  word;
 985 }       TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
 986 #else
 987 typedef union   PACKED _TX_LINK_CFG_STRUC       {
 988         struct PACKED {
 989             UINT32       RemoteMFBLifeTime:8;   //remote MFB life time. unit : 32us
 990             UINT32       MFBEnable:1;   //  TX apply remote MFB 1:enable
 991             UINT32       RemoteUMFSEnable:1;    //  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
 992             UINT32       TxMRQEn:1;     //  MCS request TX enable
 993             UINT32       TxRDGEn:1;     // RDG TX enable
 994             UINT32       TxCFAckEn:1;   //   Piggyback CF-ACK enable
 995             UINT32       rsv:3; //
 996             UINT32       RemotMFB:8;    //  remote MCS feedback
 997             UINT32       RemotMFS:8;    //remote MCS feedback sequence number
 998         }       field;
 999         UINT32                  word;
1000 }       TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
1001 #endif
1002 #define HT_FBK_CFG0     0x1354
1003 #ifdef RT_BIG_ENDIAN
1004 typedef union PACKED _HT_FBK_CFG0_STRUC {
1005         struct  {
1006             UINT32       HTMCS7FBK:4;
1007             UINT32       HTMCS6FBK:4;
1008             UINT32       HTMCS5FBK:4;
1009             UINT32       HTMCS4FBK:4;
1010             UINT32       HTMCS3FBK:4;
1011             UINT32       HTMCS2FBK:4;
1012             UINT32       HTMCS1FBK:4;
1013             UINT32       HTMCS0FBK:4;
1014         }       field;
1015         UINT32                  word;
1016 }       HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
1017 #else
1018 typedef union PACKED _HT_FBK_CFG0_STRUC {
1019         struct  {
1020             UINT32       HTMCS0FBK:4;
1021             UINT32       HTMCS1FBK:4;
1022             UINT32       HTMCS2FBK:4;
1023             UINT32       HTMCS3FBK:4;
1024             UINT32       HTMCS4FBK:4;
1025             UINT32       HTMCS5FBK:4;
1026             UINT32       HTMCS6FBK:4;
1027             UINT32       HTMCS7FBK:4;
1028         }       field;
1029         UINT32                  word;
1030 }       HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
1031 #endif
1032 #define HT_FBK_CFG1     0x1358
1033 #ifdef RT_BIG_ENDIAN
1034 typedef union   _HT_FBK_CFG1_STRUC      {
1035         struct  {
1036             UINT32       HTMCS15FBK:4;
1037             UINT32       HTMCS14FBK:4;
1038             UINT32       HTMCS13FBK:4;
1039             UINT32       HTMCS12FBK:4;
1040             UINT32       HTMCS11FBK:4;
1041             UINT32       HTMCS10FBK:4;
1042             UINT32       HTMCS9FBK:4;
1043             UINT32       HTMCS8FBK:4;
1044         }       field;
1045         UINT32                  word;
1046 }       HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
1047 #else
1048 typedef union   _HT_FBK_CFG1_STRUC      {
1049         struct  {
1050             UINT32       HTMCS8FBK:4;
1051             UINT32       HTMCS9FBK:4;
1052             UINT32       HTMCS10FBK:4;
1053             UINT32       HTMCS11FBK:4;
1054             UINT32       HTMCS12FBK:4;
1055             UINT32       HTMCS13FBK:4;
1056             UINT32       HTMCS14FBK:4;
1057             UINT32       HTMCS15FBK:4;
1058         }       field;
1059         UINT32                  word;
1060 }       HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
1061 #endif
1062 #define LG_FBK_CFG0     0x135c
1063 #ifdef RT_BIG_ENDIAN
1064 typedef union   _LG_FBK_CFG0_STRUC      {
1065         struct  {
1066             UINT32       OFDMMCS7FBK:4; //initial value is 6
1067             UINT32       OFDMMCS6FBK:4; //initial value is 5
1068             UINT32       OFDMMCS5FBK:4; //initial value is 4
1069             UINT32       OFDMMCS4FBK:4; //initial value is 3
1070             UINT32       OFDMMCS3FBK:4; //initial value is 2
1071             UINT32       OFDMMCS2FBK:4; //initial value is 1
1072             UINT32       OFDMMCS1FBK:4; //initial value is 0
1073             UINT32       OFDMMCS0FBK:4; //initial value is 0
1074         }       field;
1075         UINT32                  word;
1076 }       LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
1077 #else
1078 typedef union   _LG_FBK_CFG0_STRUC      {
1079         struct  {
1080             UINT32       OFDMMCS0FBK:4; //initial value is 0
1081             UINT32       OFDMMCS1FBK:4; //initial value is 0
1082             UINT32       OFDMMCS2FBK:4; //initial value is 1
1083             UINT32       OFDMMCS3FBK:4; //initial value is 2
1084             UINT32       OFDMMCS4FBK:4; //initial value is 3
1085             UINT32       OFDMMCS5FBK:4; //initial value is 4
1086             UINT32       OFDMMCS6FBK:4; //initial value is 5
1087             UINT32       OFDMMCS7FBK:4; //initial value is 6
1088         }       field;
1089         UINT32                  word;
1090 }       LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
1091 #endif
1092 #define LG_FBK_CFG1             0x1360
1093 #ifdef RT_BIG_ENDIAN
1094 typedef union   _LG_FBK_CFG1_STRUC      {
1095         struct  {
1096             UINT32       rsv:16;
1097             UINT32       CCKMCS3FBK:4;  //initial value is 2
1098             UINT32       CCKMCS2FBK:4;  //initial value is 1
1099             UINT32       CCKMCS1FBK:4;  //initial value is 0
1100             UINT32       CCKMCS0FBK:4;  //initial value is 0
1101         }       field;
1102         UINT32                  word;
1103 }       LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
1104 #else
1105 typedef union   _LG_FBK_CFG1_STRUC      {
1106         struct  {
1107             UINT32       CCKMCS0FBK:4;  //initial value is 0
1108             UINT32       CCKMCS1FBK:4;  //initial value is 0
1109             UINT32       CCKMCS2FBK:4;  //initial value is 1
1110             UINT32       CCKMCS3FBK:4;  //initial value is 2
1111             UINT32       rsv:16;
1112         }       field;
1113         UINT32                  word;
1114 }       LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
1115 #endif
1116
1117 //=======================================================
1118 //================ Protection Paramater================================
1119 //=======================================================
1120 #define CCK_PROT_CFG    0x1364          //CCK Protection
1121 #define ASIC_SHORTNAV           1
1122 #define ASIC_LONGNAV            2
1123 #define ASIC_RTS                1
1124 #define ASIC_CTS                2
1125 #ifdef RT_BIG_ENDIAN
1126 typedef union   _PROT_CFG_STRUC {
1127         struct  {
1128             UINT32       rsv:5;
1129             UINT32       RTSThEn:1;     //RTS threshold enable on CCK TX
1130             UINT32       TxopAllowGF40:1;       //CCK TXOP allowance.0:disallow.
1131             UINT32       TxopAllowGF20:1;       //CCK TXOP allowance.0:disallow.
1132             UINT32       TxopAllowMM40:1;       //CCK TXOP allowance.0:disallow.
1133             UINT32       TxopAllowMM20:1;       //CCK TXOP allowance. 0:disallow.
1134             UINT32       TxopAllowOfdm:1;       //CCK TXOP allowance.0:disallow.
1135             UINT32       TxopAllowCck:1;        //CCK TXOP allowance.0:disallow.
1136             UINT32       ProtectNav:2;  //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
1137             UINT32       ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
1138             UINT32       ProtectRate:16;        //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
1139         }       field;
1140         UINT32                  word;
1141 }       PROT_CFG_STRUC, *PPROT_CFG_STRUC;
1142 #else
1143 typedef union   _PROT_CFG_STRUC {
1144         struct  {
1145             UINT32       ProtectRate:16;        //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
1146             UINT32       ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
1147             UINT32       ProtectNav:2;  //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
1148             UINT32       TxopAllowCck:1;        //CCK TXOP allowance.0:disallow.
1149             UINT32       TxopAllowOfdm:1;       //CCK TXOP allowance.0:disallow.
1150             UINT32       TxopAllowMM20:1;       //CCK TXOP allowance. 0:disallow.
1151             UINT32       TxopAllowMM40:1;       //CCK TXOP allowance.0:disallow.
1152             UINT32       TxopAllowGF20:1;       //CCK TXOP allowance.0:disallow.
1153             UINT32       TxopAllowGF40:1;       //CCK TXOP allowance.0:disallow.
1154             UINT32       RTSThEn:1;     //RTS threshold enable on CCK TX
1155             UINT32       rsv:5;
1156         }       field;
1157         UINT32                  word;
1158 }       PROT_CFG_STRUC, *PPROT_CFG_STRUC;
1159 #endif
1160
1161 #define OFDM_PROT_CFG   0x1368          //OFDM Protection
1162 #define MM20_PROT_CFG   0x136C          //MM20 Protection
1163 #define MM40_PROT_CFG   0x1370          //MM40 Protection
1164 #define GF20_PROT_CFG   0x1374          //GF20 Protection
1165 #define GF40_PROT_CFG   0x1378          //GR40 Protection
1166 #define EXP_CTS_TIME    0x137C          //
1167 #define EXP_ACK_TIME    0x1380          //
1168
1169 //
1170 //  4.4 MAC RX configuration registers (offset:0x1400)
1171 //
1172 #define RX_FILTR_CFG    0x1400                  //TXRX_CSR0
1173 #define AUTO_RSP_CFG    0x1404                  //TXRX_CSR4
1174 //
1175 // TXRX_CSR4: Auto-Responder/
1176 //
1177 #ifdef RT_BIG_ENDIAN
1178 typedef union _AUTO_RSP_CFG_STRUC {
1179  struct {
1180      UINT32        :24;
1181      UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
1182      UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
1183      UINT32       rsv:1;   // Power bit value in conrtrol frame
1184      UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
1185      UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
1186      UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
1187      UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
1188      UINT32       AutoResponderEnable:1;
1189  } field;
1190  UINT32   word;
1191 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
1192 #else
1193 typedef union _AUTO_RSP_CFG_STRUC {
1194  struct {
1195      UINT32       AutoResponderEnable:1;
1196      UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
1197      UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
1198      UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
1199      UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
1200      UINT32       rsv:1;   // Power bit value in conrtrol frame
1201      UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
1202      UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
1203      UINT32        :24;
1204  } field;
1205  UINT32   word;
1206 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
1207 #endif
1208
1209 #define LEGACY_BASIC_RATE       0x1408  //  TXRX_CSR5           0x3054
1210 #define HT_BASIC_RATE           0x140c
1211 #define HT_CTRL_CFG             0x1410
1212 #define SIFS_COST_CFG           0x1414
1213 #define RX_PARSER_CFG           0x1418  //Set NAV for all received frames
1214
1215 //
1216 //  4.5 MAC Security configuration (offset:0x1500)
1217 //
1218 #define TX_SEC_CNT0             0x1500          //
1219 #define RX_SEC_CNT0             0x1504          //
1220 #define CCMP_FC_MUTE            0x1508          //
1221 //
1222 //  4.6 HCCA/PSMP (offset:0x1600)
1223 //
1224 #define TXOP_HLDR_ADDR0         0x1600
1225 #define TXOP_HLDR_ADDR1         0x1604
1226 #define TXOP_HLDR_ET            0x1608
1227 #define QOS_CFPOLL_RA_DW0               0x160c
1228 #define QOS_CFPOLL_A1_DW1               0x1610
1229 #define QOS_CFPOLL_QC           0x1614
1230 //
1231 //  4.7 MAC Statistis registers (offset:0x1700)
1232 //
1233 #define RX_STA_CNT0             0x1700          //
1234 #define RX_STA_CNT1             0x1704          //
1235 #define RX_STA_CNT2             0x1708          //
1236
1237 //
1238 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
1239 //
1240 #ifdef RT_BIG_ENDIAN
1241 typedef union   _RX_STA_CNT0_STRUC      {
1242         struct  {
1243             USHORT  PhyErr;
1244             USHORT  CrcErr;
1245         }       field;
1246         UINT32                  word;
1247 }       RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
1248 #else
1249 typedef union   _RX_STA_CNT0_STRUC      {
1250         struct  {
1251             USHORT  CrcErr;
1252             USHORT  PhyErr;
1253         }       field;
1254         UINT32                  word;
1255 }       RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
1256 #endif
1257
1258 //
1259 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
1260 //
1261 #ifdef RT_BIG_ENDIAN
1262 typedef union   _RX_STA_CNT1_STRUC      {
1263         struct  {
1264             USHORT  PlcpErr;
1265             USHORT  FalseCca;
1266         }       field;
1267         UINT32                  word;
1268 }       RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
1269 #else
1270 typedef union   _RX_STA_CNT1_STRUC      {
1271         struct  {
1272             USHORT  FalseCca;
1273             USHORT  PlcpErr;
1274         }       field;
1275         UINT32                  word;
1276 }       RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
1277 #endif
1278
1279 //
1280 // RX_STA_CNT2_STRUC:
1281 //
1282 #ifdef RT_BIG_ENDIAN
1283 typedef union   _RX_STA_CNT2_STRUC      {
1284         struct  {
1285             USHORT  RxFifoOverflowCount;
1286             USHORT  RxDupliCount;
1287         }       field;
1288         UINT32                  word;
1289 }       RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
1290 #else
1291 typedef union   _RX_STA_CNT2_STRUC      {
1292         struct  {
1293             USHORT  RxDupliCount;
1294             USHORT  RxFifoOverflowCount;
1295         }       field;
1296         UINT32                  word;
1297 }       RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
1298 #endif
1299 #define TX_STA_CNT0             0x170C          //
1300 //
1301 // STA_CSR3: TX Beacon count
1302 //
1303 #ifdef RT_BIG_ENDIAN
1304 typedef union   _TX_STA_CNT0_STRUC      {
1305         struct  {
1306             USHORT  TxBeaconCount;
1307             USHORT  TxFailCount;
1308         }       field;
1309         UINT32                  word;
1310 }       TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
1311 #else
1312 typedef union   _TX_STA_CNT0_STRUC      {
1313         struct  {
1314             USHORT  TxFailCount;
1315             USHORT  TxBeaconCount;
1316         }       field;
1317         UINT32                  word;
1318 }       TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
1319 #endif
1320 #define TX_STA_CNT1             0x1710          //
1321 //
1322 // TX_STA_CNT1: TX tx count
1323 //
1324 #ifdef RT_BIG_ENDIAN
1325 typedef union   _TX_STA_CNT1_STRUC      {
1326         struct  {
1327             USHORT  TxRetransmit;
1328             USHORT  TxSuccess;
1329         }       field;
1330         UINT32                  word;
1331 }       TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
1332 #else
1333 typedef union   _TX_STA_CNT1_STRUC      {
1334         struct  {
1335             USHORT  TxSuccess;
1336             USHORT  TxRetransmit;
1337         }       field;
1338         UINT32                  word;
1339 }       TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
1340 #endif
1341 #define TX_STA_CNT2             0x1714          //
1342 //
1343 // TX_STA_CNT2: TX tx count
1344 //
1345 #ifdef RT_BIG_ENDIAN
1346 typedef union   _TX_STA_CNT2_STRUC      {
1347         struct  {
1348             USHORT  TxUnderFlowCount;
1349             USHORT  TxZeroLenCount;
1350         }       field;
1351         UINT32                  word;
1352 }       TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
1353 #else
1354 typedef union   _TX_STA_CNT2_STRUC      {
1355         struct  {
1356             USHORT  TxZeroLenCount;
1357             USHORT  TxUnderFlowCount;
1358         }       field;
1359         UINT32                  word;
1360 }       TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
1361 #endif
1362 #define TX_STA_FIFO             0x1718          //
1363 //
1364 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
1365 //
1366 #ifdef RT_BIG_ENDIAN
1367 typedef union PACKED _TX_STA_FIFO_STRUC {
1368         struct  {
1369                 UINT32          Reserve:2;
1370                 UINT32          TxBF:1; // 3*3
1371                 UINT32          SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1372 //              UINT32          SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1373                 UINT32          wcid:8;         //wireless client index
1374                 UINT32          TxAckRequired:1;    // ack required
1375                 UINT32          TxAggre:1;    // Tx is aggregated
1376                 UINT32          TxSuccess:1;   // Tx success. whether success or not
1377                 UINT32          PidType:4;
1378                 UINT32          bValid:1;   // 1:This register contains a valid TX result
1379         }       field;
1380         UINT32                  word;
1381 }       TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
1382 #else
1383 typedef union PACKED _TX_STA_FIFO_STRUC {
1384         struct  {
1385                 UINT32          bValid:1;   // 1:This register contains a valid TX result
1386                 UINT32          PidType:4;
1387                 UINT32          TxSuccess:1;   // Tx No retry success
1388                 UINT32          TxAggre:1;    // Tx Retry Success
1389                 UINT32          TxAckRequired:1;    // Tx fail
1390                 UINT32          wcid:8;         //wireless client index
1391 //              UINT32          SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1392                 UINT32          SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
1393                 UINT32          TxBF:1;
1394                 UINT32          Reserve:2;
1395         }       field;
1396         UINT32                  word;
1397 }       TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
1398 #endif
1399 // Debug counter
1400 #define TX_AGG_CNT      0x171c
1401 #ifdef RT_BIG_ENDIAN
1402 typedef union   _TX_AGG_CNT_STRUC       {
1403         struct  {
1404             USHORT  AggTxCount;
1405             USHORT  NonAggTxCount;
1406         }       field;
1407         UINT32                  word;
1408 }       TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
1409 #else
1410 typedef union   _TX_AGG_CNT_STRUC       {
1411         struct  {
1412             USHORT  NonAggTxCount;
1413             USHORT  AggTxCount;
1414         }       field;
1415         UINT32                  word;
1416 }       TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
1417 #endif
1418 // Debug counter
1419 #define TX_AGG_CNT0     0x1720
1420 #ifdef RT_BIG_ENDIAN
1421 typedef union   _TX_AGG_CNT0_STRUC      {
1422         struct  {
1423             USHORT  AggSize2Count;
1424             USHORT  AggSize1Count;
1425         }       field;
1426         UINT32                  word;
1427 }       TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
1428 #else
1429 typedef union   _TX_AGG_CNT0_STRUC      {
1430         struct  {
1431             USHORT  AggSize1Count;
1432             USHORT  AggSize2Count;
1433         }       field;
1434         UINT32                  word;
1435 }       TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
1436 #endif
1437 // Debug counter
1438 #define TX_AGG_CNT1     0x1724
1439 #ifdef RT_BIG_ENDIAN
1440 typedef union   _TX_AGG_CNT1_STRUC      {
1441         struct  {
1442             USHORT  AggSize4Count;
1443             USHORT  AggSize3Count;
1444         }       field;
1445         UINT32                  word;
1446 }       TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
1447 #else
1448 typedef union   _TX_AGG_CNT1_STRUC      {
1449         struct  {
1450             USHORT  AggSize3Count;
1451             USHORT  AggSize4Count;
1452         }       field;
1453         UINT32                  word;
1454 }       TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
1455 #endif
1456 #define TX_AGG_CNT2     0x1728
1457 #ifdef RT_BIG_ENDIAN
1458 typedef union   _TX_AGG_CNT2_STRUC      {
1459         struct  {
1460             USHORT  AggSize6Count;
1461             USHORT  AggSize5Count;
1462         }       field;
1463         UINT32                  word;
1464 }       TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
1465 #else
1466 typedef union   _TX_AGG_CNT2_STRUC      {
1467         struct  {
1468             USHORT  AggSize5Count;
1469             USHORT  AggSize6Count;
1470         }       field;
1471         UINT32                  word;
1472 }       TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
1473 #endif
1474 // Debug counter
1475 #define TX_AGG_CNT3     0x172c
1476 #ifdef RT_BIG_ENDIAN
1477 typedef union   _TX_AGG_CNT3_STRUC      {
1478         struct  {
1479             USHORT  AggSize8Count;
1480             USHORT  AggSize7Count;
1481         }       field;
1482         UINT32                  word;
1483 }       TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
1484 #else
1485 typedef union   _TX_AGG_CNT3_STRUC      {
1486         struct  {
1487             USHORT  AggSize7Count;
1488             USHORT  AggSize8Count;
1489         }       field;
1490         UINT32                  word;
1491 }       TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
1492 #endif
1493 // Debug counter
1494 #define TX_AGG_CNT4     0x1730
1495 #ifdef RT_BIG_ENDIAN
1496 typedef union   _TX_AGG_CNT4_STRUC      {
1497         struct  {
1498             USHORT  AggSize10Count;
1499             USHORT  AggSize9Count;
1500         }       field;
1501         UINT32                  word;
1502 }       TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
1503 #else
1504 typedef union   _TX_AGG_CNT4_STRUC      {
1505         struct  {
1506             USHORT  AggSize9Count;
1507             USHORT  AggSize10Count;
1508         }       field;
1509         UINT32                  word;
1510 }       TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
1511 #endif
1512 #define TX_AGG_CNT5     0x1734
1513 #ifdef RT_BIG_ENDIAN
1514 typedef union   _TX_AGG_CNT5_STRUC      {
1515         struct  {
1516             USHORT  AggSize12Count;
1517             USHORT  AggSize11Count;
1518         }       field;
1519         UINT32                  word;
1520 }       TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
1521 #else
1522 typedef union   _TX_AGG_CNT5_STRUC      {
1523         struct  {
1524             USHORT  AggSize11Count;
1525             USHORT  AggSize12Count;
1526         }       field;
1527         UINT32                  word;
1528 }       TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
1529 #endif
1530 #define TX_AGG_CNT6             0x1738
1531 #ifdef RT_BIG_ENDIAN
1532 typedef union   _TX_AGG_CNT6_STRUC      {
1533         struct  {
1534             USHORT  AggSize14Count;
1535             USHORT  AggSize13Count;
1536         }       field;
1537         UINT32                  word;
1538 }       TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
1539 #else
1540 typedef union   _TX_AGG_CNT6_STRUC      {
1541         struct  {
1542             USHORT  AggSize13Count;
1543             USHORT  AggSize14Count;
1544         }       field;
1545         UINT32                  word;
1546 }       TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
1547 #endif
1548 #define TX_AGG_CNT7             0x173c
1549 #ifdef RT_BIG_ENDIAN
1550 typedef union   _TX_AGG_CNT7_STRUC      {
1551         struct  {
1552             USHORT  AggSize16Count;
1553             USHORT  AggSize15Count;
1554         }       field;
1555         UINT32                  word;
1556 }       TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
1557 #else
1558 typedef union   _TX_AGG_CNT7_STRUC      {
1559         struct  {
1560             USHORT  AggSize15Count;
1561             USHORT  AggSize16Count;
1562         }       field;
1563         UINT32                  word;
1564 }       TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
1565 #endif
1566 #define MPDU_DENSITY_CNT                0x1740
1567 #ifdef RT_BIG_ENDIAN
1568 typedef union   _MPDU_DEN_CNT_STRUC     {
1569         struct  {
1570             USHORT  RXZeroDelCount;     //RX zero length delimiter count
1571             USHORT  TXZeroDelCount;     //TX zero length delimiter count
1572         }       field;
1573         UINT32                  word;
1574 }       MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
1575 #else
1576 typedef union   _MPDU_DEN_CNT_STRUC     {
1577         struct  {
1578             USHORT  TXZeroDelCount;     //TX zero length delimiter count
1579             USHORT  RXZeroDelCount;     //RX zero length delimiter count
1580         }       field;
1581         UINT32                  word;
1582 }       MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
1583 #endif
1584 //
1585 // TXRX control registers - base address 0x3000
1586 //
1587 // rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1588 #define TXRX_CSR1           0x77d0
1589
1590 //
1591 // Security key table memory, base address = 0x1000
1592 //
1593 #define MAC_WCID_BASE           0x1800 //8-bytes(use only 6-bytes) * 256 entry =
1594 #define HW_WCID_ENTRY_SIZE   8
1595 #define PAIRWISE_KEY_TABLE_BASE     0x4000      // 32-byte * 256-entry =  -byte
1596 #define HW_KEY_ENTRY_SIZE           0x20
1597 #define PAIRWISE_IVEIV_TABLE_BASE     0x6000      // 8-byte * 256-entry =  -byte
1598 #define MAC_IVEIV_TABLE_BASE     0x6000      // 8-byte * 256-entry =  -byte
1599 #define HW_IVEIV_ENTRY_SIZE   8
1600 #define MAC_WCID_ATTRIBUTE_BASE     0x6800      // 4-byte * 256-entry =  -byte
1601 #define HW_WCID_ATTRI_SIZE   4
1602 #define WCID_RESERVED                   0x6bfc
1603 #define SHARED_KEY_TABLE_BASE       0x6c00      // 32-byte * 16-entry = 512-byte
1604 #define SHARED_KEY_MODE_BASE       0x7000      // 32-byte * 16-entry = 512-byte
1605 #define HW_SHARED_KEY_MODE_SIZE   4
1606 #define SHAREDKEYTABLE                  0
1607 #define PAIRWISEKEYTABLE                        1
1608
1609
1610 #ifdef RT_BIG_ENDIAN
1611 typedef union   _SHAREDKEY_MODE_STRUC   {
1612         struct  {
1613                 UINT32       :1;
1614                 UINT32       Bss1Key3CipherAlg:3;
1615                 UINT32       :1;
1616                 UINT32       Bss1Key2CipherAlg:3;
1617                 UINT32       :1;
1618                 UINT32       Bss1Key1CipherAlg:3;
1619                 UINT32       :1;
1620                 UINT32       Bss1Key0CipherAlg:3;
1621                 UINT32       :1;
1622                 UINT32       Bss0Key3CipherAlg:3;
1623                 UINT32       :1;
1624                 UINT32       Bss0Key2CipherAlg:3;
1625                 UINT32       :1;
1626                 UINT32       Bss0Key1CipherAlg:3;
1627                 UINT32       :1;
1628                 UINT32       Bss0Key0CipherAlg:3;
1629         }       field;
1630         UINT32                  word;
1631 }       SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1632 #else
1633 typedef union   _SHAREDKEY_MODE_STRUC   {
1634         struct  {
1635                 UINT32       Bss0Key0CipherAlg:3;
1636                 UINT32       :1;
1637                 UINT32       Bss0Key1CipherAlg:3;
1638                 UINT32       :1;
1639                 UINT32       Bss0Key2CipherAlg:3;
1640                 UINT32       :1;
1641                 UINT32       Bss0Key3CipherAlg:3;
1642                 UINT32       :1;
1643                 UINT32       Bss1Key0CipherAlg:3;
1644                 UINT32       :1;
1645                 UINT32       Bss1Key1CipherAlg:3;
1646                 UINT32       :1;
1647                 UINT32       Bss1Key2CipherAlg:3;
1648                 UINT32       :1;
1649                 UINT32       Bss1Key3CipherAlg:3;
1650                 UINT32       :1;
1651         }       field;
1652         UINT32                  word;
1653 }       SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1654 #endif
1655 // 64-entry for pairwise key table
1656 typedef struct _HW_WCID_ENTRY {  // 8-byte per entry
1657     UCHAR   Address[6];
1658     UCHAR   Rsv[2];
1659 } HW_WCID_ENTRY, PHW_WCID_ENTRY;
1660
1661
1662
1663 //
1664 // Other on-chip shared memory space, base = 0x2000
1665 //
1666
1667 // CIS space - base address = 0x2000
1668 #define HW_CIS_BASE             0x2000
1669
1670 // Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
1671 #define HW_CS_CTS_BASE                  0x7700
1672 // DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1673 #define HW_DFS_CTS_BASE                 0x7780
1674 #define HW_CTS_FRAME_SIZE               0x80
1675
1676 // 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
1677 // to save debugging settings
1678 #define HW_DEBUG_SETTING_BASE   0x77f0  // 0x77f0~0x77ff total 16 bytes
1679 #define HW_DEBUG_SETTING_BASE2   0x7770  // 0x77f0~0x77ff total 16 bytes
1680
1681 // In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
1682 // Three section discontinue memory segments will be used.
1683 // 1. The original region for BCN 0~3
1684 // 2. Extract memory from FCE table for BCN 4~5
1685 // 3. Extract memory from Pair-wise key table for BCN 6~7
1686 //        It occupied those memory of wcid 238~253 for BCN 6
1687 //                                                    and wcid 222~237 for BCN 7
1688 #define HW_BEACON_MAX_SIZE      0x1000 /* unit: byte */
1689 #define HW_BEACON_BASE0         0x7800
1690 #define HW_BEACON_BASE1         0x7A00
1691 #define HW_BEACON_BASE2         0x7C00
1692 #define HW_BEACON_BASE3         0x7E00
1693 #define HW_BEACON_BASE4         0x7200
1694 #define HW_BEACON_BASE5         0x7400
1695 #define HW_BEACON_BASE6         0x5DC0
1696 #define HW_BEACON_BASE7         0x5BC0
1697
1698 #define HW_BEACON_MAX_COUNT     8
1699 #define HW_BEACON_OFFSET                0x0200
1700 #define HW_BEACON_CONTENT_LEN   (HW_BEACON_OFFSET - TXWI_SIZE)
1701
1702 // HOST-MCU shared memory - base address = 0x2100
1703 #define HOST_CMD_CSR            0x404
1704 #define H2M_MAILBOX_CSR         0x7010
1705 #define H2M_MAILBOX_CID         0x7014
1706 #define H2M_MAILBOX_STATUS      0x701c
1707 #define H2M_INT_SRC             0x7024
1708 #define H2M_BBP_AGENT           0x7028
1709 #define M2H_CMD_DONE_CSR        0x000c
1710 #define MCU_TXOP_ARRAY_BASE     0x000c   // TODO: to be provided by Albert
1711 #define MCU_TXOP_ENTRY_SIZE     32       // TODO: to be provided by Albert
1712 #define MAX_NUM_OF_TXOP_ENTRY   16       // TODO: must be same with 8051 firmware
1713 #define MCU_MBOX_VERSION        0x01     // TODO: to be confirmed by Albert
1714 #define MCU_MBOX_VERSION_OFFSET 5        // TODO: to be provided by Albert
1715
1716 //
1717 // Host DMA registers - base address 0x200 .  TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
1718 //
1719 //
1720 //  DMA RING DESCRIPTOR
1721 //
1722 #define E2PROM_CSR          0x0004
1723 #define IO_CNTL_CSR         0x77d0
1724
1725 #ifdef RT2870
1726 // 8051 firmware image for usb - use last-half base address = 0x3000
1727 #define FIRMWARE_IMAGE_BASE     0x3000
1728 #define MAX_FIRMWARE_IMAGE_SIZE 0x1000    // 4kbyte
1729 #endif // RT2870 //
1730
1731 // TODO: ????? old RT2560 registers. to keep them or remove them?
1732 //#define MCAST0                  0x0178  // multicast filter register 0
1733 //#define MCAST1                  0x017c  // multicast filter register 1
1734
1735
1736 // ================================================================
1737 // Tx / Rx / Mgmt ring descriptor definition
1738 // ================================================================
1739
1740 // the following PID values are used to mark outgoing frame type in TXD->PID so that
1741 // proper TX statistics can be collected based on these categories
1742 // b3-2 of PID field -
1743 #define PID_MGMT                        0x05
1744 #define PID_BEACON                      0x0c
1745 #define PID_DATA_NORMALUCAST            0x02
1746 #define PID_DATA_AMPDU          0x04
1747 #define PID_DATA_NO_ACK         0x08
1748 #define PID_DATA_NOT_NORM_ACK           0x03
1749 // value domain of pTxD->HostQId (4-bit: 0~15)
1750 #define QID_AC_BK               1   // meet ACI definition in 802.11e
1751 #define QID_AC_BE               0   // meet ACI definition in 802.11e
1752 #define QID_AC_VI               2
1753 #define QID_AC_VO               3
1754 #define QID_HCCA                4
1755 #define NUM_OF_TX_RING          5
1756 #define QID_MGMT                13
1757 #define QID_RX                  14
1758 #define QID_OTHER               15
1759
1760
1761 // ------------------------------------------------------
1762 // BBP & RF     definition
1763 // ------------------------------------------------------
1764 #define BUSY                            1
1765 #define IDLE                            0
1766
1767 #define RF_R00                                      0
1768 #define RF_R01                                      1
1769 #define RF_R02                                      2
1770 #define RF_R03                                      3
1771 #define RF_R04                                      4
1772 #define RF_R05                                      5
1773 #define RF_R06                                      6
1774 #define RF_R07                                      7
1775 #define RF_R08                                      8
1776 #define RF_R09                                      9
1777 #define RF_R10                                      10
1778 #define RF_R11                                      11
1779 #define RF_R12                                      12
1780 #define RF_R13                                      13
1781 #define RF_R14                                      14
1782 #define RF_R15                                      15
1783 #define RF_R16                                      16
1784 #define RF_R17                                      17
1785 #define RF_R18                                      18
1786 #define RF_R19                                      19
1787 #define RF_R20                                      20
1788 #define RF_R21                                      21
1789 #define RF_R22                                      22
1790 #define RF_R23                                      23
1791 #define RF_R24                                      24
1792 #define RF_R25                                      25
1793 #define RF_R26                                      26
1794 #define RF_R27                                      27
1795 #define RF_R28                                      28
1796 #define RF_R29                                      29
1797 #define RF_R30                                      30
1798 #define RF_R31                                      31
1799
1800 #define BBP_R0                                      0  // version
1801 #define BBP_R1                                  1  // TSSI
1802 #define BBP_R2                                  2  // TX configure
1803 #define BBP_R3                      3
1804 #define BBP_R4                      4
1805 #define BBP_R5                      5
1806 #define BBP_R6                      6
1807 #define BBP_R14                             14 // RX configure
1808 #define BBP_R16                     16
1809 #define BBP_R17                     17 // RX sensibility
1810 #define BBP_R18                     18
1811 #define BBP_R21                     21
1812 #define BBP_R22                     22
1813 #define BBP_R24                     24
1814 #define BBP_R25                     25
1815 #define BBP_R31                     31
1816 #define BBP_R49                     49 //TSSI
1817 #define BBP_R50                     50
1818 #define BBP_R51                     51
1819 #define BBP_R52                     52
1820 #define BBP_R55                     55
1821 #define BBP_R62                     62 // Rx SQ0 Threshold HIGH
1822 #define BBP_R63                     63
1823 #define BBP_R64                     64
1824 #define BBP_R65                     65
1825 #define BBP_R66                     66
1826 #define BBP_R67                     67
1827 #define BBP_R68                     68
1828 #define BBP_R69                     69
1829 #define BBP_R70                     70 // Rx AGC SQ CCK Xcorr threshold
1830 #define BBP_R73                     73
1831 #define BBP_R75                                         75
1832 #define BBP_R77                     77
1833 #define BBP_R79                     79
1834 #define BBP_R80                     80
1835 #define BBP_R81                     81
1836 #define BBP_R82                     82
1837 #define BBP_R83                     83
1838 #define BBP_R84                     84
1839 #define BBP_R86                                         86
1840 #define BBP_R91                                         91
1841 #define BBP_R92                                         92
1842 #define BBP_R94                     94 // Tx Gain Control
1843 #define BBP_R103                    103
1844 #define BBP_R105                    105
1845 #define BBP_R113                    113
1846 #define BBP_R114                    114
1847 #define BBP_R115                    115
1848 #define BBP_R116                    116
1849 #define BBP_R117                    117
1850 #define BBP_R118                    118
1851 #define BBP_R119                    119
1852 #define BBP_R120                    120
1853 #define BBP_R121                    121
1854 #define BBP_R122                    122
1855 #define BBP_R123                    123
1856 #ifdef RT30xx
1857 #define BBP_R138                    138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
1858 #endif // RT30xx //
1859
1860
1861 #define BBPR94_DEFAULT              0x06 // Add 1 value will gain 1db
1862
1863 //#define PHY_TR_SWITCH_TIME          5  // usec
1864
1865 //#define BBP_R17_LOW_SENSIBILITY     0x50
1866 //#define BBP_R17_MID_SENSIBILITY     0x41
1867 //#define BBP_R17_DYNAMIC_UP_BOUND    0x40
1868 #define RSSI_FOR_VERY_LOW_SENSIBILITY -35
1869 #define RSSI_FOR_LOW_SENSIBILITY      -58
1870 #define RSSI_FOR_MID_LOW_SENSIBILITY  -80
1871 #define RSSI_FOR_MID_SENSIBILITY      -90
1872
1873 //-------------------------------------------------------------------------
1874 // EEPROM definition
1875 //-------------------------------------------------------------------------
1876 #define EEDO                        0x08
1877 #define EEDI                        0x04
1878 #define EECS                        0x02
1879 #define EESK                        0x01
1880 #define EERL                        0x80
1881
1882 #define EEPROM_WRITE_OPCODE         0x05
1883 #define EEPROM_READ_OPCODE          0x06
1884 #define EEPROM_EWDS_OPCODE          0x10
1885 #define EEPROM_EWEN_OPCODE          0x13
1886
1887 #define NUM_EEPROM_BBP_PARMS            19                      // Include NIC Config 0, 1, CR, TX ALC step, BBPs
1888 #define NUM_EEPROM_TX_G_PARMS           7
1889 #define EEPROM_NIC1_OFFSET          0x34                // The address is from NIC config 0, not BBP register ID
1890 #define EEPROM_NIC2_OFFSET          0x36                // The address is from NIC config 0, not BBP register ID
1891 #define EEPROM_BBP_BASE_OFFSET          0xf0            // The address is from NIC config 0, not BBP register ID
1892 #define EEPROM_G_TX_PWR_OFFSET          0x52
1893 #define EEPROM_G_TX2_PWR_OFFSET         0x60
1894 #define EEPROM_LED1_OFFSET                      0x3c
1895 #define EEPROM_LED2_OFFSET                      0x3e
1896 #define EEPROM_LED3_OFFSET                      0x40
1897 #define EEPROM_LNA_OFFSET                       0x44
1898 #define EEPROM_RSSI_BG_OFFSET           0x46
1899 #define EEPROM_RSSI_A_OFFSET            0x4a
1900 #define EEPROM_DEFINE_MAX_TXPWR         0x4e
1901 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G        0xde    // 20MHZ 2.4G tx power.
1902 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G        0xee    // 40MHZ 2.4G tx power.
1903 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G          0xfa    // 20MHZ 5G tx power.
1904 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G          0x10a   // 40MHZ 5G tx power.
1905 #define EEPROM_A_TX_PWR_OFFSET      0x78
1906 #define EEPROM_A_TX2_PWR_OFFSET      0xa6
1907 //#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j
1908 //#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe
1909 //#define EEPROM_TSSI_REF_OFFSET        0x54
1910 //#define EEPROM_TSSI_DELTA_OFFSET      0x24
1911 //#define EEPROM_CCK_TX_PWR_OFFSET  0x62
1912 //#define EEPROM_CALIBRATE_OFFSET       0x7c
1913 #define EEPROM_VERSION_OFFSET       0x02
1914 #define EEPROM_FREQ_OFFSET                      0x3a
1915 #define EEPROM_TXPOWER_BYRATE   0xde    // 20MHZ power.
1916 #define EEPROM_TXPOWER_DELTA            0x50    // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
1917 #define VALID_EEPROM_VERSION        1
1918
1919 // PairKeyMode definition
1920 #define PKMODE_NONE                 0
1921 #define PKMODE_WEP64                1
1922 #define PKMODE_WEP128               2
1923 #define PKMODE_TKIP                 3
1924 #define PKMODE_AES                  4
1925 #define PKMODE_CKIP64               5
1926 #define PKMODE_CKIP128              6
1927 #define PKMODE_TKIP_NO_MIC          7       // MIC appended by driver: not a valid value in hardware key table
1928
1929 // =================================================================================
1930 // WCID  format
1931 // =================================================================================
1932 //7.1   WCID  ENTRY  format  : 8bytes
1933 typedef struct  _WCID_ENTRY_STRUC {
1934         UCHAR           RXBABitmap7;    // bit0 for TID8, bit7 for TID 15
1935         UCHAR           RXBABitmap0;    // bit0 for TID0, bit7 for TID 7
1936         UCHAR           MAC[6]; // 0 for shared key table.  1 for pairwise key table
1937 }       WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
1938
1939 //8.1.1 SECURITY  KEY  format  : 8DW
1940 // 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
1941 typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
1942     UCHAR   Key[16];
1943     UCHAR   TxMic[8];
1944     UCHAR   RxMic[8];
1945 } HW_KEY_ENTRY, *PHW_KEY_ENTRY;
1946
1947 //8.1.2 IV/EIV  format  : 2DW
1948
1949 //8.1.3 RX attribute entry format  : 1DW
1950 #ifdef RT_BIG_ENDIAN
1951 typedef struct  _MAC_ATTRIBUTE_STRUC {
1952         UINT32          rsv:22;
1953         UINT32          RXWIUDF:3;
1954         UINT32          BSSIDIdx:3; //multipleBSS index for the WCID
1955         UINT32          PairKeyMode:3;
1956         UINT32          KeyTab:1;       // 0 for shared key table.  1 for pairwise key table
1957 }       MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1958 #else
1959 typedef struct  _MAC_ATTRIBUTE_STRUC {
1960         UINT32          KeyTab:1;       // 0 for shared key table.  1 for pairwise key table
1961         UINT32          PairKeyMode:3;
1962         UINT32          BSSIDIdx:3; //multipleBSS index for the WCID
1963         UINT32          RXWIUDF:3;
1964         UINT32          rsv:22;
1965 }       MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
1966 #endif
1967
1968
1969 // =================================================================================
1970 // TX / RX ring descriptor format
1971 // =================================================================================
1972
1973 // the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
1974 // MAC block use this TXINFO to control the transmission behavior of this frame.
1975 #define FIFO_MGMT                 0
1976 #define FIFO_HCCA                 1
1977 #define FIFO_EDCA                 2
1978
1979 //
1980 // TX descriptor format, Tx     ring, Mgmt Ring
1981 //
1982 #ifdef RT_BIG_ENDIAN
1983 typedef struct  PACKED _TXD_STRUC {
1984         // Word 0
1985         UINT32          SDPtr0;
1986         // Word 1
1987         UINT32          DMADONE:1;
1988         UINT32          LastSec0:1;
1989         UINT32          SDLen0:14;
1990         UINT32          Burst:1;
1991         UINT32          LastSec1:1;
1992         UINT32          SDLen1:14;
1993         // Word 2
1994         UINT32          SDPtr1;
1995         // Word 3
1996         UINT32          ICO:1;
1997         UINT32          UCO:1;
1998         UINT32          TCO:1;
1999         UINT32          rsv:2;
2000         UINT32          QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
2001         UINT32          WIV:1;  // Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
2002         UINT32          rsv2:24;
2003 }       TXD_STRUC, *PTXD_STRUC;
2004 #else
2005 typedef struct  PACKED _TXD_STRUC {
2006         // Word 0
2007         UINT32          SDPtr0;
2008         // Word 1
2009         UINT32          SDLen1:14;
2010         UINT32          LastSec1:1;
2011         UINT32          Burst:1;
2012         UINT32          SDLen0:14;
2013         UINT32          LastSec0:1;
2014         UINT32          DMADONE:1;
2015         //Word2
2016         UINT32          SDPtr1;
2017         //Word3
2018         UINT32          rsv2:24;
2019         UINT32          WIV:1;  // Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
2020         UINT32          QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
2021         UINT32          rsv:2;
2022         UINT32          TCO:1;  //
2023         UINT32          UCO:1;  //
2024         UINT32          ICO:1;  //
2025 }       TXD_STRUC, *PTXD_STRUC;
2026 #endif
2027
2028
2029 //
2030 // TXD Wireless Information format for Tx ring and Mgmt Ring
2031 //
2032 //txop : for txop mode
2033 // 0:txop for the MPDU frame will be handles by ASIC by register
2034 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
2035 #ifdef RT_BIG_ENDIAN
2036 typedef struct  PACKED _TXWI_STRUC {
2037         // Word 0
2038         UINT32          PHYMODE:2;
2039         UINT32          TxBF:1; // 3*3
2040         UINT32          rsv2:1;
2041 //      UINT32          rsv2:2;
2042         UINT32          Ifs:1;  //
2043         UINT32          STBC:2; //channel bandwidth 20MHz or 40 MHz
2044         UINT32          ShortGI:1;
2045         UINT32          BW:1;   //channel bandwidth 20MHz or 40 MHz
2046         UINT32          MCS:7;
2047
2048         UINT32          rsv:6;
2049         UINT32          txop:2; //tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
2050         UINT32          MpduDensity:3;
2051         UINT32          AMPDU:1;
2052
2053         UINT32          TS:1;
2054         UINT32          CFACK:1;
2055         UINT32          MIMOps:1;       // the remote peer is in dynamic MIMO-PS mode
2056         UINT32          FRAG:1;         // 1 to inform TKIP engine this is a fragment.
2057         // Word 1
2058         UINT32          PacketId:4;
2059         UINT32          MPDUtotalByteCount:12;
2060         UINT32          WirelessCliID:8;
2061         UINT32          BAWinSize:6;
2062         UINT32          NSEQ:1;
2063         UINT32          ACK:1;
2064         // Word 2
2065         UINT32          IV;
2066         // Word 3
2067         UINT32          EIV;
2068 }       TXWI_STRUC, *PTXWI_STRUC;
2069 #else
2070 typedef struct  PACKED _TXWI_STRUC {
2071         // Word 0
2072         UINT32          FRAG:1;         // 1 to inform TKIP engine this is a fragment.
2073         UINT32          MIMOps:1;       // the remote peer is in dynamic MIMO-PS mode
2074         UINT32          CFACK:1;
2075         UINT32          TS:1;
2076
2077         UINT32          AMPDU:1;
2078         UINT32          MpduDensity:3;
2079         UINT32          txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
2080         UINT32          rsv:6;
2081
2082         UINT32          MCS:7;
2083         UINT32          BW:1;   //channel bandwidth 20MHz or 40 MHz
2084         UINT32          ShortGI:1;
2085         UINT32          STBC:2; // 1: STBC support MCS =0-7,   2,3 : RESERVE
2086         UINT32          Ifs:1;  //
2087 //      UINT32          rsv2:2; //channel bandwidth 20MHz or 40 MHz
2088         UINT32          rsv2:1;
2089         UINT32          TxBF:1; // 3*3
2090         UINT32          PHYMODE:2;
2091         // Word 1
2092         UINT32          ACK:1;
2093         UINT32          NSEQ:1;
2094         UINT32          BAWinSize:6;
2095         UINT32          WirelessCliID:8;
2096         UINT32          MPDUtotalByteCount:12;
2097         UINT32          PacketId:4;
2098         //Word2
2099         UINT32          IV;
2100         //Word3
2101         UINT32          EIV;
2102 }       TXWI_STRUC, *PTXWI_STRUC;
2103 #endif
2104 //
2105 // Rx descriptor format, Rx     Ring
2106 //
2107 //
2108 // RXWI wireless information format, in PBF. invisible in driver.
2109 //
2110 #ifdef RT_BIG_ENDIAN
2111 typedef struct  PACKED _RXWI_STRUC {
2112         // Word 0
2113         UINT32          TID:4;
2114         UINT32          MPDUtotalByteCount:12;
2115         UINT32          UDF:3;
2116         UINT32          BSSID:3;
2117         UINT32          KeyIndex:2;
2118         UINT32          WirelessCliID:8;
2119         // Word 1
2120         UINT32          PHYMODE:2;              // 1: this RX frame is unicast to me
2121         UINT32          rsv:3;
2122         UINT32          STBC:2;
2123         UINT32          ShortGI:1;
2124         UINT32          BW:1;
2125         UINT32          MCS:7;
2126         UINT32          SEQUENCE:12;
2127         UINT32          FRAG:4;
2128         // Word 2
2129         UINT32          rsv1:8;
2130         UINT32          RSSI2:8;
2131         UINT32          RSSI1:8;
2132         UINT32          RSSI0:8;
2133         // Word 3
2134         UINT32          rsv2:16;
2135         UINT32          SNR1:8;
2136         UINT32          SNR0:8;
2137 }       RXWI_STRUC, *PRXWI_STRUC;
2138 #else
2139 typedef struct  PACKED _RXWI_STRUC {
2140         // Word 0
2141         UINT32          WirelessCliID:8;
2142         UINT32          KeyIndex:2;
2143         UINT32          BSSID:3;
2144         UINT32          UDF:3;
2145         UINT32          MPDUtotalByteCount:12;
2146         UINT32          TID:4;
2147         // Word 1
2148         UINT32          FRAG:4;
2149         UINT32          SEQUENCE:12;
2150         UINT32          MCS:7;
2151         UINT32          BW:1;
2152         UINT32          ShortGI:1;
2153         UINT32          STBC:2;
2154         UINT32          rsv:3;
2155         UINT32          PHYMODE:2;              // 1: this RX frame is unicast to me
2156         //Word2
2157         UINT32          RSSI0:8;
2158         UINT32          RSSI1:8;
2159         UINT32          RSSI2:8;
2160         UINT32          rsv1:8;
2161         //Word3
2162         UINT32          SNR0:8;
2163         UINT32          SNR1:8;
2164         UINT32          rsv2:16;
2165 }       RXWI_STRUC, *PRXWI_STRUC;
2166 #endif
2167
2168
2169 // =================================================================================
2170 // HOST-MCU communication data structure
2171 // =================================================================================
2172
2173 //
2174 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
2175 //
2176 #ifdef RT_BIG_ENDIAN
2177 typedef union  _H2M_MAILBOX_STRUC {
2178     struct {
2179         UINT32       Owner:8;
2180         UINT32       CmdToken:8;    // 0xff tells MCU not to report CmdDoneInt after excuting the command
2181         UINT32       HighByte:8;
2182         UINT32       LowByte:8;
2183     }   field;
2184     UINT32           word;
2185 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
2186 #else
2187 typedef union  _H2M_MAILBOX_STRUC {
2188     struct {
2189         UINT32       LowByte:8;
2190         UINT32       HighByte:8;
2191         UINT32       CmdToken:8;
2192         UINT32       Owner:8;
2193     }   field;
2194     UINT32           word;
2195 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
2196 #endif
2197
2198 //
2199 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
2200 //
2201 #ifdef RT_BIG_ENDIAN
2202 typedef union _M2H_CMD_DONE_STRUC {
2203     struct  {
2204         UINT32       CmdToken3;
2205         UINT32       CmdToken2;
2206         UINT32       CmdToken1;
2207         UINT32       CmdToken0;
2208     } field;
2209     UINT32           word;
2210 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
2211 #else
2212 typedef union _M2H_CMD_DONE_STRUC {
2213     struct  {
2214         UINT32       CmdToken0;
2215         UINT32       CmdToken1;
2216         UINT32       CmdToken2;
2217         UINT32       CmdToken3;
2218     } field;
2219     UINT32           word;
2220 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
2221 #endif
2222
2223
2224
2225 //
2226 // MCU_LEDCS: MCU LED Control Setting.
2227 //
2228 #ifdef RT_BIG_ENDIAN
2229 typedef union  _MCU_LEDCS_STRUC {
2230         struct  {
2231                 UCHAR           Polarity:1;
2232                 UCHAR           LedMode:7;
2233         } field;
2234         UCHAR                           word;
2235 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
2236 #else
2237 typedef union  _MCU_LEDCS_STRUC {
2238         struct  {
2239                 UCHAR           LedMode:7;
2240                 UCHAR           Polarity:1;
2241         } field;
2242         UCHAR                   word;
2243 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
2244 #endif
2245 // =================================================================================
2246 // Register format
2247 // =================================================================================
2248
2249
2250
2251 //NAV_TIME_CFG :NAV
2252 #ifdef RT_BIG_ENDIAN
2253 typedef union   _NAV_TIME_CFG_STRUC     {
2254         struct  {
2255                 USHORT          rsv:6;
2256                 USHORT          ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
2257                 USHORT          Eifs:9;               // in unit of 1-us
2258                 UCHAR       SlotTime;    // in unit of 1-us
2259                 UCHAR           Sifs;               // in unit of 1-us
2260         }       field;
2261         UINT32                  word;
2262 }       NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
2263 #else
2264 typedef union   _NAV_TIME_CFG_STRUC     {
2265         struct  {
2266                 UCHAR           Sifs;               // in unit of 1-us
2267                 UCHAR       SlotTime;    // in unit of 1-us
2268                 USHORT          Eifs:9;               // in unit of 1-us
2269                 USHORT          ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
2270                 USHORT          rsv:6;
2271         }       field;
2272         UINT32                  word;
2273 }       NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
2274 #endif
2275
2276
2277
2278
2279
2280 //
2281 // RX_FILTR_CFG:  /RX configuration register
2282 //
2283 #ifdef RT_BIG_ENDIAN
2284 typedef union   RX_FILTR_CFG_STRUC      {
2285         struct  {
2286                 UINT32          :15;
2287                 UINT32       DropRsvCntlType:1;
2288
2289                 UINT32          DropBAR:1;       //
2290                 UINT32          DropBA:1;               //
2291                 UINT32          DropPsPoll:1;           // Drop Ps-Poll
2292                 UINT32          DropRts:1;              // Drop Ps-Poll
2293
2294                 UINT32          DropCts:1;              // Drop Ps-Poll
2295                 UINT32          DropAck:1;              // Drop Ps-Poll
2296                 UINT32          DropCFEnd:1;            // Drop Ps-Poll
2297                 UINT32          DropCFEndAck:1;         // Drop Ps-Poll
2298
2299                 UINT32          DropDuplicate:1;                // Drop duplicate frame
2300                 UINT32          DropBcast:1;            // Drop broadcast frames
2301                 UINT32          DropMcast:1;            // Drop multicast frames
2302                 UINT32          DropVerErr:1;       // Drop version error frame
2303
2304                 UINT32          DropNotMyBSSID:1;                       // Drop fram ToDs bit is true
2305                 UINT32          DropNotToMe:1;          // Drop not to me unicast frame
2306                 UINT32          DropPhyErr:1;           // Drop physical error
2307                 UINT32          DropCRCErr:1;           // Drop CRC error
2308         }       field;
2309         UINT32                  word;
2310 }       RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
2311 #else
2312 typedef union   _RX_FILTR_CFG_STRUC     {
2313         struct  {
2314                 UINT32          DropCRCErr:1;           // Drop CRC error
2315                 UINT32          DropPhyErr:1;           // Drop physical error
2316                 UINT32          DropNotToMe:1;          // Drop not to me unicast frame
2317                 UINT32          DropNotMyBSSID:1;                       // Drop fram ToDs bit is true
2318
2319                 UINT32          DropVerErr:1;       // Drop version error frame
2320                 UINT32          DropMcast:1;            // Drop multicast frames
2321                 UINT32          DropBcast:1;            // Drop broadcast frames
2322                 UINT32          DropDuplicate:1;                // Drop duplicate frame
2323
2324                 UINT32          DropCFEndAck:1;         // Drop Ps-Poll
2325                 UINT32          DropCFEnd:1;            // Drop Ps-Poll
2326                 UINT32          DropAck:1;              // Drop Ps-Poll
2327                 UINT32          DropCts:1;              // Drop Ps-Poll
2328
2329                 UINT32          DropRts:1;              // Drop Ps-Poll
2330                 UINT32          DropPsPoll:1;           // Drop Ps-Poll
2331                 UINT32          DropBA:1;               //
2332                 UINT32          DropBAR:1;       //
2333
2334                 UINT32          DropRsvCntlType:1;
2335                 UINT32          :15;
2336         }       field;
2337         UINT32                  word;
2338 }       RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
2339 #endif
2340
2341
2342
2343
2344 //
2345 // PHY_CSR4: RF serial control register
2346 //
2347 #ifdef RT_BIG_ENDIAN
2348 typedef union   _PHY_CSR4_STRUC {
2349         struct  {
2350                 UINT32          Busy:1;                         // 1: ASIC is busy execute RF programming.
2351                 UINT32          PLL_LD:1;                       // RF PLL_LD status
2352                 UINT32          IFSelect:1;                     // 1: select IF to program,     0: select RF to program
2353                 UINT32          NumberOfBits:5;         // Number of bits used in RFRegValue (I:20,     RFMD:22)
2354                 UINT32          RFRegValue:24;          // Register     value (include register id)     serial out to RF/IF     chip.
2355         }       field;
2356         UINT32                  word;
2357 }       PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
2358 #else
2359 typedef union   _PHY_CSR4_STRUC {
2360         struct  {
2361                 UINT32          RFRegValue:24;          // Register     value (include register id)     serial out to RF/IF     chip.
2362                 UINT32          NumberOfBits:5;         // Number of bits used in RFRegValue (I:20,     RFMD:22)
2363                 UINT32          IFSelect:1;                     // 1: select IF to program,     0: select RF to program
2364                 UINT32          PLL_LD:1;                       // RF PLL_LD status
2365                 UINT32          Busy:1;                         // 1: ASIC is busy execute RF programming.
2366         }       field;
2367         UINT32                  word;
2368 }       PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
2369 #endif
2370
2371
2372 //
2373 // SEC_CSR5: shared key table security mode register
2374 //
2375 #ifdef RT_BIG_ENDIAN
2376 typedef union   _SEC_CSR5_STRUC {
2377         struct  {
2378         UINT32       :1;
2379         UINT32       Bss3Key3CipherAlg:3;
2380         UINT32       :1;
2381         UINT32       Bss3Key2CipherAlg:3;
2382         UINT32       :1;
2383         UINT32       Bss3Key1CipherAlg:3;
2384         UINT32       :1;
2385         UINT32       Bss3Key0CipherAlg:3;
2386         UINT32       :1;
2387         UINT32       Bss2Key3CipherAlg:3;
2388         UINT32       :1;
2389         UINT32       Bss2Key2CipherAlg:3;
2390         UINT32       :1;
2391         UINT32       Bss2Key1CipherAlg:3;
2392         UINT32       :1;
2393         UINT32       Bss2Key0CipherAlg:3;
2394         }       field;
2395         UINT32                  word;
2396 }       SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
2397 #else
2398 typedef union   _SEC_CSR5_STRUC {
2399         struct  {
2400         UINT32       Bss2Key0CipherAlg:3;
2401         UINT32       :1;
2402         UINT32       Bss2Key1CipherAlg:3;
2403         UINT32       :1;
2404         UINT32       Bss2Key2CipherAlg:3;
2405         UINT32       :1;
2406         UINT32       Bss2Key3CipherAlg:3;
2407         UINT32       :1;
2408         UINT32       Bss3Key0CipherAlg:3;
2409         UINT32       :1;
2410         UINT32       Bss3Key1CipherAlg:3;
2411         UINT32       :1;
2412         UINT32       Bss3Key2CipherAlg:3;
2413         UINT32       :1;
2414         UINT32       Bss3Key3CipherAlg:3;
2415         UINT32       :1;
2416         }       field;
2417         UINT32                  word;
2418 }       SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
2419 #endif
2420
2421
2422 //
2423 // HOST_CMD_CSR: For HOST to interrupt embedded processor
2424 //
2425 #ifdef RT_BIG_ENDIAN
2426 typedef union   _HOST_CMD_CSR_STRUC     {
2427         struct  {
2428             UINT32   Rsv:24;
2429             UINT32   HostCommand:8;
2430         }       field;
2431         UINT32                  word;
2432 }       HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
2433 #else
2434 typedef union   _HOST_CMD_CSR_STRUC     {
2435         struct  {
2436             UINT32   HostCommand:8;
2437             UINT32   Rsv:24;
2438         }       field;
2439         UINT32                  word;
2440 }       HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
2441 #endif
2442
2443
2444 //
2445 // AIFSN_CSR: AIFSN for each EDCA AC
2446 //
2447
2448
2449
2450 //
2451 // E2PROM_CSR: EEPROM control register
2452 //
2453 #ifdef RT_BIG_ENDIAN
2454 typedef union   _E2PROM_CSR_STRUC       {
2455         struct  {
2456                 UINT32          Rsvd:25;
2457                 UINT32       LoadStatus:1;   // 1:loading, 0:done
2458                 UINT32          Type:1;                 // 1: 93C46, 0:93C66
2459                 UINT32          EepromDO:1;
2460                 UINT32          EepromDI:1;
2461                 UINT32          EepromCS:1;
2462                 UINT32          EepromSK:1;
2463                 UINT32          Reload:1;               // Reload EEPROM content, write one to reload, self-cleared.
2464         }       field;
2465         UINT32                  word;
2466 }       E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
2467 #else
2468 typedef union   _E2PROM_CSR_STRUC       {
2469         struct  {
2470                 UINT32          Reload:1;               // Reload EEPROM content, write one to reload, self-cleared.
2471                 UINT32          EepromSK:1;
2472                 UINT32          EepromCS:1;
2473                 UINT32          EepromDI:1;
2474                 UINT32          EepromDO:1;
2475                 UINT32          Type:1;                 // 1: 93C46, 0:93C66
2476                 UINT32       LoadStatus:1;   // 1:loading, 0:done
2477                 UINT32          Rsvd:25;
2478         }       field;
2479         UINT32                  word;
2480 }       E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
2481 #endif
2482
2483
2484 // -------------------------------------------------------------------
2485 //  E2PROM data layout
2486 // -------------------------------------------------------------------
2487
2488 //
2489 // EEPROM antenna select format
2490 //
2491 #ifdef RT_BIG_ENDIAN
2492 typedef union   _EEPROM_ANTENNA_STRUC   {
2493         struct  {
2494                 USHORT      Rsv:4;
2495                 USHORT      RfIcType:4;             // see E2PROM document
2496                 USHORT          TxPath:4;       // 1: 1T, 2: 2T
2497                 USHORT          RxPath:4;       // 1: 1R, 2: 2R, 3: 3R
2498         }       field;
2499         USHORT                  word;
2500 }       EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
2501 #else
2502 typedef union   _EEPROM_ANTENNA_STRUC   {
2503         struct  {
2504                 USHORT          RxPath:4;       // 1: 1R, 2: 2R, 3: 3R
2505                 USHORT          TxPath:4;       // 1: 1T, 2: 2T
2506                 USHORT      RfIcType:4;             // see E2PROM document
2507                 USHORT      Rsv:4;
2508         }       field;
2509         USHORT                  word;
2510 }       EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
2511 #endif
2512
2513 #ifdef RT_BIG_ENDIAN
2514 typedef union _EEPROM_NIC_CINFIG2_STRUC {
2515         struct  {
2516         USHORT          DACTestBit:1;                   // control if driver should patch the DAC issue
2517                 USHORT          Rsv2:3;                                 // must be 0
2518         USHORT          AntDiversity:1;                 // Antenna diversity
2519                 USHORT          Rsv1:1;                                 // must be 0
2520                 USHORT          BW40MAvailForA:1;                       // 0:enable, 1:disable
2521                 USHORT          BW40MAvailForG:1;                       // 0:enable, 1:disable
2522                 USHORT          EnableWPSPBC:1;                 // WPS PBC Control bit
2523                 USHORT          BW40MSidebandForA:1;
2524                 USHORT          BW40MSidebandForG:1;
2525                 USHORT          CardbusAcceleration:1;  // !!! NOTE: 0 - enable, 1 - disable
2526                 USHORT          ExternalLNAForA:1;                      // external LNA enable for 5G
2527                 USHORT          ExternalLNAForG:1;                      // external LNA enable for 2.4G
2528                 USHORT          DynamicTxAgcControl:1;                  //
2529                 USHORT          HardwareRadioControl:1; // Whether RF is controlled by driver or HW. 1:enable hw control, 0:disable
2530         }       field;
2531         USHORT                  word;
2532 }       EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
2533 #else
2534 typedef union _EEPROM_NIC_CINFIG2_STRUC {
2535         struct {
2536                 USHORT          HardwareRadioControl:1; // 1:enable, 0:disable
2537                 USHORT          DynamicTxAgcControl:1;                  //
2538                 USHORT          ExternalLNAForG:1;                              //
2539                 USHORT          ExternalLNAForA:1;                      // external LNA enable for 2.4G
2540                 USHORT          CardbusAcceleration:1;  // !!! NOTE: 0 - enable, 1 - disable
2541                 USHORT          BW40MSidebandForG:1;
2542                 USHORT          BW40MSidebandForA:1;
2543                 USHORT          EnableWPSPBC:1;                 // WPS PBC Control bit
2544                 USHORT          BW40MAvailForG:1;                       // 0:enable, 1:disable
2545                 USHORT          BW40MAvailForA:1;                       // 0:enable, 1:disable
2546                 USHORT          Rsv1:1;                                 // must be 0
2547                 USHORT          AntDiversity:1;                 // Antenna diversity
2548                 USHORT          Rsv2:3;                                 // must be 0
2549                 USHORT          DACTestBit:1;                   // control if driver should patch the DAC issue
2550         }       field;
2551         USHORT                  word;
2552 }       EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
2553 #endif
2554
2555 //
2556 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
2557 //
2558 #ifdef RT_BIG_ENDIAN
2559 typedef union   _EEPROM_TX_PWR_STRUC    {
2560         struct  {
2561                 CHAR    Byte1;                          // High Byte
2562                 CHAR    Byte0;                          // Low Byte
2563         }       field;
2564         USHORT  word;
2565 }       EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
2566 #else
2567 typedef union   _EEPROM_TX_PWR_STRUC    {
2568         struct  {
2569                 CHAR    Byte0;                          // Low Byte
2570                 CHAR    Byte1;                          // High Byte
2571         }       field;
2572         USHORT  word;
2573 }       EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
2574 #endif
2575
2576 #ifdef RT_BIG_ENDIAN
2577 typedef union   _EEPROM_VERSION_STRUC   {
2578         struct  {
2579                 UCHAR   Version;                        // High Byte
2580                 UCHAR   FaeReleaseNumber;       // Low Byte
2581         }       field;
2582         USHORT  word;
2583 }       EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
2584 #else
2585 typedef union   _EEPROM_VERSION_STRUC   {
2586         struct  {
2587                 UCHAR   FaeReleaseNumber;       // Low Byte
2588                 UCHAR   Version;                        // High Byte
2589         }       field;
2590         USHORT  word;
2591 }       EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
2592 #endif
2593
2594 #ifdef RT_BIG_ENDIAN
2595 typedef union   _EEPROM_LED_STRUC       {
2596         struct  {
2597                 USHORT  Rsvd:3;                         // Reserved
2598                 USHORT  LedMode:5;                      // Led mode.
2599                 USHORT  PolarityGPIO_4:1;       // Polarity GPIO#4 setting.
2600                 USHORT  PolarityGPIO_3:1;       // Polarity GPIO#3 setting.
2601                 USHORT  PolarityGPIO_2:1;       // Polarity GPIO#2 setting.
2602                 USHORT  PolarityGPIO_1:1;       // Polarity GPIO#1 setting.
2603                 USHORT  PolarityGPIO_0:1;       // Polarity GPIO#0 setting.
2604                 USHORT  PolarityACT:1;          // Polarity ACT setting.
2605                 USHORT  PolarityRDY_A:1;                // Polarity RDY_A setting.
2606                 USHORT  PolarityRDY_G:1;                // Polarity RDY_G setting.
2607         }       field;
2608         USHORT  word;
2609 }       EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
2610 #else
2611 typedef union   _EEPROM_LED_STRUC       {
2612         struct  {
2613                 USHORT  PolarityRDY_G:1;                // Polarity RDY_G setting.
2614                 USHORT  PolarityRDY_A:1;                // Polarity RDY_A setting.
2615                 USHORT  PolarityACT:1;          // Polarity ACT setting.
2616                 USHORT  PolarityGPIO_0:1;       // Polarity GPIO#0 setting.
2617                 USHORT  PolarityGPIO_1:1;       // Polarity GPIO#1 setting.
2618                 USHORT  PolarityGPIO_2:1;       // Polarity GPIO#2 setting.
2619                 USHORT  PolarityGPIO_3:1;       // Polarity GPIO#3 setting.
2620                 USHORT  PolarityGPIO_4:1;       // Polarity GPIO#4 setting.
2621                 USHORT  LedMode:5;                      // Led mode.
2622                 USHORT  Rsvd:3;                         // Reserved
2623         }       field;
2624         USHORT  word;
2625 }       EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
2626 #endif
2627
2628 #ifdef RT_BIG_ENDIAN
2629 typedef union   _EEPROM_TXPOWER_DELTA_STRUC     {
2630         struct  {
2631                 UCHAR   TxPowerEnable:1;// Enable
2632                 UCHAR   Type:1;                 // 1: plus the delta value, 0: minus the delta value
2633                 UCHAR   DeltaValue:6;   // Tx Power dalta value (MAX=4)
2634         }       field;
2635         UCHAR   value;
2636 }       EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
2637 #else
2638 typedef union   _EEPROM_TXPOWER_DELTA_STRUC     {
2639         struct  {
2640                 UCHAR   DeltaValue:6;   // Tx Power dalta value (MAX=4)
2641                 UCHAR   Type:1;                 // 1: plus the delta value, 0: minus the delta value
2642                 UCHAR   TxPowerEnable:1;// Enable
2643         }       field;
2644         UCHAR   value;
2645 }       EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
2646 #endif
2647
2648 //
2649 // QOS_CSR0: TXOP holder address0 register
2650 //
2651 #ifdef RT_BIG_ENDIAN
2652 typedef union   _QOS_CSR0_STRUC {
2653         struct  {
2654                 UCHAR           Byte3;          // MAC address byte 3
2655                 UCHAR           Byte2;          // MAC address byte 2
2656                 UCHAR           Byte1;          // MAC address byte 1
2657                 UCHAR           Byte0;          // MAC address byte 0
2658         }       field;
2659         UINT32                  word;
2660 }       QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
2661 #else
2662 typedef union   _QOS_CSR0_STRUC {
2663         struct  {
2664                 UCHAR           Byte0;          // MAC address byte 0
2665                 UCHAR           Byte1;          // MAC address byte 1
2666                 UCHAR           Byte2;          // MAC address byte 2
2667                 UCHAR           Byte3;          // MAC address byte 3
2668         }       field;
2669         UINT32                  word;
2670 }       QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
2671 #endif
2672
2673 //
2674 // QOS_CSR1: TXOP holder address1 register
2675 //
2676 #ifdef RT_BIG_ENDIAN
2677 typedef union   _QOS_CSR1_STRUC {
2678         struct  {
2679                 UCHAR           Rsvd1;
2680                 UCHAR           Rsvd0;
2681                 UCHAR           Byte5;          // MAC address byte 5
2682                 UCHAR           Byte4;          // MAC address byte 4
2683         }       field;
2684         UINT32                  word;
2685 }       QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
2686 #else
2687 typedef union   _QOS_CSR1_STRUC {
2688         struct  {
2689                 UCHAR           Byte4;          // MAC address byte 4
2690                 UCHAR           Byte5;          // MAC address byte 5
2691                 UCHAR           Rsvd0;
2692                 UCHAR           Rsvd1;
2693         }       field;
2694         UINT32                  word;
2695 }       QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
2696 #endif
2697
2698 #define RF_CSR_CFG      0x500
2699 #ifdef RT_BIG_ENDIAN
2700 typedef union   _RF_CSR_CFG_STRUC       {
2701         struct  {
2702                 UINT    Rsvd1:14;                               // Reserved
2703                 UINT    RF_CSR_KICK:1;                  // kick RF register read/write
2704                 UINT    RF_CSR_WR:1;                    // 0: read  1: write
2705                 UINT    Rsvd2:3;                                // Reserved
2706                 UINT    TESTCSR_RFACC_REGNUM:5; // RF register ID
2707                 UINT    RF_CSR_DATA:8;                  // DATA
2708         }       field;
2709         UINT    word;
2710 }       RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
2711 #else
2712 typedef union   _RF_CSR_CFG_STRUC       {
2713         struct  {
2714                 UINT    RF_CSR_DATA:8;                  // DATA
2715                 UINT    TESTCSR_RFACC_REGNUM:5; // RF register ID
2716                 UINT    Rsvd2:3;                                // Reserved
2717                 UINT    RF_CSR_WR:1;                    // 0: read  1: write
2718                 UINT    RF_CSR_KICK:1;                  // kick RF register read/write
2719                 UINT    Rsvd1:14;                               // Reserved
2720         }       field;
2721         UINT    word;
2722 }       RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
2723 #endif
2724
2725 #endif  // __RT28XX_H__