2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
52 /* Macro to expand scalars to 64-bit objects */
54 #define ito64(x) (sizeof(x) == 8) ? \
55 (((unsigned long long int)(x)) & (0xff)) : \
57 (((unsigned long long int)(x)) & 0xffff) : \
58 ((sizeof(x) == 32) ? \
59 (((unsigned long long int)(x)) & 0xffffffff) : \
60 (unsigned long long int)(x))
62 /* increment with wrap-around */
63 #define INCR(_l, _sz) do { \
65 (_l) &= ((_sz) - 1); \
68 /* decrement with wrap-around */
69 #define DECR(_l, _sz) do { \
71 (_l) &= ((_sz) - 1); \
74 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
76 #define ASSERT(exp) do { \
77 if (unlikely(!(exp))) { \
83 #define memzero(_buf, _len) memset(_buf, 0, _len)
85 #define get_dma_mem_context(var, field) (&((var)->field))
86 #define copy_dma_mem_context(dst, src) (*dst = *src)
88 #define ATH9K_BH_STATUS_INTACT 0
89 #define ATH9K_BH_STATUS_CHANGE 1
91 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
93 static inline unsigned long get_timestamp(void)
95 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
98 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
105 ATH_DBG_RESET = 0x00000001,
106 ATH_DBG_PHY_IO = 0x00000002,
107 ATH_DBG_REG_IO = 0x00000004,
108 ATH_DBG_QUEUE = 0x00000008,
109 ATH_DBG_EEPROM = 0x00000010,
110 ATH_DBG_NF_CAL = 0x00000020,
111 ATH_DBG_CALIBRATE = 0x00000040,
112 ATH_DBG_CHANNEL = 0x00000080,
113 ATH_DBG_INTERRUPT = 0x00000100,
114 ATH_DBG_REGULATORY = 0x00000200,
115 ATH_DBG_ANI = 0x00000400,
116 ATH_DBG_POWER_MGMT = 0x00000800,
117 ATH_DBG_XMIT = 0x00001000,
118 ATH_DBG_BEACON = 0x00002000,
119 ATH_DBG_RATE = 0x00004000,
120 ATH_DBG_CONFIG = 0x00008000,
121 ATH_DBG_KEYCACHE = 0x00010000,
122 ATH_DBG_AGGR = 0x00020000,
123 ATH_DBG_FATAL = 0x00040000,
124 ATH_DBG_ANY = 0xffffffff
127 #define DBG_DEFAULT (ATH_DBG_FATAL)
129 #define DPRINTF(sc, _m, _fmt, ...) do { \
130 if (sc->sc_debug & (_m)) \
131 printk(_fmt , ##__VA_ARGS__); \
134 /***************************/
135 /* Load-time Configuration */
136 /***************************/
138 /* Per-instance load-time (note: NOT run-time) configurations
139 * for Atheros Device */
143 u16 txpowlimit_override;
144 u8 cabqReadytime; /* Cabq Readytime % */
145 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
148 /***********************/
149 /* Chainmask Selection */
150 /***********************/
152 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
153 /* Default - Number of last RSSI values that is used for
154 * chainmask selection */
155 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
156 /* Means use 3x3 chainmask instead of configured chainmask */
157 #define ATH_CHAINMASK_SEL_3X3 7
158 /* Default - Rssi threshold below which we have to switch to 3x3 */
159 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
160 /* Default - Rssi threshold above which we have to switch to
161 * user configured values */
162 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
163 /* Struct to store the chainmask select related info */
164 struct ath_chainmask_sel {
165 struct timer_list timer;
166 int cur_tx_mask; /* user configured or 3x3 */
167 int cur_rx_mask; /* user configured or 3x3 */
169 u8 switch_allowed:1, /* timer will set this */
173 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
174 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
176 /*************************/
177 /* Descriptor Management */
178 /*************************/
180 #define ATH_TXBUF_RESET(_bf) do { \
181 (_bf)->bf_status = 0; \
182 (_bf)->bf_lastbf = NULL; \
183 (_bf)->bf_lastfrm = NULL; \
184 (_bf)->bf_next = NULL; \
185 memzero(&((_bf)->bf_state), \
186 sizeof(struct ath_buf_state)); \
196 BUF_SHORT_PREAMBLE = BIT(6),
199 BUF_AGGR_BURST = BIT(9),
200 BUF_CALC_AIRTIME = BIT(10),
203 struct ath_buf_state {
204 int bfs_nframes; /* # frames in aggregate */
205 u16 bfs_al; /* length of aggregate */
206 u16 bfs_frmlen; /* length of frame */
207 int bfs_seqno; /* sequence number */
208 int bfs_tidno; /* tid of this frame */
209 int bfs_retries; /* current retries */
210 struct ath_rc_series bfs_rcs[4]; /* rate series */
211 u32 bf_type; /* BUF_* (enum buffer_type) */
212 /* key type use to encrypt this frame */
213 enum ath9k_key_type bfs_keytype;
216 #define bf_nframes bf_state.bfs_nframes
217 #define bf_al bf_state.bfs_al
218 #define bf_frmlen bf_state.bfs_frmlen
219 #define bf_retries bf_state.bfs_retries
220 #define bf_seqno bf_state.bfs_seqno
221 #define bf_tidno bf_state.bfs_tidno
222 #define bf_rcs bf_state.bfs_rcs
223 #define bf_keytype bf_state.bfs_keytype
224 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
225 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
226 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
227 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
228 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
229 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
230 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
231 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
232 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
233 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
236 * Abstraction of a contiguous buffer to transmit/receive. There is only
237 * a single hw descriptor encapsulated here.
240 struct list_head list;
241 struct list_head *last;
242 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
244 struct ath_buf *bf_lastfrm; /* last buf of this frame */
245 struct ath_buf *bf_next; /* next subframe in the aggregate */
246 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
247 void *bf_mpdu; /* enclosing frame structure */
248 void *bf_node; /* pointer to the node */
249 struct ath_desc *bf_desc; /* virtual addr of desc */
250 dma_addr_t bf_daddr; /* physical addr of desc */
251 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
253 u16 bf_flags; /* tx descriptor flags */
254 struct ath_buf_state bf_state; /* buffer state */
255 dma_addr_t bf_dmacontext;
259 * reset the rx buffer.
260 * any new fields added to the athbuf and require
261 * reset need to be added to this macro.
262 * currently bf_status is the only one requires that
265 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
267 /* hw processing complete, desc processed by hal */
268 #define ATH_BUFSTATUS_DONE 0x00000001
269 /* hw processing complete, desc hold for hw */
270 #define ATH_BUFSTATUS_STALE 0x00000002
271 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
272 #define ATH_BUFSTATUS_FREE 0x00000004
274 /* DMA state for tx/rx descriptors */
278 struct ath_desc *dd_desc; /* descriptors */
279 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
280 u32 dd_desc_len; /* size of dd_desc */
281 struct ath_buf *dd_bufptr; /* associated buffers */
282 dma_addr_t dd_dmacontext;
285 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
287 struct ath_rx_context {
288 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
290 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
292 int ath_descdma_setup(struct ath_softc *sc,
293 struct ath_descdma *dd,
294 struct list_head *head,
298 int ath_desc_alloc(struct ath_softc *sc);
299 void ath_desc_free(struct ath_softc *sc);
300 void ath_descdma_cleanup(struct ath_softc *sc,
301 struct ath_descdma *dd,
302 struct list_head *head);
308 #define ATH_MAX_ANTENNA 3
309 #define ATH_RXBUF 512
310 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
311 #define WME_NUM_TID 16
312 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
313 #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
316 ATH_RX_NON_CONSUMED = 0,
320 /* per frame rx status block */
321 struct ath_recv_status {
322 u64 tsf; /* mac tsf */
323 int8_t rssi; /* RSSI (noise floor ajusted) */
324 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
325 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
326 int8_t abs_rssi; /* absolute RSSI */
327 u8 rateieee; /* data rate received (IEEE rate code) */
328 u8 ratecode; /* phy rate code */
329 int rateKbps; /* data rate received (Kbps) */
330 int antenna; /* rx antenna */
331 int flags; /* status of associated skb */
332 #define ATH_RX_FCS_ERROR 0x01
333 #define ATH_RX_MIC_ERROR 0x02
334 #define ATH_RX_DECRYPT_ERROR 0x04
335 #define ATH_RX_RSSI_VALID 0x08
336 /* if any of ctl,extn chainrssis are valid */
337 #define ATH_RX_CHAIN_RSSI_VALID 0x10
338 /* if extn chain rssis are valid */
339 #define ATH_RX_RSSI_EXTN_VALID 0x20
340 /* set if 40Mhz, clear if 20Mhz */
341 #define ATH_RX_40MHZ 0x40
342 /* set if short GI, clear if full GI */
343 #define ATH_RX_SHORT_GI 0x80
347 struct sk_buff *rx_wbuf;
348 unsigned long rx_time; /* system time when received */
349 struct ath_recv_status rx_status; /* cached rx status */
352 /* Per-TID aggregate receiver state for a node */
355 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
356 struct timer_list timer;
358 int baw_head; /* seq_next at head */
359 int baw_tail; /* tail of block-ack window */
360 int seq_reset; /* need to reset start sequence */
361 int addba_exchangecomplete;
362 u16 seq_next; /* next expected sequence */
363 u16 baw_size; /* block-ack window size */
366 /* Per-node receiver aggregate state */
368 struct ath_arx_tid tid[WME_NUM_TID];
371 int ath_startrecv(struct ath_softc *sc);
372 bool ath_stoprecv(struct ath_softc *sc);
373 void ath_flushrecv(struct ath_softc *sc);
374 u32 ath_calcrxfilter(struct ath_softc *sc);
375 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
376 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
377 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
378 void ath_handle_rx_intr(struct ath_softc *sc);
379 int ath_rx_init(struct ath_softc *sc, int nbufs);
380 void ath_rx_cleanup(struct ath_softc *sc);
381 int ath_rx_tasklet(struct ath_softc *sc, int flush);
382 int ath_rx_input(struct ath_softc *sc,
383 struct ath_node *node,
386 struct ath_recv_status *rx_status,
387 enum ATH_RX_TYPE *status);
388 int ath__rx_indicate(struct ath_softc *sc,
390 struct ath_recv_status *status,
392 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
393 struct ath_recv_status *status);
399 #define ATH_TXBUF 512
400 /* max number of transmit attempts (tries) */
401 #define ATH_TXMAXTRY 13
402 /* max number of 11n transmit attempts (tries) */
403 #define ATH_11N_TXMAXTRY 10
404 /* max number of tries for management and control frames */
405 #define ATH_MGT_TXMAXTRY 4
406 #define WME_BA_BMP_SIZE 64
407 #define WME_MAX_BA WME_BA_BMP_SIZE
408 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
409 #define TID_TO_WME_AC(_tid) \
410 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
411 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
412 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
416 /* Wireless Multimedia Extension Defines */
417 #define WME_AC_BE 0 /* best effort */
418 #define WME_AC_BK 1 /* background */
419 #define WME_AC_VI 2 /* video */
420 #define WME_AC_VO 3 /* voice */
425 ATH_SM_PWRSAV_STATIC,
426 ATH_SM_PWRSAV_DYNAMIC,
430 * Data transmit queue state. One of these exists for each
431 * hardware transmit queue. Packets sent to us from above
432 * are assigned to queues based on their priority. Not all
433 * devices support a complete set of hardware transmit queues.
434 * For those devices the array sc_ac2q will map multiple
435 * priorities to fewer hardware queues (typically all to one
439 u32 axq_qnum; /* hardware q number */
440 u32 *axq_link; /* link ptr in last TX desc */
441 struct list_head axq_q; /* transmit queue */
443 unsigned long axq_lockflags; /* intr state when must cli */
444 u32 axq_depth; /* queue depth */
445 u8 axq_aggr_depth; /* aggregates queued */
446 u32 axq_totalqueued; /* total ever queued */
448 /* count to determine if descriptor should generate int on this txq. */
451 bool stopped; /* Is mac80211 queue stopped ? */
452 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
454 /* first desc of the last descriptor that contains CTS */
455 struct ath_desc *axq_lastdsWithCTS;
457 /* final desc of the gating desc that determines whether
458 lastdsWithCTS has been DMA'ed or not */
459 struct ath_desc *axq_gatingds;
461 struct list_head axq_acq;
464 /* per TID aggregate tx state for a destination */
466 struct list_head list; /* round-robin tid entry */
467 struct list_head buf_q; /* pending buffers */
469 struct ath_atx_ac *ac;
470 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
475 int baw_head; /* first un-acked tx buffer */
476 int baw_tail; /* next unused tx buffer slot */
479 int cleanup_inprogress;
480 u32 addba_exchangecomplete:1;
481 int32_t addba_exchangeinprogress;
482 int addba_exchangeattempts;
485 /* per access-category aggregate tx state for a destination */
487 int sched; /* dest-ac is scheduled */
488 int qnum; /* H/W queue number associated
490 struct list_head list; /* round-robin txq entry */
491 struct list_head tid_q; /* queue of TIDs with buffers */
494 /* per dest tx state */
496 struct ath_atx_tid tid[WME_NUM_TID];
497 struct ath_atx_ac ac[WME_NUM_AC];
500 /* per-frame tx control block */
501 struct ath_tx_control {
508 enum ath9k_pkt_type atype;
509 enum ath9k_key_type keytype;
519 struct ath_softc *dev;
520 dma_addr_t dmacontext;
523 /* per frame tx status block */
524 struct ath_xmit_status {
525 int retries; /* number of retries to successufully
526 transmit this frame */
527 int flags; /* status of transmit */
528 #define ATH_TX_ERROR 0x01
529 #define ATH_TX_XRETRY 0x02
530 #define ATH_TX_BAR 0x04
534 int rssi; /* RSSI (noise floor ajusted) */
535 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
536 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
537 int rateieee; /* data rate xmitted (IEEE rate code) */
538 int rateKbps; /* data rate xmitted (Kbps) */
539 int ratecode; /* phy rate code */
540 int flags; /* validity flags */
541 /* if any of ctl,extn chain rssis are valid */
542 #define ATH_TX_CHAIN_RSSI_VALID 0x01
543 /* if extn chain rssis are valid */
544 #define ATH_TX_RSSI_EXTN_VALID 0x02
545 u32 airtime; /* time on air per final tx rate */
548 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
549 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
550 int ath_tx_setup(struct ath_softc *sc, int haltype);
551 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
552 void ath_tx_draintxq(struct ath_softc *sc,
553 struct ath_txq *txq, bool retry_tx);
554 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
555 void ath_tx_node_cleanup(struct ath_softc *sc,
556 struct ath_node *an, bool bh_flag);
557 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
558 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
559 int ath_tx_init(struct ath_softc *sc, int nbufs);
560 int ath_tx_cleanup(struct ath_softc *sc);
561 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
562 int ath_txq_update(struct ath_softc *sc, int qnum,
563 struct ath9k_tx_queue_info *q);
564 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
565 void ath_tx_tasklet(struct ath_softc *sc);
566 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
567 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
568 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
569 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
570 struct ath_xmit_status *tx_status, struct ath_node *an);
572 /**********************/
573 /* Node / Aggregation */
574 /**********************/
576 /* indicates the node is clened up */
577 #define ATH_NODE_CLEAN 0x1
578 /* indicates the node is 80211 power save */
579 #define ATH_NODE_PWRSAVE 0x2
581 #define ADDBA_EXCHANGE_ATTEMPTS 10
582 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
583 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
584 /* number of delimiters for encryption padding */
585 #define ATH_AGGR_ENCRYPTDELIM 10
586 /* minimum h/w qdepth to be sustained to maximize aggregation */
587 #define ATH_AGGR_MIN_QDEPTH 2
588 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
589 #define IEEE80211_SEQ_SEQ_SHIFT 4
590 #define IEEE80211_SEQ_MAX 4096
591 #define IEEE80211_MIN_AMPDU_BUF 0x8
593 /* return whether a bit at index _n in bitmap _bm is set
594 * _sz is the size of the bitmap */
595 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
596 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
598 /* return block-ack bitmap index given sequence and starting sequence */
599 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
601 /* returns delimiter padding required given the packet length */
602 #define ATH_AGGR_GET_NDELIM(_len) \
603 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
604 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
606 #define BAW_WITHIN(_start, _bawsz, _seqno) \
607 ((((_seqno) - (_start)) & 4095) < (_bawsz))
609 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
610 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
611 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
612 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
614 enum ATH_AGGR_STATUS {
622 enum ATH_AGGR_CHECK {
625 AGGR_CLEANUP_PROGRESS,
626 AGGR_EXCHANGE_PROGRESS,
630 struct aggr_rifs_param {
631 int param_max_frames;
635 struct ath_rc_series *param_rcs;
638 /* Per-node aggregation state */
639 struct ath_node_aggr {
640 struct ath_atx tx; /* node transmit state */
641 struct ath_arx rx; /* node receive state */
644 /* driver-specific node state */
646 struct list_head list;
647 struct ath_softc *an_sc;
649 struct ath_chainmask_sel an_chainmask_sel;
650 struct ath_node_aggr an_aggr;
651 u8 an_smmode; /* SM Power save mode */
653 u8 an_addr[ETH_ALEN];
656 void ath_tx_resume_tid(struct ath_softc *sc,
657 struct ath_atx_tid *tid);
658 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
659 struct ath_node *an, u8 tidno);
660 void ath_tx_aggr_teardown(struct ath_softc *sc,
661 struct ath_node *an, u8 tidno);
662 void ath_rx_aggr_teardown(struct ath_softc *sc,
663 struct ath_node *an, u8 tidno);
664 int ath_rx_aggr_start(struct ath_softc *sc,
668 int ath_rx_aggr_stop(struct ath_softc *sc,
671 int ath_tx_aggr_start(struct ath_softc *sc,
675 int ath_tx_aggr_stop(struct ath_softc *sc,
678 void ath_newassoc(struct ath_softc *sc,
679 struct ath_node *node, int isnew, int isuapsd);
680 struct ath_node *ath_node_attach(struct ath_softc *sc,
681 u8 addr[ETH_ALEN], int if_id);
682 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
683 struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
684 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
685 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
687 /*******************/
688 /* Beacon Handling */
689 /*******************/
692 * Regardless of the number of beacons we stagger, (i.e. regardless of the
693 * number of BSSIDs) if a given beacon does not go out even after waiting this
694 * number of beacon intervals, the game's up.
696 #define BSTUCK_THRESH (9 * ATH_BCBUF)
697 #define ATH_BCBUF 4 /* number of beacon buffers */
698 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
699 #define ATH_DEFAULT_BMISS_LIMIT 10
700 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
702 /* beacon configuration */
703 struct ath_beacon_config {
713 } u; /* last received beacon/probe response timestamp of this BSS. */
716 /* offsets in a beacon frame for
717 * quick acess of beacon content by low-level driver */
718 struct ath_beacon_offset {
719 u8 *bo_tim; /* start of atim/dtim */
722 void ath9k_beacon_tasklet(unsigned long data);
723 void ath_beacon_config(struct ath_softc *sc, int if_id);
724 int ath_beaconq_setup(struct ath_hal *ah);
725 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
726 void ath_bstuck_process(struct ath_softc *sc);
727 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
728 void ath_beacon_sync(struct ath_softc *sc, int if_id);
729 void ath_get_beaconconfig(struct ath_softc *sc,
731 struct ath_beacon_config *conf);
737 * Define the scheme that we select MAC address for multiple
738 * BSS on the same radio. The very first VAP will just use the MAC
739 * address from the EEPROM. For the next 3 VAPs, we set the
740 * U/L bit (bit 1) in MAC address, and use the next two bits as the
744 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
745 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
747 /* VAP configuration (from protocol layer) */
748 struct ath_vap_config {
749 u32 av_fixed_rateset;
750 u32 av_fixed_retryset;
753 /* driver-specific vap state */
755 struct ieee80211_vif *av_if_data;
756 enum ath9k_opmode av_opmode; /* VAP operational mode */
757 struct ath_buf *av_bcbuf; /* beacon buffer */
758 struct ath_beacon_offset av_boff; /* dynamic update state */
759 struct ath_tx_control av_btxctl; /* txctl information for beacon */
760 int av_bslot; /* beacon slot index */
761 struct ath_txq av_mcastq; /* multicast transmit queue */
762 struct ath_vap_config av_config;/* vap configuration parameters*/
763 struct ath_rate_node *rc_node;
766 int ath_vap_attach(struct ath_softc *sc,
768 struct ieee80211_vif *if_data,
769 enum ath9k_opmode opmode);
770 int ath_vap_detach(struct ath_softc *sc, int if_id);
771 int ath_vap_config(struct ath_softc *sc,
772 int if_id, struct ath_vap_config *if_config);
773 int ath_vap_listen(struct ath_softc *sc, int if_id);
775 /*********************/
776 /* Antenna diversity */
777 /*********************/
779 #define ATH_ANT_DIV_MAX_CFG 2
780 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
781 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
783 enum ATH_ANT_DIV_STATE{
785 ATH_ANT_DIV_SCAN, /* evaluating antenna */
789 struct ath_softc *antdiv_sc;
791 enum ATH_ANT_DIV_STATE antdiv_state;
792 u8 antdiv_num_antcfg;
795 int32_t antdivf_rssitrig;
796 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
797 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
798 u64 antdiv_laststatetsf;
799 u8 antdiv_bssid[ETH_ALEN];
802 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
803 struct ath_softc *sc, int32_t rssitrig);
804 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
807 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
808 void ath_slow_ant_div(struct ath_antdiv *antdiv,
809 struct ieee80211_hdr *wh,
810 struct ath_rx_status *rx_stats);
811 void ath_setdefantenna(void *sc, u32 antenna);
813 /********************/
814 /* Main driver core */
815 /********************/
818 * Default cache line size, in bytes.
819 * Used when PCI device not fully initialized by bootrom/BIOS
821 #define DEFAULT_CACHELINE 32
822 #define ATH_DEFAULT_NOISE_FLOOR -95
823 #define ATH_REGCLASSIDS_MAX 10
824 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
825 #define ATH_MAX_SW_RETRIES 10
826 #define ATH_CHAN_MAX 255
827 #define IEEE80211_WEP_NKID 4 /* number of key ids */
828 #define IEEE80211_RATE_VAL 0x7f
830 * The key cache is used for h/w cipher state and also for
831 * tracking station state such as the current tx antenna.
832 * We also setup a mapping table between key cache slot indices
833 * and station state to short-circuit node lookups on rx.
834 * Different parts have different size key caches. We handle
835 * up to ATH_KEYMAX entries (could dynamically allocate state).
837 #define ATH_KEYMAX 128 /* max key cache size we handle */
839 #define ATH_IF_ID_ANY 0xff
840 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
842 #define RSSI_LPF_THRESHOLD -20
843 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
844 #define ATH_RATE_DUMMY_MARKER 0
845 #define ATH_RSSI_LPF_LEN 10
846 #define ATH_RSSI_DUMMY_MARKER 0x127
848 #define ATH_EP_MUL(x, mul) ((x) * (mul))
849 #define ATH_EP_RND(x, mul) \
850 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
851 #define ATH_RSSI_OUT(x) \
852 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
853 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
854 #define ATH_RSSI_IN(x) \
855 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
856 #define ATH_LPF_RSSI(x, y, len) \
857 ((x != ATH_RSSI_DUMMY_MARKER) ? \
858 (((x) * ((len) - 1) + (y)) / (len)) : (y))
859 #define ATH_RSSI_LPF(x, y) do { \
860 if ((y) >= RSSI_LPF_THRESHOLD) \
861 x = ATH_LPF_RSSI((x), \
862 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
879 enum ath9k_ht_macmode tx_chan_width;
885 #define SC_OP_INVALID BIT(0)
886 #define SC_OP_BEACONS BIT(1)
887 #define SC_OP_RXAGGR BIT(2)
888 #define SC_OP_TXAGGR BIT(3)
889 #define SC_OP_CHAINMASK_UPDATE BIT(4)
890 #define SC_OP_FULL_RESET BIT(5)
891 #define SC_OP_NO_RESET BIT(6)
892 #define SC_OP_PREAMBLE_SHORT BIT(7)
893 #define SC_OP_PROTECT_ENABLE BIT(8)
894 #define SC_OP_RXFLUSH BIT(9)
897 struct ieee80211_hw *hw;
898 struct pci_dev *pdev;
899 struct tasklet_struct intr_tq;
900 struct tasklet_struct bcon_tasklet;
901 struct ath_config sc_config;
902 struct ath_hal *sc_ah;
903 struct ath_rate_softc *sc_rc;
906 u8 sc_curbssid[ETH_ALEN];
907 u8 sc_myaddr[ETH_ALEN];
908 u8 sc_bssidmask[ETH_ALEN];
912 u32 sc_flags; /* SC_OP_* */
913 unsigned int rx_filter;
917 int sc_slotupdate; /* slot to next advance fsm */
919 int sc_bslot[ATH_BCBUF];
922 enum ath9k_int sc_imask;
923 enum wireless_mode sc_curmode; /* current phy mode */
924 enum PROT_MODE sc_protmode;
926 u8 sc_nbcnvaps; /* # of vaps sending beacons */
927 u16 sc_nvaps; /* # of active virtual ap's */
928 struct ath_vap *sc_vaps[ATH_BCBUF];
931 u8 sc_defant; /* current default antenna */
932 u8 sc_rxotherant; /* rx's on non-default antenna */
934 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
935 struct list_head node_list;
936 struct ath_ht_info sc_ht_info;
937 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
939 #ifdef CONFIG_SLOW_ANT_DIV
940 struct ath_antdiv sc_antdiv;
943 OK, /* no change needed */
944 UPDATE, /* update pending */
945 COMMIT /* beacon sent, commit change */
946 } sc_updateslot; /* slot time update fsm */
949 u32 sc_keymax; /* size of key cache */
950 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
951 u8 sc_splitmic; /* split TKIP MIC keys */
955 struct list_head sc_rxbuf;
956 struct ath_descdma sc_rxdma;
957 int sc_rxbufsize; /* rx size based on mtu */
958 u32 *sc_rxlink; /* link ptr in last RX desc */
959 u64 sc_lastrx; /* tsf of last rx'd frame */
962 struct list_head sc_txbuf;
963 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
964 struct ath_descdma sc_txdma;
966 u32 sc_txintrperiod; /* tx interrupt batching */
967 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
968 u16 seq_no; /* TX sequence number */
971 struct ath9k_tx_queue_info sc_beacon_qi;
972 struct ath_descdma sc_bdma;
973 struct ath_txq *sc_cabq;
974 struct list_head sc_bbuf;
977 u32 ast_be_xmit; /* beacons transmitted */
980 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
981 const struct ath9k_rate_table *sc_currates;
982 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
983 u8 sc_protrix; /* protection rate index */
985 u32 rateKbps; /* transfer rate in kbs */
986 u8 ieeerate; /* IEEE rate */
987 } sc_hwmap[256]; /* h/w rate ix mappings */
990 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
991 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
994 spinlock_t sc_rxflushlock;
995 spinlock_t sc_rxbuflock;
996 spinlock_t sc_txbuflock;
997 spinlock_t sc_resetlock;
998 spinlock_t node_lock;
1001 int ath_init(u16 devid, struct ath_softc *sc);
1002 void ath_deinit(struct ath_softc *sc);
1003 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1004 int ath_suspend(struct ath_softc *sc);
1005 irqreturn_t ath_isr(int irq, void *dev);
1006 int ath_reset(struct ath_softc *sc, bool retry_tx);
1007 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
1009 /*********************/
1010 /* Utility Functions */
1011 /*********************/
1013 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1014 int ath_keyset(struct ath_softc *sc,
1016 struct ath9k_keyval *hk,
1017 const u8 mac[ETH_ALEN]);
1018 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1019 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1020 void ath_setslottime(struct ath_softc *sc);
1021 void ath_update_txpow(struct ath_softc *sc);
1022 int ath_cabq_update(struct ath_softc *);
1023 void ath_get_currentCountry(struct ath_softc *sc,
1024 struct ath9k_country_entry *ctry);
1025 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
1026 dma_addr_t ath_skb_map_single(struct ath_softc *sc,
1027 struct sk_buff *skb,
1030 void ath_skb_unmap_single(struct ath_softc *sc,
1031 struct sk_buff *skb,
1034 enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);