git.oblomov.eu Git - linux-2.6/blob - arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c

   1 /*
   2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
   3  * M (part of the Centrino chipset).
   4  *
   5  * Since the original Pentium M, most new Intel CPUs support Enhanced
   6  * SpeedStep.
   7  *
   8  * Despite the "SpeedStep" in the name, this is almost entirely unlike
   9  * traditional SpeedStep.
  10  *
  11  * Modelled on speedstep.c
  12  *
  13  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/sched.h>        /* current */
  21 #include <linux/delay.h>
  22 #include <linux/compiler.h>
  23
  24 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
  25 #include <linux/acpi.h>
  26 #include <acpi/processor.h>
  27 #endif
  28
  29 #include <asm/msr.h>
  30 #include <asm/processor.h>
  31 #include <asm/cpufeature.h>
  32
  33 #define PFX             "speedstep-centrino: "
  34 #define MAINTAINER      "cpufreq@lists.linux.org.uk"
  35
  36 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
  37
  38
  39 struct cpu_id
  40 {
  41         __u8    x86;            /* CPU family */
  42         __u8    x86_model;      /* model */
  43         __u8    x86_mask;       /* stepping */
  44 };
  45
  46 enum {
  47         CPU_BANIAS,
  48         CPU_DOTHAN_A1,
  49         CPU_DOTHAN_A2,
  50         CPU_DOTHAN_B0,
  51         CPU_MP4HT_D0,
  52         CPU_MP4HT_E0,
  53 };
  54
  55 static const struct cpu_id cpu_ids[] = {
  56         [CPU_BANIAS]    = { 6,  9, 5 },
  57         [CPU_DOTHAN_A1] = { 6, 13, 1 },
  58         [CPU_DOTHAN_A2] = { 6, 13, 2 },
  59         [CPU_DOTHAN_B0] = { 6, 13, 6 },
  60         [CPU_MP4HT_D0]  = {15,  3, 4 },
  61         [CPU_MP4HT_E0]  = {15,  4, 1 },
  62 };
  63 #define N_IDS   ARRAY_SIZE(cpu_ids)
  64
  65 struct cpu_model
  66 {
  67         const struct cpu_id *cpu_id;
  68         const char      *model_name;
  69         unsigned        max_freq; /* max clock in kHz */
  70
  71         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  72 };
  73 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
  74
  75 /* Operating points for current CPU */
  76 static struct cpu_model *centrino_model[NR_CPUS];
  77 static const struct cpu_id *centrino_cpu[NR_CPUS];
  78
  79 static struct cpufreq_driver centrino_driver;
  80
  81 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  82
  83 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  84    frequency/voltage operating point; frequency in MHz, volts in mV.
  85    This is stored as "index" in the structure. */
  86 #define OP(mhz, mv)                                                     \
  87         {                                                               \
  88                 .frequency = (mhz) * 1000,                              \
  89                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
  90         }
  91
  92 /*
  93  * These voltage tables were derived from the Intel Pentium M
  94  * datasheet, document 25261202.pdf, Table 5.  I have verified they
  95  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
  96  * M.
  97  */
  98
  99 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
 100 static struct cpufreq_frequency_table banias_900[] =
 101 {
 102         OP(600,  844),
 103         OP(800,  988),
 104         OP(900, 1004),
 105         { .frequency = CPUFREQ_TABLE_END }
 106 };
 107
 108 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
 109 static struct cpufreq_frequency_table banias_1000[] =
 110 {
 111         OP(600,   844),
 112         OP(800,   972),
 113         OP(900,   988),
 114         OP(1000, 1004),
 115         { .frequency = CPUFREQ_TABLE_END }
 116 };
 117
 118 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
 119 static struct cpufreq_frequency_table banias_1100[] =
 120 {
 121         OP( 600,  956),
 122         OP( 800, 1020),
 123         OP( 900, 1100),
 124         OP(1000, 1164),
 125         OP(1100, 1180),
 126         { .frequency = CPUFREQ_TABLE_END }
 127 };
 128
 129
 130 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
 131 static struct cpufreq_frequency_table banias_1200[] =
 132 {
 133         OP( 600,  956),
 134         OP( 800, 1004),
 135         OP( 900, 1020),
 136         OP(1000, 1100),
 137         OP(1100, 1164),
 138         OP(1200, 1180),
 139         { .frequency = CPUFREQ_TABLE_END }
 140 };
 141
 142 /* Intel Pentium M processor 1.30GHz (Banias) */
 143 static struct cpufreq_frequency_table banias_1300[] =
 144 {
 145         OP( 600,  956),
 146         OP( 800, 1260),
 147         OP(1000, 1292),
 148         OP(1200, 1356),
 149         OP(1300, 1388),
 150         { .frequency = CPUFREQ_TABLE_END }
 151 };
 152
 153 /* Intel Pentium M processor 1.40GHz (Banias) */
 154 static struct cpufreq_frequency_table banias_1400[] =
 155 {
 156         OP( 600,  956),
 157         OP( 800, 1180),
 158         OP(1000, 1308),
 159         OP(1200, 1436),
 160         OP(1400, 1484),
 161         { .frequency = CPUFREQ_TABLE_END }
 162 };
 163
 164 /* Intel Pentium M processor 1.50GHz (Banias) */
 165 static struct cpufreq_frequency_table banias_1500[] =
 166 {
 167         OP( 600,  956),
 168         OP( 800, 1116),
 169         OP(1000, 1228),
 170         OP(1200, 1356),
 171         OP(1400, 1452),
 172         OP(1500, 1484),
 173         { .frequency = CPUFREQ_TABLE_END }
 174 };
 175
 176 /* Intel Pentium M processor 1.60GHz (Banias) */
 177 static struct cpufreq_frequency_table banias_1600[] =
 178 {
 179         OP( 600,  956),
 180         OP( 800, 1036),
 181         OP(1000, 1164),
 182         OP(1200, 1276),
 183         OP(1400, 1420),
 184         OP(1600, 1484),
 185         { .frequency = CPUFREQ_TABLE_END }
 186 };
 187
 188 /* Intel Pentium M processor 1.70GHz (Banias) */
 189 static struct cpufreq_frequency_table banias_1700[] =
 190 {
 191         OP( 600,  956),
 192         OP( 800, 1004),
 193         OP(1000, 1116),
 194         OP(1200, 1228),
 195         OP(1400, 1308),
 196         OP(1700, 1484),
 197         { .frequency = CPUFREQ_TABLE_END }
 198 };
 199 #undef OP
 200
 201 #define _BANIAS(cpuid, max, name)       \
 202 {       .cpu_id         = cpuid,        \
 203         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
 204         .max_freq       = (max)*1000,   \
 205         .op_points      = banias_##max, \
 206 }
 207 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
 208
 209 /* CPU models, their operating frequency range, and freq/voltage
 210    operating points */
 211 static struct cpu_model models[] =
 212 {
 213         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
 214         BANIAS(1000),
 215         BANIAS(1100),
 216         BANIAS(1200),
 217         BANIAS(1300),
 218         BANIAS(1400),
 219         BANIAS(1500),
 220         BANIAS(1600),
 221         BANIAS(1700),
 222
 223         /* NULL model_name is a wildcard */
 224         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
 225         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
 226         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
 227         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
 228         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 229
 230         { NULL, }
 231 };
 232 #undef _BANIAS
 233 #undef BANIAS
 234
 235 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 236 {
 237         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 238         struct cpu_model *model;
 239
 240         for(model = models; model->cpu_id != NULL; model++)
 241                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
 242                     (model->model_name == NULL ||
 243                      strcmp(cpu->x86_model_id, model->model_name) == 0))
 244                         break;
 245
 246         if (model->cpu_id == NULL) {
 247                 /* No match at all */
 248                 dprintk("no support for CPU model \"%s\": "
 249                        "send /proc/cpuinfo to " MAINTAINER "\n",
 250                        cpu->x86_model_id);
 251                 return -ENOENT;
 252         }
 253
 254         if (model->op_points == NULL) {
 255                 /* Matched a non-match */
 256                 dprintk("no table support for CPU model \"%s\"\n",
 257                        cpu->x86_model_id);
 258 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 259                 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
 260 #endif
 261                 return -ENOENT;
 262         }
 263
 264         centrino_model[policy->cpu] = model;
 265
 266         dprintk("found \"%s\": max frequency: %dkHz\n",
 267                model->model_name, model->max_freq);
 268
 269         return 0;
 270 }
 271
 272 #else
 273 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
 274 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
 275
 276 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
 277 {
 278         if ((c->x86 == x->x86) &&
 279             (c->x86_model == x->x86_model) &&
 280             (c->x86_mask == x->x86_mask))
 281                 return 1;
 282         return 0;
 283 }
 284
 285 /* To be called only after centrino_model is initialized */
 286 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
 287 {
 288         int i;
 289
 290         /*
 291          * Extract clock in kHz from PERF_CTL value
 292          * for centrino, as some DSDTs are buggy.
 293          * Ideally, this can be done using the acpi_data structure.
 294          */
 295         if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
 296             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
 297             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
 298                 msr = (msr >> 8) & 0xff;
 299                 return msr * 100000;
 300         }
 301
 302         if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
 303                 return 0;
 304
 305         msr &= 0xffff;
 306         for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
 307                 if (msr == centrino_model[cpu]->op_points[i].index)
 308                         return centrino_model[cpu]->op_points[i].frequency;
 309         }
 310         if (failsafe)
 311                 return centrino_model[cpu]->op_points[i-1].frequency;
 312         else
 313                 return 0;
 314 }
 315
 316 /* Return the current CPU frequency in kHz */
 317 static unsigned int get_cur_freq(unsigned int cpu)
 318 {
 319         unsigned l, h;
 320         unsigned clock_freq;
 321         cpumask_t saved_mask;
 322
 323         saved_mask = current->cpus_allowed;
 324         set_cpus_allowed(current, cpumask_of_cpu(cpu));
 325         if (smp_processor_id() != cpu)
 326                 return 0;
 327
 328         rdmsr(MSR_IA32_PERF_STATUS, l, h);
 329         clock_freq = extract_clock(l, cpu, 0);
 330
 331         if (unlikely(clock_freq == 0)) {
 332                 /*
 333                  * On some CPUs, we can see transient MSR values (which are
 334                  * not present in _PSS), while CPU is doing some automatic
 335                  * P-state transition (like TM2). Get the last freq set
 336                  * in PERF_CTL.
 337                  */
 338                 rdmsr(MSR_IA32_PERF_CTL, l, h);
 339                 clock_freq = extract_clock(l, cpu, 1);
 340         }
 341
 342         set_cpus_allowed(current, saved_mask);
 343         return clock_freq;
 344 }
 345
 346
 347 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 348
 349 static struct acpi_processor_performance *acpi_perf_data[NR_CPUS];
 350
 351 /*
 352  * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States
 353  * library
 354  *
 355  * Before doing the actual init, we need to do _PSD related setup whenever
 356  * supported by the BIOS. These are handled by this early_init routine.
 357  */
 358 static int centrino_cpu_early_init_acpi(void)
 359 {
 360         unsigned int    i, j;
 361         struct acpi_processor_performance       *data;
 362
 363         for_each_possible_cpu(i) {
 364                 data = kzalloc(sizeof(struct acpi_processor_performance),
 365                                 GFP_KERNEL);
 366                 if (!data) {
 367                         for_each_possible_cpu(j) {
 368                                 kfree(acpi_perf_data[j]);
 369                                 acpi_perf_data[j] = NULL;
 370                         }
 371                         return (-ENOMEM);
 372                 }
 373                 acpi_perf_data[i] = data;
 374         }
 375
 376         acpi_processor_preregister_performance(acpi_perf_data);
 377         return 0;
 378 }
 379
 380 /*
 381  * centrino_cpu_init_acpi - register with ACPI P-States library
 382  *
 383  * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
 384  * in order to determine correct frequency and voltage pairings by reading
 385  * the _PSS of the ACPI DSDT or SSDT tables.
 386  */
 387 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
 388 {
 389         unsigned long                   cur_freq;
 390         int                             result = 0, i;
 391         unsigned int                    cpu = policy->cpu;
 392         struct acpi_processor_performance       *p;
 393
 394         p = acpi_perf_data[cpu];
 395
 396         /* register with ACPI core */
 397         if (acpi_processor_register_performance(p, cpu)) {
 398                 dprintk(PFX "obtaining ACPI data failed\n");
 399                 return -EIO;
 400         }
 401         policy->shared_type = p->shared_type;
 402         /*
 403          * Will let policy->cpus know about dependency only when software
 404          * coordination is required.
 405          */
 406         if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL ||
 407             policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 408                 policy->cpus = p->shared_cpu_map;
 409
 410         /* verify the acpi_data */
 411         if (p->state_count <= 1) {
 412                 dprintk("No P-States\n");
 413                 result = -ENODEV;
 414                 goto err_unreg;
 415         }
 416
 417         if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
 418             (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
 419                 dprintk("Invalid control/status registers (%x - %x)\n",
 420                         p->control_register.space_id, p->status_register.space_id);
 421                 result = -EIO;
 422                 goto err_unreg;
 423         }
 424
 425         for (i=0; i<p->state_count; i++) {
 426                 if (p->states[i].control != p->states[i].status) {
 427                         dprintk("Different control (%llu) and status values (%llu)\n",
 428                                 p->states[i].control, p->states[i].status);
 429                         result = -EINVAL;
 430                         goto err_unreg;
 431                 }
 432
 433                 if (!p->states[i].core_frequency) {
 434                         dprintk("Zero core frequency for state %u\n", i);
 435                         result = -EINVAL;
 436                         goto err_unreg;
 437                 }
 438
 439                 if (p->states[i].core_frequency > p->states[0].core_frequency) {
 440                         dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
 441                                 p->states[i].core_frequency, p->states[0].core_frequency);
 442                         p->states[i].core_frequency = 0;
 443                         continue;
 444                 }
 445         }
 446
 447         centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
 448         if (!centrino_model[cpu]) {
 449                 result = -ENOMEM;
 450                 goto err_unreg;
 451         }
 452
 453         centrino_model[cpu]->model_name=NULL;
 454         centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000;
 455         centrino_model[cpu]->op_points =  kmalloc(sizeof(struct cpufreq_frequency_table) *
 456                                              (p->state_count + 1), GFP_KERNEL);
 457         if (!centrino_model[cpu]->op_points) {
 458                 result = -ENOMEM;
 459                 goto err_kfree;
 460         }
 461
 462         for (i=0; i<p->state_count; i++) {
 463                 centrino_model[cpu]->op_points[i].index = p->states[i].control;
 464                 centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
 465                 dprintk("adding state %i with frequency %u and control value %04x\n",
 466                         i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
 467         }
 468         centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END;
 469
 470         cur_freq = get_cur_freq(cpu);
 471
 472         for (i=0; i<p->state_count; i++) {
 473                 if (!p->states[i].core_frequency) {
 474                         dprintk("skipping state %u\n", i);
 475                         centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
 476                         continue;
 477                 }
 478
 479                 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
 480                     (centrino_model[cpu]->op_points[i].frequency)) {
 481                         dprintk("Invalid encoded frequency (%u vs. %u)\n",
 482                                 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
 483                                 centrino_model[cpu]->op_points[i].frequency);
 484                         result = -EINVAL;
 485                         goto err_kfree_all;
 486                 }
 487
 488                 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
 489                         p->state = i;
 490         }
 491
 492         /* notify BIOS that we exist */
 493         acpi_processor_notify_smm(THIS_MODULE);
 494
 495         return 0;
 496
 497  err_kfree_all:
 498         kfree(centrino_model[cpu]->op_points);
 499  err_kfree:
 500         kfree(centrino_model[cpu]);
 501  err_unreg:
 502         acpi_processor_unregister_performance(p, cpu);
 503         dprintk(PFX "invalid ACPI data\n");
 504         return (result);
 505 }
 506 #else
 507 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
 508 static inline int centrino_cpu_early_init_acpi(void) { return 0; }
 509 #endif
 510
 511 static int centrino_cpu_init(struct cpufreq_policy *policy)
 512 {
 513         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 514         unsigned freq;
 515         unsigned l, h;
 516         int ret;
 517         int i;
 518
 519         /* Only Intel makes Enhanced Speedstep-capable CPUs */
 520         if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
 521                 return -ENODEV;
 522
 523         if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
 524                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
 525
 526         if (centrino_cpu_init_acpi(policy)) {
 527                 if (policy->cpu != 0)
 528                         return -ENODEV;
 529
 530                 for (i = 0; i < N_IDS; i++)
 531                         if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
 532                                 break;
 533
 534                 if (i != N_IDS)
 535                         centrino_cpu[policy->cpu] = &cpu_ids[i];
 536
 537                 if (!centrino_cpu[policy->cpu]) {
 538                         dprintk("found unsupported CPU with "
 539                         "Enhanced SpeedStep: send /proc/cpuinfo to "
 540                         MAINTAINER "\n");
 541                         return -ENODEV;
 542                 }
 543
 544                 if (centrino_cpu_init_table(policy)) {
 545                         return -ENODEV;
 546                 }
 547         }
 548
 549         /* Check to see if Enhanced SpeedStep is enabled, and try to
 550            enable it if not. */
 551         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 552
 553         if (!(l & (1<<16))) {
 554                 l |= (1<<16);
 555                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
 556                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 557
 558                 /* check to see if it stuck */
 559                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 560                 if (!(l & (1<<16))) {
 561                         printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
 562                         return -ENODEV;
 563                 }
 564         }
 565
 566         freq = get_cur_freq(policy->cpu);
 567
 568         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 569         policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
 570         policy->cur = freq;
 571
 572         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
 573
 574         ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
 575         if (ret)
 576                 return (ret);
 577
 578         cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
 579
 580         return 0;
 581 }
 582
 583 static int centrino_cpu_exit(struct cpufreq_policy *policy)
 584 {
 585         unsigned int cpu = policy->cpu;
 586
 587         if (!centrino_model[cpu])
 588                 return -ENODEV;
 589
 590         cpufreq_frequency_table_put_attr(cpu);
 591
 592 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 593         if (!centrino_model[cpu]->model_name) {
 594                 static struct acpi_processor_performance *p;
 595
 596                 if (acpi_perf_data[cpu]) {
 597                         p = acpi_perf_data[cpu];
 598                         dprintk("unregistering and freeing ACPI data\n");
 599                         acpi_processor_unregister_performance(p, cpu);
 600                         kfree(centrino_model[cpu]->op_points);
 601                         kfree(centrino_model[cpu]);
 602                 }
 603         }
 604 #endif
 605
 606         centrino_model[cpu] = NULL;
 607
 608         return 0;
 609 }
 610
 611 /**
 612  * centrino_verify - verifies a new CPUFreq policy
 613  * @policy: new policy
 614  *
 615  * Limit must be within this model's frequency range at least one
 616  * border included.
 617  */
 618 static int centrino_verify (struct cpufreq_policy *policy)
 619 {
 620         return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
 621 }
 622
 623 /**
 624  * centrino_setpolicy - set a new CPUFreq policy
 625  * @policy: new policy
 626  * @target_freq: the target frequency
 627  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 628  *
 629  * Sets a new CPUFreq policy.
 630  */
 631 static int centrino_target (struct cpufreq_policy *policy,
 632                             unsigned int target_freq,
 633                             unsigned int relation)
 634 {
 635         unsigned int    newstate = 0;
 636         unsigned int    msr, oldmsr = 0, h = 0, cpu = policy->cpu;
 637         struct cpufreq_freqs    freqs;
 638         cpumask_t               online_policy_cpus;
 639         cpumask_t               saved_mask;
 640         cpumask_t               set_mask;
 641         cpumask_t               covered_cpus;
 642         int                     retval = 0;
 643         unsigned int            j, k, first_cpu, tmp;
 644
 645         if (unlikely(centrino_model[cpu] == NULL))
 646                 return -ENODEV;
 647
 648         if (unlikely(cpufreq_frequency_table_target(policy,
 649                         centrino_model[cpu]->op_points,
 650                         target_freq,
 651                         relation,
 652                         &newstate))) {
 653                 return -EINVAL;
 654         }
 655
 656 #ifdef CONFIG_HOTPLUG_CPU
 657         /* cpufreq holds the hotplug lock, so we are safe from here on */
 658         cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
 659 #else
 660         online_policy_cpus = policy->cpus;
 661 #endif
 662
 663         saved_mask = current->cpus_allowed;
 664         first_cpu = 1;
 665         cpus_clear(covered_cpus);
 666         for_each_cpu_mask(j, online_policy_cpus) {
 667                 /*
 668                  * Support for SMP systems.
 669                  * Make sure we are running on CPU that wants to change freq
 670                  */
 671                 cpus_clear(set_mask);
 672                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 673                         cpus_or(set_mask, set_mask, online_policy_cpus);
 674                 else
 675                         cpu_set(j, set_mask);
 676
 677                 set_cpus_allowed(current, set_mask);
 678                 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
 679                         dprintk("couldn't limit to CPUs in this domain\n");
 680                         retval = -EAGAIN;
 681                         if (first_cpu) {
 682                                 /* We haven't started the transition yet. */
 683                                 goto migrate_end;
 684                         }
 685                         break;
 686                 }
 687
 688                 msr = centrino_model[cpu]->op_points[newstate].index;
 689
 690                 if (first_cpu) {
 691                         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 692                         if (msr == (oldmsr & 0xffff)) {
 693                                 dprintk("no change needed - msr was and needs "
 694                                         "to be %x\n", oldmsr);
 695                                 retval = 0;
 696                                 goto migrate_end;
 697                         }
 698
 699                         freqs.old = extract_clock(oldmsr, cpu, 0);
 700                         freqs.new = extract_clock(msr, cpu, 0);
 701
 702                         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
 703                                 target_freq, freqs.old, freqs.new, msr);
 704
 705                         for_each_cpu_mask(k, online_policy_cpus) {
 706                                 freqs.cpu = k;
 707                                 cpufreq_notify_transition(&freqs,
 708                                         CPUFREQ_PRECHANGE);
 709                         }
 710
 711                         first_cpu = 0;
 712                         /* all but 16 LSB are reserved, treat them with care */
 713                         oldmsr &= ~0xffff;
 714                         msr &= 0xffff;
 715                         oldmsr |= msr;
 716                 }
 717
 718                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 719                 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
 720                         break;
 721
 722                 cpu_set(j, covered_cpus);
 723         }
 724
 725         for_each_cpu_mask(k, online_policy_cpus) {
 726                 freqs.cpu = k;
 727                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 728         }
 729
 730         if (unlikely(retval)) {
 731                 /*
 732                  * We have failed halfway through the frequency change.
 733                  * We have sent callbacks to policy->cpus and
 734                  * MSRs have already been written on coverd_cpus.
 735                  * Best effort undo..
 736                  */
 737
 738                 if (!cpus_empty(covered_cpus)) {
 739                         for_each_cpu_mask(j, covered_cpus) {
 740                                 set_cpus_allowed(current, cpumask_of_cpu(j));
 741                                 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 742                         }
 743                 }
 744
 745                 tmp = freqs.new;
 746                 freqs.new = freqs.old;
 747                 freqs.old = tmp;
 748                 for_each_cpu_mask(j, online_policy_cpus) {
 749                         freqs.cpu = j;
 750                         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 751                         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 752                 }
 753         }
 754
 755 migrate_end:
 756         set_cpus_allowed(current, saved_mask);
 757         return 0;
 758 }
 759
 760 static struct freq_attr* centrino_attr[] = {
 761         &cpufreq_freq_attr_scaling_available_freqs,
 762         NULL,
 763 };
 764
 765 static struct cpufreq_driver centrino_driver = {
 766         .name           = "centrino", /* should be speedstep-centrino,
 767                                          but there's a 16 char limit */
 768         .init           = centrino_cpu_init,
 769         .exit           = centrino_cpu_exit,
 770         .verify         = centrino_verify,
 771         .target         = centrino_target,
 772         .get            = get_cur_freq,
 773         .attr           = centrino_attr,
 774         .owner          = THIS_MODULE,
 775 };
 776
 777
 778 /**
 779  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 780  *
 781  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 782  * unsupported devices, -ENOENT if there's no voltage table for this
 783  * particular CPU model, -EINVAL on problems during initiatization,
 784  * and zero on success.
 785  *
 786  * This is quite picky.  Not only does the CPU have to advertise the
 787  * "est" flag in the cpuid capability flags, we look for a specific
 788  * CPU model and stepping, and we need to have the exact model name in
 789  * our voltage tables.  That is, be paranoid about not releasing
 790  * someone's valuable magic smoke.
 791  */
 792 static int __init centrino_init(void)
 793 {
 794         struct cpuinfo_x86 *cpu = cpu_data;
 795
 796         if (!cpu_has(cpu, X86_FEATURE_EST))
 797                 return -ENODEV;
 798
 799         centrino_cpu_early_init_acpi();
 800
 801         return cpufreq_register_driver(&centrino_driver);
 802 }
 803
 804 static void __exit centrino_exit(void)
 805 {
 806 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 807         unsigned int j;
 808 #endif
 809
 810         cpufreq_unregister_driver(&centrino_driver);
 811
 812 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 813         for_each_possible_cpu(j) {
 814                 kfree(acpi_perf_data[j]);
 815                 acpi_perf_data[j] = NULL;
 816         }
 817 #endif
 818 }
 819
 820 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
 821 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
 822 MODULE_LICENSE ("GPL");
 823
 824 late_initcall(centrino_init);
 825 module_exit(centrino_exit);